1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file performs vector type splitting and scalarization for LegalizeTypes.
11 // Scalarization is the act of changing a computation in an illegal one-element
12 // vector type to be a computation in its scalar element type. For example,
13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
17 // Splitting is the act of changing a computation in an invalid vector type to
18 // be a computation in two vectors of half the size. For example, implementing
19 // <128 x f32> operations in terms of two <64 x f32> operations.
21 //===----------------------------------------------------------------------===//
23 #include "LegalizeTypes.h"
24 #include "llvm/IR/DataLayout.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/raw_ostream.h"
29 #define DEBUG_TYPE "legalize-types"
31 //===----------------------------------------------------------------------===//
32 // Result Vector Scalarization: <1 x ty> -> ty.
33 //===----------------------------------------------------------------------===//
35 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
36 DEBUG(dbgs() << "Scalarize node result " << ResNo << ": ";
39 SDValue R = SDValue();
41 switch (N->getOpcode()) {
44 dbgs() << "ScalarizeVectorResult #" << ResNo << ": ";
48 report_fatal_error("Do not know how to scalarize the result of this "
51 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break;
52 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
53 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break;
54 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
55 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
56 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
57 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break;
58 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
59 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
60 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
61 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
62 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
63 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break;
64 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
65 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
66 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
67 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
68 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
73 case ISD::CTLZ_ZERO_UNDEF:
76 case ISD::CTTZ_ZERO_UNDEF:
96 case ISD::SIGN_EXTEND:
100 case ISD::ZERO_EXTEND:
101 R = ScalarizeVecRes_UnaryOp(N);
133 R = ScalarizeVecRes_BinOp(N);
136 R = ScalarizeVecRes_TernaryOp(N);
140 // If R is null, the sub-method took care of registering the result.
142 SetScalarizedVector(SDValue(N, ResNo), R);
145 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
146 SDValue LHS = GetScalarizedVector(N->getOperand(0));
147 SDValue RHS = GetScalarizedVector(N->getOperand(1));
148 return DAG.getNode(N->getOpcode(), SDLoc(N),
149 LHS.getValueType(), LHS, RHS, N->getFlags());
152 SDValue DAGTypeLegalizer::ScalarizeVecRes_TernaryOp(SDNode *N) {
153 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
154 SDValue Op1 = GetScalarizedVector(N->getOperand(1));
155 SDValue Op2 = GetScalarizedVector(N->getOperand(2));
156 return DAG.getNode(N->getOpcode(), SDLoc(N),
157 Op0.getValueType(), Op0, Op1, Op2);
160 SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N,
162 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
163 return GetScalarizedVector(Op);
166 SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
167 EVT NewVT = N->getValueType(0).getVectorElementType();
168 return DAG.getNode(ISD::BITCAST, SDLoc(N),
169 NewVT, N->getOperand(0));
172 SDValue DAGTypeLegalizer::ScalarizeVecRes_BUILD_VECTOR(SDNode *N) {
173 EVT EltVT = N->getValueType(0).getVectorElementType();
174 SDValue InOp = N->getOperand(0);
175 // The BUILD_VECTOR operands may be of wider element types and
176 // we may need to truncate them back to the requested return type.
177 if (EltVT.isInteger())
178 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
182 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
183 EVT NewVT = N->getValueType(0).getVectorElementType();
184 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
185 return DAG.getConvertRndSat(NewVT, SDLoc(N),
186 Op0, DAG.getValueType(NewVT),
187 DAG.getValueType(Op0.getValueType()),
190 cast<CvtRndSatSDNode>(N)->getCvtCode());
193 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
194 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
195 N->getValueType(0).getVectorElementType(),
196 N->getOperand(0), N->getOperand(1));
199 SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) {
200 EVT NewVT = N->getValueType(0).getVectorElementType();
201 SDValue Op = GetScalarizedVector(N->getOperand(0));
202 return DAG.getNode(ISD::FP_ROUND, SDLoc(N),
203 NewVT, Op, N->getOperand(1));
206 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
207 SDValue Op = GetScalarizedVector(N->getOperand(0));
208 return DAG.getNode(ISD::FPOWI, SDLoc(N),
209 Op.getValueType(), Op, N->getOperand(1));
212 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
213 // The value to insert may have a wider type than the vector element type,
214 // so be sure to truncate it to the element type if necessary.
215 SDValue Op = N->getOperand(1);
216 EVT EltVT = N->getValueType(0).getVectorElementType();
217 if (Op.getValueType() != EltVT)
218 // FIXME: Can this happen for floating point types?
219 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, Op);
223 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
224 assert(N->isUnindexed() && "Indexed vector load?");
226 SDValue Result = DAG.getLoad(
227 ISD::UNINDEXED, N->getExtensionType(),
228 N->getValueType(0).getVectorElementType(), SDLoc(N), N->getChain(),
229 N->getBasePtr(), DAG.getUNDEF(N->getBasePtr().getValueType()),
230 N->getPointerInfo(), N->getMemoryVT().getVectorElementType(),
231 N->getOriginalAlignment(), N->getMemOperand()->getFlags(),
234 // Legalize the chain result - switch anything that used the old chain to
236 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
240 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
241 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
242 EVT DestVT = N->getValueType(0).getVectorElementType();
243 SDValue Op = N->getOperand(0);
244 EVT OpVT = Op.getValueType();
246 // The result needs scalarizing, but it's not a given that the source does.
247 // This is a workaround for targets where it's impossible to scalarize the
248 // result of a conversion, because the source type is legal.
249 // For instance, this happens on AArch64: v1i1 is illegal but v1i{8,16,32}
250 // are widened to v8i8, v4i16, and v2i32, which is legal, because v1i64 is
251 // legal and was not scalarized.
252 // See the similar logic in ScalarizeVecRes_VSETCC
253 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
254 Op = GetScalarizedVector(Op);
256 EVT VT = OpVT.getVectorElementType();
258 ISD::EXTRACT_VECTOR_ELT, DL, VT, Op,
259 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
261 return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op);
264 SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) {
265 EVT EltVT = N->getValueType(0).getVectorElementType();
266 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType();
267 SDValue LHS = GetScalarizedVector(N->getOperand(0));
268 return DAG.getNode(N->getOpcode(), SDLoc(N), EltVT,
269 LHS, DAG.getValueType(ExtVT));
272 SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
273 // If the operand is wider than the vector element type then it is implicitly
274 // truncated. Make that explicit here.
275 EVT EltVT = N->getValueType(0).getVectorElementType();
276 SDValue InOp = N->getOperand(0);
277 if (InOp.getValueType() != EltVT)
278 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
282 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSELECT(SDNode *N) {
283 SDValue Cond = GetScalarizedVector(N->getOperand(0));
284 SDValue LHS = GetScalarizedVector(N->getOperand(1));
285 TargetLowering::BooleanContent ScalarBool =
286 TLI.getBooleanContents(false, false);
287 TargetLowering::BooleanContent VecBool = TLI.getBooleanContents(true, false);
289 // If integer and float booleans have different contents then we can't
290 // reliably optimize in all cases. There is a full explanation for this in
291 // DAGCombiner::visitSELECT() where the same issue affects folding
292 // (select C, 0, 1) to (xor C, 1).
293 if (TLI.getBooleanContents(false, false) !=
294 TLI.getBooleanContents(false, true)) {
295 // At least try the common case where the boolean is generated by a
297 if (Cond->getOpcode() == ISD::SETCC) {
298 EVT OpVT = Cond->getOperand(0)->getValueType(0);
299 ScalarBool = TLI.getBooleanContents(OpVT.getScalarType());
300 VecBool = TLI.getBooleanContents(OpVT);
302 ScalarBool = TargetLowering::UndefinedBooleanContent;
305 if (ScalarBool != VecBool) {
306 EVT CondVT = Cond.getValueType();
307 switch (ScalarBool) {
308 case TargetLowering::UndefinedBooleanContent:
310 case TargetLowering::ZeroOrOneBooleanContent:
311 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
312 VecBool == TargetLowering::ZeroOrNegativeOneBooleanContent);
313 // Vector read from all ones, scalar expects a single 1 so mask.
314 Cond = DAG.getNode(ISD::AND, SDLoc(N), CondVT,
315 Cond, DAG.getConstant(1, SDLoc(N), CondVT));
317 case TargetLowering::ZeroOrNegativeOneBooleanContent:
318 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
319 VecBool == TargetLowering::ZeroOrOneBooleanContent);
320 // Vector reads from a one, scalar from all ones so sign extend.
321 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), CondVT,
322 Cond, DAG.getValueType(MVT::i1));
327 return DAG.getSelect(SDLoc(N),
328 LHS.getValueType(), Cond, LHS,
329 GetScalarizedVector(N->getOperand(2)));
332 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
333 SDValue LHS = GetScalarizedVector(N->getOperand(1));
334 return DAG.getSelect(SDLoc(N),
335 LHS.getValueType(), N->getOperand(0), LHS,
336 GetScalarizedVector(N->getOperand(2)));
339 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
340 SDValue LHS = GetScalarizedVector(N->getOperand(2));
341 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), LHS.getValueType(),
342 N->getOperand(0), N->getOperand(1),
343 LHS, GetScalarizedVector(N->getOperand(3)),
347 SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
348 assert(N->getValueType(0).isVector() ==
349 N->getOperand(0).getValueType().isVector() &&
350 "Scalar/Vector type mismatch");
352 if (N->getValueType(0).isVector()) return ScalarizeVecRes_VSETCC(N);
354 SDValue LHS = GetScalarizedVector(N->getOperand(0));
355 SDValue RHS = GetScalarizedVector(N->getOperand(1));
358 // Turn it into a scalar SETCC.
359 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
362 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
363 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
366 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
367 // Figure out if the scalar is the LHS or RHS and return it.
368 SDValue Arg = N->getOperand(2).getOperand(0);
370 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
371 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
372 return GetScalarizedVector(N->getOperand(Op));
375 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
376 assert(N->getValueType(0).isVector() &&
377 N->getOperand(0).getValueType().isVector() &&
378 "Operand types must be vectors");
379 SDValue LHS = N->getOperand(0);
380 SDValue RHS = N->getOperand(1);
381 EVT OpVT = LHS.getValueType();
382 EVT NVT = N->getValueType(0).getVectorElementType();
385 // The result needs scalarizing, but it's not a given that the source does.
386 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
387 LHS = GetScalarizedVector(LHS);
388 RHS = GetScalarizedVector(RHS);
390 EVT VT = OpVT.getVectorElementType();
392 ISD::EXTRACT_VECTOR_ELT, DL, VT, LHS,
393 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
395 ISD::EXTRACT_VECTOR_ELT, DL, VT, RHS,
396 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
399 // Turn it into a scalar SETCC.
400 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
402 // Vectors may have a different boolean contents to scalars. Promote the
403 // value appropriately.
404 ISD::NodeType ExtendCode =
405 TargetLowering::getExtendForContent(TLI.getBooleanContents(OpVT));
406 return DAG.getNode(ExtendCode, DL, NVT, Res);
410 //===----------------------------------------------------------------------===//
411 // Operand Vector Scalarization <1 x ty> -> ty.
412 //===----------------------------------------------------------------------===//
414 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
415 DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": ";
418 SDValue Res = SDValue();
420 if (!Res.getNode()) {
421 switch (N->getOpcode()) {
424 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": ";
428 llvm_unreachable("Do not know how to scalarize this operator's operand!");
430 Res = ScalarizeVecOp_BITCAST(N);
432 case ISD::ANY_EXTEND:
433 case ISD::ZERO_EXTEND:
434 case ISD::SIGN_EXTEND:
436 case ISD::FP_TO_SINT:
437 case ISD::FP_TO_UINT:
438 case ISD::SINT_TO_FP:
439 case ISD::UINT_TO_FP:
440 Res = ScalarizeVecOp_UnaryOp(N);
442 case ISD::CONCAT_VECTORS:
443 Res = ScalarizeVecOp_CONCAT_VECTORS(N);
445 case ISD::EXTRACT_VECTOR_ELT:
446 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N);
449 Res = ScalarizeVecOp_VSELECT(N);
452 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo);
455 Res = ScalarizeVecOp_FP_ROUND(N, OpNo);
460 // If the result is null, the sub-method took care of registering results etc.
461 if (!Res.getNode()) return false;
463 // If the result is N, the sub-method updated N in place. Tell the legalizer
465 if (Res.getNode() == N)
468 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
469 "Invalid operand expansion");
471 ReplaceValueWith(SDValue(N, 0), Res);
475 /// If the value to convert is a vector that needs to be scalarized, it must be
476 /// <1 x ty>. Convert the element instead.
477 SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) {
478 SDValue Elt = GetScalarizedVector(N->getOperand(0));
479 return DAG.getNode(ISD::BITCAST, SDLoc(N),
480 N->getValueType(0), Elt);
483 /// If the input is a vector that needs to be scalarized, it must be <1 x ty>.
484 /// Do the operation on the element instead.
485 SDValue DAGTypeLegalizer::ScalarizeVecOp_UnaryOp(SDNode *N) {
486 assert(N->getValueType(0).getVectorNumElements() == 1 &&
487 "Unexpected vector type!");
488 SDValue Elt = GetScalarizedVector(N->getOperand(0));
489 SDValue Op = DAG.getNode(N->getOpcode(), SDLoc(N),
490 N->getValueType(0).getScalarType(), Elt);
491 // Revectorize the result so the types line up with what the uses of this
492 // expression expect.
493 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Op);
496 /// The vectors to concatenate have length one - use a BUILD_VECTOR instead.
497 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
498 SmallVector<SDValue, 8> Ops(N->getNumOperands());
499 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
500 Ops[i] = GetScalarizedVector(N->getOperand(i));
501 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Ops);
504 /// If the input is a vector that needs to be scalarized, it must be <1 x ty>,
505 /// so just return the element, ignoring the index.
506 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
507 SDValue Res = GetScalarizedVector(N->getOperand(0));
508 if (Res.getValueType() != N->getValueType(0))
509 Res = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0),
515 /// If the input condition is a vector that needs to be scalarized, it must be
516 /// <1 x i1>, so just convert to a normal ISD::SELECT
517 /// (still with vector output type since that was acceptable if we got here).
518 SDValue DAGTypeLegalizer::ScalarizeVecOp_VSELECT(SDNode *N) {
519 SDValue ScalarCond = GetScalarizedVector(N->getOperand(0));
520 EVT VT = N->getValueType(0);
522 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, ScalarCond, N->getOperand(1),
526 /// If the value to store is a vector that needs to be scalarized, it must be
527 /// <1 x ty>. Just store the element.
528 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
529 assert(N->isUnindexed() && "Indexed store of one-element vector?");
530 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
533 if (N->isTruncatingStore())
534 return DAG.getTruncStore(
535 N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
536 N->getBasePtr(), N->getPointerInfo(),
537 N->getMemoryVT().getVectorElementType(), N->getAlignment(),
538 N->getMemOperand()->getFlags(), N->getAAInfo());
540 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
541 N->getBasePtr(), N->getPointerInfo(),
542 N->getOriginalAlignment(), N->getMemOperand()->getFlags(),
546 /// If the value to round is a vector that needs to be scalarized, it must be
547 /// <1 x ty>. Convert the element instead.
548 SDValue DAGTypeLegalizer::ScalarizeVecOp_FP_ROUND(SDNode *N, unsigned OpNo) {
549 SDValue Elt = GetScalarizedVector(N->getOperand(0));
550 SDValue Res = DAG.getNode(ISD::FP_ROUND, SDLoc(N),
551 N->getValueType(0).getVectorElementType(), Elt,
553 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res);
556 //===----------------------------------------------------------------------===//
557 // Result Vector Splitting
558 //===----------------------------------------------------------------------===//
560 /// This method is called when the specified result of the specified node is
561 /// found to need vector splitting. At this point, the node may also have
562 /// invalid operands or may have other results that need legalization, we just
563 /// know that (at least) one result needs vector splitting.
564 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
565 DEBUG(dbgs() << "Split node result: ";
570 // See if the target wants to custom expand this node.
571 if (CustomLowerNode(N, N->getValueType(ResNo), true))
574 switch (N->getOpcode()) {
577 dbgs() << "SplitVectorResult #" << ResNo << ": ";
581 report_fatal_error("Do not know how to split the result of this "
584 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
586 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
587 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
588 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
589 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
590 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
591 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
592 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
593 case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break;
594 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
595 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
596 case ISD::FCOPYSIGN: SplitVecRes_FCOPYSIGN(N, Lo, Hi); break;
597 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
598 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
599 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
601 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
604 SplitVecRes_MLOAD(cast<MaskedLoadSDNode>(N), Lo, Hi);
607 SplitVecRes_MGATHER(cast<MaskedGatherSDNode>(N), Lo, Hi);
610 SplitVecRes_SETCC(N, Lo, Hi);
612 case ISD::VECTOR_SHUFFLE:
613 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
616 case ISD::ANY_EXTEND_VECTOR_INREG:
617 case ISD::SIGN_EXTEND_VECTOR_INREG:
618 case ISD::ZERO_EXTEND_VECTOR_INREG:
619 SplitVecRes_ExtVecInRegOp(N, Lo, Hi);
622 case ISD::BITREVERSE:
624 case ISD::CONVERT_RNDSAT:
627 case ISD::CTLZ_ZERO_UNDEF:
628 case ISD::CTTZ_ZERO_UNDEF:
639 case ISD::FNEARBYINT:
643 case ISD::FP_TO_SINT:
644 case ISD::FP_TO_UINT:
650 case ISD::SINT_TO_FP:
652 case ISD::UINT_TO_FP:
653 SplitVecRes_UnaryOp(N, Lo, Hi);
656 case ISD::ANY_EXTEND:
657 case ISD::SIGN_EXTEND:
658 case ISD::ZERO_EXTEND:
659 SplitVecRes_ExtendOp(N, Lo, Hi);
691 SplitVecRes_BinOp(N, Lo, Hi);
694 SplitVecRes_TernaryOp(N, Lo, Hi);
698 // If Lo/Hi is null, the sub-method took care of registering results etc.
700 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
703 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
705 SDValue LHSLo, LHSHi;
706 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
707 SDValue RHSLo, RHSHi;
708 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
711 const SDNodeFlags *Flags = N->getFlags();
712 unsigned Opcode = N->getOpcode();
713 Lo = DAG.getNode(Opcode, dl, LHSLo.getValueType(), LHSLo, RHSLo, Flags);
714 Hi = DAG.getNode(Opcode, dl, LHSHi.getValueType(), LHSHi, RHSHi, Flags);
717 void DAGTypeLegalizer::SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo,
719 SDValue Op0Lo, Op0Hi;
720 GetSplitVector(N->getOperand(0), Op0Lo, Op0Hi);
721 SDValue Op1Lo, Op1Hi;
722 GetSplitVector(N->getOperand(1), Op1Lo, Op1Hi);
723 SDValue Op2Lo, Op2Hi;
724 GetSplitVector(N->getOperand(2), Op2Lo, Op2Hi);
727 Lo = DAG.getNode(N->getOpcode(), dl, Op0Lo.getValueType(),
728 Op0Lo, Op1Lo, Op2Lo);
729 Hi = DAG.getNode(N->getOpcode(), dl, Op0Hi.getValueType(),
730 Op0Hi, Op1Hi, Op2Hi);
733 void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo,
735 // We know the result is a vector. The input may be either a vector or a
738 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
741 SDValue InOp = N->getOperand(0);
742 EVT InVT = InOp.getValueType();
744 // Handle some special cases efficiently.
745 switch (getTypeAction(InVT)) {
746 case TargetLowering::TypeLegal:
747 case TargetLowering::TypePromoteInteger:
748 case TargetLowering::TypePromoteFloat:
749 case TargetLowering::TypeSoftenFloat:
750 case TargetLowering::TypeScalarizeVector:
751 case TargetLowering::TypeWidenVector:
753 case TargetLowering::TypeExpandInteger:
754 case TargetLowering::TypeExpandFloat:
755 // A scalar to vector conversion, where the scalar needs expansion.
756 // If the vector is being split in two then we can just convert the
759 GetExpandedOp(InOp, Lo, Hi);
760 if (DAG.getDataLayout().isBigEndian())
762 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
763 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
767 case TargetLowering::TypeSplitVector:
768 // If the input is a vector that needs to be split, convert each split
769 // piece of the input now.
770 GetSplitVector(InOp, Lo, Hi);
771 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
772 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
776 // In the general case, convert the input to an integer and split it by hand.
777 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits());
778 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits());
779 if (DAG.getDataLayout().isBigEndian())
780 std::swap(LoIntVT, HiIntVT);
782 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
784 if (DAG.getDataLayout().isBigEndian())
786 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
787 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
790 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
794 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
795 unsigned LoNumElts = LoVT.getVectorNumElements();
796 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
797 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, LoOps);
799 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
800 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, HiOps);
803 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
805 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
807 unsigned NumSubvectors = N->getNumOperands() / 2;
808 if (NumSubvectors == 1) {
809 Lo = N->getOperand(0);
810 Hi = N->getOperand(1);
815 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
817 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
818 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, LoOps);
820 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
821 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, HiOps);
824 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
826 SDValue Vec = N->getOperand(0);
827 SDValue Idx = N->getOperand(1);
831 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
833 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
834 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
835 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec,
836 DAG.getConstant(IdxVal + LoVT.getVectorNumElements(), dl,
837 TLI.getVectorIdxTy(DAG.getDataLayout())));
840 void DAGTypeLegalizer::SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo,
842 SDValue Vec = N->getOperand(0);
843 SDValue SubVec = N->getOperand(1);
844 SDValue Idx = N->getOperand(2);
846 GetSplitVector(Vec, Lo, Hi);
848 EVT VecVT = Vec.getValueType();
849 EVT VecElemVT = VecVT.getVectorElementType();
850 unsigned VecElems = VecVT.getVectorNumElements();
851 unsigned SubElems = SubVec.getValueType().getVectorNumElements();
853 // If we know the index is 0, and we know the subvector doesn't cross the
854 // boundary between the halves, we can avoid spilling the vector, and insert
855 // into the lower half of the split vector directly.
856 // TODO: The IdxVal == 0 constraint is artificial, we could do this whenever
857 // the index is constant and there is no boundary crossing. But those cases
858 // don't seem to get hit in practice.
859 if (ConstantSDNode *ConstIdx = dyn_cast<ConstantSDNode>(Idx)) {
860 unsigned IdxVal = ConstIdx->getZExtValue();
861 if ((IdxVal == 0) && (IdxVal + SubElems <= VecElems / 2)) {
863 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
864 Lo = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, LoVT, Lo, SubVec, Idx);
869 // Spill the vector to the stack.
870 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
872 DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, MachinePointerInfo());
874 // Store the new subvector into the specified index.
875 SDValue SubVecPtr = GetVectorElementPointer(StackPtr, VecElemVT, Idx);
876 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
877 unsigned Alignment = DAG.getDataLayout().getPrefTypeAlignment(VecType);
878 Store = DAG.getStore(Store, dl, SubVec, SubVecPtr, MachinePointerInfo());
880 // Load the Lo part from the stack slot.
882 DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo());
884 // Increment the pointer to the other part.
885 unsigned IncrementSize = Lo.getValueSizeInBits() / 8;
887 DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
888 DAG.getConstant(IncrementSize, dl, StackPtr.getValueType()));
890 // Load the Hi part from the stack slot.
891 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
892 MinAlign(Alignment, IncrementSize));
895 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
898 GetSplitVector(N->getOperand(0), Lo, Hi);
899 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1));
900 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1));
903 void DAGTypeLegalizer::SplitVecRes_FCOPYSIGN(SDNode *N, SDValue &Lo,
905 SDValue LHSLo, LHSHi;
906 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
909 SDValue RHSLo, RHSHi;
910 SDValue RHS = N->getOperand(1);
911 EVT RHSVT = RHS.getValueType();
912 if (getTypeAction(RHSVT) == TargetLowering::TypeSplitVector)
913 GetSplitVector(RHS, RHSLo, RHSHi);
915 std::tie(RHSLo, RHSHi) = DAG.SplitVector(RHS, SDLoc(RHS));
918 Lo = DAG.getNode(ISD::FCOPYSIGN, DL, LHSLo.getValueType(), LHSLo, RHSLo);
919 Hi = DAG.getNode(ISD::FCOPYSIGN, DL, LHSHi.getValueType(), LHSHi, RHSHi);
922 void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo,
924 SDValue LHSLo, LHSHi;
925 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
929 std::tie(LoVT, HiVT) =
930 DAG.GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT());
932 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,
933 DAG.getValueType(LoVT));
934 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi,
935 DAG.getValueType(HiVT));
938 void DAGTypeLegalizer::SplitVecRes_ExtVecInRegOp(SDNode *N, SDValue &Lo,
940 unsigned Opcode = N->getOpcode();
941 SDValue N0 = N->getOperand(0);
945 GetSplitVector(N0, InLo, InHi);
946 EVT InLoVT = InLo.getValueType();
947 unsigned InNumElements = InLoVT.getVectorNumElements();
949 EVT OutLoVT, OutHiVT;
950 std::tie(OutLoVT, OutHiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
951 unsigned OutNumElements = OutLoVT.getVectorNumElements();
952 assert((2 * OutNumElements) <= InNumElements &&
953 "Illegal extend vector in reg split");
955 // *_EXTEND_VECTOR_INREG instructions extend the lowest elements of the
956 // input vector (i.e. we only use InLo):
957 // OutLo will extend the first OutNumElements from InLo.
958 // OutHi will extend the next OutNumElements from InLo.
960 // Shuffle the elements from InLo for OutHi into the bottom elements to
961 // create a 'fake' InHi.
962 SmallVector<int, 8> SplitHi(InNumElements, -1);
963 for (unsigned i = 0; i != OutNumElements; ++i)
964 SplitHi[i] = i + OutNumElements;
965 InHi = DAG.getVectorShuffle(InLoVT, dl, InLo, DAG.getUNDEF(InLoVT), SplitHi);
967 Lo = DAG.getNode(Opcode, dl, OutLoVT, InLo);
968 Hi = DAG.getNode(Opcode, dl, OutHiVT, InHi);
971 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
973 SDValue Vec = N->getOperand(0);
974 SDValue Elt = N->getOperand(1);
975 SDValue Idx = N->getOperand(2);
977 GetSplitVector(Vec, Lo, Hi);
979 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
980 unsigned IdxVal = CIdx->getZExtValue();
981 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
982 if (IdxVal < LoNumElts)
983 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
984 Lo.getValueType(), Lo, Elt, Idx);
987 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
988 DAG.getConstant(IdxVal - LoNumElts, dl,
989 TLI.getVectorIdxTy(DAG.getDataLayout())));
993 // See if the target wants to custom expand this node.
994 if (CustomLowerNode(N, N->getValueType(0), true))
997 // Spill the vector to the stack.
998 EVT VecVT = Vec.getValueType();
999 EVT EltVT = VecVT.getVectorElementType();
1000 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1002 DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, MachinePointerInfo());
1004 // Store the new element. This may be larger than the vector element type,
1005 // so use a truncating store.
1006 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
1007 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
1008 unsigned Alignment = DAG.getDataLayout().getPrefTypeAlignment(VecType);
1010 DAG.getTruncStore(Store, dl, Elt, EltPtr, MachinePointerInfo(), EltVT);
1012 // Load the Lo part from the stack slot.
1014 DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo());
1016 // Increment the pointer to the other part.
1017 unsigned IncrementSize = Lo.getValueSizeInBits() / 8;
1018 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
1019 DAG.getConstant(IncrementSize, dl,
1020 StackPtr.getValueType()));
1022 // Load the Hi part from the stack slot.
1023 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
1024 MinAlign(Alignment, IncrementSize));
1027 void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
1031 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1032 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
1033 Hi = DAG.getUNDEF(HiVT);
1036 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
1038 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
1041 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(LD->getValueType(0));
1043 ISD::LoadExtType ExtType = LD->getExtensionType();
1044 SDValue Ch = LD->getChain();
1045 SDValue Ptr = LD->getBasePtr();
1046 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
1047 EVT MemoryVT = LD->getMemoryVT();
1048 unsigned Alignment = LD->getOriginalAlignment();
1049 MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
1050 AAMDNodes AAInfo = LD->getAAInfo();
1052 EVT LoMemVT, HiMemVT;
1053 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1055 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
1056 LD->getPointerInfo(), LoMemVT, Alignment, MMOFlags, AAInfo);
1058 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1059 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1060 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
1061 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset,
1062 LD->getPointerInfo().getWithOffset(IncrementSize), HiMemVT,
1063 Alignment, MMOFlags, AAInfo);
1065 // Build a factor node to remember that this load is independent of the
1067 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1070 // Legalize the chain result - switch anything that used the old chain to
1072 ReplaceValueWith(SDValue(LD, 1), Ch);
1075 void DAGTypeLegalizer::SplitVecRes_MLOAD(MaskedLoadSDNode *MLD,
1076 SDValue &Lo, SDValue &Hi) {
1079 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MLD->getValueType(0));
1081 SDValue Ch = MLD->getChain();
1082 SDValue Ptr = MLD->getBasePtr();
1083 SDValue Mask = MLD->getMask();
1084 SDValue Src0 = MLD->getSrc0();
1085 unsigned Alignment = MLD->getOriginalAlignment();
1086 ISD::LoadExtType ExtType = MLD->getExtensionType();
1088 // if Alignment is equal to the vector size,
1089 // take the half of it for the second part
1090 unsigned SecondHalfAlignment =
1091 (Alignment == MLD->getValueType(0).getSizeInBits()/8) ?
1092 Alignment/2 : Alignment;
1094 // Split Mask operand
1095 SDValue MaskLo, MaskHi;
1096 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
1097 GetSplitVector(Mask, MaskLo, MaskHi);
1099 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1101 EVT MemoryVT = MLD->getMemoryVT();
1102 EVT LoMemVT, HiMemVT;
1103 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1105 SDValue Src0Lo, Src0Hi;
1106 if (getTypeAction(Src0.getValueType()) == TargetLowering::TypeSplitVector)
1107 GetSplitVector(Src0, Src0Lo, Src0Hi);
1109 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, dl);
1111 MachineMemOperand *MMO = DAG.getMachineFunction().
1112 getMachineMemOperand(MLD->getPointerInfo(),
1113 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1114 Alignment, MLD->getAAInfo(), MLD->getRanges());
1116 Lo = DAG.getMaskedLoad(LoVT, dl, Ch, Ptr, MaskLo, Src0Lo, LoMemVT, MMO,
1117 ExtType, MLD->isExpandingLoad());
1119 Ptr = TLI.IncrementMemoryAddress(Ptr, MaskLo, dl, LoMemVT, DAG,
1120 MLD->isExpandingLoad());
1122 MMO = DAG.getMachineFunction().
1123 getMachineMemOperand(MLD->getPointerInfo(),
1124 MachineMemOperand::MOLoad, HiMemVT.getStoreSize(),
1125 SecondHalfAlignment, MLD->getAAInfo(), MLD->getRanges());
1127 Hi = DAG.getMaskedLoad(HiVT, dl, Ch, Ptr, MaskHi, Src0Hi, HiMemVT, MMO,
1128 ExtType, MLD->isExpandingLoad());
1131 // Build a factor node to remember that this load is independent of the
1133 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1136 // Legalize the chain result - switch anything that used the old chain to
1138 ReplaceValueWith(SDValue(MLD, 1), Ch);
1142 void DAGTypeLegalizer::SplitVecRes_MGATHER(MaskedGatherSDNode *MGT,
1143 SDValue &Lo, SDValue &Hi) {
1146 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MGT->getValueType(0));
1148 SDValue Ch = MGT->getChain();
1149 SDValue Ptr = MGT->getBasePtr();
1150 SDValue Mask = MGT->getMask();
1151 SDValue Src0 = MGT->getValue();
1152 SDValue Index = MGT->getIndex();
1153 unsigned Alignment = MGT->getOriginalAlignment();
1155 // Split Mask operand
1156 SDValue MaskLo, MaskHi;
1157 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
1158 GetSplitVector(Mask, MaskLo, MaskHi);
1160 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1162 EVT MemoryVT = MGT->getMemoryVT();
1163 EVT LoMemVT, HiMemVT;
1165 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1167 SDValue Src0Lo, Src0Hi;
1168 if (getTypeAction(Src0.getValueType()) == TargetLowering::TypeSplitVector)
1169 GetSplitVector(Src0, Src0Lo, Src0Hi);
1171 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, dl);
1173 SDValue IndexHi, IndexLo;
1174 if (getTypeAction(Index.getValueType()) == TargetLowering::TypeSplitVector)
1175 GetSplitVector(Index, IndexLo, IndexHi);
1177 std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, dl);
1179 MachineMemOperand *MMO = DAG.getMachineFunction().
1180 getMachineMemOperand(MGT->getPointerInfo(),
1181 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1182 Alignment, MGT->getAAInfo(), MGT->getRanges());
1184 SDValue OpsLo[] = {Ch, Src0Lo, MaskLo, Ptr, IndexLo};
1185 Lo = DAG.getMaskedGather(DAG.getVTList(LoVT, MVT::Other), LoVT, dl, OpsLo,
1188 SDValue OpsHi[] = {Ch, Src0Hi, MaskHi, Ptr, IndexHi};
1189 Hi = DAG.getMaskedGather(DAG.getVTList(HiVT, MVT::Other), HiVT, dl, OpsHi,
1192 // Build a factor node to remember that this load is independent of the
1194 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1197 // Legalize the chain result - switch anything that used the old chain to
1199 ReplaceValueWith(SDValue(MGT, 1), Ch);
1203 void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
1204 assert(N->getValueType(0).isVector() &&
1205 N->getOperand(0).getValueType().isVector() &&
1206 "Operand types must be vectors");
1210 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1213 SDValue LL, LH, RL, RH;
1214 std::tie(LL, LH) = DAG.SplitVectorOperand(N, 0);
1215 std::tie(RL, RH) = DAG.SplitVectorOperand(N, 1);
1217 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
1218 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
1221 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
1223 // Get the dest types - they may not match the input types, e.g. int_to_fp.
1226 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1228 // If the input also splits, handle it directly for a compile time speedup.
1229 // Otherwise split it by hand.
1230 EVT InVT = N->getOperand(0).getValueType();
1231 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector)
1232 GetSplitVector(N->getOperand(0), Lo, Hi);
1234 std::tie(Lo, Hi) = DAG.SplitVectorOperand(N, 0);
1236 if (N->getOpcode() == ISD::FP_ROUND) {
1237 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1));
1238 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1));
1239 } else if (N->getOpcode() == ISD::CONVERT_RNDSAT) {
1240 SDValue DTyOpLo = DAG.getValueType(LoVT);
1241 SDValue DTyOpHi = DAG.getValueType(HiVT);
1242 SDValue STyOpLo = DAG.getValueType(Lo.getValueType());
1243 SDValue STyOpHi = DAG.getValueType(Hi.getValueType());
1244 SDValue RndOp = N->getOperand(3);
1245 SDValue SatOp = N->getOperand(4);
1246 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1247 Lo = DAG.getConvertRndSat(LoVT, dl, Lo, DTyOpLo, STyOpLo, RndOp, SatOp,
1249 Hi = DAG.getConvertRndSat(HiVT, dl, Hi, DTyOpHi, STyOpHi, RndOp, SatOp,
1252 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
1253 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
1257 void DAGTypeLegalizer::SplitVecRes_ExtendOp(SDNode *N, SDValue &Lo,
1260 EVT SrcVT = N->getOperand(0).getValueType();
1261 EVT DestVT = N->getValueType(0);
1263 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(DestVT);
1265 // We can do better than a generic split operation if the extend is doing
1266 // more than just doubling the width of the elements and the following are
1268 // - The number of vector elements is even,
1269 // - the source type is legal,
1270 // - the type of a split source is illegal,
1271 // - the type of an extended (by doubling element size) source is legal, and
1272 // - the type of that extended source when split is legal.
1274 // This won't necessarily completely legalize the operation, but it will
1275 // more effectively move in the right direction and prevent falling down
1276 // to scalarization in many cases due to the input vector being split too
1278 unsigned NumElements = SrcVT.getVectorNumElements();
1279 if ((NumElements & 1) == 0 &&
1280 SrcVT.getSizeInBits() * 2 < DestVT.getSizeInBits()) {
1281 LLVMContext &Ctx = *DAG.getContext();
1282 EVT NewSrcVT = EVT::getVectorVT(
1283 Ctx, EVT::getIntegerVT(
1284 Ctx, SrcVT.getScalarSizeInBits() * 2),
1287 EVT::getVectorVT(Ctx, SrcVT.getVectorElementType(), NumElements / 2);
1288 EVT SplitLoVT, SplitHiVT;
1289 std::tie(SplitLoVT, SplitHiVT) = DAG.GetSplitDestVTs(NewSrcVT);
1290 if (TLI.isTypeLegal(SrcVT) && !TLI.isTypeLegal(SplitSrcVT) &&
1291 TLI.isTypeLegal(NewSrcVT) && TLI.isTypeLegal(SplitLoVT)) {
1292 DEBUG(dbgs() << "Split vector extend via incremental extend:";
1293 N->dump(&DAG); dbgs() << "\n");
1294 // Extend the source vector by one step.
1296 DAG.getNode(N->getOpcode(), dl, NewSrcVT, N->getOperand(0));
1297 // Get the low and high halves of the new, extended one step, vector.
1298 std::tie(Lo, Hi) = DAG.SplitVector(NewSrc, dl);
1299 // Extend those vector halves the rest of the way.
1300 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
1301 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
1305 // Fall back to the generic unary operator splitting otherwise.
1306 SplitVecRes_UnaryOp(N, Lo, Hi);
1309 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
1310 SDValue &Lo, SDValue &Hi) {
1311 // The low and high parts of the original input give four input vectors.
1314 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
1315 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
1316 EVT NewVT = Inputs[0].getValueType();
1317 unsigned NewElts = NewVT.getVectorNumElements();
1319 // If Lo or Hi uses elements from at most two of the four input vectors, then
1320 // express it as a vector shuffle of those two inputs. Otherwise extract the
1321 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
1322 SmallVector<int, 16> Ops;
1323 for (unsigned High = 0; High < 2; ++High) {
1324 SDValue &Output = High ? Hi : Lo;
1326 // Build a shuffle mask for the output, discovering on the fly which
1327 // input vectors to use as shuffle operands (recorded in InputUsed).
1328 // If building a suitable shuffle vector proves too hard, then bail
1329 // out with useBuildVector set.
1330 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
1331 unsigned FirstMaskIdx = High * NewElts;
1332 bool useBuildVector = false;
1333 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1334 // The mask element. This indexes into the input.
1335 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
1337 // The input vector this mask element indexes into.
1338 unsigned Input = (unsigned)Idx / NewElts;
1340 if (Input >= array_lengthof(Inputs)) {
1341 // The mask element does not index into any input vector.
1346 // Turn the index into an offset from the start of the input vector.
1347 Idx -= Input * NewElts;
1349 // Find or create a shuffle vector operand to hold this input.
1351 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
1352 if (InputUsed[OpNo] == Input) {
1353 // This input vector is already an operand.
1355 } else if (InputUsed[OpNo] == -1U) {
1356 // Create a new operand for this input vector.
1357 InputUsed[OpNo] = Input;
1362 if (OpNo >= array_lengthof(InputUsed)) {
1363 // More than two input vectors used! Give up on trying to create a
1364 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
1365 useBuildVector = true;
1369 // Add the mask index for the new shuffle vector.
1370 Ops.push_back(Idx + OpNo * NewElts);
1373 if (useBuildVector) {
1374 EVT EltVT = NewVT.getVectorElementType();
1375 SmallVector<SDValue, 16> SVOps;
1377 // Extract the input elements by hand.
1378 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1379 // The mask element. This indexes into the input.
1380 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
1382 // The input vector this mask element indexes into.
1383 unsigned Input = (unsigned)Idx / NewElts;
1385 if (Input >= array_lengthof(Inputs)) {
1386 // The mask element is "undef" or indexes off the end of the input.
1387 SVOps.push_back(DAG.getUNDEF(EltVT));
1391 // Turn the index into an offset from the start of the input vector.
1392 Idx -= Input * NewElts;
1394 // Extract the vector element by hand.
1395 SVOps.push_back(DAG.getNode(
1396 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Inputs[Input],
1397 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout()))));
1400 // Construct the Lo/Hi output using a BUILD_VECTOR.
1401 Output = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, SVOps);
1402 } else if (InputUsed[0] == -1U) {
1403 // No input vectors were used! The result is undefined.
1404 Output = DAG.getUNDEF(NewVT);
1406 SDValue Op0 = Inputs[InputUsed[0]];
1407 // If only one input was used, use an undefined vector for the other.
1408 SDValue Op1 = InputUsed[1] == -1U ?
1409 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];
1410 // At least one input vector was used. Create a new shuffle vector.
1411 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, Ops);
1419 //===----------------------------------------------------------------------===//
1420 // Operand Vector Splitting
1421 //===----------------------------------------------------------------------===//
1423 /// This method is called when the specified operand of the specified node is
1424 /// found to need vector splitting. At this point, all of the result types of
1425 /// the node are known to be legal, but other operands of the node may need
1426 /// legalization as well as the specified one.
1427 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
1428 DEBUG(dbgs() << "Split node operand: ";
1431 SDValue Res = SDValue();
1433 // See if the target wants to custom split this node.
1434 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
1437 if (!Res.getNode()) {
1438 switch (N->getOpcode()) {
1441 dbgs() << "SplitVectorOperand Op #" << OpNo << ": ";
1445 report_fatal_error("Do not know how to split this operator's "
1448 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break;
1449 case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break;
1450 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
1451 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
1452 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break;
1454 Res = SplitVecOp_TruncateHelper(N);
1456 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break;
1457 case ISD::FCOPYSIGN: Res = SplitVecOp_FCOPYSIGN(N); break;
1459 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo);
1462 Res = SplitVecOp_MSTORE(cast<MaskedStoreSDNode>(N), OpNo);
1465 Res = SplitVecOp_MSCATTER(cast<MaskedScatterSDNode>(N), OpNo);
1468 Res = SplitVecOp_MGATHER(cast<MaskedGatherSDNode>(N), OpNo);
1471 Res = SplitVecOp_VSELECT(N, OpNo);
1473 case ISD::FP_TO_SINT:
1474 case ISD::FP_TO_UINT:
1475 if (N->getValueType(0).bitsLT(N->getOperand(0)->getValueType(0)))
1476 Res = SplitVecOp_TruncateHelper(N);
1478 Res = SplitVecOp_UnaryOp(N);
1480 case ISD::SINT_TO_FP:
1481 case ISD::UINT_TO_FP:
1482 if (N->getValueType(0).bitsLT(N->getOperand(0)->getValueType(0)))
1483 Res = SplitVecOp_TruncateHelper(N);
1485 Res = SplitVecOp_UnaryOp(N);
1490 case ISD::FP_EXTEND:
1491 case ISD::SIGN_EXTEND:
1492 case ISD::ZERO_EXTEND:
1493 case ISD::ANY_EXTEND:
1495 Res = SplitVecOp_UnaryOp(N);
1500 // If the result is null, the sub-method took care of registering results etc.
1501 if (!Res.getNode()) return false;
1503 // If the result is N, the sub-method updated N in place. Tell the legalizer
1505 if (Res.getNode() == N)
1508 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1509 "Invalid operand expansion");
1511 ReplaceValueWith(SDValue(N, 0), Res);
1515 SDValue DAGTypeLegalizer::SplitVecOp_VSELECT(SDNode *N, unsigned OpNo) {
1516 // The only possibility for an illegal operand is the mask, since result type
1517 // legalization would have handled this node already otherwise.
1518 assert(OpNo == 0 && "Illegal operand must be mask");
1520 SDValue Mask = N->getOperand(0);
1521 SDValue Src0 = N->getOperand(1);
1522 SDValue Src1 = N->getOperand(2);
1523 EVT Src0VT = Src0.getValueType();
1525 assert(Mask.getValueType().isVector() && "VSELECT without a vector mask?");
1528 GetSplitVector(N->getOperand(0), Lo, Hi);
1529 assert(Lo.getValueType() == Hi.getValueType() &&
1530 "Lo and Hi have differing types");
1533 std::tie(LoOpVT, HiOpVT) = DAG.GetSplitDestVTs(Src0VT);
1534 assert(LoOpVT == HiOpVT && "Asymmetric vector split?");
1536 SDValue LoOp0, HiOp0, LoOp1, HiOp1, LoMask, HiMask;
1537 std::tie(LoOp0, HiOp0) = DAG.SplitVector(Src0, DL);
1538 std::tie(LoOp1, HiOp1) = DAG.SplitVector(Src1, DL);
1539 std::tie(LoMask, HiMask) = DAG.SplitVector(Mask, DL);
1542 DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1);
1544 DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1);
1546 return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect);
1549 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
1550 // The result has a legal vector type, but the input needs splitting.
1551 EVT ResVT = N->getValueType(0);
1554 GetSplitVector(N->getOperand(0), Lo, Hi);
1555 EVT InVT = Lo.getValueType();
1557 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1558 InVT.getVectorNumElements());
1560 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
1561 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi);
1563 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
1566 SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) {
1567 // For example, i64 = BITCAST v4i16 on alpha. Typically the vector will
1568 // end up being split all the way down to individual components. Convert the
1569 // split pieces into integers and reassemble.
1571 GetSplitVector(N->getOperand(0), Lo, Hi);
1572 Lo = BitConvertToInteger(Lo);
1573 Hi = BitConvertToInteger(Hi);
1575 if (DAG.getDataLayout().isBigEndian())
1578 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0),
1579 JoinIntegers(Lo, Hi));
1582 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
1583 // We know that the extracted result type is legal.
1584 EVT SubVT = N->getValueType(0);
1585 SDValue Idx = N->getOperand(1);
1588 GetSplitVector(N->getOperand(0), Lo, Hi);
1590 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1591 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1593 if (IdxVal < LoElts) {
1594 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
1595 "Extracted subvector crosses vector split!");
1596 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
1598 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
1599 DAG.getConstant(IdxVal - LoElts, dl,
1600 Idx.getValueType()));
1604 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
1605 SDValue Vec = N->getOperand(0);
1606 SDValue Idx = N->getOperand(1);
1607 EVT VecVT = Vec.getValueType();
1609 if (isa<ConstantSDNode>(Idx)) {
1610 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1611 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
1614 GetSplitVector(Vec, Lo, Hi);
1616 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1618 if (IdxVal < LoElts)
1619 return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0);
1620 return SDValue(DAG.UpdateNodeOperands(N, Hi,
1621 DAG.getConstant(IdxVal - LoElts, SDLoc(N),
1622 Idx.getValueType())), 0);
1625 // See if the target wants to custom expand this node.
1626 if (CustomLowerNode(N, N->getValueType(0), true))
1629 // Make the vector elements byte-addressable if they aren't already.
1631 EVT EltVT = VecVT.getVectorElementType();
1632 if (EltVT.getSizeInBits() < 8) {
1633 SmallVector<SDValue, 4> ElementOps;
1634 for (unsigned i = 0; i < VecVT.getVectorNumElements(); ++i) {
1635 ElementOps.push_back(DAG.getAnyExtOrTrunc(
1636 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Vec,
1637 DAG.getConstant(i, dl, MVT::i8)),
1642 VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT,
1643 VecVT.getVectorNumElements());
1644 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, ElementOps);
1647 // Store the vector to the stack.
1648 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1650 DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, MachinePointerInfo());
1652 // Load back the required element.
1653 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
1654 return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,
1655 MachinePointerInfo(), EltVT);
1658 SDValue DAGTypeLegalizer::SplitVecOp_MGATHER(MaskedGatherSDNode *MGT,
1662 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MGT->getValueType(0));
1664 SDValue Ch = MGT->getChain();
1665 SDValue Ptr = MGT->getBasePtr();
1666 SDValue Index = MGT->getIndex();
1667 SDValue Mask = MGT->getMask();
1668 SDValue Src0 = MGT->getValue();
1669 unsigned Alignment = MGT->getOriginalAlignment();
1671 SDValue MaskLo, MaskHi;
1672 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
1673 // Split Mask operand
1674 GetSplitVector(Mask, MaskLo, MaskHi);
1676 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1678 EVT MemoryVT = MGT->getMemoryVT();
1679 EVT LoMemVT, HiMemVT;
1680 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1682 SDValue Src0Lo, Src0Hi;
1683 if (getTypeAction(Src0.getValueType()) == TargetLowering::TypeSplitVector)
1684 GetSplitVector(Src0, Src0Lo, Src0Hi);
1686 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, dl);
1688 SDValue IndexHi, IndexLo;
1689 if (getTypeAction(Index.getValueType()) == TargetLowering::TypeSplitVector)
1690 GetSplitVector(Index, IndexLo, IndexHi);
1692 std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, dl);
1694 MachineMemOperand *MMO = DAG.getMachineFunction().
1695 getMachineMemOperand(MGT->getPointerInfo(),
1696 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1697 Alignment, MGT->getAAInfo(), MGT->getRanges());
1699 SDValue OpsLo[] = {Ch, Src0Lo, MaskLo, Ptr, IndexLo};
1700 SDValue Lo = DAG.getMaskedGather(DAG.getVTList(LoVT, MVT::Other), LoVT, dl,
1703 MMO = DAG.getMachineFunction().
1704 getMachineMemOperand(MGT->getPointerInfo(),
1705 MachineMemOperand::MOLoad, HiMemVT.getStoreSize(),
1706 Alignment, MGT->getAAInfo(),
1709 SDValue OpsHi[] = {Ch, Src0Hi, MaskHi, Ptr, IndexHi};
1710 SDValue Hi = DAG.getMaskedGather(DAG.getVTList(HiVT, MVT::Other), HiVT, dl,
1713 // Build a factor node to remember that this load is independent of the
1715 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1718 // Legalize the chain result - switch anything that used the old chain to
1720 ReplaceValueWith(SDValue(MGT, 1), Ch);
1722 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, dl, MGT->getValueType(0), Lo,
1724 ReplaceValueWith(SDValue(MGT, 0), Res);
1728 SDValue DAGTypeLegalizer::SplitVecOp_MSTORE(MaskedStoreSDNode *N,
1730 SDValue Ch = N->getChain();
1731 SDValue Ptr = N->getBasePtr();
1732 SDValue Mask = N->getMask();
1733 SDValue Data = N->getValue();
1734 EVT MemoryVT = N->getMemoryVT();
1735 unsigned Alignment = N->getOriginalAlignment();
1738 EVT LoMemVT, HiMemVT;
1739 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1741 SDValue DataLo, DataHi;
1742 if (getTypeAction(Data.getValueType()) == TargetLowering::TypeSplitVector)
1743 // Split Data operand
1744 GetSplitVector(Data, DataLo, DataHi);
1746 std::tie(DataLo, DataHi) = DAG.SplitVector(Data, DL);
1748 SDValue MaskLo, MaskHi;
1749 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
1750 // Split Mask operand
1751 GetSplitVector(Mask, MaskLo, MaskHi);
1753 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, DL);
1755 MaskLo = PromoteTargetBoolean(MaskLo, DataLo.getValueType());
1756 MaskHi = PromoteTargetBoolean(MaskHi, DataHi.getValueType());
1758 // if Alignment is equal to the vector size,
1759 // take the half of it for the second part
1760 unsigned SecondHalfAlignment =
1761 (Alignment == Data->getValueType(0).getSizeInBits()/8) ?
1762 Alignment/2 : Alignment;
1765 MachineMemOperand *MMO = DAG.getMachineFunction().
1766 getMachineMemOperand(N->getPointerInfo(),
1767 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
1768 Alignment, N->getAAInfo(), N->getRanges());
1770 Lo = DAG.getMaskedStore(Ch, DL, DataLo, Ptr, MaskLo, LoMemVT, MMO,
1771 N->isTruncatingStore(),
1772 N->isCompressingStore());
1774 Ptr = TLI.IncrementMemoryAddress(Ptr, MaskLo, DL, LoMemVT, DAG,
1775 N->isCompressingStore());
1776 MMO = DAG.getMachineFunction().
1777 getMachineMemOperand(N->getPointerInfo(),
1778 MachineMemOperand::MOStore, HiMemVT.getStoreSize(),
1779 SecondHalfAlignment, N->getAAInfo(), N->getRanges());
1781 Hi = DAG.getMaskedStore(Ch, DL, DataHi, Ptr, MaskHi, HiMemVT, MMO,
1782 N->isTruncatingStore(), N->isCompressingStore());
1784 // Build a factor node to remember that this store is independent of the
1786 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1789 SDValue DAGTypeLegalizer::SplitVecOp_MSCATTER(MaskedScatterSDNode *N,
1791 SDValue Ch = N->getChain();
1792 SDValue Ptr = N->getBasePtr();
1793 SDValue Mask = N->getMask();
1794 SDValue Index = N->getIndex();
1795 SDValue Data = N->getValue();
1796 EVT MemoryVT = N->getMemoryVT();
1797 unsigned Alignment = N->getOriginalAlignment();
1800 // Split all operands
1801 EVT LoMemVT, HiMemVT;
1802 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1804 SDValue DataLo, DataHi;
1805 if (getTypeAction(Data.getValueType()) == TargetLowering::TypeSplitVector)
1806 // Split Data operand
1807 GetSplitVector(Data, DataLo, DataHi);
1809 std::tie(DataLo, DataHi) = DAG.SplitVector(Data, DL);
1811 SDValue MaskLo, MaskHi;
1812 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
1813 // Split Mask operand
1814 GetSplitVector(Mask, MaskLo, MaskHi);
1816 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, DL);
1818 SDValue IndexHi, IndexLo;
1819 if (getTypeAction(Index.getValueType()) == TargetLowering::TypeSplitVector)
1820 GetSplitVector(Index, IndexLo, IndexHi);
1822 std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, DL);
1825 MachineMemOperand *MMO = DAG.getMachineFunction().
1826 getMachineMemOperand(N->getPointerInfo(),
1827 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
1828 Alignment, N->getAAInfo(), N->getRanges());
1830 SDValue OpsLo[] = {Ch, DataLo, MaskLo, Ptr, IndexLo};
1831 Lo = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataLo.getValueType(),
1834 MMO = DAG.getMachineFunction().
1835 getMachineMemOperand(N->getPointerInfo(),
1836 MachineMemOperand::MOStore, HiMemVT.getStoreSize(),
1837 Alignment, N->getAAInfo(), N->getRanges());
1839 SDValue OpsHi[] = {Ch, DataHi, MaskHi, Ptr, IndexHi};
1840 Hi = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataHi.getValueType(),
1843 // Build a factor node to remember that this store is independent of the
1845 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1848 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
1849 assert(N->isUnindexed() && "Indexed store of vector?");
1850 assert(OpNo == 1 && "Can only split the stored value");
1853 bool isTruncating = N->isTruncatingStore();
1854 SDValue Ch = N->getChain();
1855 SDValue Ptr = N->getBasePtr();
1856 EVT MemoryVT = N->getMemoryVT();
1857 unsigned Alignment = N->getOriginalAlignment();
1858 MachineMemOperand::Flags MMOFlags = N->getMemOperand()->getFlags();
1859 AAMDNodes AAInfo = N->getAAInfo();
1861 GetSplitVector(N->getOperand(1), Lo, Hi);
1863 EVT LoMemVT, HiMemVT;
1864 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1866 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1869 Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(), LoMemVT,
1870 Alignment, MMOFlags, AAInfo);
1872 Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(), Alignment, MMOFlags,
1875 // Increment the pointer to the other half.
1876 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1877 DAG.getConstant(IncrementSize, DL, Ptr.getValueType()));
1880 Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr,
1881 N->getPointerInfo().getWithOffset(IncrementSize),
1882 HiMemVT, Alignment, MMOFlags, AAInfo);
1884 Hi = DAG.getStore(Ch, DL, Hi, Ptr,
1885 N->getPointerInfo().getWithOffset(IncrementSize),
1886 Alignment, MMOFlags, AAInfo);
1888 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1891 SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) {
1894 // The input operands all must have the same type, and we know the result
1895 // type is valid. Convert this to a buildvector which extracts all the
1897 // TODO: If the input elements are power-two vectors, we could convert this to
1898 // a new CONCAT_VECTORS node with elements that are half-wide.
1899 SmallVector<SDValue, 32> Elts;
1900 EVT EltVT = N->getValueType(0).getVectorElementType();
1901 for (const SDValue &Op : N->op_values()) {
1902 for (unsigned i = 0, e = Op.getValueType().getVectorNumElements();
1904 Elts.push_back(DAG.getNode(
1905 ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Op,
1906 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))));
1910 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0), Elts);
1913 SDValue DAGTypeLegalizer::SplitVecOp_TruncateHelper(SDNode *N) {
1914 // The result type is legal, but the input type is illegal. If splitting
1915 // ends up with the result type of each half still being legal, just
1916 // do that. If, however, that would result in an illegal result type,
1917 // we can try to get more clever with power-two vectors. Specifically,
1918 // split the input type, but also widen the result element size, then
1919 // concatenate the halves and truncate again. For example, consider a target
1920 // where v8i8 is legal and v8i32 is not (ARM, which doesn't have 256-bit
1921 // vectors). To perform a "%res = v8i8 trunc v8i32 %in" we do:
1922 // %inlo = v4i32 extract_subvector %in, 0
1923 // %inhi = v4i32 extract_subvector %in, 4
1924 // %lo16 = v4i16 trunc v4i32 %inlo
1925 // %hi16 = v4i16 trunc v4i32 %inhi
1926 // %in16 = v8i16 concat_vectors v4i16 %lo16, v4i16 %hi16
1927 // %res = v8i8 trunc v8i16 %in16
1929 // Without this transform, the original truncate would end up being
1930 // scalarized, which is pretty much always a last resort.
1931 SDValue InVec = N->getOperand(0);
1932 EVT InVT = InVec->getValueType(0);
1933 EVT OutVT = N->getValueType(0);
1934 unsigned NumElements = OutVT.getVectorNumElements();
1935 bool IsFloat = OutVT.isFloatingPoint();
1937 // Widening should have already made sure this is a power-two vector
1938 // if we're trying to split it at all. assert() that's true, just in case.
1939 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
1941 unsigned InElementSize = InVT.getScalarSizeInBits();
1942 unsigned OutElementSize = OutVT.getScalarSizeInBits();
1944 // If the input elements are only 1/2 the width of the result elements,
1945 // just use the normal splitting. Our trick only work if there's room
1946 // to split more than once.
1947 if (InElementSize <= OutElementSize * 2)
1948 return SplitVecOp_UnaryOp(N);
1951 // Extract the halves of the input via extract_subvector.
1952 SDValue InLoVec, InHiVec;
1953 std::tie(InLoVec, InHiVec) = DAG.SplitVector(InVec, DL);
1954 // Truncate them to 1/2 the element size.
1955 EVT HalfElementVT = IsFloat ?
1956 EVT::getFloatingPointVT(InElementSize/2) :
1957 EVT::getIntegerVT(*DAG.getContext(), InElementSize/2);
1958 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT,
1960 SDValue HalfLo = DAG.getNode(N->getOpcode(), DL, HalfVT, InLoVec);
1961 SDValue HalfHi = DAG.getNode(N->getOpcode(), DL, HalfVT, InHiVec);
1962 // Concatenate them to get the full intermediate truncation result.
1963 EVT InterVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT, NumElements);
1964 SDValue InterVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InterVT, HalfLo,
1966 // Now finish up by truncating all the way down to the original result
1967 // type. This should normally be something that ends up being legal directly,
1968 // but in theory if a target has very wide vectors and an annoyingly
1969 // restricted set of legal types, this split can chain to build things up.
1971 ? DAG.getNode(ISD::FP_ROUND, DL, OutVT, InterVec,
1972 DAG.getTargetConstant(
1973 0, DL, TLI.getPointerTy(DAG.getDataLayout())))
1974 : DAG.getNode(ISD::TRUNCATE, DL, OutVT, InterVec);
1977 SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
1978 assert(N->getValueType(0).isVector() &&
1979 N->getOperand(0).getValueType().isVector() &&
1980 "Operand types must be vectors");
1981 // The result has a legal vector type, but the input needs splitting.
1982 SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes;
1984 GetSplitVector(N->getOperand(0), Lo0, Hi0);
1985 GetSplitVector(N->getOperand(1), Lo1, Hi1);
1986 unsigned PartElements = Lo0.getValueType().getVectorNumElements();
1987 EVT PartResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, PartElements);
1988 EVT WideResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, 2*PartElements);
1990 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
1991 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
1992 SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes);
1993 return PromoteTargetBoolean(Con, N->getValueType(0));
1997 SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) {
1998 // The result has a legal vector type, but the input needs splitting.
1999 EVT ResVT = N->getValueType(0);
2002 GetSplitVector(N->getOperand(0), Lo, Hi);
2003 EVT InVT = Lo.getValueType();
2005 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
2006 InVT.getVectorNumElements());
2008 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1));
2009 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1));
2011 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
2014 SDValue DAGTypeLegalizer::SplitVecOp_FCOPYSIGN(SDNode *N) {
2015 // The result (and the first input) has a legal vector type, but the second
2016 // input needs splitting.
2017 return DAG.UnrollVectorOp(N, N->getValueType(0).getVectorNumElements());
2021 //===----------------------------------------------------------------------===//
2022 // Result Vector Widening
2023 //===----------------------------------------------------------------------===//
2025 void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
2026 DEBUG(dbgs() << "Widen node result " << ResNo << ": ";
2030 // See if the target wants to custom widen this node.
2031 if (CustomWidenLowerNode(N, N->getValueType(ResNo)))
2034 SDValue Res = SDValue();
2035 switch (N->getOpcode()) {
2038 dbgs() << "WidenVectorResult #" << ResNo << ": ";
2042 llvm_unreachable("Do not know how to widen the result of this operator!");
2044 case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break;
2045 case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break;
2046 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
2047 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
2048 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break;
2049 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
2050 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break;
2051 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
2052 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
2053 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
2054 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;
2056 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
2057 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
2058 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
2059 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
2060 case ISD::VECTOR_SHUFFLE:
2061 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
2064 Res = WidenVecRes_MLOAD(cast<MaskedLoadSDNode>(N));
2067 Res = WidenVecRes_MGATHER(cast<MaskedGatherSDNode>(N));
2086 Res = WidenVecRes_Binary(N);
2099 Res = WidenVecRes_BinaryCanTrap(N);
2102 case ISD::FCOPYSIGN:
2103 Res = WidenVecRes_FCOPYSIGN(N);
2107 Res = WidenVecRes_POWI(N);
2113 Res = WidenVecRes_Shift(N);
2116 case ISD::ANY_EXTEND_VECTOR_INREG:
2117 case ISD::SIGN_EXTEND_VECTOR_INREG:
2118 case ISD::ZERO_EXTEND_VECTOR_INREG:
2119 Res = WidenVecRes_EXTEND_VECTOR_INREG(N);
2122 case ISD::ANY_EXTEND:
2123 case ISD::FP_EXTEND:
2125 case ISD::FP_TO_SINT:
2126 case ISD::FP_TO_UINT:
2127 case ISD::SIGN_EXTEND:
2128 case ISD::SINT_TO_FP:
2130 case ISD::UINT_TO_FP:
2131 case ISD::ZERO_EXTEND:
2132 Res = WidenVecRes_Convert(N);
2135 case ISD::BITREVERSE:
2149 case ISD::FNEARBYINT:
2156 Res = WidenVecRes_Unary(N);
2159 Res = WidenVecRes_Ternary(N);
2163 // If Res is null, the sub-method took care of registering the result.
2165 SetWidenedVector(SDValue(N, ResNo), Res);
2168 SDValue DAGTypeLegalizer::WidenVecRes_Ternary(SDNode *N) {
2169 // Ternary op widening.
2171 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2172 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2173 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2174 SDValue InOp3 = GetWidenedVector(N->getOperand(2));
2175 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, InOp3);
2178 SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
2179 // Binary op widening.
2181 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2182 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2183 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2184 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, N->getFlags());
2187 SDValue DAGTypeLegalizer::WidenVecRes_BinaryCanTrap(SDNode *N) {
2188 // Binary op widening for operations that can trap.
2189 unsigned Opcode = N->getOpcode();
2191 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2192 EVT WidenEltVT = WidenVT.getVectorElementType();
2194 unsigned NumElts = VT.getVectorNumElements();
2195 const SDNodeFlags *Flags = N->getFlags();
2196 while (!TLI.isTypeLegal(VT) && NumElts != 1) {
2197 NumElts = NumElts / 2;
2198 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
2201 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) {
2202 // Operation doesn't trap so just widen as normal.
2203 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2204 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2205 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, Flags);
2208 // No legal vector version so unroll the vector operation and then widen.
2210 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
2212 // Since the operation can trap, apply operation on the original vector.
2214 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2215 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2216 unsigned CurNumElts = N->getValueType(0).getVectorNumElements();
2218 SmallVector<SDValue, 16> ConcatOps(CurNumElts);
2219 unsigned ConcatEnd = 0; // Current ConcatOps index.
2220 int Idx = 0; // Current Idx into input vectors.
2222 // NumElts := greatest legal vector size (at most WidenVT)
2223 // while (orig. vector has unhandled elements) {
2224 // take munches of size NumElts from the beginning and add to ConcatOps
2225 // NumElts := next smaller supported vector size or 1
2227 while (CurNumElts != 0) {
2228 while (CurNumElts >= NumElts) {
2229 SDValue EOp1 = DAG.getNode(
2230 ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1,
2231 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2232 SDValue EOp2 = DAG.getNode(
2233 ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2,
2234 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2235 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2, Flags);
2237 CurNumElts -= NumElts;
2240 NumElts = NumElts / 2;
2241 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
2242 } while (!TLI.isTypeLegal(VT) && NumElts != 1);
2245 for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) {
2246 SDValue EOp1 = DAG.getNode(
2247 ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, InOp1,
2248 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2249 SDValue EOp2 = DAG.getNode(
2250 ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, InOp2,
2251 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2252 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT,
2259 // Check to see if we have a single operation with the widen type.
2260 if (ConcatEnd == 1) {
2261 VT = ConcatOps[0].getValueType();
2263 return ConcatOps[0];
2266 // while (Some element of ConcatOps is not of type MaxVT) {
2267 // From the end of ConcatOps, collect elements of the same type and put
2268 // them into an op of the next larger supported type
2270 while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) {
2271 Idx = ConcatEnd - 1;
2272 VT = ConcatOps[Idx--].getValueType();
2273 while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT)
2276 int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1;
2280 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize);
2281 } while (!TLI.isTypeLegal(NextVT));
2283 if (!VT.isVector()) {
2284 // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT
2285 SDValue VecOp = DAG.getUNDEF(NextVT);
2286 unsigned NumToInsert = ConcatEnd - Idx - 1;
2287 for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) {
2288 VecOp = DAG.getNode(
2289 ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, ConcatOps[OpIdx],
2290 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2292 ConcatOps[Idx+1] = VecOp;
2293 ConcatEnd = Idx + 2;
2295 // Vector type, create a CONCAT_VECTORS of type NextVT
2296 SDValue undefVec = DAG.getUNDEF(VT);
2297 unsigned OpsToConcat = NextSize/VT.getVectorNumElements();
2298 SmallVector<SDValue, 16> SubConcatOps(OpsToConcat);
2299 unsigned RealVals = ConcatEnd - Idx - 1;
2300 unsigned SubConcatEnd = 0;
2301 unsigned SubConcatIdx = Idx + 1;
2302 while (SubConcatEnd < RealVals)
2303 SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx];
2304 while (SubConcatEnd < OpsToConcat)
2305 SubConcatOps[SubConcatEnd++] = undefVec;
2306 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl,
2307 NextVT, SubConcatOps);
2308 ConcatEnd = SubConcatIdx + 1;
2312 // Check to see if we have a single operation with the widen type.
2313 if (ConcatEnd == 1) {
2314 VT = ConcatOps[0].getValueType();
2316 return ConcatOps[0];
2319 // add undefs of size MaxVT until ConcatOps grows to length of WidenVT
2320 unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements();
2321 if (NumOps != ConcatEnd ) {
2322 SDValue UndefVal = DAG.getUNDEF(MaxVT);
2323 for (unsigned j = ConcatEnd; j < NumOps; ++j)
2324 ConcatOps[j] = UndefVal;
2326 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
2327 makeArrayRef(ConcatOps.data(), NumOps));
2330 SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
2331 SDValue InOp = N->getOperand(0);
2334 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2335 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2337 EVT InVT = InOp.getValueType();
2338 EVT InEltVT = InVT.getVectorElementType();
2339 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
2341 unsigned Opcode = N->getOpcode();
2342 unsigned InVTNumElts = InVT.getVectorNumElements();
2343 const SDNodeFlags *Flags = N->getFlags();
2344 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
2345 InOp = GetWidenedVector(N->getOperand(0));
2346 InVT = InOp.getValueType();
2347 InVTNumElts = InVT.getVectorNumElements();
2348 if (InVTNumElts == WidenNumElts) {
2349 if (N->getNumOperands() == 1)
2350 return DAG.getNode(Opcode, DL, WidenVT, InOp);
2351 return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1), Flags);
2355 if (TLI.isTypeLegal(InWidenVT)) {
2356 // Because the result and the input are different vector types, widening
2357 // the result could create a legal type but widening the input might make
2358 // it an illegal type that might lead to repeatedly splitting the input
2359 // and then widening it. To avoid this, we widen the input only if
2360 // it results in a legal type.
2361 if (WidenNumElts % InVTNumElts == 0) {
2362 // Widen the input and call convert on the widened input vector.
2363 unsigned NumConcat = WidenNumElts/InVTNumElts;
2364 SmallVector<SDValue, 16> Ops(NumConcat);
2366 SDValue UndefVal = DAG.getUNDEF(InVT);
2367 for (unsigned i = 1; i != NumConcat; ++i)
2369 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, Ops);
2370 if (N->getNumOperands() == 1)
2371 return DAG.getNode(Opcode, DL, WidenVT, InVec);
2372 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1), Flags);
2375 if (InVTNumElts % WidenNumElts == 0) {
2376 SDValue InVal = DAG.getNode(
2377 ISD::EXTRACT_SUBVECTOR, DL, InWidenVT, InOp,
2378 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
2379 // Extract the input and convert the shorten input vector.
2380 if (N->getNumOperands() == 1)
2381 return DAG.getNode(Opcode, DL, WidenVT, InVal);
2382 return DAG.getNode(Opcode, DL, WidenVT, InVal, N->getOperand(1), Flags);
2386 // Otherwise unroll into some nasty scalar code and rebuild the vector.
2387 SmallVector<SDValue, 16> Ops(WidenNumElts);
2388 EVT EltVT = WidenVT.getVectorElementType();
2389 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
2391 for (i=0; i < MinElts; ++i) {
2392 SDValue Val = DAG.getNode(
2393 ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp,
2394 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
2395 if (N->getNumOperands() == 1)
2396 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val);
2398 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, N->getOperand(1), Flags);
2401 SDValue UndefVal = DAG.getUNDEF(EltVT);
2402 for (; i < WidenNumElts; ++i)
2405 return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, Ops);
2408 SDValue DAGTypeLegalizer::WidenVecRes_EXTEND_VECTOR_INREG(SDNode *N) {
2409 unsigned Opcode = N->getOpcode();
2410 SDValue InOp = N->getOperand(0);
2413 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2414 EVT WidenSVT = WidenVT.getVectorElementType();
2415 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2417 EVT InVT = InOp.getValueType();
2418 EVT InSVT = InVT.getVectorElementType();
2419 unsigned InVTNumElts = InVT.getVectorNumElements();
2421 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
2422 InOp = GetWidenedVector(InOp);
2423 InVT = InOp.getValueType();
2424 if (InVT.getSizeInBits() == WidenVT.getSizeInBits()) {
2426 case ISD::ANY_EXTEND_VECTOR_INREG:
2427 return DAG.getAnyExtendVectorInReg(InOp, DL, WidenVT);
2428 case ISD::SIGN_EXTEND_VECTOR_INREG:
2429 return DAG.getSignExtendVectorInReg(InOp, DL, WidenVT);
2430 case ISD::ZERO_EXTEND_VECTOR_INREG:
2431 return DAG.getZeroExtendVectorInReg(InOp, DL, WidenVT);
2436 // Unroll, extend the scalars and rebuild the vector.
2437 SmallVector<SDValue, 16> Ops;
2438 for (unsigned i = 0, e = std::min(InVTNumElts, WidenNumElts); i != e; ++i) {
2439 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InSVT, InOp,
2440 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
2442 case ISD::ANY_EXTEND_VECTOR_INREG:
2443 Val = DAG.getNode(ISD::ANY_EXTEND, DL, WidenSVT, Val);
2445 case ISD::SIGN_EXTEND_VECTOR_INREG:
2446 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, WidenSVT, Val);
2448 case ISD::ZERO_EXTEND_VECTOR_INREG:
2449 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, WidenSVT, Val);
2452 llvm_unreachable("A *_EXTEND_VECTOR_INREG node was expected");
2457 while (Ops.size() != WidenNumElts)
2458 Ops.push_back(DAG.getUNDEF(WidenSVT));
2460 return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, Ops);
2463 SDValue DAGTypeLegalizer::WidenVecRes_FCOPYSIGN(SDNode *N) {
2464 // If this is an FCOPYSIGN with same input types, we can treat it as a
2465 // normal (can trap) binary op.
2466 if (N->getOperand(0).getValueType() == N->getOperand(1).getValueType())
2467 return WidenVecRes_BinaryCanTrap(N);
2469 // If the types are different, fall back to unrolling.
2470 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2471 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
2474 SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) {
2475 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2476 SDValue InOp = GetWidenedVector(N->getOperand(0));
2477 SDValue ShOp = N->getOperand(1);
2478 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
2481 SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
2482 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2483 SDValue InOp = GetWidenedVector(N->getOperand(0));
2484 SDValue ShOp = N->getOperand(1);
2486 EVT ShVT = ShOp.getValueType();
2487 if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) {
2488 ShOp = GetWidenedVector(ShOp);
2489 ShVT = ShOp.getValueType();
2491 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(),
2492 ShVT.getVectorElementType(),
2493 WidenVT.getVectorNumElements());
2494 if (ShVT != ShWidenVT)
2495 ShOp = ModifyToType(ShOp, ShWidenVT);
2497 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
2500 SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
2501 // Unary op widening.
2502 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2503 SDValue InOp = GetWidenedVector(N->getOperand(0));
2504 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp);
2507 SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) {
2508 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2509 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(),
2510 cast<VTSDNode>(N->getOperand(1))->getVT()
2511 .getVectorElementType(),
2512 WidenVT.getVectorNumElements());
2513 SDValue WidenLHS = GetWidenedVector(N->getOperand(0));
2514 return DAG.getNode(N->getOpcode(), SDLoc(N),
2515 WidenVT, WidenLHS, DAG.getValueType(ExtVT));
2518 SDValue DAGTypeLegalizer::WidenVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo) {
2519 SDValue WidenVec = DisintegrateMERGE_VALUES(N, ResNo);
2520 return GetWidenedVector(WidenVec);
2523 SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) {
2524 SDValue InOp = N->getOperand(0);
2525 EVT InVT = InOp.getValueType();
2526 EVT VT = N->getValueType(0);
2527 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2530 switch (getTypeAction(InVT)) {
2531 case TargetLowering::TypeLegal:
2533 case TargetLowering::TypePromoteInteger:
2534 // If the incoming type is a vector that is being promoted, then
2535 // we know that the elements are arranged differently and that we
2536 // must perform the conversion using a stack slot.
2537 if (InVT.isVector())
2540 // If the InOp is promoted to the same size, convert it. Otherwise,
2541 // fall out of the switch and widen the promoted input.
2542 InOp = GetPromotedInteger(InOp);
2543 InVT = InOp.getValueType();
2544 if (WidenVT.bitsEq(InVT))
2545 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
2547 case TargetLowering::TypeSoftenFloat:
2548 case TargetLowering::TypePromoteFloat:
2549 case TargetLowering::TypeExpandInteger:
2550 case TargetLowering::TypeExpandFloat:
2551 case TargetLowering::TypeScalarizeVector:
2552 case TargetLowering::TypeSplitVector:
2554 case TargetLowering::TypeWidenVector:
2555 // If the InOp is widened to the same size, convert it. Otherwise, fall
2556 // out of the switch and widen the widened input.
2557 InOp = GetWidenedVector(InOp);
2558 InVT = InOp.getValueType();
2559 if (WidenVT.bitsEq(InVT))
2560 // The input widens to the same size. Convert to the widen value.
2561 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
2565 unsigned WidenSize = WidenVT.getSizeInBits();
2566 unsigned InSize = InVT.getSizeInBits();
2567 // x86mmx is not an acceptable vector element type, so don't try.
2568 if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) {
2569 // Determine new input vector type. The new input vector type will use
2570 // the same element type (if its a vector) or use the input type as a
2571 // vector. It is the same size as the type to widen to.
2573 unsigned NewNumElts = WidenSize / InSize;
2574 if (InVT.isVector()) {
2575 EVT InEltVT = InVT.getVectorElementType();
2576 NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT,
2577 WidenSize / InEltVT.getSizeInBits());
2579 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts);
2582 if (TLI.isTypeLegal(NewInVT)) {
2583 // Because the result and the input are different vector types, widening
2584 // the result could create a legal type but widening the input might make
2585 // it an illegal type that might lead to repeatedly splitting the input
2586 // and then widening it. To avoid this, we widen the input only if
2587 // it results in a legal type.
2588 SmallVector<SDValue, 16> Ops(NewNumElts);
2589 SDValue UndefVal = DAG.getUNDEF(InVT);
2591 for (unsigned i = 1; i < NewNumElts; ++i)
2595 if (InVT.isVector())
2596 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewInVT, Ops);
2598 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, NewInVT, Ops);
2599 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec);
2603 return CreateStackStoreLoad(InOp, WidenVT);
2606 SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
2608 // Build a vector with undefined for the new nodes.
2609 EVT VT = N->getValueType(0);
2611 // Integer BUILD_VECTOR operands may be larger than the node's vector element
2612 // type. The UNDEFs need to have the same type as the existing operands.
2613 EVT EltVT = N->getOperand(0).getValueType();
2614 unsigned NumElts = VT.getVectorNumElements();
2616 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2617 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2619 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
2620 assert(WidenNumElts >= NumElts && "Shrinking vector instead of widening!");
2621 NewOps.append(WidenNumElts - NumElts, DAG.getUNDEF(EltVT));
2623 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, NewOps);
2626 SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
2627 EVT InVT = N->getOperand(0).getValueType();
2628 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2630 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2631 unsigned NumInElts = InVT.getVectorNumElements();
2632 unsigned NumOperands = N->getNumOperands();
2634 bool InputWidened = false; // Indicates we need to widen the input.
2635 if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) {
2636 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) {
2637 // Add undef vectors to widen to correct length.
2638 unsigned NumConcat = WidenVT.getVectorNumElements() /
2639 InVT.getVectorNumElements();
2640 SDValue UndefVal = DAG.getUNDEF(InVT);
2641 SmallVector<SDValue, 16> Ops(NumConcat);
2642 for (unsigned i=0; i < NumOperands; ++i)
2643 Ops[i] = N->getOperand(i);
2644 for (unsigned i = NumOperands; i != NumConcat; ++i)
2646 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, Ops);
2649 InputWidened = true;
2650 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) {
2651 // The inputs and the result are widen to the same value.
2653 for (i=1; i < NumOperands; ++i)
2654 if (!N->getOperand(i).isUndef())
2657 if (i == NumOperands)
2658 // Everything but the first operand is an UNDEF so just return the
2659 // widened first operand.
2660 return GetWidenedVector(N->getOperand(0));
2662 if (NumOperands == 2) {
2663 // Replace concat of two operands with a shuffle.
2664 SmallVector<int, 16> MaskOps(WidenNumElts, -1);
2665 for (unsigned i = 0; i < NumInElts; ++i) {
2667 MaskOps[i + NumInElts] = i + WidenNumElts;
2669 return DAG.getVectorShuffle(WidenVT, dl,
2670 GetWidenedVector(N->getOperand(0)),
2671 GetWidenedVector(N->getOperand(1)),
2677 // Fall back to use extracts and build vector.
2678 EVT EltVT = WidenVT.getVectorElementType();
2679 SmallVector<SDValue, 16> Ops(WidenNumElts);
2681 for (unsigned i=0; i < NumOperands; ++i) {
2682 SDValue InOp = N->getOperand(i);
2684 InOp = GetWidenedVector(InOp);
2685 for (unsigned j=0; j < NumInElts; ++j)
2686 Ops[Idx++] = DAG.getNode(
2687 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2688 DAG.getConstant(j, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2690 SDValue UndefVal = DAG.getUNDEF(EltVT);
2691 for (; Idx < WidenNumElts; ++Idx)
2692 Ops[Idx] = UndefVal;
2693 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2696 SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
2698 SDValue InOp = N->getOperand(0);
2699 SDValue RndOp = N->getOperand(3);
2700 SDValue SatOp = N->getOperand(4);
2702 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2703 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2705 EVT InVT = InOp.getValueType();
2706 EVT InEltVT = InVT.getVectorElementType();
2707 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
2709 SDValue DTyOp = DAG.getValueType(WidenVT);
2710 SDValue STyOp = DAG.getValueType(InWidenVT);
2711 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
2713 unsigned InVTNumElts = InVT.getVectorNumElements();
2714 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
2715 InOp = GetWidenedVector(InOp);
2716 InVT = InOp.getValueType();
2717 InVTNumElts = InVT.getVectorNumElements();
2718 if (InVTNumElts == WidenNumElts)
2719 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2723 if (TLI.isTypeLegal(InWidenVT)) {
2724 // Because the result and the input are different vector types, widening
2725 // the result could create a legal type but widening the input might make
2726 // it an illegal type that might lead to repeatedly splitting the input
2727 // and then widening it. To avoid this, we widen the input only if
2728 // it results in a legal type.
2729 if (WidenNumElts % InVTNumElts == 0) {
2730 // Widen the input and call convert on the widened input vector.
2731 unsigned NumConcat = WidenNumElts/InVTNumElts;
2732 SmallVector<SDValue, 16> Ops(NumConcat);
2734 SDValue UndefVal = DAG.getUNDEF(InVT);
2735 for (unsigned i = 1; i != NumConcat; ++i)
2738 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, Ops);
2739 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2743 if (InVTNumElts % WidenNumElts == 0) {
2744 // Extract the input and convert the shorten input vector.
2746 ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp,
2747 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2748 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2753 // Otherwise unroll into some nasty scalar code and rebuild the vector.
2754 SmallVector<SDValue, 16> Ops(WidenNumElts);
2755 EVT EltVT = WidenVT.getVectorElementType();
2756 DTyOp = DAG.getValueType(EltVT);
2757 STyOp = DAG.getValueType(InEltVT);
2759 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
2761 for (i=0; i < MinElts; ++i) {
2762 SDValue ExtVal = DAG.getNode(
2763 ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
2764 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2765 Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp,
2769 SDValue UndefVal = DAG.getUNDEF(EltVT);
2770 for (; i < WidenNumElts; ++i)
2773 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2776 SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
2777 EVT VT = N->getValueType(0);
2778 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2779 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2780 SDValue InOp = N->getOperand(0);
2781 SDValue Idx = N->getOperand(1);
2784 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2785 InOp = GetWidenedVector(InOp);
2787 EVT InVT = InOp.getValueType();
2789 // Check if we can just return the input vector after widening.
2790 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
2791 if (IdxVal == 0 && InVT == WidenVT)
2794 // Check if we can extract from the vector.
2795 unsigned InNumElts = InVT.getVectorNumElements();
2796 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
2797 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
2799 // We could try widening the input to the right length but for now, extract
2800 // the original elements, fill the rest with undefs and build a vector.
2801 SmallVector<SDValue, 16> Ops(WidenNumElts);
2802 EVT EltVT = VT.getVectorElementType();
2803 unsigned NumElts = VT.getVectorNumElements();
2805 for (i=0; i < NumElts; ++i)
2807 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2808 DAG.getConstant(IdxVal + i, dl,
2809 TLI.getVectorIdxTy(DAG.getDataLayout())));
2811 SDValue UndefVal = DAG.getUNDEF(EltVT);
2812 for (; i < WidenNumElts; ++i)
2814 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2817 SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
2818 SDValue InOp = GetWidenedVector(N->getOperand(0));
2819 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N),
2820 InOp.getValueType(), InOp,
2821 N->getOperand(1), N->getOperand(2));
2824 SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
2825 LoadSDNode *LD = cast<LoadSDNode>(N);
2826 ISD::LoadExtType ExtType = LD->getExtensionType();
2829 SmallVector<SDValue, 16> LdChain; // Chain for the series of load
2830 if (ExtType != ISD::NON_EXTLOAD)
2831 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType);
2833 Result = GenWidenVectorLoads(LdChain, LD);
2835 // If we generate a single load, we can use that for the chain. Otherwise,
2836 // build a factor node to remember the multiple loads are independent and
2839 if (LdChain.size() == 1)
2840 NewChain = LdChain[0];
2842 NewChain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other, LdChain);
2844 // Modified the chain - switch anything that used the old chain to use
2846 ReplaceValueWith(SDValue(N, 1), NewChain);
2851 SDValue DAGTypeLegalizer::WidenVecRes_MLOAD(MaskedLoadSDNode *N) {
2853 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),N->getValueType(0));
2854 SDValue Mask = N->getMask();
2855 EVT MaskVT = Mask.getValueType();
2856 SDValue Src0 = GetWidenedVector(N->getSrc0());
2857 ISD::LoadExtType ExtType = N->getExtensionType();
2860 if (getTypeAction(MaskVT) == TargetLowering::TypeWidenVector)
2861 Mask = GetWidenedVector(Mask);
2863 EVT BoolVT = getSetCCResultType(WidenVT);
2865 // We can't use ModifyToType() because we should fill the mask with
2867 unsigned WidenNumElts = BoolVT.getVectorNumElements();
2868 unsigned MaskNumElts = MaskVT.getVectorNumElements();
2870 unsigned NumConcat = WidenNumElts / MaskNumElts;
2871 SmallVector<SDValue, 16> Ops(NumConcat);
2872 SDValue ZeroVal = DAG.getConstant(0, dl, MaskVT);
2874 for (unsigned i = 1; i != NumConcat; ++i)
2877 Mask = DAG.getNode(ISD::CONCAT_VECTORS, dl, BoolVT, Ops);
2880 SDValue Res = DAG.getMaskedLoad(WidenVT, dl, N->getChain(), N->getBasePtr(),
2881 Mask, Src0, N->getMemoryVT(),
2882 N->getMemOperand(), ExtType,
2883 N->isExpandingLoad());
2884 // Legalize the chain result - switch anything that used the old chain to
2886 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
2890 SDValue DAGTypeLegalizer::WidenVecRes_MGATHER(MaskedGatherSDNode *N) {
2892 EVT WideVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2893 SDValue Mask = N->getMask();
2894 SDValue Src0 = GetWidenedVector(N->getValue());
2895 unsigned NumElts = WideVT.getVectorNumElements();
2898 // The mask should be widened as well
2899 Mask = WidenTargetBoolean(Mask, WideVT, true);
2901 // Widen the Index operand
2902 SDValue Index = N->getIndex();
2903 EVT WideIndexVT = EVT::getVectorVT(*DAG.getContext(),
2904 Index.getValueType().getScalarType(),
2906 Index = ModifyToType(Index, WideIndexVT);
2907 SDValue Ops[] = { N->getChain(), Src0, Mask, N->getBasePtr(), Index };
2908 SDValue Res = DAG.getMaskedGather(DAG.getVTList(WideVT, MVT::Other),
2909 N->getMemoryVT(), dl, Ops,
2910 N->getMemOperand());
2912 // Legalize the chain result - switch anything that used the old chain to
2914 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
2918 SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
2919 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2920 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N),
2921 WidenVT, N->getOperand(0));
2924 SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
2925 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2926 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2928 SDValue Cond1 = N->getOperand(0);
2929 EVT CondVT = Cond1.getValueType();
2930 if (CondVT.isVector()) {
2931 EVT CondEltVT = CondVT.getVectorElementType();
2932 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(),
2933 CondEltVT, WidenNumElts);
2934 if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector)
2935 Cond1 = GetWidenedVector(Cond1);
2937 // If we have to split the condition there is no point in widening the
2938 // select. This would result in an cycle of widening the select ->
2939 // widening the condition operand -> splitting the condition operand ->
2940 // splitting the select -> widening the select. Instead split this select
2941 // further and widen the resulting type.
2942 if (getTypeAction(CondVT) == TargetLowering::TypeSplitVector) {
2943 SDValue SplitSelect = SplitVecOp_VSELECT(N, 0);
2944 SDValue Res = ModifyToType(SplitSelect, WidenVT);
2948 if (Cond1.getValueType() != CondWidenVT)
2949 Cond1 = ModifyToType(Cond1, CondWidenVT);
2952 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
2953 SDValue InOp2 = GetWidenedVector(N->getOperand(2));
2954 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT);
2955 return DAG.getNode(N->getOpcode(), SDLoc(N),
2956 WidenVT, Cond1, InOp1, InOp2);
2959 SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
2960 SDValue InOp1 = GetWidenedVector(N->getOperand(2));
2961 SDValue InOp2 = GetWidenedVector(N->getOperand(3));
2962 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
2963 InOp1.getValueType(), N->getOperand(0),
2964 N->getOperand(1), InOp1, InOp2, N->getOperand(4));
2967 SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
2968 assert(N->getValueType(0).isVector() ==
2969 N->getOperand(0).getValueType().isVector() &&
2970 "Scalar/Vector type mismatch");
2971 if (N->getValueType(0).isVector()) return WidenVecRes_VSETCC(N);
2973 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2974 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2975 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2976 return DAG.getNode(ISD::SETCC, SDLoc(N), WidenVT,
2977 InOp1, InOp2, N->getOperand(2));
2980 SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
2981 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2982 return DAG.getUNDEF(WidenVT);
2985 SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
2986 EVT VT = N->getValueType(0);
2989 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2990 unsigned NumElts = VT.getVectorNumElements();
2991 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2993 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2994 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2996 // Adjust mask based on new input vector length.
2997 SmallVector<int, 16> NewMask;
2998 for (unsigned i = 0; i != NumElts; ++i) {
2999 int Idx = N->getMaskElt(i);
3000 if (Idx < (int)NumElts)
3001 NewMask.push_back(Idx);
3003 NewMask.push_back(Idx - NumElts + WidenNumElts);
3005 for (unsigned i = NumElts; i != WidenNumElts; ++i)
3006 NewMask.push_back(-1);
3007 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, NewMask);
3010 SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
3011 assert(N->getValueType(0).isVector() &&
3012 N->getOperand(0).getValueType().isVector() &&
3013 "Operands must be vectors");
3014 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3015 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3017 SDValue InOp1 = N->getOperand(0);
3018 EVT InVT = InOp1.getValueType();
3019 assert(InVT.isVector() && "can not widen non-vector type");
3020 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(),
3021 InVT.getVectorElementType(), WidenNumElts);
3023 // The input and output types often differ here, and it could be that while
3024 // we'd prefer to widen the result type, the input operands have been split.
3025 // In this case, we also need to split the result of this node as well.
3026 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector) {
3027 SDValue SplitVSetCC = SplitVecOp_VSETCC(N);
3028 SDValue Res = ModifyToType(SplitVSetCC, WidenVT);
3032 InOp1 = GetWidenedVector(InOp1);
3033 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
3035 // Assume that the input and output will be widen appropriately. If not,
3036 // we will have to unroll it at some point.
3037 assert(InOp1.getValueType() == WidenInVT &&
3038 InOp2.getValueType() == WidenInVT &&
3039 "Input not widened to expected type!");
3041 return DAG.getNode(ISD::SETCC, SDLoc(N),
3042 WidenVT, InOp1, InOp2, N->getOperand(2));
3046 //===----------------------------------------------------------------------===//
3047 // Widen Vector Operand
3048 //===----------------------------------------------------------------------===//
3049 bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
3050 DEBUG(dbgs() << "Widen node operand " << OpNo << ": ";
3053 SDValue Res = SDValue();
3055 // See if the target wants to custom widen this node.
3056 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
3059 switch (N->getOpcode()) {
3062 dbgs() << "WidenVectorOperand op #" << OpNo << ": ";
3066 llvm_unreachable("Do not know how to widen this operator's operand!");
3068 case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break;
3069 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
3070 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break;
3071 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
3072 case ISD::STORE: Res = WidenVecOp_STORE(N); break;
3073 case ISD::MSTORE: Res = WidenVecOp_MSTORE(N, OpNo); break;
3074 case ISD::MSCATTER: Res = WidenVecOp_MSCATTER(N, OpNo); break;
3075 case ISD::SETCC: Res = WidenVecOp_SETCC(N); break;
3076 case ISD::FCOPYSIGN: Res = WidenVecOp_FCOPYSIGN(N); break;
3078 case ISD::ANY_EXTEND:
3079 case ISD::SIGN_EXTEND:
3080 case ISD::ZERO_EXTEND:
3081 Res = WidenVecOp_EXTEND(N);
3084 case ISD::FP_EXTEND:
3085 case ISD::FP_TO_SINT:
3086 case ISD::FP_TO_UINT:
3087 case ISD::SINT_TO_FP:
3088 case ISD::UINT_TO_FP:
3090 Res = WidenVecOp_Convert(N);
3094 // If Res is null, the sub-method took care of registering the result.
3095 if (!Res.getNode()) return false;
3097 // If the result is N, the sub-method updated N in place. Tell the legalizer
3099 if (Res.getNode() == N)
3103 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
3104 "Invalid operand expansion");
3106 ReplaceValueWith(SDValue(N, 0), Res);
3110 SDValue DAGTypeLegalizer::WidenVecOp_EXTEND(SDNode *N) {
3112 EVT VT = N->getValueType(0);
3114 SDValue InOp = N->getOperand(0);
3115 // If some legalization strategy other than widening is used on the operand,
3116 // we can't safely assume that just extending the low lanes is the correct
3118 if (getTypeAction(InOp.getValueType()) != TargetLowering::TypeWidenVector)
3119 return WidenVecOp_Convert(N);
3120 InOp = GetWidenedVector(InOp);
3121 assert(VT.getVectorNumElements() <
3122 InOp.getValueType().getVectorNumElements() &&
3123 "Input wasn't widened!");
3125 // We may need to further widen the operand until it has the same total
3126 // vector size as the result.
3127 EVT InVT = InOp.getValueType();
3128 if (InVT.getSizeInBits() != VT.getSizeInBits()) {
3129 EVT InEltVT = InVT.getVectorElementType();
3130 for (int i = MVT::FIRST_VECTOR_VALUETYPE, e = MVT::LAST_VECTOR_VALUETYPE; i < e; ++i) {
3131 EVT FixedVT = (MVT::SimpleValueType)i;
3132 EVT FixedEltVT = FixedVT.getVectorElementType();
3133 if (TLI.isTypeLegal(FixedVT) &&
3134 FixedVT.getSizeInBits() == VT.getSizeInBits() &&
3135 FixedEltVT == InEltVT) {
3136 assert(FixedVT.getVectorNumElements() >= VT.getVectorNumElements() &&
3137 "Not enough elements in the fixed type for the operand!");
3138 assert(FixedVT.getVectorNumElements() != InVT.getVectorNumElements() &&
3139 "We can't have the same type as we started with!");
3140 if (FixedVT.getVectorNumElements() > InVT.getVectorNumElements())
3142 ISD::INSERT_SUBVECTOR, DL, FixedVT, DAG.getUNDEF(FixedVT), InOp,
3143 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
3146 ISD::EXTRACT_SUBVECTOR, DL, FixedVT, InOp,
3147 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
3151 InVT = InOp.getValueType();
3152 if (InVT.getSizeInBits() != VT.getSizeInBits())
3153 // We couldn't find a legal vector type that was a widening of the input
3154 // and could be extended in-register to the result type, so we have to
3156 return WidenVecOp_Convert(N);
3159 // Use special DAG nodes to represent the operation of extending the
3161 switch (N->getOpcode()) {
3163 llvm_unreachable("Extend legalization on on extend operation!");
3164 case ISD::ANY_EXTEND:
3165 return DAG.getAnyExtendVectorInReg(InOp, DL, VT);
3166 case ISD::SIGN_EXTEND:
3167 return DAG.getSignExtendVectorInReg(InOp, DL, VT);
3168 case ISD::ZERO_EXTEND:
3169 return DAG.getZeroExtendVectorInReg(InOp, DL, VT);
3173 SDValue DAGTypeLegalizer::WidenVecOp_FCOPYSIGN(SDNode *N) {
3174 // The result (and first input) is legal, but the second input is illegal.
3175 // We can't do much to fix that, so just unroll and let the extracts off of
3176 // the second input be widened as needed later.
3177 return DAG.UnrollVectorOp(N);
3180 SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
3181 // Since the result is legal and the input is illegal, it is unlikely that we
3182 // can fix the input to a legal type so unroll the convert into some scalar
3183 // code and create a nasty build vector.
3184 EVT VT = N->getValueType(0);
3185 EVT EltVT = VT.getVectorElementType();
3187 unsigned NumElts = VT.getVectorNumElements();
3188 SDValue InOp = N->getOperand(0);
3189 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
3190 InOp = GetWidenedVector(InOp);
3191 EVT InVT = InOp.getValueType();
3192 EVT InEltVT = InVT.getVectorElementType();
3194 unsigned Opcode = N->getOpcode();
3195 SmallVector<SDValue, 16> Ops(NumElts);
3196 for (unsigned i=0; i < NumElts; ++i)
3197 Ops[i] = DAG.getNode(
3200 ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
3201 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout()))));
3203 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
3206 SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) {
3207 EVT VT = N->getValueType(0);
3208 SDValue InOp = GetWidenedVector(N->getOperand(0));
3209 EVT InWidenVT = InOp.getValueType();
3212 // Check if we can convert between two legal vector types and extract.
3213 unsigned InWidenSize = InWidenVT.getSizeInBits();
3214 unsigned Size = VT.getSizeInBits();
3215 // x86mmx is not an acceptable vector element type, so don't try.
3216 if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) {
3217 unsigned NewNumElts = InWidenSize / Size;
3218 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts);
3219 if (TLI.isTypeLegal(NewVT)) {
3220 SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp);
3222 ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
3223 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3227 return CreateStackStoreLoad(InOp, VT);
3230 SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
3231 // If the input vector is not legal, it is likely that we will not find a
3232 // legal vector of the same size. Replace the concatenate vector with a
3233 // nasty build vector.
3234 EVT VT = N->getValueType(0);
3235 EVT EltVT = VT.getVectorElementType();
3237 unsigned NumElts = VT.getVectorNumElements();
3238 SmallVector<SDValue, 16> Ops(NumElts);
3240 EVT InVT = N->getOperand(0).getValueType();
3241 unsigned NumInElts = InVT.getVectorNumElements();
3244 unsigned NumOperands = N->getNumOperands();
3245 for (unsigned i=0; i < NumOperands; ++i) {
3246 SDValue InOp = N->getOperand(i);
3247 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
3248 InOp = GetWidenedVector(InOp);
3249 for (unsigned j=0; j < NumInElts; ++j)
3250 Ops[Idx++] = DAG.getNode(
3251 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
3252 DAG.getConstant(j, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3254 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
3257 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
3258 SDValue InOp = GetWidenedVector(N->getOperand(0));
3259 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N),
3260 N->getValueType(0), InOp, N->getOperand(1));
3263 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
3264 SDValue InOp = GetWidenedVector(N->getOperand(0));
3265 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
3266 N->getValueType(0), InOp, N->getOperand(1));
3269 SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
3270 // We have to widen the value, but we want only to store the original
3272 StoreSDNode *ST = cast<StoreSDNode>(N);
3274 SmallVector<SDValue, 16> StChain;
3275 if (ST->isTruncatingStore())
3276 GenWidenVectorTruncStores(StChain, ST);
3278 GenWidenVectorStores(StChain, ST);
3280 if (StChain.size() == 1)
3283 return DAG.getNode(ISD::TokenFactor, SDLoc(ST), MVT::Other, StChain);
3286 SDValue DAGTypeLegalizer::WidenVecOp_MSTORE(SDNode *N, unsigned OpNo) {
3287 MaskedStoreSDNode *MST = cast<MaskedStoreSDNode>(N);
3288 SDValue Mask = MST->getMask();
3289 EVT MaskVT = Mask.getValueType();
3290 SDValue StVal = MST->getValue();
3292 SDValue WideVal = GetWidenedVector(StVal);
3295 if (OpNo == 2 || getTypeAction(MaskVT) == TargetLowering::TypeWidenVector)
3296 Mask = GetWidenedVector(Mask);
3298 // The mask should be widened as well.
3299 EVT BoolVT = getSetCCResultType(WideVal.getValueType());
3300 // We can't use ModifyToType() because we should fill the mask with
3302 unsigned WidenNumElts = BoolVT.getVectorNumElements();
3303 unsigned MaskNumElts = MaskVT.getVectorNumElements();
3305 unsigned NumConcat = WidenNumElts / MaskNumElts;
3306 SmallVector<SDValue, 16> Ops(NumConcat);
3307 SDValue ZeroVal = DAG.getConstant(0, dl, MaskVT);
3309 for (unsigned i = 1; i != NumConcat; ++i)
3312 Mask = DAG.getNode(ISD::CONCAT_VECTORS, dl, BoolVT, Ops);
3314 assert(Mask.getValueType().getVectorNumElements() ==
3315 WideVal.getValueType().getVectorNumElements() &&
3316 "Mask and data vectors should have the same number of elements");
3317 return DAG.getMaskedStore(MST->getChain(), dl, WideVal, MST->getBasePtr(),
3318 Mask, MST->getMemoryVT(), MST->getMemOperand(),
3319 false, MST->isCompressingStore());
3322 SDValue DAGTypeLegalizer::WidenVecOp_MSCATTER(SDNode *N, unsigned OpNo) {
3323 assert(OpNo == 1 && "Can widen only data operand of mscatter");
3324 MaskedScatterSDNode *MSC = cast<MaskedScatterSDNode>(N);
3325 SDValue DataOp = MSC->getValue();
3326 SDValue Mask = MSC->getMask();
3329 SDValue WideVal = GetWidenedVector(DataOp);
3330 EVT WideVT = WideVal.getValueType();
3331 unsigned NumElts = WideVal.getValueType().getVectorNumElements();
3334 // The mask should be widened as well.
3335 Mask = WidenTargetBoolean(Mask, WideVT, true);
3338 SDValue Index = MSC->getIndex();
3339 EVT WideIndexVT = EVT::getVectorVT(*DAG.getContext(),
3340 Index.getValueType().getScalarType(),
3342 Index = ModifyToType(Index, WideIndexVT);
3344 SDValue Ops[] = {MSC->getChain(), WideVal, Mask, MSC->getBasePtr(), Index};
3345 return DAG.getMaskedScatter(DAG.getVTList(MVT::Other),
3346 MSC->getMemoryVT(), dl, Ops,
3347 MSC->getMemOperand());
3350 SDValue DAGTypeLegalizer::WidenVecOp_SETCC(SDNode *N) {
3351 SDValue InOp0 = GetWidenedVector(N->getOperand(0));
3352 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
3355 // WARNING: In this code we widen the compare instruction with garbage.
3356 // This garbage may contain denormal floats which may be slow. Is this a real
3357 // concern ? Should we zero the unused lanes if this is a float compare ?
3359 // Get a new SETCC node to compare the newly widened operands.
3360 // Only some of the compared elements are legal.
3361 EVT SVT = TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
3362 InOp0.getValueType());
3363 SDValue WideSETCC = DAG.getNode(ISD::SETCC, SDLoc(N),
3364 SVT, InOp0, InOp1, N->getOperand(2));
3366 // Extract the needed results from the result vector.
3367 EVT ResVT = EVT::getVectorVT(*DAG.getContext(),
3368 SVT.getVectorElementType(),
3369 N->getValueType(0).getVectorNumElements());
3370 SDValue CC = DAG.getNode(
3371 ISD::EXTRACT_SUBVECTOR, dl, ResVT, WideSETCC,
3372 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3374 return PromoteTargetBoolean(CC, N->getValueType(0));
3378 //===----------------------------------------------------------------------===//
3379 // Vector Widening Utilities
3380 //===----------------------------------------------------------------------===//
3382 // Utility function to find the type to chop up a widen vector for load/store
3383 // TLI: Target lowering used to determine legal types.
3384 // Width: Width left need to load/store.
3385 // WidenVT: The widen vector type to load to/store from
3386 // Align: If 0, don't allow use of a wider type
3387 // WidenEx: If Align is not 0, the amount additional we can load/store from.
3389 static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI,
3390 unsigned Width, EVT WidenVT,
3391 unsigned Align = 0, unsigned WidenEx = 0) {
3392 EVT WidenEltVT = WidenVT.getVectorElementType();
3393 unsigned WidenWidth = WidenVT.getSizeInBits();
3394 unsigned WidenEltWidth = WidenEltVT.getSizeInBits();
3395 unsigned AlignInBits = Align*8;
3397 // If we have one element to load/store, return it.
3398 EVT RetVT = WidenEltVT;
3399 if (Width == WidenEltWidth)
3402 // See if there is larger legal integer than the element type to load/store.
3404 for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE;
3405 VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) {
3406 EVT MemVT((MVT::SimpleValueType) VT);
3407 unsigned MemVTWidth = MemVT.getSizeInBits();
3408 if (MemVT.getSizeInBits() <= WidenEltWidth)
3410 auto Action = TLI.getTypeAction(*DAG.getContext(), MemVT);
3411 if ((Action == TargetLowering::TypeLegal ||
3412 Action == TargetLowering::TypePromoteInteger) &&
3413 (WidenWidth % MemVTWidth) == 0 &&
3414 isPowerOf2_32(WidenWidth / MemVTWidth) &&
3415 (MemVTWidth <= Width ||
3416 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
3422 // See if there is a larger vector type to load/store that has the same vector
3423 // element type and is evenly divisible with the WidenVT.
3424 for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
3425 VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) {
3426 EVT MemVT = (MVT::SimpleValueType) VT;
3427 unsigned MemVTWidth = MemVT.getSizeInBits();
3428 if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() &&
3429 (WidenWidth % MemVTWidth) == 0 &&
3430 isPowerOf2_32(WidenWidth / MemVTWidth) &&
3431 (MemVTWidth <= Width ||
3432 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
3433 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT)
3441 // Builds a vector type from scalar loads
3442 // VecTy: Resulting Vector type
3443 // LDOps: Load operators to build a vector type
3444 // [Start,End) the list of loads to use.
3445 static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy,
3446 SmallVectorImpl<SDValue> &LdOps,
3447 unsigned Start, unsigned End) {
3448 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3449 SDLoc dl(LdOps[Start]);
3450 EVT LdTy = LdOps[Start].getValueType();
3451 unsigned Width = VecTy.getSizeInBits();
3452 unsigned NumElts = Width / LdTy.getSizeInBits();
3453 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts);
3456 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]);
3458 for (unsigned i = Start + 1; i != End; ++i) {
3459 EVT NewLdTy = LdOps[i].getValueType();
3460 if (NewLdTy != LdTy) {
3461 NumElts = Width / NewLdTy.getSizeInBits();
3462 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts);
3463 VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp);
3464 // Readjust position and vector position based on new load type.
3465 Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits();
3468 VecOp = DAG.getNode(
3469 ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
3470 DAG.getConstant(Idx++, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3472 return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp);
3475 SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
3477 // The strategy assumes that we can efficiently load power-of-two widths.
3478 // The routine chops the vector into the largest vector loads with the same
3479 // element type or scalar loads and then recombines it to the widen vector
3481 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
3482 unsigned WidenWidth = WidenVT.getSizeInBits();
3483 EVT LdVT = LD->getMemoryVT();
3485 assert(LdVT.isVector() && WidenVT.isVector());
3486 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType());
3489 SDValue Chain = LD->getChain();
3490 SDValue BasePtr = LD->getBasePtr();
3491 unsigned Align = LD->getAlignment();
3492 MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
3493 AAMDNodes AAInfo = LD->getAAInfo();
3495 int LdWidth = LdVT.getSizeInBits();
3496 int WidthDiff = WidenWidth - LdWidth;
3497 unsigned LdAlign = LD->isVolatile() ? 0 : Align; // Allow wider loads.
3499 // Find the vector type that can load from.
3500 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
3501 int NewVTWidth = NewVT.getSizeInBits();
3502 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(),
3503 Align, MMOFlags, AAInfo);
3504 LdChain.push_back(LdOp.getValue(1));
3506 // Check if we can load the element with one instruction.
3507 if (LdWidth <= NewVTWidth) {
3508 if (!NewVT.isVector()) {
3509 unsigned NumElts = WidenWidth / NewVTWidth;
3510 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
3511 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
3512 return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp);
3514 if (NewVT == WidenVT)
3517 assert(WidenWidth % NewVTWidth == 0);
3518 unsigned NumConcat = WidenWidth / NewVTWidth;
3519 SmallVector<SDValue, 16> ConcatOps(NumConcat);
3520 SDValue UndefVal = DAG.getUNDEF(NewVT);
3521 ConcatOps[0] = LdOp;
3522 for (unsigned i = 1; i != NumConcat; ++i)
3523 ConcatOps[i] = UndefVal;
3524 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, ConcatOps);
3527 // Load vector by using multiple loads from largest vector to scalar.
3528 SmallVector<SDValue, 16> LdOps;
3529 LdOps.push_back(LdOp);
3531 LdWidth -= NewVTWidth;
3532 unsigned Offset = 0;
3534 while (LdWidth > 0) {
3535 unsigned Increment = NewVTWidth / 8;
3536 Offset += Increment;
3537 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3538 DAG.getConstant(Increment, dl, BasePtr.getValueType()));
3541 if (LdWidth < NewVTWidth) {
3542 // The current type we are using is too large. Find a better size.
3543 NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
3544 NewVTWidth = NewVT.getSizeInBits();
3545 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
3546 LD->getPointerInfo().getWithOffset(Offset),
3547 MinAlign(Align, Increment), MMOFlags, AAInfo);
3548 LdChain.push_back(L.getValue(1));
3549 if (L->getValueType(0).isVector()) {
3550 SmallVector<SDValue, 16> Loads;
3552 unsigned size = L->getValueSizeInBits(0);
3553 while (size < LdOp->getValueSizeInBits(0)) {
3554 Loads.push_back(DAG.getUNDEF(L->getValueType(0)));
3555 size += L->getValueSizeInBits(0);
3557 L = DAG.getNode(ISD::CONCAT_VECTORS, dl, LdOp->getValueType(0), Loads);
3560 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
3561 LD->getPointerInfo().getWithOffset(Offset),
3562 MinAlign(Align, Increment), MMOFlags, AAInfo);
3563 LdChain.push_back(L.getValue(1));
3569 LdWidth -= NewVTWidth;
3572 // Build the vector from the load operations.
3573 unsigned End = LdOps.size();
3574 if (!LdOps[0].getValueType().isVector())
3575 // All the loads are scalar loads.
3576 return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End);
3578 // If the load contains vectors, build the vector using concat vector.
3579 // All of the vectors used to load are power-of-2, and the scalar loads can be
3580 // combined to make a power-of-2 vector.
3581 SmallVector<SDValue, 16> ConcatOps(End);
3584 EVT LdTy = LdOps[i].getValueType();
3585 // First, combine the scalar loads to a vector.
3586 if (!LdTy.isVector()) {
3587 for (--i; i >= 0; --i) {
3588 LdTy = LdOps[i].getValueType();
3589 if (LdTy.isVector())
3592 ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i + 1, End);
3594 ConcatOps[--Idx] = LdOps[i];
3595 for (--i; i >= 0; --i) {
3596 EVT NewLdTy = LdOps[i].getValueType();
3597 if (NewLdTy != LdTy) {
3598 // Create a larger vector.
3599 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
3600 makeArrayRef(&ConcatOps[Idx], End - Idx));
3604 ConcatOps[--Idx] = LdOps[i];
3607 if (WidenWidth == LdTy.getSizeInBits() * (End - Idx))
3608 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
3609 makeArrayRef(&ConcatOps[Idx], End - Idx));
3611 // We need to fill the rest with undefs to build the vector.
3612 unsigned NumOps = WidenWidth / LdTy.getSizeInBits();
3613 SmallVector<SDValue, 16> WidenOps(NumOps);
3614 SDValue UndefVal = DAG.getUNDEF(LdTy);
3617 for (; i != End-Idx; ++i)
3618 WidenOps[i] = ConcatOps[Idx+i];
3619 for (; i != NumOps; ++i)
3620 WidenOps[i] = UndefVal;
3622 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, WidenOps);
3626 DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVectorImpl<SDValue> &LdChain,
3628 ISD::LoadExtType ExtType) {
3629 // For extension loads, it may not be more efficient to chop up the vector
3630 // and then extend it. Instead, we unroll the load and build a new vector.
3631 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
3632 EVT LdVT = LD->getMemoryVT();
3634 assert(LdVT.isVector() && WidenVT.isVector());
3637 SDValue Chain = LD->getChain();
3638 SDValue BasePtr = LD->getBasePtr();
3639 unsigned Align = LD->getAlignment();
3640 MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
3641 AAMDNodes AAInfo = LD->getAAInfo();
3643 EVT EltVT = WidenVT.getVectorElementType();
3644 EVT LdEltVT = LdVT.getVectorElementType();
3645 unsigned NumElts = LdVT.getVectorNumElements();
3647 // Load each element and widen.
3648 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3649 SmallVector<SDValue, 16> Ops(WidenNumElts);
3650 unsigned Increment = LdEltVT.getSizeInBits() / 8;
3652 DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr, LD->getPointerInfo(),
3653 LdEltVT, Align, MMOFlags, AAInfo);
3654 LdChain.push_back(Ops[0].getValue(1));
3655 unsigned i = 0, Offset = Increment;
3656 for (i=1; i < NumElts; ++i, Offset += Increment) {
3657 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
3659 DAG.getConstant(Offset, dl,
3660 BasePtr.getValueType()));
3661 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr,
3662 LD->getPointerInfo().getWithOffset(Offset), LdEltVT,
3663 Align, MMOFlags, AAInfo);
3664 LdChain.push_back(Ops[i].getValue(1));
3667 // Fill the rest with undefs.
3668 SDValue UndefVal = DAG.getUNDEF(EltVT);
3669 for (; i != WidenNumElts; ++i)
3672 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
3676 void DAGTypeLegalizer::GenWidenVectorStores(SmallVectorImpl<SDValue> &StChain,
3678 // The strategy assumes that we can efficiently store power-of-two widths.
3679 // The routine chops the vector into the largest vector stores with the same
3680 // element type or scalar stores.
3681 SDValue Chain = ST->getChain();
3682 SDValue BasePtr = ST->getBasePtr();
3683 unsigned Align = ST->getAlignment();
3684 MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags();
3685 AAMDNodes AAInfo = ST->getAAInfo();
3686 SDValue ValOp = GetWidenedVector(ST->getValue());
3689 EVT StVT = ST->getMemoryVT();
3690 unsigned StWidth = StVT.getSizeInBits();
3691 EVT ValVT = ValOp.getValueType();
3692 unsigned ValWidth = ValVT.getSizeInBits();
3693 EVT ValEltVT = ValVT.getVectorElementType();
3694 unsigned ValEltWidth = ValEltVT.getSizeInBits();
3695 assert(StVT.getVectorElementType() == ValEltVT);
3697 int Idx = 0; // current index to store
3698 unsigned Offset = 0; // offset from base to store
3699 while (StWidth != 0) {
3700 // Find the largest vector type we can store with.
3701 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT);
3702 unsigned NewVTWidth = NewVT.getSizeInBits();
3703 unsigned Increment = NewVTWidth / 8;
3704 if (NewVT.isVector()) {
3705 unsigned NumVTElts = NewVT.getVectorNumElements();
3707 SDValue EOp = DAG.getNode(
3708 ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp,
3709 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3710 StChain.push_back(DAG.getStore(
3711 Chain, dl, EOp, BasePtr, ST->getPointerInfo().getWithOffset(Offset),
3712 MinAlign(Align, Offset), MMOFlags, AAInfo));
3713 StWidth -= NewVTWidth;
3714 Offset += Increment;
3716 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3717 DAG.getConstant(Increment, dl,
3718 BasePtr.getValueType()));
3719 } while (StWidth != 0 && StWidth >= NewVTWidth);
3721 // Cast the vector to the scalar type we can store.
3722 unsigned NumElts = ValWidth / NewVTWidth;
3723 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
3724 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp);
3725 // Readjust index position based on new vector type.
3726 Idx = Idx * ValEltWidth / NewVTWidth;
3728 SDValue EOp = DAG.getNode(
3729 ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp,
3730 DAG.getConstant(Idx++, dl,
3731 TLI.getVectorIdxTy(DAG.getDataLayout())));
3732 StChain.push_back(DAG.getStore(
3733 Chain, dl, EOp, BasePtr, ST->getPointerInfo().getWithOffset(Offset),
3734 MinAlign(Align, Offset), MMOFlags, AAInfo));
3735 StWidth -= NewVTWidth;
3736 Offset += Increment;
3737 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3738 DAG.getConstant(Increment, dl,
3739 BasePtr.getValueType()));
3740 } while (StWidth != 0 && StWidth >= NewVTWidth);
3741 // Restore index back to be relative to the original widen element type.
3742 Idx = Idx * NewVTWidth / ValEltWidth;
3748 DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVectorImpl<SDValue> &StChain,
3750 // For extension loads, it may not be more efficient to truncate the vector
3751 // and then store it. Instead, we extract each element and then store it.
3752 SDValue Chain = ST->getChain();
3753 SDValue BasePtr = ST->getBasePtr();
3754 unsigned Align = ST->getAlignment();
3755 MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags();
3756 AAMDNodes AAInfo = ST->getAAInfo();
3757 SDValue ValOp = GetWidenedVector(ST->getValue());
3760 EVT StVT = ST->getMemoryVT();
3761 EVT ValVT = ValOp.getValueType();
3763 // It must be true that the wide vector type is bigger than where we need to
3765 assert(StVT.isVector() && ValOp.getValueType().isVector());
3766 assert(StVT.bitsLT(ValOp.getValueType()));
3768 // For truncating stores, we can not play the tricks of chopping legal vector
3769 // types and bitcast it to the right type. Instead, we unroll the store.
3770 EVT StEltVT = StVT.getVectorElementType();
3771 EVT ValEltVT = ValVT.getVectorElementType();
3772 unsigned Increment = ValEltVT.getSizeInBits() / 8;
3773 unsigned NumElts = StVT.getVectorNumElements();
3774 SDValue EOp = DAG.getNode(
3775 ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
3776 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3777 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr,
3778 ST->getPointerInfo(), StEltVT, Align,
3780 unsigned Offset = Increment;
3781 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
3782 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
3784 DAG.getConstant(Offset, dl,
3785 BasePtr.getValueType()));
3786 SDValue EOp = DAG.getNode(
3787 ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
3788 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3789 StChain.push_back(DAG.getTruncStore(
3790 Chain, dl, EOp, NewBasePtr, ST->getPointerInfo().getWithOffset(Offset),
3791 StEltVT, MinAlign(Align, Offset), MMOFlags, AAInfo));
3795 /// Modifies a vector input (widen or narrows) to a vector of NVT. The
3796 /// input vector must have the same element type as NVT.
3797 /// FillWithZeroes specifies that the vector should be widened with zeroes.
3798 SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT,
3799 bool FillWithZeroes) {
3800 // Note that InOp might have been widened so it might already have
3801 // the right width or it might need be narrowed.
3802 EVT InVT = InOp.getValueType();
3803 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
3804 "input and widen element type must match");
3807 // Check if InOp already has the right width.
3811 unsigned InNumElts = InVT.getVectorNumElements();
3812 unsigned WidenNumElts = NVT.getVectorNumElements();
3813 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
3814 unsigned NumConcat = WidenNumElts / InNumElts;
3815 SmallVector<SDValue, 16> Ops(NumConcat);
3816 SDValue FillVal = FillWithZeroes ? DAG.getConstant(0, dl, InVT) :
3819 for (unsigned i = 1; i != NumConcat; ++i)
3822 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, Ops);
3825 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
3827 ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,
3828 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3830 // Fall back to extract and build.
3831 SmallVector<SDValue, 16> Ops(WidenNumElts);
3832 EVT EltVT = NVT.getVectorElementType();
3833 unsigned MinNumElts = std::min(WidenNumElts, InNumElts);
3835 for (Idx = 0; Idx < MinNumElts; ++Idx)
3836 Ops[Idx] = DAG.getNode(
3837 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
3838 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3840 SDValue FillVal = FillWithZeroes ? DAG.getConstant(0, dl, EltVT) :
3841 DAG.getUNDEF(EltVT);
3842 for ( ; Idx < WidenNumElts; ++Idx)
3844 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, Ops);