1 //===----- ScheduleDAGRRList.cpp - Reg pressure reduction list scheduler --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements bottom-up and top-down register pressure reduction list
11 // schedulers, using standard algorithms. The basic approach uses a priority
12 // queue of available nodes to schedule. One at a time, nodes are taken from
13 // the priority queue (thus in priority order), checked for legality to
14 // schedule, and emitted if legal.
16 //===----------------------------------------------------------------------===//
18 #include "llvm/CodeGen/SchedulerRegistry.h"
19 #include "ScheduleDAGSDNodes.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/SmallSet.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
25 #include "llvm/CodeGen/SelectionDAGISel.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/InlineAsm.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/raw_ostream.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/Target/TargetLowering.h"
33 #include "llvm/Target/TargetRegisterInfo.h"
34 #include "llvm/Target/TargetSubtargetInfo.h"
38 #define DEBUG_TYPE "pre-RA-sched"
40 STATISTIC(NumBacktracks, "Number of times scheduler backtracked");
41 STATISTIC(NumUnfolds, "Number of nodes unfolded");
42 STATISTIC(NumDups, "Number of duplicated nodes");
43 STATISTIC(NumPRCopies, "Number of physical register copies");
45 static RegisterScheduler
46 burrListDAGScheduler("list-burr",
47 "Bottom-up register reduction list scheduling",
48 createBURRListDAGScheduler);
49 static RegisterScheduler
50 sourceListDAGScheduler("source",
51 "Similar to list-burr but schedules in source "
52 "order when possible",
53 createSourceListDAGScheduler);
55 static RegisterScheduler
56 hybridListDAGScheduler("list-hybrid",
57 "Bottom-up register pressure aware list scheduling "
58 "which tries to balance latency and register pressure",
59 createHybridListDAGScheduler);
61 static RegisterScheduler
62 ILPListDAGScheduler("list-ilp",
63 "Bottom-up register pressure aware list scheduling "
64 "which tries to balance ILP and register pressure",
65 createILPListDAGScheduler);
67 static cl::opt<bool> DisableSchedCycles(
68 "disable-sched-cycles", cl::Hidden, cl::init(false),
69 cl::desc("Disable cycle-level precision during preRA scheduling"));
71 // Temporary sched=list-ilp flags until the heuristics are robust.
72 // Some options are also available under sched=list-hybrid.
73 static cl::opt<bool> DisableSchedRegPressure(
74 "disable-sched-reg-pressure", cl::Hidden, cl::init(false),
75 cl::desc("Disable regpressure priority in sched=list-ilp"));
76 static cl::opt<bool> DisableSchedLiveUses(
77 "disable-sched-live-uses", cl::Hidden, cl::init(true),
78 cl::desc("Disable live use priority in sched=list-ilp"));
79 static cl::opt<bool> DisableSchedVRegCycle(
80 "disable-sched-vrcycle", cl::Hidden, cl::init(false),
81 cl::desc("Disable virtual register cycle interference checks"));
82 static cl::opt<bool> DisableSchedPhysRegJoin(
83 "disable-sched-physreg-join", cl::Hidden, cl::init(false),
84 cl::desc("Disable physreg def-use affinity"));
85 static cl::opt<bool> DisableSchedStalls(
86 "disable-sched-stalls", cl::Hidden, cl::init(true),
87 cl::desc("Disable no-stall priority in sched=list-ilp"));
88 static cl::opt<bool> DisableSchedCriticalPath(
89 "disable-sched-critical-path", cl::Hidden, cl::init(false),
90 cl::desc("Disable critical path priority in sched=list-ilp"));
91 static cl::opt<bool> DisableSchedHeight(
92 "disable-sched-height", cl::Hidden, cl::init(false),
93 cl::desc("Disable scheduled-height priority in sched=list-ilp"));
94 static cl::opt<bool> Disable2AddrHack(
95 "disable-2addr-hack", cl::Hidden, cl::init(true),
96 cl::desc("Disable scheduler's two-address hack"));
98 static cl::opt<int> MaxReorderWindow(
99 "max-sched-reorder", cl::Hidden, cl::init(6),
100 cl::desc("Number of instructions to allow ahead of the critical path "
101 "in sched=list-ilp"));
103 static cl::opt<unsigned> AvgIPC(
104 "sched-avg-ipc", cl::Hidden, cl::init(1),
105 cl::desc("Average inst/cycle whan no target itinerary exists."));
108 //===----------------------------------------------------------------------===//
109 /// ScheduleDAGRRList - The actual register reduction list scheduler
110 /// implementation. This supports both top-down and bottom-up scheduling.
112 class ScheduleDAGRRList : public ScheduleDAGSDNodes {
114 /// NeedLatency - True if the scheduler will make use of latency information.
118 /// AvailableQueue - The priority queue to use for the available SUnits.
119 SchedulingPriorityQueue *AvailableQueue;
121 /// PendingQueue - This contains all of the instructions whose operands have
122 /// been issued, but their results are not ready yet (due to the latency of
123 /// the operation). Once the operands becomes available, the instruction is
124 /// added to the AvailableQueue.
125 std::vector<SUnit*> PendingQueue;
127 /// HazardRec - The hazard recognizer to use.
128 ScheduleHazardRecognizer *HazardRec;
130 /// CurCycle - The current scheduler state corresponds to this cycle.
133 /// MinAvailableCycle - Cycle of the soonest available instruction.
134 unsigned MinAvailableCycle;
136 /// IssueCount - Count instructions issued in this cycle
137 /// Currently valid only for bottom-up scheduling.
140 /// LiveRegDefs - A set of physical registers and their definition
141 /// that are "live". These nodes must be scheduled before any other nodes that
142 /// modifies the registers can be scheduled.
143 unsigned NumLiveRegs;
144 std::unique_ptr<SUnit*[]> LiveRegDefs;
145 std::unique_ptr<SUnit*[]> LiveRegGens;
147 // Collect interferences between physical register use/defs.
148 // Each interference is an SUnit and set of physical registers.
149 SmallVector<SUnit*, 4> Interferences;
150 typedef DenseMap<SUnit*, SmallVector<unsigned, 4> > LRegsMapT;
153 /// Topo - A topological ordering for SUnits which permits fast IsReachable
154 /// and similar queries.
155 ScheduleDAGTopologicalSort Topo;
157 // Hack to keep track of the inverse of FindCallSeqStart without more crazy
159 DenseMap<SUnit*, SUnit*> CallSeqEndForStart;
162 ScheduleDAGRRList(MachineFunction &mf, bool needlatency,
163 SchedulingPriorityQueue *availqueue,
164 CodeGenOpt::Level OptLevel)
165 : ScheduleDAGSDNodes(mf),
166 NeedLatency(needlatency), AvailableQueue(availqueue), CurCycle(0),
167 Topo(SUnits, nullptr) {
169 const TargetSubtargetInfo &STI = mf.getSubtarget();
170 if (DisableSchedCycles || !NeedLatency)
171 HazardRec = new ScheduleHazardRecognizer();
173 HazardRec = STI.getInstrInfo()->CreateTargetHazardRecognizer(&STI, this);
176 ~ScheduleDAGRRList() override {
178 delete AvailableQueue;
181 void Schedule() override;
183 ScheduleHazardRecognizer *getHazardRec() { return HazardRec; }
185 /// IsReachable - Checks if SU is reachable from TargetSU.
186 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) {
187 return Topo.IsReachable(SU, TargetSU);
190 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU will
192 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) {
193 return Topo.WillCreateCycle(SU, TargetSU);
196 /// AddPred - adds a predecessor edge to SUnit SU.
197 /// This returns true if this is a new predecessor.
198 /// Updates the topological ordering if required.
199 void AddPred(SUnit *SU, const SDep &D) {
200 Topo.AddPred(SU, D.getSUnit());
204 /// RemovePred - removes a predecessor edge from SUnit SU.
205 /// This returns true if an edge was removed.
206 /// Updates the topological ordering if required.
207 void RemovePred(SUnit *SU, const SDep &D) {
208 Topo.RemovePred(SU, D.getSUnit());
213 bool isReady(SUnit *SU) {
214 return DisableSchedCycles || !AvailableQueue->hasReadyFilter() ||
215 AvailableQueue->isReady(SU);
218 void ReleasePred(SUnit *SU, const SDep *PredEdge);
219 void ReleasePredecessors(SUnit *SU);
220 void ReleasePending();
221 void AdvanceToCycle(unsigned NextCycle);
222 void AdvancePastStalls(SUnit *SU);
223 void EmitNode(SUnit *SU);
224 void ScheduleNodeBottomUp(SUnit*);
225 void CapturePred(SDep *PredEdge);
226 void UnscheduleNodeBottomUp(SUnit*);
227 void RestoreHazardCheckerBottomUp();
228 void BacktrackBottomUp(SUnit*, SUnit*);
229 SUnit *CopyAndMoveSuccessors(SUnit*);
230 void InsertCopiesAndMoveSuccs(SUnit*, unsigned,
231 const TargetRegisterClass*,
232 const TargetRegisterClass*,
233 SmallVectorImpl<SUnit*>&);
234 bool DelayForLiveRegsBottomUp(SUnit*, SmallVectorImpl<unsigned>&);
236 void releaseInterferences(unsigned Reg = 0);
238 SUnit *PickNodeToScheduleBottomUp();
239 void ListScheduleBottomUp();
241 /// CreateNewSUnit - Creates a new SUnit and returns a pointer to it.
242 /// Updates the topological ordering if required.
243 SUnit *CreateNewSUnit(SDNode *N) {
244 unsigned NumSUnits = SUnits.size();
245 SUnit *NewNode = newSUnit(N);
246 // Update the topological ordering.
247 if (NewNode->NodeNum >= NumSUnits)
248 Topo.InitDAGTopologicalSorting();
252 /// CreateClone - Creates a new SUnit from an existing one.
253 /// Updates the topological ordering if required.
254 SUnit *CreateClone(SUnit *N) {
255 unsigned NumSUnits = SUnits.size();
256 SUnit *NewNode = Clone(N);
257 // Update the topological ordering.
258 if (NewNode->NodeNum >= NumSUnits)
259 Topo.InitDAGTopologicalSorting();
263 /// forceUnitLatencies - Register-pressure-reducing scheduling doesn't
264 /// need actual latency information but the hybrid scheduler does.
265 bool forceUnitLatencies() const override {
269 } // end anonymous namespace
271 /// GetCostForDef - Looks up the register class and cost for a given definition.
272 /// Typically this just means looking up the representative register class,
273 /// but for untyped values (MVT::Untyped) it means inspecting the node's
274 /// opcode to determine what register class is being generated.
275 static void GetCostForDef(const ScheduleDAGSDNodes::RegDefIter &RegDefPos,
276 const TargetLowering *TLI,
277 const TargetInstrInfo *TII,
278 const TargetRegisterInfo *TRI,
279 unsigned &RegClass, unsigned &Cost,
280 const MachineFunction &MF) {
281 MVT VT = RegDefPos.GetValue();
283 // Special handling for untyped values. These values can only come from
284 // the expansion of custom DAG-to-DAG patterns.
285 if (VT == MVT::Untyped) {
286 const SDNode *Node = RegDefPos.GetNode();
288 // Special handling for CopyFromReg of untyped values.
289 if (!Node->isMachineOpcode() && Node->getOpcode() == ISD::CopyFromReg) {
290 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
291 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(Reg);
292 RegClass = RC->getID();
297 unsigned Opcode = Node->getMachineOpcode();
298 if (Opcode == TargetOpcode::REG_SEQUENCE) {
299 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
300 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
301 RegClass = RC->getID();
306 unsigned Idx = RegDefPos.GetIdx();
307 const MCInstrDesc Desc = TII->get(Opcode);
308 const TargetRegisterClass *RC = TII->getRegClass(Desc, Idx, TRI, MF);
309 RegClass = RC->getID();
310 // FIXME: Cost arbitrarily set to 1 because there doesn't seem to be a
311 // better way to determine it.
314 RegClass = TLI->getRepRegClassFor(VT)->getID();
315 Cost = TLI->getRepRegClassCostFor(VT);
319 /// Schedule - Schedule the DAG using list scheduling.
320 void ScheduleDAGRRList::Schedule() {
322 << "********** List Scheduling BB#" << BB->getNumber()
323 << " '" << BB->getName() << "' **********\n");
327 MinAvailableCycle = DisableSchedCycles ? 0 : UINT_MAX;
329 // Allocate slots for each physical register, plus one for a special register
330 // to track the virtual resource of a calling sequence.
331 LiveRegDefs.reset(new SUnit*[TRI->getNumRegs() + 1]());
332 LiveRegGens.reset(new SUnit*[TRI->getNumRegs() + 1]());
333 CallSeqEndForStart.clear();
334 assert(Interferences.empty() && LRegsMap.empty() && "stale Interferences");
336 // Build the scheduling graph.
337 BuildSchedGraph(nullptr);
339 DEBUG(for (SUnit &SU : SUnits)
341 Topo.InitDAGTopologicalSorting();
343 AvailableQueue->initNodes(SUnits);
347 // Execute the actual scheduling loop.
348 ListScheduleBottomUp();
350 AvailableQueue->releaseState();
353 dbgs() << "*** Final schedule ***\n";
359 //===----------------------------------------------------------------------===//
360 // Bottom-Up Scheduling
361 //===----------------------------------------------------------------------===//
363 /// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. Add it to
364 /// the AvailableQueue if the count reaches zero. Also update its cycle bound.
365 void ScheduleDAGRRList::ReleasePred(SUnit *SU, const SDep *PredEdge) {
366 SUnit *PredSU = PredEdge->getSUnit();
369 if (PredSU->NumSuccsLeft == 0) {
370 dbgs() << "*** Scheduling failed! ***\n";
372 dbgs() << " has been released too many times!\n";
373 llvm_unreachable(nullptr);
376 --PredSU->NumSuccsLeft;
378 if (!forceUnitLatencies()) {
379 // Updating predecessor's height. This is now the cycle when the
380 // predecessor can be scheduled without causing a pipeline stall.
381 PredSU->setHeightToAtLeast(SU->getHeight() + PredEdge->getLatency());
384 // If all the node's successors are scheduled, this node is ready
385 // to be scheduled. Ignore the special EntrySU node.
386 if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU) {
387 PredSU->isAvailable = true;
389 unsigned Height = PredSU->getHeight();
390 if (Height < MinAvailableCycle)
391 MinAvailableCycle = Height;
393 if (isReady(PredSU)) {
394 AvailableQueue->push(PredSU);
396 // CapturePred and others may have left the node in the pending queue, avoid
398 else if (!PredSU->isPending) {
399 PredSU->isPending = true;
400 PendingQueue.push_back(PredSU);
405 /// IsChainDependent - Test if Outer is reachable from Inner through
406 /// chain dependencies.
407 static bool IsChainDependent(SDNode *Outer, SDNode *Inner,
409 const TargetInstrInfo *TII) {
414 // For a TokenFactor, examine each operand. There may be multiple ways
415 // to get to the CALLSEQ_BEGIN, but we need to find the path with the
416 // most nesting in order to ensure that we find the corresponding match.
417 if (N->getOpcode() == ISD::TokenFactor) {
418 for (const SDValue &Op : N->op_values())
419 if (IsChainDependent(Op.getNode(), Inner, NestLevel, TII))
423 // Check for a lowered CALLSEQ_BEGIN or CALLSEQ_END.
424 if (N->isMachineOpcode()) {
425 if (N->getMachineOpcode() ==
426 (unsigned)TII->getCallFrameDestroyOpcode()) {
428 } else if (N->getMachineOpcode() ==
429 (unsigned)TII->getCallFrameSetupOpcode()) {
435 // Otherwise, find the chain and continue climbing.
436 for (const SDValue &Op : N->op_values())
437 if (Op.getValueType() == MVT::Other) {
439 goto found_chain_operand;
442 found_chain_operand:;
443 if (N->getOpcode() == ISD::EntryToken)
448 /// FindCallSeqStart - Starting from the (lowered) CALLSEQ_END node, locate
449 /// the corresponding (lowered) CALLSEQ_BEGIN node.
451 /// NestLevel and MaxNested are used in recursion to indcate the current level
452 /// of nesting of CALLSEQ_BEGIN and CALLSEQ_END pairs, as well as the maximum
453 /// level seen so far.
455 /// TODO: It would be better to give CALLSEQ_END an explicit operand to point
456 /// to the corresponding CALLSEQ_BEGIN to avoid needing to search for it.
458 FindCallSeqStart(SDNode *N, unsigned &NestLevel, unsigned &MaxNest,
459 const TargetInstrInfo *TII) {
461 // For a TokenFactor, examine each operand. There may be multiple ways
462 // to get to the CALLSEQ_BEGIN, but we need to find the path with the
463 // most nesting in order to ensure that we find the corresponding match.
464 if (N->getOpcode() == ISD::TokenFactor) {
465 SDNode *Best = nullptr;
466 unsigned BestMaxNest = MaxNest;
467 for (const SDValue &Op : N->op_values()) {
468 unsigned MyNestLevel = NestLevel;
469 unsigned MyMaxNest = MaxNest;
470 if (SDNode *New = FindCallSeqStart(Op.getNode(),
471 MyNestLevel, MyMaxNest, TII))
472 if (!Best || (MyMaxNest > BestMaxNest)) {
474 BestMaxNest = MyMaxNest;
478 MaxNest = BestMaxNest;
481 // Check for a lowered CALLSEQ_BEGIN or CALLSEQ_END.
482 if (N->isMachineOpcode()) {
483 if (N->getMachineOpcode() ==
484 (unsigned)TII->getCallFrameDestroyOpcode()) {
486 MaxNest = std::max(MaxNest, NestLevel);
487 } else if (N->getMachineOpcode() ==
488 (unsigned)TII->getCallFrameSetupOpcode()) {
489 assert(NestLevel != 0);
495 // Otherwise, find the chain and continue climbing.
496 for (const SDValue &Op : N->op_values())
497 if (Op.getValueType() == MVT::Other) {
499 goto found_chain_operand;
502 found_chain_operand:;
503 if (N->getOpcode() == ISD::EntryToken)
508 /// Call ReleasePred for each predecessor, then update register live def/gen.
509 /// Always update LiveRegDefs for a register dependence even if the current SU
510 /// also defines the register. This effectively create one large live range
511 /// across a sequence of two-address node. This is important because the
512 /// entire chain must be scheduled together. Example:
515 /// flags = (2) addc flags
516 /// flags = (1) addc flags
520 /// LiveRegDefs[flags] = 3
521 /// LiveRegGens[flags] = 1
523 /// If (2) addc is unscheduled, then (1) addc must also be unscheduled to avoid
524 /// interference on flags.
525 void ScheduleDAGRRList::ReleasePredecessors(SUnit *SU) {
526 // Bottom up: release predecessors
527 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
529 ReleasePred(SU, &*I);
530 if (I->isAssignedRegDep()) {
531 // This is a physical register dependency and it's impossible or
532 // expensive to copy the register. Make sure nothing that can
533 // clobber the register is scheduled between the predecessor and
535 SUnit *RegDef = LiveRegDefs[I->getReg()]; (void)RegDef;
536 assert((!RegDef || RegDef == SU || RegDef == I->getSUnit()) &&
537 "interference on register dependence");
538 LiveRegDefs[I->getReg()] = I->getSUnit();
539 if (!LiveRegGens[I->getReg()]) {
541 LiveRegGens[I->getReg()] = SU;
546 // If we're scheduling a lowered CALLSEQ_END, find the corresponding
547 // CALLSEQ_BEGIN. Inject an artificial physical register dependence between
548 // these nodes, to prevent other calls from being interscheduled with them.
549 unsigned CallResource = TRI->getNumRegs();
550 if (!LiveRegDefs[CallResource])
551 for (SDNode *Node = SU->getNode(); Node; Node = Node->getGluedNode())
552 if (Node->isMachineOpcode() &&
553 Node->getMachineOpcode() == (unsigned)TII->getCallFrameDestroyOpcode()) {
554 unsigned NestLevel = 0;
555 unsigned MaxNest = 0;
556 SDNode *N = FindCallSeqStart(Node, NestLevel, MaxNest, TII);
558 SUnit *Def = &SUnits[N->getNodeId()];
559 CallSeqEndForStart[Def] = SU;
562 LiveRegDefs[CallResource] = Def;
563 LiveRegGens[CallResource] = SU;
568 /// Check to see if any of the pending instructions are ready to issue. If
569 /// so, add them to the available queue.
570 void ScheduleDAGRRList::ReleasePending() {
571 if (DisableSchedCycles) {
572 assert(PendingQueue.empty() && "pending instrs not allowed in this mode");
576 // If the available queue is empty, it is safe to reset MinAvailableCycle.
577 if (AvailableQueue->empty())
578 MinAvailableCycle = UINT_MAX;
580 // Check to see if any of the pending instructions are ready to issue. If
581 // so, add them to the available queue.
582 for (unsigned i = 0, e = PendingQueue.size(); i != e; ++i) {
583 unsigned ReadyCycle = PendingQueue[i]->getHeight();
584 if (ReadyCycle < MinAvailableCycle)
585 MinAvailableCycle = ReadyCycle;
587 if (PendingQueue[i]->isAvailable) {
588 if (!isReady(PendingQueue[i]))
590 AvailableQueue->push(PendingQueue[i]);
592 PendingQueue[i]->isPending = false;
593 PendingQueue[i] = PendingQueue.back();
594 PendingQueue.pop_back();
599 /// Move the scheduler state forward by the specified number of Cycles.
600 void ScheduleDAGRRList::AdvanceToCycle(unsigned NextCycle) {
601 if (NextCycle <= CurCycle)
605 AvailableQueue->setCurCycle(NextCycle);
606 if (!HazardRec->isEnabled()) {
607 // Bypass lots of virtual calls in case of long latency.
608 CurCycle = NextCycle;
611 for (; CurCycle != NextCycle; ++CurCycle) {
612 HazardRec->RecedeCycle();
615 // FIXME: Instead of visiting the pending Q each time, set a dirty flag on the
616 // available Q to release pending nodes at least once before popping.
620 /// Move the scheduler state forward until the specified node's dependents are
621 /// ready and can be scheduled with no resource conflicts.
622 void ScheduleDAGRRList::AdvancePastStalls(SUnit *SU) {
623 if (DisableSchedCycles)
626 // FIXME: Nodes such as CopyFromReg probably should not advance the current
627 // cycle. Otherwise, we can wrongly mask real stalls. If the non-machine node
628 // has predecessors the cycle will be advanced when they are scheduled.
629 // But given the crude nature of modeling latency though such nodes, we
630 // currently need to treat these nodes like real instructions.
631 // if (!SU->getNode() || !SU->getNode()->isMachineOpcode()) return;
633 unsigned ReadyCycle = SU->getHeight();
635 // Bump CurCycle to account for latency. We assume the latency of other
636 // available instructions may be hidden by the stall (not a full pipe stall).
637 // This updates the hazard recognizer's cycle before reserving resources for
639 AdvanceToCycle(ReadyCycle);
641 // Calls are scheduled in their preceding cycle, so don't conflict with
642 // hazards from instructions after the call. EmitNode will reset the
643 // scoreboard state before emitting the call.
647 // FIXME: For resource conflicts in very long non-pipelined stages, we
648 // should probably skip ahead here to avoid useless scoreboard checks.
651 ScheduleHazardRecognizer::HazardType HT =
652 HazardRec->getHazardType(SU, -Stalls);
654 if (HT == ScheduleHazardRecognizer::NoHazard)
659 AdvanceToCycle(CurCycle + Stalls);
662 /// Record this SUnit in the HazardRecognizer.
663 /// Does not update CurCycle.
664 void ScheduleDAGRRList::EmitNode(SUnit *SU) {
665 if (!HazardRec->isEnabled())
668 // Check for phys reg copy.
672 switch (SU->getNode()->getOpcode()) {
674 assert(SU->getNode()->isMachineOpcode() &&
675 "This target-independent node should not be scheduled.");
677 case ISD::MERGE_VALUES:
678 case ISD::TokenFactor:
679 case ISD::LIFETIME_START:
680 case ISD::LIFETIME_END:
682 case ISD::CopyFromReg:
684 // Noops don't affect the scoreboard state. Copies are likely to be
688 // For inline asm, clear the pipeline state.
693 // Calls are scheduled with their preceding instructions. For bottom-up
694 // scheduling, clear the pipeline state before emitting.
698 HazardRec->EmitInstruction(SU);
701 static void resetVRegCycle(SUnit *SU);
703 /// ScheduleNodeBottomUp - Add the node to the schedule. Decrement the pending
704 /// count of its predecessors. If a predecessor pending count is zero, add it to
705 /// the Available queue.
706 void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU) {
707 DEBUG(dbgs() << "\n*** Scheduling [" << CurCycle << "]: ");
708 DEBUG(SU->dump(this));
711 if (CurCycle < SU->getHeight())
712 DEBUG(dbgs() << " Height [" << SU->getHeight()
713 << "] pipeline stall!\n");
716 // FIXME: Do not modify node height. It may interfere with
717 // backtracking. Instead add a "ready cycle" to SUnit. Before scheduling the
718 // node its ready cycle can aid heuristics, and after scheduling it can
719 // indicate the scheduled cycle.
720 SU->setHeightToAtLeast(CurCycle);
722 // Reserve resources for the scheduled instruction.
725 Sequence.push_back(SU);
727 AvailableQueue->scheduledNode(SU);
729 // If HazardRec is disabled, and each inst counts as one cycle, then
730 // advance CurCycle before ReleasePredecessors to avoid useless pushes to
731 // PendingQueue for schedulers that implement HasReadyFilter.
732 if (!HazardRec->isEnabled() && AvgIPC < 2)
733 AdvanceToCycle(CurCycle + 1);
735 // Update liveness of predecessors before successors to avoid treating a
736 // two-address node as a live range def.
737 ReleasePredecessors(SU);
739 // Release all the implicit physical register defs that are live.
740 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
742 // LiveRegDegs[I->getReg()] != SU when SU is a two-address node.
743 if (I->isAssignedRegDep() && LiveRegDefs[I->getReg()] == SU) {
744 assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!");
746 LiveRegDefs[I->getReg()] = nullptr;
747 LiveRegGens[I->getReg()] = nullptr;
748 releaseInterferences(I->getReg());
751 // Release the special call resource dependence, if this is the beginning
753 unsigned CallResource = TRI->getNumRegs();
754 if (LiveRegDefs[CallResource] == SU)
755 for (const SDNode *SUNode = SU->getNode(); SUNode;
756 SUNode = SUNode->getGluedNode()) {
757 if (SUNode->isMachineOpcode() &&
758 SUNode->getMachineOpcode() == (unsigned)TII->getCallFrameSetupOpcode()) {
759 assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!");
761 LiveRegDefs[CallResource] = nullptr;
762 LiveRegGens[CallResource] = nullptr;
763 releaseInterferences(CallResource);
769 SU->isScheduled = true;
771 // Conditions under which the scheduler should eagerly advance the cycle:
772 // (1) No available instructions
773 // (2) All pipelines full, so available instructions must have hazards.
775 // If HazardRec is disabled, the cycle was pre-advanced before calling
776 // ReleasePredecessors. In that case, IssueCount should remain 0.
778 // Check AvailableQueue after ReleasePredecessors in case of zero latency.
779 if (HazardRec->isEnabled() || AvgIPC > 1) {
780 if (SU->getNode() && SU->getNode()->isMachineOpcode())
782 if ((HazardRec->isEnabled() && HazardRec->atIssueLimit())
783 || (!HazardRec->isEnabled() && IssueCount == AvgIPC))
784 AdvanceToCycle(CurCycle + 1);
788 /// CapturePred - This does the opposite of ReleasePred. Since SU is being
789 /// unscheduled, incrcease the succ left count of its predecessors. Remove
790 /// them from AvailableQueue if necessary.
791 void ScheduleDAGRRList::CapturePred(SDep *PredEdge) {
792 SUnit *PredSU = PredEdge->getSUnit();
793 if (PredSU->isAvailable) {
794 PredSU->isAvailable = false;
795 if (!PredSU->isPending)
796 AvailableQueue->remove(PredSU);
799 assert(PredSU->NumSuccsLeft < UINT_MAX && "NumSuccsLeft will overflow!");
800 ++PredSU->NumSuccsLeft;
803 /// UnscheduleNodeBottomUp - Remove the node from the schedule, update its and
804 /// its predecessor states to reflect the change.
805 void ScheduleDAGRRList::UnscheduleNodeBottomUp(SUnit *SU) {
806 DEBUG(dbgs() << "*** Unscheduling [" << SU->getHeight() << "]: ");
807 DEBUG(SU->dump(this));
809 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
812 if (I->isAssignedRegDep() && SU == LiveRegGens[I->getReg()]){
813 assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!");
814 assert(LiveRegDefs[I->getReg()] == I->getSUnit() &&
815 "Physical register dependency violated?");
817 LiveRegDefs[I->getReg()] = nullptr;
818 LiveRegGens[I->getReg()] = nullptr;
819 releaseInterferences(I->getReg());
823 // Reclaim the special call resource dependence, if this is the beginning
825 unsigned CallResource = TRI->getNumRegs();
826 for (const SDNode *SUNode = SU->getNode(); SUNode;
827 SUNode = SUNode->getGluedNode()) {
828 if (SUNode->isMachineOpcode() &&
829 SUNode->getMachineOpcode() == (unsigned)TII->getCallFrameSetupOpcode()) {
831 LiveRegDefs[CallResource] = SU;
832 LiveRegGens[CallResource] = CallSeqEndForStart[SU];
836 // Release the special call resource dependence, if this is the end
838 if (LiveRegGens[CallResource] == SU)
839 for (const SDNode *SUNode = SU->getNode(); SUNode;
840 SUNode = SUNode->getGluedNode()) {
841 if (SUNode->isMachineOpcode() &&
842 SUNode->getMachineOpcode() == (unsigned)TII->getCallFrameDestroyOpcode()) {
843 assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!");
845 LiveRegDefs[CallResource] = nullptr;
846 LiveRegGens[CallResource] = nullptr;
847 releaseInterferences(CallResource);
851 for (auto &Succ : SU->Succs) {
852 if (Succ.isAssignedRegDep()) {
853 auto Reg = Succ.getReg();
854 if (!LiveRegDefs[Reg])
856 // This becomes the nearest def. Note that an earlier def may still be
857 // pending if this is a two-address node.
858 LiveRegDefs[Reg] = SU;
860 // Update LiveRegGen only if was empty before this unscheduling.
861 // This is to avoid incorrect updating LiveRegGen set in previous run.
862 if (!LiveRegGens[Reg]) {
863 // Find the successor with the lowest height.
864 LiveRegGens[Reg] = Succ.getSUnit();
865 for (auto &Succ2 : SU->Succs) {
866 if (Succ2.isAssignedRegDep() && Succ2.getReg() == Reg &&
867 Succ2.getSUnit()->getHeight() < LiveRegGens[Reg]->getHeight())
868 LiveRegGens[Reg] = Succ2.getSUnit();
873 if (SU->getHeight() < MinAvailableCycle)
874 MinAvailableCycle = SU->getHeight();
876 SU->setHeightDirty();
877 SU->isScheduled = false;
878 SU->isAvailable = true;
879 if (!DisableSchedCycles && AvailableQueue->hasReadyFilter()) {
880 // Don't make available until backtracking is complete.
881 SU->isPending = true;
882 PendingQueue.push_back(SU);
885 AvailableQueue->push(SU);
887 AvailableQueue->unscheduledNode(SU);
890 /// After backtracking, the hazard checker needs to be restored to a state
891 /// corresponding the current cycle.
892 void ScheduleDAGRRList::RestoreHazardCheckerBottomUp() {
895 unsigned LookAhead = std::min((unsigned)Sequence.size(),
896 HazardRec->getMaxLookAhead());
900 std::vector<SUnit*>::const_iterator I = (Sequence.end() - LookAhead);
901 unsigned HazardCycle = (*I)->getHeight();
902 for (std::vector<SUnit*>::const_iterator E = Sequence.end(); I != E; ++I) {
904 for (; SU->getHeight() > HazardCycle; ++HazardCycle) {
905 HazardRec->RecedeCycle();
911 /// BacktrackBottomUp - Backtrack scheduling to a previous cycle specified in
912 /// BTCycle in order to schedule a specific node.
913 void ScheduleDAGRRList::BacktrackBottomUp(SUnit *SU, SUnit *BtSU) {
914 SUnit *OldSU = Sequence.back();
917 // FIXME: use ready cycle instead of height
918 CurCycle = OldSU->getHeight();
919 UnscheduleNodeBottomUp(OldSU);
920 AvailableQueue->setCurCycle(CurCycle);
923 OldSU = Sequence.back();
926 assert(!SU->isSucc(OldSU) && "Something is wrong!");
928 RestoreHazardCheckerBottomUp();
935 static bool isOperandOf(const SUnit *SU, SDNode *N) {
936 for (const SDNode *SUNode = SU->getNode(); SUNode;
937 SUNode = SUNode->getGluedNode()) {
938 if (SUNode->isOperandOf(N))
944 /// CopyAndMoveSuccessors - Clone the specified node and move its scheduled
945 /// successors to the newly created node.
946 SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
947 SDNode *N = SU->getNode();
951 if (SU->getNode()->getGluedNode())
955 bool TryUnfold = false;
956 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
957 MVT VT = N->getSimpleValueType(i);
960 else if (VT == MVT::Other)
963 for (const SDValue &Op : N->op_values()) {
964 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo());
970 SmallVector<SDNode*, 2> NewNodes;
971 if (!TII->unfoldMemoryOperand(*DAG, N, NewNodes))
974 // unfolding an x86 DEC64m operation results in store, dec, load which
975 // can't be handled here so quit
976 if (NewNodes.size() == 3)
979 DEBUG(dbgs() << "Unfolding SU #" << SU->NodeNum << "\n");
980 assert(NewNodes.size() == 2 && "Expected a load folding node!");
983 SDNode *LoadNode = NewNodes[0];
984 unsigned NumVals = N->getNumValues();
985 unsigned OldNumVals = SU->getNode()->getNumValues();
986 for (unsigned i = 0; i != NumVals; ++i)
987 DAG->ReplaceAllUsesOfValueWith(SDValue(SU->getNode(), i), SDValue(N, i));
988 DAG->ReplaceAllUsesOfValueWith(SDValue(SU->getNode(), OldNumVals-1),
989 SDValue(LoadNode, 1));
991 // LoadNode may already exist. This can happen when there is another
992 // load from the same location and producing the same type of value
993 // but it has different alignment or volatileness.
994 bool isNewLoad = true;
996 if (LoadNode->getNodeId() != -1) {
997 LoadSU = &SUnits[LoadNode->getNodeId()];
1000 LoadSU = CreateNewSUnit(LoadNode);
1001 LoadNode->setNodeId(LoadSU->NodeNum);
1003 InitNumRegDefsLeft(LoadSU);
1004 computeLatency(LoadSU);
1007 SUnit *NewSU = CreateNewSUnit(N);
1008 assert(N->getNodeId() == -1 && "Node already inserted!");
1009 N->setNodeId(NewSU->NodeNum);
1011 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1012 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) {
1013 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) {
1014 NewSU->isTwoAddress = true;
1018 if (MCID.isCommutable())
1019 NewSU->isCommutable = true;
1021 InitNumRegDefsLeft(NewSU);
1022 computeLatency(NewSU);
1024 // Record all the edges to and from the old SU, by category.
1025 SmallVector<SDep, 4> ChainPreds;
1026 SmallVector<SDep, 4> ChainSuccs;
1027 SmallVector<SDep, 4> LoadPreds;
1028 SmallVector<SDep, 4> NodePreds;
1029 SmallVector<SDep, 4> NodeSuccs;
1030 for (SDep &Pred : SU->Preds) {
1032 ChainPreds.push_back(Pred);
1033 else if (isOperandOf(Pred.getSUnit(), LoadNode))
1034 LoadPreds.push_back(Pred);
1036 NodePreds.push_back(Pred);
1038 for (SDep &Succ : SU->Succs) {
1040 ChainSuccs.push_back(Succ);
1042 NodeSuccs.push_back(Succ);
1045 // Now assign edges to the newly-created nodes.
1046 for (const SDep &Pred : ChainPreds) {
1047 RemovePred(SU, Pred);
1049 AddPred(LoadSU, Pred);
1051 for (const SDep &Pred : LoadPreds) {
1052 RemovePred(SU, Pred);
1054 AddPred(LoadSU, Pred);
1056 for (const SDep &Pred : NodePreds) {
1057 RemovePred(SU, Pred);
1058 AddPred(NewSU, Pred);
1060 for (SDep D : NodeSuccs) {
1061 SUnit *SuccDep = D.getSUnit();
1063 RemovePred(SuccDep, D);
1065 AddPred(SuccDep, D);
1066 // Balance register pressure.
1067 if (AvailableQueue->tracksRegPressure() && SuccDep->isScheduled
1068 && !D.isCtrl() && NewSU->NumRegDefsLeft > 0)
1069 --NewSU->NumRegDefsLeft;
1071 for (SDep D : ChainSuccs) {
1072 SUnit *SuccDep = D.getSUnit();
1074 RemovePred(SuccDep, D);
1077 AddPred(SuccDep, D);
1081 // Add a data dependency to reflect that NewSU reads the value defined
1083 SDep D(LoadSU, SDep::Data, 0);
1084 D.setLatency(LoadSU->Latency);
1088 AvailableQueue->addNode(LoadSU);
1089 AvailableQueue->addNode(NewSU);
1093 if (NewSU->NumSuccsLeft == 0) {
1094 NewSU->isAvailable = true;
1100 DEBUG(dbgs() << " Duplicating SU #" << SU->NodeNum << "\n");
1101 NewSU = CreateClone(SU);
1103 // New SUnit has the exact same predecessors.
1104 for (SDep &Pred : SU->Preds)
1105 if (!Pred.isArtificial())
1106 AddPred(NewSU, Pred);
1108 // Only copy scheduled successors. Cut them from old node's successor
1109 // list and move them over.
1110 SmallVector<std::pair<SUnit *, SDep>, 4> DelDeps;
1111 for (SDep &Succ : SU->Succs) {
1112 if (Succ.isArtificial())
1114 SUnit *SuccSU = Succ.getSUnit();
1115 if (SuccSU->isScheduled) {
1120 DelDeps.push_back(std::make_pair(SuccSU, D));
1123 for (auto &DelDep : DelDeps)
1124 RemovePred(DelDep.first, DelDep.second);
1126 AvailableQueue->updateNode(SU);
1127 AvailableQueue->addNode(NewSU);
1133 /// InsertCopiesAndMoveSuccs - Insert register copies and move all
1134 /// scheduled successors of the given SUnit to the last copy.
1135 void ScheduleDAGRRList::InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg,
1136 const TargetRegisterClass *DestRC,
1137 const TargetRegisterClass *SrcRC,
1138 SmallVectorImpl<SUnit*> &Copies) {
1139 SUnit *CopyFromSU = CreateNewSUnit(nullptr);
1140 CopyFromSU->CopySrcRC = SrcRC;
1141 CopyFromSU->CopyDstRC = DestRC;
1143 SUnit *CopyToSU = CreateNewSUnit(nullptr);
1144 CopyToSU->CopySrcRC = DestRC;
1145 CopyToSU->CopyDstRC = SrcRC;
1147 // Only copy scheduled successors. Cut them from old node's successor
1148 // list and move them over.
1149 SmallVector<std::pair<SUnit *, SDep>, 4> DelDeps;
1150 for (SDep &Succ : SU->Succs) {
1151 if (Succ.isArtificial())
1153 SUnit *SuccSU = Succ.getSUnit();
1154 if (SuccSU->isScheduled) {
1156 D.setSUnit(CopyToSU);
1158 DelDeps.push_back(std::make_pair(SuccSU, Succ));
1161 // Avoid scheduling the def-side copy before other successors. Otherwise
1162 // we could introduce another physreg interference on the copy and
1163 // continue inserting copies indefinitely.
1164 AddPred(SuccSU, SDep(CopyFromSU, SDep::Artificial));
1167 for (auto &DelDep : DelDeps)
1168 RemovePred(DelDep.first, DelDep.second);
1170 SDep FromDep(SU, SDep::Data, Reg);
1171 FromDep.setLatency(SU->Latency);
1172 AddPred(CopyFromSU, FromDep);
1173 SDep ToDep(CopyFromSU, SDep::Data, 0);
1174 ToDep.setLatency(CopyFromSU->Latency);
1175 AddPred(CopyToSU, ToDep);
1177 AvailableQueue->updateNode(SU);
1178 AvailableQueue->addNode(CopyFromSU);
1179 AvailableQueue->addNode(CopyToSU);
1180 Copies.push_back(CopyFromSU);
1181 Copies.push_back(CopyToSU);
1186 /// getPhysicalRegisterVT - Returns the ValueType of the physical register
1187 /// definition of the specified node.
1188 /// FIXME: Move to SelectionDAG?
1189 static MVT getPhysicalRegisterVT(SDNode *N, unsigned Reg,
1190 const TargetInstrInfo *TII) {
1192 if (N->getOpcode() == ISD::CopyFromReg) {
1193 // CopyFromReg has: "chain, Val, glue" so operand 1 gives the type.
1196 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1197 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!");
1198 NumRes = MCID.getNumDefs();
1199 for (const MCPhysReg *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) {
1205 return N->getSimpleValueType(NumRes);
1208 /// CheckForLiveRegDef - Return true and update live register vector if the
1209 /// specified register def of the specified SUnit clobbers any "live" registers.
1210 static void CheckForLiveRegDef(SUnit *SU, unsigned Reg,
1211 SUnit **LiveRegDefs,
1212 SmallSet<unsigned, 4> &RegAdded,
1213 SmallVectorImpl<unsigned> &LRegs,
1214 const TargetRegisterInfo *TRI) {
1215 for (MCRegAliasIterator AliasI(Reg, TRI, true); AliasI.isValid(); ++AliasI) {
1217 // Check if Ref is live.
1218 if (!LiveRegDefs[*AliasI]) continue;
1220 // Allow multiple uses of the same def.
1221 if (LiveRegDefs[*AliasI] == SU) continue;
1223 // Add Reg to the set of interfering live regs.
1224 if (RegAdded.insert(*AliasI).second) {
1225 LRegs.push_back(*AliasI);
1230 /// CheckForLiveRegDefMasked - Check for any live physregs that are clobbered
1231 /// by RegMask, and add them to LRegs.
1232 static void CheckForLiveRegDefMasked(SUnit *SU, const uint32_t *RegMask,
1233 ArrayRef<SUnit*> LiveRegDefs,
1234 SmallSet<unsigned, 4> &RegAdded,
1235 SmallVectorImpl<unsigned> &LRegs) {
1236 // Look at all live registers. Skip Reg0 and the special CallResource.
1237 for (unsigned i = 1, e = LiveRegDefs.size()-1; i != e; ++i) {
1238 if (!LiveRegDefs[i]) continue;
1239 if (LiveRegDefs[i] == SU) continue;
1240 if (!MachineOperand::clobbersPhysReg(RegMask, i)) continue;
1241 if (RegAdded.insert(i).second)
1246 /// getNodeRegMask - Returns the register mask attached to an SDNode, if any.
1247 static const uint32_t *getNodeRegMask(const SDNode *N) {
1248 for (const SDValue &Op : N->op_values())
1249 if (const auto *RegOp = dyn_cast<RegisterMaskSDNode>(Op.getNode()))
1250 return RegOp->getRegMask();
1254 /// DelayForLiveRegsBottomUp - Returns true if it is necessary to delay
1255 /// scheduling of the given node to satisfy live physical register dependencies.
1256 /// If the specific node is the last one that's available to schedule, do
1257 /// whatever is necessary (i.e. backtracking or cloning) to make it possible.
1258 bool ScheduleDAGRRList::
1259 DelayForLiveRegsBottomUp(SUnit *SU, SmallVectorImpl<unsigned> &LRegs) {
1260 if (NumLiveRegs == 0)
1263 SmallSet<unsigned, 4> RegAdded;
1264 // If this node would clobber any "live" register, then it's not ready.
1266 // If SU is the currently live definition of the same register that it uses,
1267 // then we are free to schedule it.
1268 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
1270 if (I->isAssignedRegDep() && LiveRegDefs[I->getReg()] != SU)
1271 CheckForLiveRegDef(I->getSUnit(), I->getReg(), LiveRegDefs.get(),
1272 RegAdded, LRegs, TRI);
1275 for (SDNode *Node = SU->getNode(); Node; Node = Node->getGluedNode()) {
1276 if (Node->getOpcode() == ISD::INLINEASM) {
1277 // Inline asm can clobber physical defs.
1278 unsigned NumOps = Node->getNumOperands();
1279 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
1280 --NumOps; // Ignore the glue operand.
1282 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
1284 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
1285 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
1287 ++i; // Skip the ID value.
1288 if (InlineAsm::isRegDefKind(Flags) ||
1289 InlineAsm::isRegDefEarlyClobberKind(Flags) ||
1290 InlineAsm::isClobberKind(Flags)) {
1291 // Check for def of register or earlyclobber register.
1292 for (; NumVals; --NumVals, ++i) {
1293 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1294 if (TargetRegisterInfo::isPhysicalRegister(Reg))
1295 CheckForLiveRegDef(SU, Reg, LiveRegDefs.get(), RegAdded, LRegs, TRI);
1303 if (!Node->isMachineOpcode())
1305 // If we're in the middle of scheduling a call, don't begin scheduling
1306 // another call. Also, don't allow any physical registers to be live across
1308 if (Node->getMachineOpcode() == (unsigned)TII->getCallFrameDestroyOpcode()) {
1309 // Check the special calling-sequence resource.
1310 unsigned CallResource = TRI->getNumRegs();
1311 if (LiveRegDefs[CallResource]) {
1312 SDNode *Gen = LiveRegGens[CallResource]->getNode();
1313 while (SDNode *Glued = Gen->getGluedNode())
1315 if (!IsChainDependent(Gen, Node, 0, TII) &&
1316 RegAdded.insert(CallResource).second)
1317 LRegs.push_back(CallResource);
1320 if (const uint32_t *RegMask = getNodeRegMask(Node))
1321 CheckForLiveRegDefMasked(SU, RegMask,
1322 makeArrayRef(LiveRegDefs.get(), TRI->getNumRegs()),
1325 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
1326 if (!MCID.ImplicitDefs)
1328 for (const MCPhysReg *Reg = MCID.getImplicitDefs(); *Reg; ++Reg)
1329 CheckForLiveRegDef(SU, *Reg, LiveRegDefs.get(), RegAdded, LRegs, TRI);
1332 return !LRegs.empty();
1335 void ScheduleDAGRRList::releaseInterferences(unsigned Reg) {
1336 // Add the nodes that aren't ready back onto the available list.
1337 for (unsigned i = Interferences.size(); i > 0; --i) {
1338 SUnit *SU = Interferences[i-1];
1339 LRegsMapT::iterator LRegsPos = LRegsMap.find(SU);
1341 SmallVectorImpl<unsigned> &LRegs = LRegsPos->second;
1342 if (!is_contained(LRegs, Reg))
1345 SU->isPending = false;
1346 // The interfering node may no longer be available due to backtracking.
1347 // Furthermore, it may have been made available again, in which case it is
1348 // now already in the AvailableQueue.
1349 if (SU->isAvailable && !SU->NodeQueueId) {
1350 DEBUG(dbgs() << " Repushing SU #" << SU->NodeNum << '\n');
1351 AvailableQueue->push(SU);
1353 if (i < Interferences.size())
1354 Interferences[i-1] = Interferences.back();
1355 Interferences.pop_back();
1356 LRegsMap.erase(LRegsPos);
1360 /// Return a node that can be scheduled in this cycle. Requirements:
1361 /// (1) Ready: latency has been satisfied
1362 /// (2) No Hazards: resources are available
1363 /// (3) No Interferences: may unschedule to break register interferences.
1364 SUnit *ScheduleDAGRRList::PickNodeToScheduleBottomUp() {
1365 SUnit *CurSU = AvailableQueue->empty() ? nullptr : AvailableQueue->pop();
1367 SmallVector<unsigned, 4> LRegs;
1368 if (!DelayForLiveRegsBottomUp(CurSU, LRegs))
1370 DEBUG(dbgs() << " Interfering reg " <<
1371 (LRegs[0] == TRI->getNumRegs() ? "CallResource"
1372 : TRI->getName(LRegs[0]))
1373 << " SU #" << CurSU->NodeNum << '\n');
1374 std::pair<LRegsMapT::iterator, bool> LRegsPair =
1375 LRegsMap.insert(std::make_pair(CurSU, LRegs));
1376 if (LRegsPair.second) {
1377 CurSU->isPending = true; // This SU is not in AvailableQueue right now.
1378 Interferences.push_back(CurSU);
1381 assert(CurSU->isPending && "Interferences are pending");
1382 // Update the interference with current live regs.
1383 LRegsPair.first->second = LRegs;
1385 CurSU = AvailableQueue->pop();
1390 // All candidates are delayed due to live physical reg dependencies.
1391 // Try backtracking, code duplication, or inserting cross class copies
1393 for (SUnit *TrySU : Interferences) {
1394 SmallVectorImpl<unsigned> &LRegs = LRegsMap[TrySU];
1396 // Try unscheduling up to the point where it's safe to schedule
1398 SUnit *BtSU = nullptr;
1399 unsigned LiveCycle = UINT_MAX;
1400 for (unsigned Reg : LRegs) {
1401 if (LiveRegGens[Reg]->getHeight() < LiveCycle) {
1402 BtSU = LiveRegGens[Reg];
1403 LiveCycle = BtSU->getHeight();
1406 if (!WillCreateCycle(TrySU, BtSU)) {
1407 // BacktrackBottomUp mutates Interferences!
1408 BacktrackBottomUp(TrySU, BtSU);
1410 // Force the current node to be scheduled before the node that
1411 // requires the physical reg dep.
1412 if (BtSU->isAvailable) {
1413 BtSU->isAvailable = false;
1414 if (!BtSU->isPending)
1415 AvailableQueue->remove(BtSU);
1417 DEBUG(dbgs() << "ARTIFICIAL edge from SU(" << BtSU->NodeNum << ") to SU("
1418 << TrySU->NodeNum << ")\n");
1419 AddPred(TrySU, SDep(BtSU, SDep::Artificial));
1421 // If one or more successors has been unscheduled, then the current
1422 // node is no longer available.
1423 if (!TrySU->isAvailable || !TrySU->NodeQueueId)
1424 CurSU = AvailableQueue->pop();
1426 // Available and in AvailableQueue
1427 AvailableQueue->remove(TrySU);
1430 // Interferences has been mutated. We must break.
1436 // Can't backtrack. If it's too expensive to copy the value, then try
1437 // duplicate the nodes that produces these "too expensive to copy"
1438 // values to break the dependency. In case even that doesn't work,
1439 // insert cross class copies.
1440 // If it's not too expensive, i.e. cost != -1, issue copies.
1441 SUnit *TrySU = Interferences[0];
1442 SmallVectorImpl<unsigned> &LRegs = LRegsMap[TrySU];
1443 assert(LRegs.size() == 1 && "Can't handle this yet!");
1444 unsigned Reg = LRegs[0];
1445 SUnit *LRDef = LiveRegDefs[Reg];
1446 MVT VT = getPhysicalRegisterVT(LRDef->getNode(), Reg, TII);
1447 const TargetRegisterClass *RC =
1448 TRI->getMinimalPhysRegClass(Reg, VT);
1449 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC);
1451 // If cross copy register class is the same as RC, then it must be possible
1452 // copy the value directly. Do not try duplicate the def.
1453 // If cross copy register class is not the same as RC, then it's possible to
1454 // copy the value but it require cross register class copies and it is
1456 // If cross copy register class is null, then it's not possible to copy
1457 // the value at all.
1458 SUnit *NewDef = nullptr;
1460 NewDef = CopyAndMoveSuccessors(LRDef);
1461 if (!DestRC && !NewDef)
1462 report_fatal_error("Can't handle live physical register dependency!");
1465 // Issue copies, these can be expensive cross register class copies.
1466 SmallVector<SUnit*, 2> Copies;
1467 InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies);
1468 DEBUG(dbgs() << " Adding an edge from SU #" << TrySU->NodeNum
1469 << " to SU #" << Copies.front()->NodeNum << "\n");
1470 AddPred(TrySU, SDep(Copies.front(), SDep::Artificial));
1471 NewDef = Copies.back();
1474 DEBUG(dbgs() << " Adding an edge from SU #" << NewDef->NodeNum
1475 << " to SU #" << TrySU->NodeNum << "\n");
1476 LiveRegDefs[Reg] = NewDef;
1477 AddPred(NewDef, SDep(TrySU, SDep::Artificial));
1478 TrySU->isAvailable = false;
1481 assert(CurSU && "Unable to resolve live physical register dependencies!");
1485 /// ListScheduleBottomUp - The main loop of list scheduling for bottom-up
1487 void ScheduleDAGRRList::ListScheduleBottomUp() {
1488 // Release any predecessors of the special Exit node.
1489 ReleasePredecessors(&ExitSU);
1491 // Add root to Available queue.
1492 if (!SUnits.empty()) {
1493 SUnit *RootSU = &SUnits[DAG->getRoot().getNode()->getNodeId()];
1494 assert(RootSU->Succs.empty() && "Graph root shouldn't have successors!");
1495 RootSU->isAvailable = true;
1496 AvailableQueue->push(RootSU);
1499 // While Available queue is not empty, grab the node with the highest
1500 // priority. If it is not ready put it back. Schedule the node.
1501 Sequence.reserve(SUnits.size());
1502 while (!AvailableQueue->empty() || !Interferences.empty()) {
1503 DEBUG(dbgs() << "\nExamining Available:\n";
1504 AvailableQueue->dump(this));
1506 // Pick the best node to schedule taking all constraints into
1508 SUnit *SU = PickNodeToScheduleBottomUp();
1510 AdvancePastStalls(SU);
1512 ScheduleNodeBottomUp(SU);
1514 while (AvailableQueue->empty() && !PendingQueue.empty()) {
1515 // Advance the cycle to free resources. Skip ahead to the next ready SU.
1516 assert(MinAvailableCycle < UINT_MAX && "MinAvailableCycle uninitialized");
1517 AdvanceToCycle(std::max(CurCycle + 1, MinAvailableCycle));
1521 // Reverse the order if it is bottom up.
1522 std::reverse(Sequence.begin(), Sequence.end());
1525 VerifyScheduledSequence(/*isBottomUp=*/true);
1529 //===----------------------------------------------------------------------===//
1530 // RegReductionPriorityQueue Definition
1531 //===----------------------------------------------------------------------===//
1533 // This is a SchedulingPriorityQueue that schedules using Sethi Ullman numbers
1534 // to reduce register pressure.
1537 class RegReductionPQBase;
1539 struct queue_sort : public std::binary_function<SUnit*, SUnit*, bool> {
1540 bool isReady(SUnit* SU, unsigned CurCycle) const { return true; }
1545 struct reverse_sort : public queue_sort {
1547 reverse_sort(SF &sf) : SortFunc(sf) {}
1549 bool operator()(SUnit* left, SUnit* right) const {
1550 // reverse left/right rather than simply !SortFunc(left, right)
1551 // to expose different paths in the comparison logic.
1552 return SortFunc(right, left);
1557 /// bu_ls_rr_sort - Priority function for bottom up register pressure
1558 // reduction scheduler.
1559 struct bu_ls_rr_sort : public queue_sort {
1562 HasReadyFilter = false
1565 RegReductionPQBase *SPQ;
1566 bu_ls_rr_sort(RegReductionPQBase *spq) : SPQ(spq) {}
1568 bool operator()(SUnit* left, SUnit* right) const;
1571 // src_ls_rr_sort - Priority function for source order scheduler.
1572 struct src_ls_rr_sort : public queue_sort {
1575 HasReadyFilter = false
1578 RegReductionPQBase *SPQ;
1579 src_ls_rr_sort(RegReductionPQBase *spq)
1582 bool operator()(SUnit* left, SUnit* right) const;
1585 // hybrid_ls_rr_sort - Priority function for hybrid scheduler.
1586 struct hybrid_ls_rr_sort : public queue_sort {
1589 HasReadyFilter = false
1592 RegReductionPQBase *SPQ;
1593 hybrid_ls_rr_sort(RegReductionPQBase *spq)
1596 bool isReady(SUnit *SU, unsigned CurCycle) const;
1598 bool operator()(SUnit* left, SUnit* right) const;
1601 // ilp_ls_rr_sort - Priority function for ILP (instruction level parallelism)
1603 struct ilp_ls_rr_sort : public queue_sort {
1606 HasReadyFilter = false
1609 RegReductionPQBase *SPQ;
1610 ilp_ls_rr_sort(RegReductionPQBase *spq)
1613 bool isReady(SUnit *SU, unsigned CurCycle) const;
1615 bool operator()(SUnit* left, SUnit* right) const;
1618 class RegReductionPQBase : public SchedulingPriorityQueue {
1620 std::vector<SUnit*> Queue;
1621 unsigned CurQueueId;
1622 bool TracksRegPressure;
1625 // SUnits - The SUnits for the current graph.
1626 std::vector<SUnit> *SUnits;
1628 MachineFunction &MF;
1629 const TargetInstrInfo *TII;
1630 const TargetRegisterInfo *TRI;
1631 const TargetLowering *TLI;
1632 ScheduleDAGRRList *scheduleDAG;
1634 // SethiUllmanNumbers - The SethiUllman number for each node.
1635 std::vector<unsigned> SethiUllmanNumbers;
1637 /// RegPressure - Tracking current reg pressure per register class.
1639 std::vector<unsigned> RegPressure;
1641 /// RegLimit - Tracking the number of allocatable registers per register
1643 std::vector<unsigned> RegLimit;
1646 RegReductionPQBase(MachineFunction &mf,
1647 bool hasReadyFilter,
1650 const TargetInstrInfo *tii,
1651 const TargetRegisterInfo *tri,
1652 const TargetLowering *tli)
1653 : SchedulingPriorityQueue(hasReadyFilter),
1654 CurQueueId(0), TracksRegPressure(tracksrp), SrcOrder(srcorder),
1655 MF(mf), TII(tii), TRI(tri), TLI(tli), scheduleDAG(nullptr) {
1656 if (TracksRegPressure) {
1657 unsigned NumRC = TRI->getNumRegClasses();
1658 RegLimit.resize(NumRC);
1659 RegPressure.resize(NumRC);
1660 std::fill(RegLimit.begin(), RegLimit.end(), 0);
1661 std::fill(RegPressure.begin(), RegPressure.end(), 0);
1662 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
1663 E = TRI->regclass_end(); I != E; ++I)
1664 RegLimit[(*I)->getID()] = tri->getRegPressureLimit(*I, MF);
1668 void setScheduleDAG(ScheduleDAGRRList *scheduleDag) {
1669 scheduleDAG = scheduleDag;
1672 ScheduleHazardRecognizer* getHazardRec() {
1673 return scheduleDAG->getHazardRec();
1676 void initNodes(std::vector<SUnit> &sunits) override;
1678 void addNode(const SUnit *SU) override;
1680 void updateNode(const SUnit *SU) override;
1682 void releaseState() override {
1684 SethiUllmanNumbers.clear();
1685 std::fill(RegPressure.begin(), RegPressure.end(), 0);
1688 unsigned getNodePriority(const SUnit *SU) const;
1690 unsigned getNodeOrdering(const SUnit *SU) const {
1691 if (!SU->getNode()) return 0;
1693 return SU->getNode()->getIROrder();
1696 bool empty() const override { return Queue.empty(); }
1698 void push(SUnit *U) override {
1699 assert(!U->NodeQueueId && "Node in the queue already");
1700 U->NodeQueueId = ++CurQueueId;
1704 void remove(SUnit *SU) override {
1705 assert(!Queue.empty() && "Queue is empty!");
1706 assert(SU->NodeQueueId != 0 && "Not in queue!");
1707 std::vector<SUnit *>::iterator I = find(Queue, SU);
1708 if (I != std::prev(Queue.end()))
1709 std::swap(*I, Queue.back());
1711 SU->NodeQueueId = 0;
1714 bool tracksRegPressure() const override { return TracksRegPressure; }
1716 void dumpRegPressure() const;
1718 bool HighRegPressure(const SUnit *SU) const;
1720 bool MayReduceRegPressure(SUnit *SU) const;
1722 int RegPressureDiff(SUnit *SU, unsigned &LiveUses) const;
1724 void scheduledNode(SUnit *SU) override;
1726 void unscheduledNode(SUnit *SU) override;
1729 bool canClobber(const SUnit *SU, const SUnit *Op);
1730 void AddPseudoTwoAddrDeps();
1731 void PrescheduleNodesWithMultipleUses();
1732 void CalculateSethiUllmanNumbers();
1736 static SUnit *popFromQueueImpl(std::vector<SUnit*> &Q, SF &Picker) {
1737 std::vector<SUnit *>::iterator Best = Q.begin();
1738 for (std::vector<SUnit *>::iterator I = std::next(Q.begin()),
1739 E = Q.end(); I != E; ++I)
1740 if (Picker(*Best, *I))
1743 if (Best != std::prev(Q.end()))
1744 std::swap(*Best, Q.back());
1750 SUnit *popFromQueue(std::vector<SUnit*> &Q, SF &Picker, ScheduleDAG *DAG) {
1752 if (DAG->StressSched) {
1753 reverse_sort<SF> RPicker(Picker);
1754 return popFromQueueImpl(Q, RPicker);
1758 return popFromQueueImpl(Q, Picker);
1762 class RegReductionPriorityQueue : public RegReductionPQBase {
1766 RegReductionPriorityQueue(MachineFunction &mf,
1769 const TargetInstrInfo *tii,
1770 const TargetRegisterInfo *tri,
1771 const TargetLowering *tli)
1772 : RegReductionPQBase(mf, SF::HasReadyFilter, tracksrp, srcorder,
1776 bool isBottomUp() const override { return SF::IsBottomUp; }
1778 bool isReady(SUnit *U) const override {
1779 return Picker.HasReadyFilter && Picker.isReady(U, getCurCycle());
1782 SUnit *pop() override {
1783 if (Queue.empty()) return nullptr;
1785 SUnit *V = popFromQueue(Queue, Picker, scheduleDAG);
1790 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1791 void dump(ScheduleDAG *DAG) const override {
1792 // Emulate pop() without clobbering NodeQueueIds.
1793 std::vector<SUnit*> DumpQueue = Queue;
1794 SF DumpPicker = Picker;
1795 while (!DumpQueue.empty()) {
1796 SUnit *SU = popFromQueue(DumpQueue, DumpPicker, scheduleDAG);
1797 dbgs() << "Height " << SU->getHeight() << ": ";
1804 typedef RegReductionPriorityQueue<bu_ls_rr_sort>
1805 BURegReductionPriorityQueue;
1807 typedef RegReductionPriorityQueue<src_ls_rr_sort>
1808 SrcRegReductionPriorityQueue;
1810 typedef RegReductionPriorityQueue<hybrid_ls_rr_sort>
1811 HybridBURRPriorityQueue;
1813 typedef RegReductionPriorityQueue<ilp_ls_rr_sort>
1814 ILPBURRPriorityQueue;
1815 } // end anonymous namespace
1817 //===----------------------------------------------------------------------===//
1818 // Static Node Priority for Register Pressure Reduction
1819 //===----------------------------------------------------------------------===//
1821 // Check for special nodes that bypass scheduling heuristics.
1822 // Currently this pushes TokenFactor nodes down, but may be used for other
1823 // pseudo-ops as well.
1825 // Return -1 to schedule right above left, 1 for left above right.
1826 // Return 0 if no bias exists.
1827 static int checkSpecialNodes(const SUnit *left, const SUnit *right) {
1828 bool LSchedLow = left->isScheduleLow;
1829 bool RSchedLow = right->isScheduleLow;
1830 if (LSchedLow != RSchedLow)
1831 return LSchedLow < RSchedLow ? 1 : -1;
1835 /// CalcNodeSethiUllmanNumber - Compute Sethi Ullman number.
1836 /// Smaller number is the higher priority.
1838 CalcNodeSethiUllmanNumber(const SUnit *SU, std::vector<unsigned> &SUNumbers) {
1839 unsigned &SethiUllmanNumber = SUNumbers[SU->NodeNum];
1840 if (SethiUllmanNumber != 0)
1841 return SethiUllmanNumber;
1844 for (const SDep &Pred : SU->Preds) {
1845 if (Pred.isCtrl()) continue; // ignore chain preds
1846 SUnit *PredSU = Pred.getSUnit();
1847 unsigned PredSethiUllman = CalcNodeSethiUllmanNumber(PredSU, SUNumbers);
1848 if (PredSethiUllman > SethiUllmanNumber) {
1849 SethiUllmanNumber = PredSethiUllman;
1851 } else if (PredSethiUllman == SethiUllmanNumber)
1855 SethiUllmanNumber += Extra;
1857 if (SethiUllmanNumber == 0)
1858 SethiUllmanNumber = 1;
1860 return SethiUllmanNumber;
1863 /// CalculateSethiUllmanNumbers - Calculate Sethi-Ullman numbers of all
1864 /// scheduling units.
1865 void RegReductionPQBase::CalculateSethiUllmanNumbers() {
1866 SethiUllmanNumbers.assign(SUnits->size(), 0);
1868 for (const SUnit &SU : *SUnits)
1869 CalcNodeSethiUllmanNumber(&SU, SethiUllmanNumbers);
1872 void RegReductionPQBase::addNode(const SUnit *SU) {
1873 unsigned SUSize = SethiUllmanNumbers.size();
1874 if (SUnits->size() > SUSize)
1875 SethiUllmanNumbers.resize(SUSize*2, 0);
1876 CalcNodeSethiUllmanNumber(SU, SethiUllmanNumbers);
1879 void RegReductionPQBase::updateNode(const SUnit *SU) {
1880 SethiUllmanNumbers[SU->NodeNum] = 0;
1881 CalcNodeSethiUllmanNumber(SU, SethiUllmanNumbers);
1884 // Lower priority means schedule further down. For bottom-up scheduling, lower
1885 // priority SUs are scheduled before higher priority SUs.
1886 unsigned RegReductionPQBase::getNodePriority(const SUnit *SU) const {
1887 assert(SU->NodeNum < SethiUllmanNumbers.size());
1888 unsigned Opc = SU->getNode() ? SU->getNode()->getOpcode() : 0;
1889 if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg)
1890 // CopyToReg should be close to its uses to facilitate coalescing and
1893 if (Opc == TargetOpcode::EXTRACT_SUBREG ||
1894 Opc == TargetOpcode::SUBREG_TO_REG ||
1895 Opc == TargetOpcode::INSERT_SUBREG)
1896 // EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG nodes should be
1897 // close to their uses to facilitate coalescing.
1899 if (SU->NumSuccs == 0 && SU->NumPreds != 0)
1900 // If SU does not have a register use, i.e. it doesn't produce a value
1901 // that would be consumed (e.g. store), then it terminates a chain of
1902 // computation. Give it a large SethiUllman number so it will be
1903 // scheduled right before its predecessors that it doesn't lengthen
1904 // their live ranges.
1906 if (SU->NumPreds == 0 && SU->NumSuccs != 0)
1907 // If SU does not have a register def, schedule it close to its uses
1908 // because it does not lengthen any live ranges.
1911 return SethiUllmanNumbers[SU->NodeNum];
1913 unsigned Priority = SethiUllmanNumbers[SU->NodeNum];
1915 // FIXME: This assumes all of the defs are used as call operands.
1916 int NP = (int)Priority - SU->getNode()->getNumValues();
1917 return (NP > 0) ? NP : 0;
1923 //===----------------------------------------------------------------------===//
1924 // Register Pressure Tracking
1925 //===----------------------------------------------------------------------===//
1927 void RegReductionPQBase::dumpRegPressure() const {
1928 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1929 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
1930 E = TRI->regclass_end(); I != E; ++I) {
1931 const TargetRegisterClass *RC = *I;
1932 unsigned Id = RC->getID();
1933 unsigned RP = RegPressure[Id];
1935 DEBUG(dbgs() << TRI->getRegClassName(RC) << ": " << RP << " / "
1936 << RegLimit[Id] << '\n');
1941 bool RegReductionPQBase::HighRegPressure(const SUnit *SU) const {
1945 for (const SDep &Pred : SU->Preds) {
1948 SUnit *PredSU = Pred.getSUnit();
1949 // NumRegDefsLeft is zero when enough uses of this node have been scheduled
1950 // to cover the number of registers defined (they are all live).
1951 if (PredSU->NumRegDefsLeft == 0) {
1954 for (ScheduleDAGSDNodes::RegDefIter RegDefPos(PredSU, scheduleDAG);
1955 RegDefPos.IsValid(); RegDefPos.Advance()) {
1956 unsigned RCId, Cost;
1957 GetCostForDef(RegDefPos, TLI, TII, TRI, RCId, Cost, MF);
1959 if ((RegPressure[RCId] + Cost) >= RegLimit[RCId])
1966 bool RegReductionPQBase::MayReduceRegPressure(SUnit *SU) const {
1967 const SDNode *N = SU->getNode();
1969 if (!N->isMachineOpcode() || !SU->NumSuccs)
1972 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
1973 for (unsigned i = 0; i != NumDefs; ++i) {
1974 MVT VT = N->getSimpleValueType(i);
1975 if (!N->hasAnyUseOfValue(i))
1977 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
1978 if (RegPressure[RCId] >= RegLimit[RCId])
1984 // Compute the register pressure contribution by this instruction by count up
1985 // for uses that are not live and down for defs. Only count register classes
1986 // that are already under high pressure. As a side effect, compute the number of
1987 // uses of registers that are already live.
1989 // FIXME: This encompasses the logic in HighRegPressure and MayReduceRegPressure
1990 // so could probably be factored.
1991 int RegReductionPQBase::RegPressureDiff(SUnit *SU, unsigned &LiveUses) const {
1994 for (const SDep &Pred : SU->Preds) {
1997 SUnit *PredSU = Pred.getSUnit();
1998 // NumRegDefsLeft is zero when enough uses of this node have been scheduled
1999 // to cover the number of registers defined (they are all live).
2000 if (PredSU->NumRegDefsLeft == 0) {
2001 if (PredSU->getNode()->isMachineOpcode())
2005 for (ScheduleDAGSDNodes::RegDefIter RegDefPos(PredSU, scheduleDAG);
2006 RegDefPos.IsValid(); RegDefPos.Advance()) {
2007 MVT VT = RegDefPos.GetValue();
2008 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
2009 if (RegPressure[RCId] >= RegLimit[RCId])
2013 const SDNode *N = SU->getNode();
2015 if (!N || !N->isMachineOpcode() || !SU->NumSuccs)
2018 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
2019 for (unsigned i = 0; i != NumDefs; ++i) {
2020 MVT VT = N->getSimpleValueType(i);
2021 if (!N->hasAnyUseOfValue(i))
2023 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
2024 if (RegPressure[RCId] >= RegLimit[RCId])
2030 void RegReductionPQBase::scheduledNode(SUnit *SU) {
2031 if (!TracksRegPressure)
2037 for (const SDep &Pred : SU->Preds) {
2040 SUnit *PredSU = Pred.getSUnit();
2041 // NumRegDefsLeft is zero when enough uses of this node have been scheduled
2042 // to cover the number of registers defined (they are all live).
2043 if (PredSU->NumRegDefsLeft == 0) {
2046 // FIXME: The ScheduleDAG currently loses information about which of a
2047 // node's values is consumed by each dependence. Consequently, if the node
2048 // defines multiple register classes, we don't know which to pressurize
2049 // here. Instead the following loop consumes the register defs in an
2050 // arbitrary order. At least it handles the common case of clustered loads
2051 // to the same class. For precise liveness, each SDep needs to indicate the
2052 // result number. But that tightly couples the ScheduleDAG with the
2053 // SelectionDAG making updates tricky. A simpler hack would be to attach a
2054 // value type or register class to SDep.
2056 // The most important aspect of register tracking is balancing the increase
2057 // here with the reduction further below. Note that this SU may use multiple
2058 // defs in PredSU. The can't be determined here, but we've already
2059 // compensated by reducing NumRegDefsLeft in PredSU during
2060 // ScheduleDAGSDNodes::AddSchedEdges.
2061 --PredSU->NumRegDefsLeft;
2062 unsigned SkipRegDefs = PredSU->NumRegDefsLeft;
2063 for (ScheduleDAGSDNodes::RegDefIter RegDefPos(PredSU, scheduleDAG);
2064 RegDefPos.IsValid(); RegDefPos.Advance(), --SkipRegDefs) {
2068 unsigned RCId, Cost;
2069 GetCostForDef(RegDefPos, TLI, TII, TRI, RCId, Cost, MF);
2070 RegPressure[RCId] += Cost;
2075 // We should have this assert, but there may be dead SDNodes that never
2076 // materialize as SUnits, so they don't appear to generate liveness.
2077 //assert(SU->NumRegDefsLeft == 0 && "not all regdefs have scheduled uses");
2078 int SkipRegDefs = (int)SU->NumRegDefsLeft;
2079 for (ScheduleDAGSDNodes::RegDefIter RegDefPos(SU, scheduleDAG);
2080 RegDefPos.IsValid(); RegDefPos.Advance(), --SkipRegDefs) {
2081 if (SkipRegDefs > 0)
2083 unsigned RCId, Cost;
2084 GetCostForDef(RegDefPos, TLI, TII, TRI, RCId, Cost, MF);
2085 if (RegPressure[RCId] < Cost) {
2086 // Register pressure tracking is imprecise. This can happen. But we try
2087 // hard not to let it happen because it likely results in poor scheduling.
2088 DEBUG(dbgs() << " SU(" << SU->NodeNum << ") has too many regdefs\n");
2089 RegPressure[RCId] = 0;
2092 RegPressure[RCId] -= Cost;
2098 void RegReductionPQBase::unscheduledNode(SUnit *SU) {
2099 if (!TracksRegPressure)
2102 const SDNode *N = SU->getNode();
2105 if (!N->isMachineOpcode()) {
2106 if (N->getOpcode() != ISD::CopyToReg)
2109 unsigned Opc = N->getMachineOpcode();
2110 if (Opc == TargetOpcode::EXTRACT_SUBREG ||
2111 Opc == TargetOpcode::INSERT_SUBREG ||
2112 Opc == TargetOpcode::SUBREG_TO_REG ||
2113 Opc == TargetOpcode::REG_SEQUENCE ||
2114 Opc == TargetOpcode::IMPLICIT_DEF)
2118 for (const SDep &Pred : SU->Preds) {
2121 SUnit *PredSU = Pred.getSUnit();
2122 // NumSuccsLeft counts all deps. Don't compare it with NumSuccs which only
2123 // counts data deps.
2124 if (PredSU->NumSuccsLeft != PredSU->Succs.size())
2126 const SDNode *PN = PredSU->getNode();
2127 if (!PN->isMachineOpcode()) {
2128 if (PN->getOpcode() == ISD::CopyFromReg) {
2129 MVT VT = PN->getSimpleValueType(0);
2130 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
2131 RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
2135 unsigned POpc = PN->getMachineOpcode();
2136 if (POpc == TargetOpcode::IMPLICIT_DEF)
2138 if (POpc == TargetOpcode::EXTRACT_SUBREG ||
2139 POpc == TargetOpcode::INSERT_SUBREG ||
2140 POpc == TargetOpcode::SUBREG_TO_REG) {
2141 MVT VT = PN->getSimpleValueType(0);
2142 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
2143 RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
2146 unsigned NumDefs = TII->get(PN->getMachineOpcode()).getNumDefs();
2147 for (unsigned i = 0; i != NumDefs; ++i) {
2148 MVT VT = PN->getSimpleValueType(i);
2149 if (!PN->hasAnyUseOfValue(i))
2151 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
2152 if (RegPressure[RCId] < TLI->getRepRegClassCostFor(VT))
2153 // Register pressure tracking is imprecise. This can happen.
2154 RegPressure[RCId] = 0;
2156 RegPressure[RCId] -= TLI->getRepRegClassCostFor(VT);
2160 // Check for isMachineOpcode() as PrescheduleNodesWithMultipleUses()
2161 // may transfer data dependencies to CopyToReg.
2162 if (SU->NumSuccs && N->isMachineOpcode()) {
2163 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
2164 for (unsigned i = NumDefs, e = N->getNumValues(); i != e; ++i) {
2165 MVT VT = N->getSimpleValueType(i);
2166 if (VT == MVT::Glue || VT == MVT::Other)
2168 if (!N->hasAnyUseOfValue(i))
2170 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
2171 RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
2178 //===----------------------------------------------------------------------===//
2179 // Dynamic Node Priority for Register Pressure Reduction
2180 //===----------------------------------------------------------------------===//
2182 /// closestSucc - Returns the scheduled cycle of the successor which is
2183 /// closest to the current cycle.
2184 static unsigned closestSucc(const SUnit *SU) {
2185 unsigned MaxHeight = 0;
2186 for (const SDep &Succ : SU->Succs) {
2187 if (Succ.isCtrl()) continue; // ignore chain succs
2188 unsigned Height = Succ.getSUnit()->getHeight();
2189 // If there are bunch of CopyToRegs stacked up, they should be considered
2190 // to be at the same position.
2191 if (Succ.getSUnit()->getNode() &&
2192 Succ.getSUnit()->getNode()->getOpcode() == ISD::CopyToReg)
2193 Height = closestSucc(Succ.getSUnit())+1;
2194 if (Height > MaxHeight)
2200 /// calcMaxScratches - Returns an cost estimate of the worse case requirement
2201 /// for scratch registers, i.e. number of data dependencies.
2202 static unsigned calcMaxScratches(const SUnit *SU) {
2203 unsigned Scratches = 0;
2204 for (const SDep &Pred : SU->Preds) {
2205 if (Pred.isCtrl()) continue; // ignore chain preds
2211 /// hasOnlyLiveInOpers - Return true if SU has only value predecessors that are
2212 /// CopyFromReg from a virtual register.
2213 static bool hasOnlyLiveInOpers(const SUnit *SU) {
2214 bool RetVal = false;
2215 for (const SDep &Pred : SU->Preds) {
2216 if (Pred.isCtrl()) continue;
2217 const SUnit *PredSU = Pred.getSUnit();
2218 if (PredSU->getNode() &&
2219 PredSU->getNode()->getOpcode() == ISD::CopyFromReg) {
2221 cast<RegisterSDNode>(PredSU->getNode()->getOperand(1))->getReg();
2222 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
2232 /// hasOnlyLiveOutUses - Return true if SU has only value successors that are
2233 /// CopyToReg to a virtual register. This SU def is probably a liveout and
2234 /// it has no other use. It should be scheduled closer to the terminator.
2235 static bool hasOnlyLiveOutUses(const SUnit *SU) {
2236 bool RetVal = false;
2237 for (const SDep &Succ : SU->Succs) {
2238 if (Succ.isCtrl()) continue;
2239 const SUnit *SuccSU = Succ.getSUnit();
2240 if (SuccSU->getNode() && SuccSU->getNode()->getOpcode() == ISD::CopyToReg) {
2242 cast<RegisterSDNode>(SuccSU->getNode()->getOperand(1))->getReg();
2243 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
2253 // Set isVRegCycle for a node with only live in opers and live out uses. Also
2254 // set isVRegCycle for its CopyFromReg operands.
2256 // This is only relevant for single-block loops, in which case the VRegCycle
2257 // node is likely an induction variable in which the operand and target virtual
2258 // registers should be coalesced (e.g. pre/post increment values). Setting the
2259 // isVRegCycle flag helps the scheduler prioritize other uses of the same
2260 // CopyFromReg so that this node becomes the virtual register "kill". This
2261 // avoids interference between the values live in and out of the block and
2262 // eliminates a copy inside the loop.
2263 static void initVRegCycle(SUnit *SU) {
2264 if (DisableSchedVRegCycle)
2267 if (!hasOnlyLiveInOpers(SU) || !hasOnlyLiveOutUses(SU))
2270 DEBUG(dbgs() << "VRegCycle: SU(" << SU->NodeNum << ")\n");
2272 SU->isVRegCycle = true;
2274 for (const SDep &Pred : SU->Preds) {
2275 if (Pred.isCtrl()) continue;
2276 Pred.getSUnit()->isVRegCycle = true;
2280 // After scheduling the definition of a VRegCycle, clear the isVRegCycle flag of
2281 // CopyFromReg operands. We should no longer penalize other uses of this VReg.
2282 static void resetVRegCycle(SUnit *SU) {
2283 if (!SU->isVRegCycle)
2286 for (const SDep &Pred : SU->Preds) {
2287 if (Pred.isCtrl()) continue; // ignore chain preds
2288 SUnit *PredSU = Pred.getSUnit();
2289 if (PredSU->isVRegCycle) {
2290 assert(PredSU->getNode()->getOpcode() == ISD::CopyFromReg &&
2291 "VRegCycle def must be CopyFromReg");
2292 Pred.getSUnit()->isVRegCycle = false;
2297 // Return true if this SUnit uses a CopyFromReg node marked as a VRegCycle. This
2298 // means a node that defines the VRegCycle has not been scheduled yet.
2299 static bool hasVRegCycleUse(const SUnit *SU) {
2300 // If this SU also defines the VReg, don't hoist it as a "use".
2301 if (SU->isVRegCycle)
2304 for (const SDep &Pred : SU->Preds) {
2305 if (Pred.isCtrl()) continue; // ignore chain preds
2306 if (Pred.getSUnit()->isVRegCycle &&
2307 Pred.getSUnit()->getNode()->getOpcode() == ISD::CopyFromReg) {
2308 DEBUG(dbgs() << " VReg cycle use: SU (" << SU->NodeNum << ")\n");
2315 // Check for either a dependence (latency) or resource (hazard) stall.
2317 // Note: The ScheduleHazardRecognizer interface requires a non-const SU.
2318 static bool BUHasStall(SUnit *SU, int Height, RegReductionPQBase *SPQ) {
2319 if ((int)SPQ->getCurCycle() < Height) return true;
2320 if (SPQ->getHazardRec()->getHazardType(SU, 0)
2321 != ScheduleHazardRecognizer::NoHazard)
2326 // Return -1 if left has higher priority, 1 if right has higher priority.
2327 // Return 0 if latency-based priority is equivalent.
2328 static int BUCompareLatency(SUnit *left, SUnit *right, bool checkPref,
2329 RegReductionPQBase *SPQ) {
2330 // Scheduling an instruction that uses a VReg whose postincrement has not yet
2331 // been scheduled will induce a copy. Model this as an extra cycle of latency.
2332 int LPenalty = hasVRegCycleUse(left) ? 1 : 0;
2333 int RPenalty = hasVRegCycleUse(right) ? 1 : 0;
2334 int LHeight = (int)left->getHeight() + LPenalty;
2335 int RHeight = (int)right->getHeight() + RPenalty;
2337 bool LStall = (!checkPref || left->SchedulingPref == Sched::ILP) &&
2338 BUHasStall(left, LHeight, SPQ);
2339 bool RStall = (!checkPref || right->SchedulingPref == Sched::ILP) &&
2340 BUHasStall(right, RHeight, SPQ);
2342 // If scheduling one of the node will cause a pipeline stall, delay it.
2343 // If scheduling either one of the node will cause a pipeline stall, sort
2344 // them according to their height.
2348 if (LHeight != RHeight)
2349 return LHeight > RHeight ? 1 : -1;
2353 // If either node is scheduling for latency, sort them by height/depth
2355 if (!checkPref || (left->SchedulingPref == Sched::ILP ||
2356 right->SchedulingPref == Sched::ILP)) {
2357 // If neither instruction stalls (!LStall && !RStall) and HazardRecognizer
2358 // is enabled, grouping instructions by cycle, then its height is already
2359 // covered so only its depth matters. We also reach this point if both stall
2360 // but have the same height.
2361 if (!SPQ->getHazardRec()->isEnabled()) {
2362 if (LHeight != RHeight)
2363 return LHeight > RHeight ? 1 : -1;
2365 int LDepth = left->getDepth() - LPenalty;
2366 int RDepth = right->getDepth() - RPenalty;
2367 if (LDepth != RDepth) {
2368 DEBUG(dbgs() << " Comparing latency of SU (" << left->NodeNum
2369 << ") depth " << LDepth << " vs SU (" << right->NodeNum
2370 << ") depth " << RDepth << "\n");
2371 return LDepth < RDepth ? 1 : -1;
2373 if (left->Latency != right->Latency)
2374 return left->Latency > right->Latency ? 1 : -1;
2379 static bool BURRSort(SUnit *left, SUnit *right, RegReductionPQBase *SPQ) {
2380 // Schedule physical register definitions close to their use. This is
2381 // motivated by microarchitectures that can fuse cmp+jump macro-ops. But as
2382 // long as shortening physreg live ranges is generally good, we can defer
2383 // creating a subtarget hook.
2384 if (!DisableSchedPhysRegJoin) {
2385 bool LHasPhysReg = left->hasPhysRegDefs;
2386 bool RHasPhysReg = right->hasPhysRegDefs;
2387 if (LHasPhysReg != RHasPhysReg) {
2389 static const char *const PhysRegMsg[] = { " has no physreg",
2390 " defines a physreg" };
2392 DEBUG(dbgs() << " SU (" << left->NodeNum << ") "
2393 << PhysRegMsg[LHasPhysReg] << " SU(" << right->NodeNum << ") "
2394 << PhysRegMsg[RHasPhysReg] << "\n");
2395 return LHasPhysReg < RHasPhysReg;
2399 // Prioritize by Sethi-Ulmann number and push CopyToReg nodes down.
2400 unsigned LPriority = SPQ->getNodePriority(left);
2401 unsigned RPriority = SPQ->getNodePriority(right);
2403 // Be really careful about hoisting call operands above previous calls.
2404 // Only allows it if it would reduce register pressure.
2405 if (left->isCall && right->isCallOp) {
2406 unsigned RNumVals = right->getNode()->getNumValues();
2407 RPriority = (RPriority > RNumVals) ? (RPriority - RNumVals) : 0;
2409 if (right->isCall && left->isCallOp) {
2410 unsigned LNumVals = left->getNode()->getNumValues();
2411 LPriority = (LPriority > LNumVals) ? (LPriority - LNumVals) : 0;
2414 if (LPriority != RPriority)
2415 return LPriority > RPriority;
2417 // One or both of the nodes are calls and their sethi-ullman numbers are the
2418 // same, then keep source order.
2419 if (left->isCall || right->isCall) {
2420 unsigned LOrder = SPQ->getNodeOrdering(left);
2421 unsigned ROrder = SPQ->getNodeOrdering(right);
2423 // Prefer an ordering where the lower the non-zero order number, the higher
2425 if ((LOrder || ROrder) && LOrder != ROrder)
2426 return LOrder != 0 && (LOrder < ROrder || ROrder == 0);
2429 // Try schedule def + use closer when Sethi-Ullman numbers are the same.
2434 // and the following instructions are both ready.
2438 // Then schedule t2 = op first.
2445 // This creates more short live intervals.
2446 unsigned LDist = closestSucc(left);
2447 unsigned RDist = closestSucc(right);
2449 return LDist < RDist;
2451 // How many registers becomes live when the node is scheduled.
2452 unsigned LScratch = calcMaxScratches(left);
2453 unsigned RScratch = calcMaxScratches(right);
2454 if (LScratch != RScratch)
2455 return LScratch > RScratch;
2457 // Comparing latency against a call makes little sense unless the node
2458 // is register pressure-neutral.
2459 if ((left->isCall && RPriority > 0) || (right->isCall && LPriority > 0))
2460 return (left->NodeQueueId > right->NodeQueueId);
2462 // Do not compare latencies when one or both of the nodes are calls.
2463 if (!DisableSchedCycles &&
2464 !(left->isCall || right->isCall)) {
2465 int result = BUCompareLatency(left, right, false /*checkPref*/, SPQ);
2470 if (left->getHeight() != right->getHeight())
2471 return left->getHeight() > right->getHeight();
2473 if (left->getDepth() != right->getDepth())
2474 return left->getDepth() < right->getDepth();
2477 assert(left->NodeQueueId && right->NodeQueueId &&
2478 "NodeQueueId cannot be zero");
2479 return (left->NodeQueueId > right->NodeQueueId);
2483 bool bu_ls_rr_sort::operator()(SUnit *left, SUnit *right) const {
2484 if (int res = checkSpecialNodes(left, right))
2487 return BURRSort(left, right, SPQ);
2490 // Source order, otherwise bottom up.
2491 bool src_ls_rr_sort::operator()(SUnit *left, SUnit *right) const {
2492 if (int res = checkSpecialNodes(left, right))
2495 unsigned LOrder = SPQ->getNodeOrdering(left);
2496 unsigned ROrder = SPQ->getNodeOrdering(right);
2498 // Prefer an ordering where the lower the non-zero order number, the higher
2500 if ((LOrder || ROrder) && LOrder != ROrder)
2501 return LOrder != 0 && (LOrder < ROrder || ROrder == 0);
2503 return BURRSort(left, right, SPQ);
2506 // If the time between now and when the instruction will be ready can cover
2507 // the spill code, then avoid adding it to the ready queue. This gives long
2508 // stalls highest priority and allows hoisting across calls. It should also
2509 // speed up processing the available queue.
2510 bool hybrid_ls_rr_sort::isReady(SUnit *SU, unsigned CurCycle) const {
2511 static const unsigned ReadyDelay = 3;
2513 if (SPQ->MayReduceRegPressure(SU)) return true;
2515 if (SU->getHeight() > (CurCycle + ReadyDelay)) return false;
2517 if (SPQ->getHazardRec()->getHazardType(SU, -ReadyDelay)
2518 != ScheduleHazardRecognizer::NoHazard)
2524 // Return true if right should be scheduled with higher priority than left.
2525 bool hybrid_ls_rr_sort::operator()(SUnit *left, SUnit *right) const {
2526 if (int res = checkSpecialNodes(left, right))
2529 if (left->isCall || right->isCall)
2530 // No way to compute latency of calls.
2531 return BURRSort(left, right, SPQ);
2533 bool LHigh = SPQ->HighRegPressure(left);
2534 bool RHigh = SPQ->HighRegPressure(right);
2535 // Avoid causing spills. If register pressure is high, schedule for
2536 // register pressure reduction.
2537 if (LHigh && !RHigh) {
2538 DEBUG(dbgs() << " pressure SU(" << left->NodeNum << ") > SU("
2539 << right->NodeNum << ")\n");
2542 else if (!LHigh && RHigh) {
2543 DEBUG(dbgs() << " pressure SU(" << right->NodeNum << ") > SU("
2544 << left->NodeNum << ")\n");
2547 if (!LHigh && !RHigh) {
2548 int result = BUCompareLatency(left, right, true /*checkPref*/, SPQ);
2552 return BURRSort(left, right, SPQ);
2555 // Schedule as many instructions in each cycle as possible. So don't make an
2556 // instruction available unless it is ready in the current cycle.
2557 bool ilp_ls_rr_sort::isReady(SUnit *SU, unsigned CurCycle) const {
2558 if (SU->getHeight() > CurCycle) return false;
2560 if (SPQ->getHazardRec()->getHazardType(SU, 0)
2561 != ScheduleHazardRecognizer::NoHazard)
2567 static bool canEnableCoalescing(SUnit *SU) {
2568 unsigned Opc = SU->getNode() ? SU->getNode()->getOpcode() : 0;
2569 if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg)
2570 // CopyToReg should be close to its uses to facilitate coalescing and
2574 if (Opc == TargetOpcode::EXTRACT_SUBREG ||
2575 Opc == TargetOpcode::SUBREG_TO_REG ||
2576 Opc == TargetOpcode::INSERT_SUBREG)
2577 // EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG nodes should be
2578 // close to their uses to facilitate coalescing.
2581 if (SU->NumPreds == 0 && SU->NumSuccs != 0)
2582 // If SU does not have a register def, schedule it close to its uses
2583 // because it does not lengthen any live ranges.
2589 // list-ilp is currently an experimental scheduler that allows various
2590 // heuristics to be enabled prior to the normal register reduction logic.
2591 bool ilp_ls_rr_sort::operator()(SUnit *left, SUnit *right) const {
2592 if (int res = checkSpecialNodes(left, right))
2595 if (left->isCall || right->isCall)
2596 // No way to compute latency of calls.
2597 return BURRSort(left, right, SPQ);
2599 unsigned LLiveUses = 0, RLiveUses = 0;
2600 int LPDiff = 0, RPDiff = 0;
2601 if (!DisableSchedRegPressure || !DisableSchedLiveUses) {
2602 LPDiff = SPQ->RegPressureDiff(left, LLiveUses);
2603 RPDiff = SPQ->RegPressureDiff(right, RLiveUses);
2605 if (!DisableSchedRegPressure && LPDiff != RPDiff) {
2606 DEBUG(dbgs() << "RegPressureDiff SU(" << left->NodeNum << "): " << LPDiff
2607 << " != SU(" << right->NodeNum << "): " << RPDiff << "\n");
2608 return LPDiff > RPDiff;
2611 if (!DisableSchedRegPressure && (LPDiff > 0 || RPDiff > 0)) {
2612 bool LReduce = canEnableCoalescing(left);
2613 bool RReduce = canEnableCoalescing(right);
2614 if (LReduce && !RReduce) return false;
2615 if (RReduce && !LReduce) return true;
2618 if (!DisableSchedLiveUses && (LLiveUses != RLiveUses)) {
2619 DEBUG(dbgs() << "Live uses SU(" << left->NodeNum << "): " << LLiveUses
2620 << " != SU(" << right->NodeNum << "): " << RLiveUses << "\n");
2621 return LLiveUses < RLiveUses;
2624 if (!DisableSchedStalls) {
2625 bool LStall = BUHasStall(left, left->getHeight(), SPQ);
2626 bool RStall = BUHasStall(right, right->getHeight(), SPQ);
2627 if (LStall != RStall)
2628 return left->getHeight() > right->getHeight();
2631 if (!DisableSchedCriticalPath) {
2632 int spread = (int)left->getDepth() - (int)right->getDepth();
2633 if (std::abs(spread) > MaxReorderWindow) {
2634 DEBUG(dbgs() << "Depth of SU(" << left->NodeNum << "): "
2635 << left->getDepth() << " != SU(" << right->NodeNum << "): "
2636 << right->getDepth() << "\n");
2637 return left->getDepth() < right->getDepth();
2641 if (!DisableSchedHeight && left->getHeight() != right->getHeight()) {
2642 int spread = (int)left->getHeight() - (int)right->getHeight();
2643 if (std::abs(spread) > MaxReorderWindow)
2644 return left->getHeight() > right->getHeight();
2647 return BURRSort(left, right, SPQ);
2650 void RegReductionPQBase::initNodes(std::vector<SUnit> &sunits) {
2652 // Add pseudo dependency edges for two-address nodes.
2653 if (!Disable2AddrHack)
2654 AddPseudoTwoAddrDeps();
2655 // Reroute edges to nodes with multiple uses.
2656 if (!TracksRegPressure && !SrcOrder)
2657 PrescheduleNodesWithMultipleUses();
2658 // Calculate node priorities.
2659 CalculateSethiUllmanNumbers();
2661 // For single block loops, mark nodes that look like canonical IV increments.
2662 if (scheduleDAG->BB->isSuccessor(scheduleDAG->BB))
2663 for (SUnit &SU : sunits)
2667 //===----------------------------------------------------------------------===//
2668 // Preschedule for Register Pressure
2669 //===----------------------------------------------------------------------===//
2671 bool RegReductionPQBase::canClobber(const SUnit *SU, const SUnit *Op) {
2672 if (SU->isTwoAddress) {
2673 unsigned Opc = SU->getNode()->getMachineOpcode();
2674 const MCInstrDesc &MCID = TII->get(Opc);
2675 unsigned NumRes = MCID.getNumDefs();
2676 unsigned NumOps = MCID.getNumOperands() - NumRes;
2677 for (unsigned i = 0; i != NumOps; ++i) {
2678 if (MCID.getOperandConstraint(i+NumRes, MCOI::TIED_TO) != -1) {
2679 SDNode *DU = SU->getNode()->getOperand(i).getNode();
2680 if (DU->getNodeId() != -1 &&
2681 Op->OrigNode == &(*SUnits)[DU->getNodeId()])
2689 /// canClobberReachingPhysRegUse - True if SU would clobber one of it's
2690 /// successor's explicit physregs whose definition can reach DepSU.
2691 /// i.e. DepSU should not be scheduled above SU.
2692 static bool canClobberReachingPhysRegUse(const SUnit *DepSU, const SUnit *SU,
2693 ScheduleDAGRRList *scheduleDAG,
2694 const TargetInstrInfo *TII,
2695 const TargetRegisterInfo *TRI) {
2696 const MCPhysReg *ImpDefs
2697 = TII->get(SU->getNode()->getMachineOpcode()).getImplicitDefs();
2698 const uint32_t *RegMask = getNodeRegMask(SU->getNode());
2699 if(!ImpDefs && !RegMask)
2702 for (const SDep &Succ : SU->Succs) {
2703 SUnit *SuccSU = Succ.getSUnit();
2704 for (const SDep &SuccPred : SuccSU->Preds) {
2705 if (!SuccPred.isAssignedRegDep())
2709 MachineOperand::clobbersPhysReg(RegMask, SuccPred.getReg()) &&
2710 scheduleDAG->IsReachable(DepSU, SuccPred.getSUnit()))
2714 for (const MCPhysReg *ImpDef = ImpDefs; *ImpDef; ++ImpDef)
2715 // Return true if SU clobbers this physical register use and the
2716 // definition of the register reaches from DepSU. IsReachable queries
2717 // a topological forward sort of the DAG (following the successors).
2718 if (TRI->regsOverlap(*ImpDef, SuccPred.getReg()) &&
2719 scheduleDAG->IsReachable(DepSU, SuccPred.getSUnit()))
2726 /// canClobberPhysRegDefs - True if SU would clobber one of SuccSU's
2727 /// physical register defs.
2728 static bool canClobberPhysRegDefs(const SUnit *SuccSU, const SUnit *SU,
2729 const TargetInstrInfo *TII,
2730 const TargetRegisterInfo *TRI) {
2731 SDNode *N = SuccSU->getNode();
2732 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
2733 const MCPhysReg *ImpDefs = TII->get(N->getMachineOpcode()).getImplicitDefs();
2734 assert(ImpDefs && "Caller should check hasPhysRegDefs");
2735 for (const SDNode *SUNode = SU->getNode(); SUNode;
2736 SUNode = SUNode->getGluedNode()) {
2737 if (!SUNode->isMachineOpcode())
2739 const MCPhysReg *SUImpDefs =
2740 TII->get(SUNode->getMachineOpcode()).getImplicitDefs();
2741 const uint32_t *SURegMask = getNodeRegMask(SUNode);
2742 if (!SUImpDefs && !SURegMask)
2744 for (unsigned i = NumDefs, e = N->getNumValues(); i != e; ++i) {
2745 MVT VT = N->getSimpleValueType(i);
2746 if (VT == MVT::Glue || VT == MVT::Other)
2748 if (!N->hasAnyUseOfValue(i))
2750 unsigned Reg = ImpDefs[i - NumDefs];
2751 if (SURegMask && MachineOperand::clobbersPhysReg(SURegMask, Reg))
2755 for (;*SUImpDefs; ++SUImpDefs) {
2756 unsigned SUReg = *SUImpDefs;
2757 if (TRI->regsOverlap(Reg, SUReg))
2765 /// PrescheduleNodesWithMultipleUses - Nodes with multiple uses
2766 /// are not handled well by the general register pressure reduction
2767 /// heuristics. When presented with code like this:
2776 /// the heuristics tend to push the store up, but since the
2777 /// operand of the store has another use (U), this would increase
2778 /// the length of that other use (the U->N edge).
2780 /// This function transforms code like the above to route U's
2781 /// dependence through the store when possible, like this:
2792 /// This results in the store being scheduled immediately
2793 /// after N, which shortens the U->N live range, reducing
2794 /// register pressure.
2796 void RegReductionPQBase::PrescheduleNodesWithMultipleUses() {
2797 // Visit all the nodes in topological order, working top-down.
2798 for (SUnit &SU : *SUnits) {
2799 // For now, only look at nodes with no data successors, such as stores.
2800 // These are especially important, due to the heuristics in
2801 // getNodePriority for nodes with no data successors.
2802 if (SU.NumSuccs != 0)
2804 // For now, only look at nodes with exactly one data predecessor.
2805 if (SU.NumPreds != 1)
2807 // Avoid prescheduling copies to virtual registers, which don't behave
2808 // like other nodes from the perspective of scheduling heuristics.
2809 if (SDNode *N = SU.getNode())
2810 if (N->getOpcode() == ISD::CopyToReg &&
2811 TargetRegisterInfo::isVirtualRegister
2812 (cast<RegisterSDNode>(N->getOperand(1))->getReg()))
2815 // Locate the single data predecessor.
2816 SUnit *PredSU = nullptr;
2817 for (const SDep &Pred : SU.Preds)
2818 if (!Pred.isCtrl()) {
2819 PredSU = Pred.getSUnit();
2824 // Don't rewrite edges that carry physregs, because that requires additional
2825 // support infrastructure.
2826 if (PredSU->hasPhysRegDefs)
2828 // Short-circuit the case where SU is PredSU's only data successor.
2829 if (PredSU->NumSuccs == 1)
2831 // Avoid prescheduling to copies from virtual registers, which don't behave
2832 // like other nodes from the perspective of scheduling heuristics.
2833 if (SDNode *N = SU.getNode())
2834 if (N->getOpcode() == ISD::CopyFromReg &&
2835 TargetRegisterInfo::isVirtualRegister
2836 (cast<RegisterSDNode>(N->getOperand(1))->getReg()))
2839 // Perform checks on the successors of PredSU.
2840 for (const SDep &PredSucc : PredSU->Succs) {
2841 SUnit *PredSuccSU = PredSucc.getSUnit();
2842 if (PredSuccSU == &SU) continue;
2843 // If PredSU has another successor with no data successors, for
2844 // now don't attempt to choose either over the other.
2845 if (PredSuccSU->NumSuccs == 0)
2846 goto outer_loop_continue;
2847 // Don't break physical register dependencies.
2848 if (SU.hasPhysRegClobbers && PredSuccSU->hasPhysRegDefs)
2849 if (canClobberPhysRegDefs(PredSuccSU, &SU, TII, TRI))
2850 goto outer_loop_continue;
2851 // Don't introduce graph cycles.
2852 if (scheduleDAG->IsReachable(&SU, PredSuccSU))
2853 goto outer_loop_continue;
2856 // Ok, the transformation is safe and the heuristics suggest it is
2857 // profitable. Update the graph.
2858 DEBUG(dbgs() << " Prescheduling SU #" << SU.NodeNum
2859 << " next to PredSU #" << PredSU->NodeNum
2860 << " to guide scheduling in the presence of multiple uses\n");
2861 for (unsigned i = 0; i != PredSU->Succs.size(); ++i) {
2862 SDep Edge = PredSU->Succs[i];
2863 assert(!Edge.isAssignedRegDep());
2864 SUnit *SuccSU = Edge.getSUnit();
2865 if (SuccSU != &SU) {
2866 Edge.setSUnit(PredSU);
2867 scheduleDAG->RemovePred(SuccSU, Edge);
2868 scheduleDAG->AddPred(&SU, Edge);
2870 scheduleDAG->AddPred(SuccSU, Edge);
2874 outer_loop_continue:;
2878 /// AddPseudoTwoAddrDeps - If two nodes share an operand and one of them uses
2879 /// it as a def&use operand. Add a pseudo control edge from it to the other
2880 /// node (if it won't create a cycle) so the two-address one will be scheduled
2881 /// first (lower in the schedule). If both nodes are two-address, favor the
2882 /// one that has a CopyToReg use (more likely to be a loop induction update).
2883 /// If both are two-address, but one is commutable while the other is not
2884 /// commutable, favor the one that's not commutable.
2885 void RegReductionPQBase::AddPseudoTwoAddrDeps() {
2886 for (SUnit &SU : *SUnits) {
2887 if (!SU.isTwoAddress)
2890 SDNode *Node = SU.getNode();
2891 if (!Node || !Node->isMachineOpcode() || SU.getNode()->getGluedNode())
2894 bool isLiveOut = hasOnlyLiveOutUses(&SU);
2895 unsigned Opc = Node->getMachineOpcode();
2896 const MCInstrDesc &MCID = TII->get(Opc);
2897 unsigned NumRes = MCID.getNumDefs();
2898 unsigned NumOps = MCID.getNumOperands() - NumRes;
2899 for (unsigned j = 0; j != NumOps; ++j) {
2900 if (MCID.getOperandConstraint(j+NumRes, MCOI::TIED_TO) == -1)
2902 SDNode *DU = SU.getNode()->getOperand(j).getNode();
2903 if (DU->getNodeId() == -1)
2905 const SUnit *DUSU = &(*SUnits)[DU->getNodeId()];
2908 for (const SDep &Succ : DUSU->Succs) {
2911 SUnit *SuccSU = Succ.getSUnit();
2914 // Be conservative. Ignore if nodes aren't at roughly the same
2915 // depth and height.
2916 if (SuccSU->getHeight() < SU.getHeight() &&
2917 (SU.getHeight() - SuccSU->getHeight()) > 1)
2919 // Skip past COPY_TO_REGCLASS nodes, so that the pseudo edge
2920 // constrains whatever is using the copy, instead of the copy
2921 // itself. In the case that the copy is coalesced, this
2922 // preserves the intent of the pseudo two-address heurietics.
2923 while (SuccSU->Succs.size() == 1 &&
2924 SuccSU->getNode()->isMachineOpcode() &&
2925 SuccSU->getNode()->getMachineOpcode() ==
2926 TargetOpcode::COPY_TO_REGCLASS)
2927 SuccSU = SuccSU->Succs.front().getSUnit();
2928 // Don't constrain non-instruction nodes.
2929 if (!SuccSU->getNode() || !SuccSU->getNode()->isMachineOpcode())
2931 // Don't constrain nodes with physical register defs if the
2932 // predecessor can clobber them.
2933 if (SuccSU->hasPhysRegDefs && SU.hasPhysRegClobbers) {
2934 if (canClobberPhysRegDefs(SuccSU, &SU, TII, TRI))
2937 // Don't constrain EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG;
2938 // these may be coalesced away. We want them close to their uses.
2939 unsigned SuccOpc = SuccSU->getNode()->getMachineOpcode();
2940 if (SuccOpc == TargetOpcode::EXTRACT_SUBREG ||
2941 SuccOpc == TargetOpcode::INSERT_SUBREG ||
2942 SuccOpc == TargetOpcode::SUBREG_TO_REG)
2944 if (!canClobberReachingPhysRegUse(SuccSU, &SU, scheduleDAG, TII, TRI) &&
2945 (!canClobber(SuccSU, DUSU) ||
2946 (isLiveOut && !hasOnlyLiveOutUses(SuccSU)) ||
2947 (!SU.isCommutable && SuccSU->isCommutable)) &&
2948 !scheduleDAG->IsReachable(SuccSU, &SU)) {
2949 DEBUG(dbgs() << " Adding a pseudo-two-addr edge from SU #"
2950 << SU.NodeNum << " to SU #" << SuccSU->NodeNum << "\n");
2951 scheduleDAG->AddPred(&SU, SDep(SuccSU, SDep::Artificial));
2958 //===----------------------------------------------------------------------===//
2959 // Public Constructor Functions
2960 //===----------------------------------------------------------------------===//
2962 llvm::ScheduleDAGSDNodes *
2963 llvm::createBURRListDAGScheduler(SelectionDAGISel *IS,
2964 CodeGenOpt::Level OptLevel) {
2965 const TargetSubtargetInfo &STI = IS->MF->getSubtarget();
2966 const TargetInstrInfo *TII = STI.getInstrInfo();
2967 const TargetRegisterInfo *TRI = STI.getRegisterInfo();
2969 BURegReductionPriorityQueue *PQ =
2970 new BURegReductionPriorityQueue(*IS->MF, false, false, TII, TRI, nullptr);
2971 ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, false, PQ, OptLevel);
2972 PQ->setScheduleDAG(SD);
2976 llvm::ScheduleDAGSDNodes *
2977 llvm::createSourceListDAGScheduler(SelectionDAGISel *IS,
2978 CodeGenOpt::Level OptLevel) {
2979 const TargetSubtargetInfo &STI = IS->MF->getSubtarget();
2980 const TargetInstrInfo *TII = STI.getInstrInfo();
2981 const TargetRegisterInfo *TRI = STI.getRegisterInfo();
2983 SrcRegReductionPriorityQueue *PQ =
2984 new SrcRegReductionPriorityQueue(*IS->MF, false, true, TII, TRI, nullptr);
2985 ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, false, PQ, OptLevel);
2986 PQ->setScheduleDAG(SD);
2990 llvm::ScheduleDAGSDNodes *
2991 llvm::createHybridListDAGScheduler(SelectionDAGISel *IS,
2992 CodeGenOpt::Level OptLevel) {
2993 const TargetSubtargetInfo &STI = IS->MF->getSubtarget();
2994 const TargetInstrInfo *TII = STI.getInstrInfo();
2995 const TargetRegisterInfo *TRI = STI.getRegisterInfo();
2996 const TargetLowering *TLI = IS->TLI;
2998 HybridBURRPriorityQueue *PQ =
2999 new HybridBURRPriorityQueue(*IS->MF, true, false, TII, TRI, TLI);
3001 ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, true, PQ, OptLevel);
3002 PQ->setScheduleDAG(SD);
3006 llvm::ScheduleDAGSDNodes *
3007 llvm::createILPListDAGScheduler(SelectionDAGISel *IS,
3008 CodeGenOpt::Level OptLevel) {
3009 const TargetSubtargetInfo &STI = IS->MF->getSubtarget();
3010 const TargetInstrInfo *TII = STI.getInstrInfo();
3011 const TargetRegisterInfo *TRI = STI.getRegisterInfo();
3012 const TargetLowering *TLI = IS->TLI;
3014 ILPBURRPriorityQueue *PQ =
3015 new ILPBURRPriorityQueue(*IS->MF, true, false, TII, TRI, TLI);
3016 ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, true, PQ, OptLevel);
3017 PQ->setScheduleDAG(SD);