1 //===--- ScheduleDAGSDNodes.cpp - Implement the ScheduleDAGSDNodes class --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the ScheduleDAG class, which is a base class used by
11 // scheduling implementation classes.
13 //===----------------------------------------------------------------------===//
15 #include "ScheduleDAGSDNodes.h"
16 #include "InstrEmitter.h"
17 #include "SDNodeDbgValue.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/SmallPtrSet.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/CodeGen/TargetInstrInfo.h"
27 #include "llvm/CodeGen/TargetLowering.h"
28 #include "llvm/CodeGen/TargetRegisterInfo.h"
29 #include "llvm/CodeGen/TargetSubtargetInfo.h"
30 #include "llvm/MC/MCInstrItineraries.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/raw_ostream.h"
36 #define DEBUG_TYPE "pre-RA-sched"
38 STATISTIC(LoadsClustered, "Number of loads clustered together");
40 // This allows the latency-based scheduler to notice high latency instructions
41 // without a target itinerary. The choice of number here has more to do with
42 // balancing scheduler heuristics than with the actual machine latency.
43 static cl::opt<int> HighLatencyCycles(
44 "sched-high-latency-cycles", cl::Hidden, cl::init(10),
45 cl::desc("Roughly estimate the number of cycles that 'long latency'"
46 "instructions take for targets with no itinerary"));
48 ScheduleDAGSDNodes::ScheduleDAGSDNodes(MachineFunction &mf)
49 : ScheduleDAG(mf), BB(nullptr), DAG(nullptr),
50 InstrItins(mf.getSubtarget().getInstrItineraryData()) {}
52 /// Run - perform scheduling.
54 void ScheduleDAGSDNodes::Run(SelectionDAG *dag, MachineBasicBlock *bb) {
58 // Clear the scheduler's SUnit DAG.
59 ScheduleDAG::clearDAG();
62 // Invoke the target's selection of scheduler.
66 /// NewSUnit - Creates a new SUnit and return a ptr to it.
68 SUnit *ScheduleDAGSDNodes::newSUnit(SDNode *N) {
70 const SUnit *Addr = nullptr;
74 SUnits.emplace_back(N, (unsigned)SUnits.size());
75 assert((Addr == nullptr || Addr == &SUnits[0]) &&
76 "SUnits std::vector reallocated on the fly!");
77 SUnits.back().OrigNode = &SUnits.back();
78 SUnit *SU = &SUnits.back();
79 const TargetLowering &TLI = DAG->getTargetLoweringInfo();
81 (N->isMachineOpcode() &&
82 N->getMachineOpcode() == TargetOpcode::IMPLICIT_DEF))
83 SU->SchedulingPref = Sched::None;
85 SU->SchedulingPref = TLI.getSchedulingPreference(N);
89 SUnit *ScheduleDAGSDNodes::Clone(SUnit *Old) {
90 SUnit *SU = newSUnit(Old->getNode());
91 SU->OrigNode = Old->OrigNode;
92 SU->Latency = Old->Latency;
93 SU->isVRegCycle = Old->isVRegCycle;
94 SU->isCall = Old->isCall;
95 SU->isCallOp = Old->isCallOp;
96 SU->isTwoAddress = Old->isTwoAddress;
97 SU->isCommutable = Old->isCommutable;
98 SU->hasPhysRegDefs = Old->hasPhysRegDefs;
99 SU->hasPhysRegClobbers = Old->hasPhysRegClobbers;
100 SU->isScheduleHigh = Old->isScheduleHigh;
101 SU->isScheduleLow = Old->isScheduleLow;
102 SU->SchedulingPref = Old->SchedulingPref;
103 Old->isCloned = true;
107 /// CheckForPhysRegDependency - Check if the dependency between def and use of
108 /// a specified operand is a physical register dependency. If so, returns the
109 /// register and the cost of copying the register.
110 static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op,
111 const TargetRegisterInfo *TRI,
112 const TargetInstrInfo *TII,
113 unsigned &PhysReg, int &Cost) {
114 if (Op != 2 || User->getOpcode() != ISD::CopyToReg)
117 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
118 if (TargetRegisterInfo::isVirtualRegister(Reg))
121 unsigned ResNo = User->getOperand(2).getResNo();
122 if (Def->getOpcode() == ISD::CopyFromReg &&
123 cast<RegisterSDNode>(Def->getOperand(1))->getReg() == Reg) {
125 } else if (Def->isMachineOpcode()) {
126 const MCInstrDesc &II = TII->get(Def->getMachineOpcode());
127 if (ResNo >= II.getNumDefs() &&
128 II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg)
133 const TargetRegisterClass *RC =
134 TRI->getMinimalPhysRegClass(Reg, Def->getSimpleValueType(ResNo));
135 Cost = RC->getCopyCost();
139 // Helper for AddGlue to clone node operands.
140 static void CloneNodeWithValues(SDNode *N, SelectionDAG *DAG, ArrayRef<EVT> VTs,
141 SDValue ExtraOper = SDValue()) {
142 SmallVector<SDValue, 8> Ops(N->op_begin(), N->op_end());
143 if (ExtraOper.getNode())
144 Ops.push_back(ExtraOper);
146 SDVTList VTList = DAG->getVTList(VTs);
147 MachineSDNode::mmo_iterator Begin = nullptr, End = nullptr;
148 MachineSDNode *MN = dyn_cast<MachineSDNode>(N);
150 // Store memory references.
152 Begin = MN->memoperands_begin();
153 End = MN->memoperands_end();
156 DAG->MorphNodeTo(N, N->getOpcode(), VTList, Ops);
158 // Reset the memory references
160 MN->setMemRefs(Begin, End);
163 static bool AddGlue(SDNode *N, SDValue Glue, bool AddGlue, SelectionDAG *DAG) {
164 SDNode *GlueDestNode = Glue.getNode();
166 // Don't add glue from a node to itself.
167 if (GlueDestNode == N) return false;
169 // Don't add a glue operand to something that already uses glue.
171 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) {
174 // Don't add glue to something that already has a glue value.
175 if (N->getValueType(N->getNumValues() - 1) == MVT::Glue) return false;
177 SmallVector<EVT, 4> VTs(N->value_begin(), N->value_end());
179 VTs.push_back(MVT::Glue);
181 CloneNodeWithValues(N, DAG, VTs, Glue);
186 // Cleanup after unsuccessful AddGlue. Use the standard method of morphing the
187 // node even though simply shrinking the value list is sufficient.
188 static void RemoveUnusedGlue(SDNode *N, SelectionDAG *DAG) {
189 assert((N->getValueType(N->getNumValues() - 1) == MVT::Glue &&
190 !N->hasAnyUseOfValue(N->getNumValues() - 1)) &&
191 "expected an unused glue value");
193 CloneNodeWithValues(N, DAG,
194 makeArrayRef(N->value_begin(), N->getNumValues() - 1));
197 /// ClusterNeighboringLoads - Force nearby loads together by "gluing" them.
198 /// This function finds loads of the same base and different offsets. If the
199 /// offsets are not far apart (target specific), it add MVT::Glue inputs and
200 /// outputs to ensure they are scheduled together and in order. This
201 /// optimization may benefit some targets by improving cache locality.
202 void ScheduleDAGSDNodes::ClusterNeighboringLoads(SDNode *Node) {
203 SDNode *Chain = nullptr;
204 unsigned NumOps = Node->getNumOperands();
205 if (Node->getOperand(NumOps-1).getValueType() == MVT::Other)
206 Chain = Node->getOperand(NumOps-1).getNode();
210 // Look for other loads of the same chain. Find loads that are loading from
211 // the same base pointer and different offsets.
212 SmallPtrSet<SDNode*, 16> Visited;
213 SmallVector<int64_t, 4> Offsets;
214 DenseMap<long long, SDNode*> O2SMap; // Map from offset to SDNode.
215 bool Cluster = false;
217 // This algorithm requires a reasonably low use count before finding a match
218 // to avoid uselessly blowing up compile time in large blocks.
219 unsigned UseCount = 0;
220 for (SDNode::use_iterator I = Chain->use_begin(), E = Chain->use_end();
221 I != E && UseCount < 100; ++I, ++UseCount) {
223 if (User == Node || !Visited.insert(User).second)
225 int64_t Offset1, Offset2;
226 if (!TII->areLoadsFromSameBasePtr(Base, User, Offset1, Offset2) ||
228 // FIXME: Should be ok if they addresses are identical. But earlier
229 // optimizations really should have eliminated one of the loads.
231 if (O2SMap.insert(std::make_pair(Offset1, Base)).second)
232 Offsets.push_back(Offset1);
233 O2SMap.insert(std::make_pair(Offset2, User));
234 Offsets.push_back(Offset2);
235 if (Offset2 < Offset1)
238 // Reset UseCount to allow more matches.
245 // Sort them in increasing order.
246 std::sort(Offsets.begin(), Offsets.end());
248 // Check if the loads are close enough.
249 SmallVector<SDNode*, 4> Loads;
250 unsigned NumLoads = 0;
251 int64_t BaseOff = Offsets[0];
252 SDNode *BaseLoad = O2SMap[BaseOff];
253 Loads.push_back(BaseLoad);
254 for (unsigned i = 1, e = Offsets.size(); i != e; ++i) {
255 int64_t Offset = Offsets[i];
256 SDNode *Load = O2SMap[Offset];
257 if (!TII->shouldScheduleLoadsNear(BaseLoad, Load, BaseOff, Offset,NumLoads))
258 break; // Stop right here. Ignore loads that are further away.
259 Loads.push_back(Load);
266 // Cluster loads by adding MVT::Glue outputs and inputs. This also
267 // ensure they are scheduled in order of increasing addresses.
268 SDNode *Lead = Loads[0];
269 SDValue InGlue = SDValue(nullptr, 0);
270 if (AddGlue(Lead, InGlue, true, DAG))
271 InGlue = SDValue(Lead, Lead->getNumValues() - 1);
272 for (unsigned I = 1, E = Loads.size(); I != E; ++I) {
273 bool OutGlue = I < E - 1;
274 SDNode *Load = Loads[I];
276 // If AddGlue fails, we could leave an unsused glue value. This should not
278 if (AddGlue(Load, InGlue, OutGlue, DAG)) {
280 InGlue = SDValue(Load, Load->getNumValues() - 1);
284 else if (!OutGlue && InGlue.getNode())
285 RemoveUnusedGlue(InGlue.getNode(), DAG);
289 /// ClusterNodes - Cluster certain nodes which should be scheduled together.
291 void ScheduleDAGSDNodes::ClusterNodes() {
292 for (SDNode &NI : DAG->allnodes()) {
294 if (!Node || !Node->isMachineOpcode())
297 unsigned Opc = Node->getMachineOpcode();
298 const MCInstrDesc &MCID = TII->get(Opc);
300 // Cluster loads from "near" addresses into combined SUnits.
301 ClusterNeighboringLoads(Node);
305 void ScheduleDAGSDNodes::BuildSchedUnits() {
306 // During scheduling, the NodeId field of SDNode is used to map SDNodes
307 // to their associated SUnits by holding SUnits table indices. A value
308 // of -1 means the SDNode does not yet have an associated SUnit.
309 unsigned NumNodes = 0;
310 for (SDNode &NI : DAG->allnodes()) {
315 // Reserve entries in the vector for each of the SUnits we are creating. This
316 // ensure that reallocation of the vector won't happen, so SUnit*'s won't get
318 // FIXME: Multiply by 2 because we may clone nodes during scheduling.
319 // This is a temporary workaround.
320 SUnits.reserve(NumNodes * 2);
322 // Add all nodes in depth first order.
323 SmallVector<SDNode*, 64> Worklist;
324 SmallPtrSet<SDNode*, 32> Visited;
325 Worklist.push_back(DAG->getRoot().getNode());
326 Visited.insert(DAG->getRoot().getNode());
328 SmallVector<SUnit*, 8> CallSUnits;
329 while (!Worklist.empty()) {
330 SDNode *NI = Worklist.pop_back_val();
332 // Add all operands to the worklist unless they've already been added.
333 for (const SDValue &Op : NI->op_values())
334 if (Visited.insert(Op.getNode()).second)
335 Worklist.push_back(Op.getNode());
337 if (isPassiveNode(NI)) // Leaf node, e.g. a TargetImmediate.
340 // If this node has already been processed, stop now.
341 if (NI->getNodeId() != -1) continue;
343 SUnit *NodeSUnit = newSUnit(NI);
345 // See if anything is glued to this node, if so, add them to glued
346 // nodes. Nodes can have at most one glue input and one glue output. Glue
347 // is required to be the last operand and result of a node.
349 // Scan up to find glued preds.
351 while (N->getNumOperands() &&
352 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) {
353 N = N->getOperand(N->getNumOperands()-1).getNode();
354 assert(N->getNodeId() == -1 && "Node already inserted!");
355 N->setNodeId(NodeSUnit->NodeNum);
356 if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall())
357 NodeSUnit->isCall = true;
360 // Scan down to find any glued succs.
362 while (N->getValueType(N->getNumValues()-1) == MVT::Glue) {
363 SDValue GlueVal(N, N->getNumValues()-1);
365 // There are either zero or one users of the Glue result.
366 bool HasGlueUse = false;
367 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
369 if (GlueVal.isOperandOf(*UI)) {
371 assert(N->getNodeId() == -1 && "Node already inserted!");
372 N->setNodeId(NodeSUnit->NodeNum);
374 if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall())
375 NodeSUnit->isCall = true;
378 if (!HasGlueUse) break;
381 if (NodeSUnit->isCall)
382 CallSUnits.push_back(NodeSUnit);
384 // Schedule zero-latency TokenFactor below any nodes that may increase the
385 // schedule height. Otherwise, ancestors of the TokenFactor may appear to
386 // have false stalls.
387 if (NI->getOpcode() == ISD::TokenFactor)
388 NodeSUnit->isScheduleLow = true;
390 // If there are glue operands involved, N is now the bottom-most node
391 // of the sequence of nodes that are glued together.
393 NodeSUnit->setNode(N);
394 assert(N->getNodeId() == -1 && "Node already inserted!");
395 N->setNodeId(NodeSUnit->NodeNum);
397 // Compute NumRegDefsLeft. This must be done before AddSchedEdges.
398 InitNumRegDefsLeft(NodeSUnit);
400 // Assign the Latency field of NodeSUnit using target-provided information.
401 computeLatency(NodeSUnit);
404 // Find all call operands.
405 while (!CallSUnits.empty()) {
406 SUnit *SU = CallSUnits.pop_back_val();
407 for (const SDNode *SUNode = SU->getNode(); SUNode;
408 SUNode = SUNode->getGluedNode()) {
409 if (SUNode->getOpcode() != ISD::CopyToReg)
411 SDNode *SrcN = SUNode->getOperand(2).getNode();
412 if (isPassiveNode(SrcN)) continue; // Not scheduled.
413 SUnit *SrcSU = &SUnits[SrcN->getNodeId()];
414 SrcSU->isCallOp = true;
419 void ScheduleDAGSDNodes::AddSchedEdges() {
420 const TargetSubtargetInfo &ST = MF.getSubtarget();
422 // Check to see if the scheduler cares about latencies.
423 bool UnitLatencies = forceUnitLatencies();
425 // Pass 2: add the preds, succs, etc.
426 for (unsigned su = 0, e = SUnits.size(); su != e; ++su) {
427 SUnit *SU = &SUnits[su];
428 SDNode *MainNode = SU->getNode();
430 if (MainNode->isMachineOpcode()) {
431 unsigned Opc = MainNode->getMachineOpcode();
432 const MCInstrDesc &MCID = TII->get(Opc);
433 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) {
434 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) {
435 SU->isTwoAddress = true;
439 if (MCID.isCommutable())
440 SU->isCommutable = true;
443 // Find all predecessors and successors of the group.
444 for (SDNode *N = SU->getNode(); N; N = N->getGluedNode()) {
445 if (N->isMachineOpcode() &&
446 TII->get(N->getMachineOpcode()).getImplicitDefs()) {
447 SU->hasPhysRegClobbers = true;
448 unsigned NumUsed = InstrEmitter::CountResults(N);
449 while (NumUsed != 0 && !N->hasAnyUseOfValue(NumUsed - 1))
450 --NumUsed; // Skip over unused values at the end.
451 if (NumUsed > TII->get(N->getMachineOpcode()).getNumDefs())
452 SU->hasPhysRegDefs = true;
455 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
456 SDNode *OpN = N->getOperand(i).getNode();
457 if (isPassiveNode(OpN)) continue; // Not scheduled.
458 SUnit *OpSU = &SUnits[OpN->getNodeId()];
459 assert(OpSU && "Node has no SUnit!");
460 if (OpSU == SU) continue; // In the same group.
462 EVT OpVT = N->getOperand(i).getValueType();
463 assert(OpVT != MVT::Glue && "Glued nodes should be in same sunit!");
464 bool isChain = OpVT == MVT::Other;
466 unsigned PhysReg = 0;
468 // Determine if this is a physical register dependency.
469 CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost);
470 assert((PhysReg == 0 || !isChain) &&
471 "Chain dependence via physreg data?");
472 // FIXME: See ScheduleDAGSDNodes::EmitCopyFromReg. For now, scheduler
473 // emits a copy from the physical register to a virtual register unless
474 // it requires a cross class copy (cost < 0). That means we are only
475 // treating "expensive to copy" register dependency as physical register
476 // dependency. This may change in the future though.
477 if (Cost >= 0 && !StressSched)
480 // If this is a ctrl dep, latency is 1.
481 unsigned OpLatency = isChain ? 1 : OpSU->Latency;
482 // Special-case TokenFactor chains as zero-latency.
483 if(isChain && OpN->getOpcode() == ISD::TokenFactor)
486 SDep Dep = isChain ? SDep(OpSU, SDep::Barrier)
487 : SDep(OpSU, SDep::Data, PhysReg);
488 Dep.setLatency(OpLatency);
489 if (!isChain && !UnitLatencies) {
490 computeOperandLatency(OpN, N, i, Dep);
491 ST.adjustSchedDependency(OpSU, SU, Dep);
494 if (!SU->addPred(Dep) && !Dep.isCtrl() && OpSU->NumRegDefsLeft > 1) {
495 // Multiple register uses are combined in the same SUnit. For example,
496 // we could have a set of glued nodes with all their defs consumed by
497 // another set of glued nodes. Register pressure tracking sees this as
498 // a single use, so to keep pressure balanced we reduce the defs.
500 // We can't tell (without more book-keeping) if this results from
501 // glued nodes or duplicate operands. As long as we don't reduce
502 // NumRegDefsLeft to zero, we handle the common cases well.
503 --OpSU->NumRegDefsLeft;
510 /// BuildSchedGraph - Build the SUnit graph from the selection dag that we
511 /// are input. This SUnit graph is similar to the SelectionDAG, but
512 /// excludes nodes that aren't interesting to scheduling, and represents
513 /// glued together nodes with a single SUnit.
514 void ScheduleDAGSDNodes::BuildSchedGraph(AliasAnalysis *AA) {
515 // Cluster certain nodes which should be scheduled together.
517 // Populate the SUnits array.
519 // Compute all the scheduling dependencies between nodes.
523 // Initialize NumNodeDefs for the current Node's opcode.
524 void ScheduleDAGSDNodes::RegDefIter::InitNodeNumDefs() {
525 // Check for phys reg copy.
529 if (!Node->isMachineOpcode()) {
530 if (Node->getOpcode() == ISD::CopyFromReg)
536 unsigned POpc = Node->getMachineOpcode();
537 if (POpc == TargetOpcode::IMPLICIT_DEF) {
538 // No register need be allocated for this.
542 if (POpc == TargetOpcode::PATCHPOINT &&
543 Node->getValueType(0) == MVT::Other) {
544 // PATCHPOINT is defined to have one result, but it might really have none
545 // if we're not using CallingConv::AnyReg. Don't mistake the chain for a
550 unsigned NRegDefs = SchedDAG->TII->get(Node->getMachineOpcode()).getNumDefs();
551 // Some instructions define regs that are not represented in the selection DAG
552 // (e.g. unused flags). See tMOVi8. Make sure we don't access past NumValues.
553 NodeNumDefs = std::min(Node->getNumValues(), NRegDefs);
557 // Construct a RegDefIter for this SUnit and find the first valid value.
558 ScheduleDAGSDNodes::RegDefIter::RegDefIter(const SUnit *SU,
559 const ScheduleDAGSDNodes *SD)
560 : SchedDAG(SD), Node(SU->getNode()), DefIdx(0), NodeNumDefs(0) {
565 // Advance to the next valid value defined by the SUnit.
566 void ScheduleDAGSDNodes::RegDefIter::Advance() {
567 for (;Node;) { // Visit all glued nodes.
568 for (;DefIdx < NodeNumDefs; ++DefIdx) {
569 if (!Node->hasAnyUseOfValue(DefIdx))
571 ValueType = Node->getSimpleValueType(DefIdx);
573 return; // Found a normal regdef.
575 Node = Node->getGluedNode();
577 return; // No values left to visit.
583 void ScheduleDAGSDNodes::InitNumRegDefsLeft(SUnit *SU) {
584 assert(SU->NumRegDefsLeft == 0 && "expect a new node");
585 for (RegDefIter I(SU, this); I.IsValid(); I.Advance()) {
586 assert(SU->NumRegDefsLeft < USHRT_MAX && "overflow is ok but unexpected");
587 ++SU->NumRegDefsLeft;
591 void ScheduleDAGSDNodes::computeLatency(SUnit *SU) {
592 SDNode *N = SU->getNode();
594 // TokenFactor operands are considered zero latency, and some schedulers
595 // (e.g. Top-Down list) may rely on the fact that operand latency is nonzero
596 // whenever node latency is nonzero.
597 if (N && N->getOpcode() == ISD::TokenFactor) {
602 // Check to see if the scheduler cares about latencies.
603 if (forceUnitLatencies()) {
608 if (!InstrItins || InstrItins->isEmpty()) {
609 if (N && N->isMachineOpcode() &&
610 TII->isHighLatencyDef(N->getMachineOpcode()))
611 SU->Latency = HighLatencyCycles;
617 // Compute the latency for the node. We use the sum of the latencies for
618 // all nodes glued together into this SUnit.
620 for (SDNode *N = SU->getNode(); N; N = N->getGluedNode())
621 if (N->isMachineOpcode())
622 SU->Latency += TII->getInstrLatency(InstrItins, N);
625 void ScheduleDAGSDNodes::computeOperandLatency(SDNode *Def, SDNode *Use,
626 unsigned OpIdx, SDep& dep) const{
627 // Check to see if the scheduler cares about latencies.
628 if (forceUnitLatencies())
631 if (dep.getKind() != SDep::Data)
634 unsigned DefIdx = Use->getOperand(OpIdx).getResNo();
635 if (Use->isMachineOpcode())
636 // Adjust the use operand index by num of defs.
637 OpIdx += TII->get(Use->getMachineOpcode()).getNumDefs();
638 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx);
639 if (Latency > 1 && Use->getOpcode() == ISD::CopyToReg &&
641 unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
642 if (TargetRegisterInfo::isVirtualRegister(Reg))
643 // This copy is a liveout value. It is likely coalesced, so reduce the
644 // latency so not to penalize the def.
645 // FIXME: need target specific adjustment here?
646 Latency = (Latency > 1) ? Latency - 1 : 1;
649 dep.setLatency(Latency);
652 void ScheduleDAGSDNodes::dumpNode(const SUnit *SU) const {
653 // Cannot completely remove virtual function even in release mode.
654 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
655 if (!SU->getNode()) {
656 dbgs() << "PHYS REG COPY\n";
660 SU->getNode()->dump(DAG);
662 SmallVector<SDNode *, 4> GluedNodes;
663 for (SDNode *N = SU->getNode()->getGluedNode(); N; N = N->getGluedNode())
664 GluedNodes.push_back(N);
665 while (!GluedNodes.empty()) {
667 GluedNodes.back()->dump(DAG);
669 GluedNodes.pop_back();
674 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
675 void ScheduleDAGSDNodes::dumpSchedule() const {
676 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
677 if (SUnit *SU = Sequence[i])
680 dbgs() << "**** NOOP ****\n";
686 /// VerifyScheduledSequence - Verify that all SUnits were scheduled and that
687 /// their state is consistent with the nodes listed in Sequence.
689 void ScheduleDAGSDNodes::VerifyScheduledSequence(bool isBottomUp) {
690 unsigned ScheduledNodes = ScheduleDAG::VerifyScheduledDAG(isBottomUp);
692 for (unsigned i = 0, e = Sequence.size(); i != e; ++i)
695 assert(Sequence.size() - Noops == ScheduledNodes &&
696 "The number of nodes scheduled doesn't match the expected number!");
700 /// ProcessSDDbgValues - Process SDDbgValues associated with this node.
702 ProcessSDDbgValues(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter,
703 SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &Orders,
704 DenseMap<SDValue, unsigned> &VRBaseMap, unsigned Order) {
705 if (!N->getHasDebugValue())
708 // Opportunistically insert immediate dbg_value uses, i.e. those with the same
709 // source order number as N.
710 MachineBasicBlock *BB = Emitter.getBlock();
711 MachineBasicBlock::iterator InsertPos = Emitter.getInsertPos();
712 for (auto DV : DAG->GetDbgValues(N)) {
713 if (DV->isInvalidated())
715 unsigned DVOrder = DV->getOrder();
716 if (!Order || DVOrder == Order) {
717 MachineInstr *DbgMI = Emitter.EmitDbgValue(DV, VRBaseMap);
719 Orders.push_back({DVOrder, DbgMI});
720 BB->insert(InsertPos, DbgMI);
722 DV->setIsInvalidated();
727 // ProcessSourceNode - Process nodes with source order numbers. These are added
728 // to a vector which EmitSchedule uses to determine how to insert dbg_value
729 // instructions in the right order.
731 ProcessSourceNode(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter,
732 DenseMap<SDValue, unsigned> &VRBaseMap,
733 SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &Orders,
734 SmallSet<unsigned, 8> &Seen) {
735 unsigned Order = N->getIROrder();
736 if (!Order || !Seen.insert(Order).second) {
737 // Process any valid SDDbgValues even if node does not have any order
739 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, 0);
743 MachineBasicBlock *BB = Emitter.getBlock();
744 auto IP = Emitter.getInsertPos();
745 if (IP == BB->begin() || BB->back().isPHI() ||
746 // Fast-isel may have inserted some instructions, in which case the
747 // BB->back().isPHI() test will not fire when we want it to.
748 std::prev(IP)->isPHI()) {
749 // Did not insert any instruction.
750 Orders.push_back({Order, (MachineInstr *)nullptr});
754 Orders.push_back({Order, &*std::prev(IP)});
755 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order);
758 void ScheduleDAGSDNodes::
759 EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap,
760 MachineBasicBlock::iterator InsertPos) {
761 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
763 if (I->isCtrl()) continue; // ignore chain preds
764 if (I->getSUnit()->CopyDstRC) {
765 // Copy to physical register.
766 DenseMap<SUnit*, unsigned>::iterator VRI = VRBaseMap.find(I->getSUnit());
767 assert(VRI != VRBaseMap.end() && "Node emitted out of order - late");
768 // Find the destination physical register.
770 for (SUnit::const_succ_iterator II = SU->Succs.begin(),
771 EE = SU->Succs.end(); II != EE; ++II) {
772 if (II->isCtrl()) continue; // ignore chain preds
778 BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), Reg)
779 .addReg(VRI->second);
781 // Copy from physical register.
782 assert(I->getReg() && "Unknown physical register!");
783 unsigned VRBase = MRI.createVirtualRegister(SU->CopyDstRC);
784 bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase)).second;
785 (void)isNew; // Silence compiler warning.
786 assert(isNew && "Node emitted out of order - early");
787 BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), VRBase)
788 .addReg(I->getReg());
794 /// EmitSchedule - Emit the machine code in scheduled order. Return the new
795 /// InsertPos and MachineBasicBlock that contains this insertion
796 /// point. ScheduleDAGSDNodes holds a BB pointer for convenience, but this does
797 /// not necessarily refer to returned BB. The emitter may split blocks.
798 MachineBasicBlock *ScheduleDAGSDNodes::
799 EmitSchedule(MachineBasicBlock::iterator &InsertPos) {
800 InstrEmitter Emitter(BB, InsertPos);
801 DenseMap<SDValue, unsigned> VRBaseMap;
802 DenseMap<SUnit*, unsigned> CopyVRBaseMap;
803 SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders;
804 SmallSet<unsigned, 8> Seen;
805 bool HasDbg = DAG->hasDebugValues();
807 // If this is the first BB, emit byval parameter dbg_value's.
808 if (HasDbg && BB->getParent()->begin() == MachineFunction::iterator(BB)) {
809 SDDbgInfo::DbgIterator PDI = DAG->ByvalParmDbgBegin();
810 SDDbgInfo::DbgIterator PDE = DAG->ByvalParmDbgEnd();
811 for (; PDI != PDE; ++PDI) {
812 MachineInstr *DbgMI= Emitter.EmitDbgValue(*PDI, VRBaseMap);
814 BB->insert(InsertPos, DbgMI);
818 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
819 SUnit *SU = Sequence[i];
821 // Null SUnit* is a noop.
822 TII->insertNoop(*Emitter.getBlock(), InsertPos);
826 // For pre-regalloc scheduling, create instructions corresponding to the
827 // SDNode and any glued SDNodes and append them to the block.
828 if (!SU->getNode()) {
830 EmitPhysRegCopy(SU, CopyVRBaseMap, InsertPos);
834 SmallVector<SDNode *, 4> GluedNodes;
835 for (SDNode *N = SU->getNode()->getGluedNode(); N; N = N->getGluedNode())
836 GluedNodes.push_back(N);
837 while (!GluedNodes.empty()) {
838 SDNode *N = GluedNodes.back();
839 Emitter.EmitNode(N, SU->OrigNode != SU, SU->isCloned, VRBaseMap);
840 // Remember the source order of the inserted instruction.
842 ProcessSourceNode(N, DAG, Emitter, VRBaseMap, Orders, Seen);
843 GluedNodes.pop_back();
845 Emitter.EmitNode(SU->getNode(), SU->OrigNode != SU, SU->isCloned,
847 // Remember the source order of the inserted instruction.
849 ProcessSourceNode(SU->getNode(), DAG, Emitter, VRBaseMap, Orders,
853 // Insert all the dbg_values which have not already been inserted in source
856 MachineBasicBlock::iterator BBBegin = BB->getFirstNonPHI();
858 // Sort the source order instructions and use the order to insert debug
859 // values. Use stable_sort so that DBG_VALUEs are inserted in the same order
860 // regardless of the host's implementation fo std::sort.
861 std::stable_sort(Orders.begin(), Orders.end(), less_first());
862 std::stable_sort(DAG->DbgBegin(), DAG->DbgEnd(),
863 [](const SDDbgValue *LHS, const SDDbgValue *RHS) {
864 return LHS->getOrder() < RHS->getOrder();
867 SDDbgInfo::DbgIterator DI = DAG->DbgBegin();
868 SDDbgInfo::DbgIterator DE = DAG->DbgEnd();
869 // Now emit the rest according to source order.
870 unsigned LastOrder = 0;
871 for (unsigned i = 0, e = Orders.size(); i != e && DI != DE; ++i) {
872 unsigned Order = Orders[i].first;
873 MachineInstr *MI = Orders[i].second;
874 // Insert all SDDbgValue's whose order(s) are before "Order".
877 for (; DI != DE; ++DI) {
878 if ((*DI)->getOrder() < LastOrder || (*DI)->getOrder() >= Order)
880 if ((*DI)->isInvalidated())
883 MachineInstr *DbgMI = Emitter.EmitDbgValue(*DI, VRBaseMap);
886 // Insert to start of the BB (after PHIs).
887 BB->insert(BBBegin, DbgMI);
889 // Insert at the instruction, which may be in a different
890 // block, if the block was split by a custom inserter.
891 MachineBasicBlock::iterator Pos = MI;
892 MI->getParent()->insert(Pos, DbgMI);
898 // Add trailing DbgValue's before the terminator. FIXME: May want to add
899 // some of them before one or more conditional branches?
900 SmallVector<MachineInstr*, 8> DbgMIs;
901 for (; DI != DE; ++DI) {
902 if ((*DI)->isInvalidated())
904 assert((*DI)->getOrder() >= LastOrder &&
905 "emitting DBG_VALUE out of order");
906 if (MachineInstr *DbgMI = Emitter.EmitDbgValue(*DI, VRBaseMap))
907 DbgMIs.push_back(DbgMI);
910 MachineBasicBlock *InsertBB = Emitter.getBlock();
911 MachineBasicBlock::iterator Pos = InsertBB->getFirstTerminator();
912 InsertBB->insert(Pos, DbgMIs.begin(), DbgMIs.end());
915 InsertPos = Emitter.getInsertPos();
916 return Emitter.getBlock();
919 /// Return the basic block label.
920 std::string ScheduleDAGSDNodes::getDAGName() const {
921 return "sunit-dag." + BB->getFullName();