1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SelectionDAGBuilder.h"
16 #include "SDNodeDbgValue.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/ConstantFolding.h"
22 #include "llvm/Analysis/ValueTracking.h"
23 #include "llvm/CodeGen/Analysis.h"
24 #include "llvm/CodeGen/FastISel.h"
25 #include "llvm/CodeGen/FunctionLoweringInfo.h"
26 #include "llvm/CodeGen/GCMetadata.h"
27 #include "llvm/CodeGen/GCStrategy.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/DebugInfo.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DataLayout.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/InlineAsm.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/IntrinsicInst.h"
45 #include "llvm/IR/Intrinsics.h"
46 #include "llvm/IR/LLVMContext.h"
47 #include "llvm/IR/Module.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/IntegersSubsetMapping.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetFrameLowering.h"
55 #include "llvm/Target/TargetInstrInfo.h"
56 #include "llvm/Target/TargetIntrinsicInfo.h"
57 #include "llvm/Target/TargetLibraryInfo.h"
58 #include "llvm/Target/TargetLowering.h"
59 #include "llvm/Target/TargetOptions.h"
63 /// LimitFloatPrecision - Generate low-precision inline sequences for
64 /// some float libcalls (6, 8 or 12 bits).
65 static unsigned LimitFloatPrecision;
67 static cl::opt<unsigned, true>
68 LimitFPPrecision("limit-float-precision",
69 cl::desc("Generate low-precision inline sequences "
70 "for some float libcalls"),
71 cl::location(LimitFloatPrecision),
74 // Limit the width of DAG chains. This is important in general to prevent
75 // prevent DAG-based analysis from blowing up. For example, alias analysis and
76 // load clustering may not complete in reasonable time. It is difficult to
77 // recognize and avoid this situation within each individual analysis, and
78 // future analyses are likely to have the same behavior. Limiting DAG width is
79 // the safe approach, and will be especially important with global DAGs.
81 // MaxParallelChains default is arbitrarily high to avoid affecting
82 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
83 // sequence over this should have been converted to llvm.memcpy by the
84 // frontend. It easy to induce this behavior with .ll code such as:
85 // %buffer = alloca [4096 x i8]
86 // %data = load [4096 x i8]* %argPtr
87 // store [4096 x i8] %data, [4096 x i8]* %buffer
88 static const unsigned MaxParallelChains = 64;
90 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
91 const SDValue *Parts, unsigned NumParts,
92 MVT PartVT, EVT ValueVT, const Value *V);
94 /// getCopyFromParts - Create a value that contains the specified legal parts
95 /// combined into the value they represent. If the parts combine to a type
96 /// larger then ValueVT then AssertOp can be used to specify whether the extra
97 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
98 /// (ISD::AssertSext).
99 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL,
100 const SDValue *Parts,
101 unsigned NumParts, MVT PartVT, EVT ValueVT,
103 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
104 if (ValueVT.isVector())
105 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
108 assert(NumParts > 0 && "No parts to assemble!");
109 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
110 SDValue Val = Parts[0];
113 // Assemble the value from multiple parts.
114 if (ValueVT.isInteger()) {
115 unsigned PartBits = PartVT.getSizeInBits();
116 unsigned ValueBits = ValueVT.getSizeInBits();
118 // Assemble the power of 2 part.
119 unsigned RoundParts = NumParts & (NumParts - 1) ?
120 1 << Log2_32(NumParts) : NumParts;
121 unsigned RoundBits = PartBits * RoundParts;
122 EVT RoundVT = RoundBits == ValueBits ?
123 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
126 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
128 if (RoundParts > 2) {
129 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
131 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
132 RoundParts / 2, PartVT, HalfVT, V);
134 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
135 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
138 if (TLI.isBigEndian())
141 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
143 if (RoundParts < NumParts) {
144 // Assemble the trailing non-power-of-2 part.
145 unsigned OddParts = NumParts - RoundParts;
146 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
147 Hi = getCopyFromParts(DAG, DL,
148 Parts + RoundParts, OddParts, PartVT, OddVT, V);
150 // Combine the round and odd parts.
152 if (TLI.isBigEndian())
154 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
155 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
156 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
157 DAG.getConstant(Lo.getValueType().getSizeInBits(),
158 TLI.getPointerTy()));
159 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
160 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
162 } else if (PartVT.isFloatingPoint()) {
163 // FP split into multiple FP parts (for ppcf128)
164 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
167 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
168 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
169 if (TLI.isBigEndian())
171 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
173 // FP split into integer parts (soft fp)
174 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
175 !PartVT.isVector() && "Unexpected split");
176 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
177 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
181 // There is now one part, held in Val. Correct it to match ValueVT.
182 EVT PartEVT = Val.getValueType();
184 if (PartEVT == ValueVT)
187 if (PartEVT.isInteger() && ValueVT.isInteger()) {
188 if (ValueVT.bitsLT(PartEVT)) {
189 // For a truncate, see if we have any information to
190 // indicate whether the truncated bits will always be
191 // zero or sign-extension.
192 if (AssertOp != ISD::DELETED_NODE)
193 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
194 DAG.getValueType(ValueVT));
195 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
197 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
200 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
201 // FP_ROUND's are always exact here.
202 if (ValueVT.bitsLT(Val.getValueType()))
203 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
204 DAG.getTargetConstant(1, TLI.getPointerTy()));
206 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
209 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
210 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
212 llvm_unreachable("Unknown mismatch!");
215 /// getCopyFromPartsVector - Create a value that contains the specified legal
216 /// parts combined into the value they represent. If the parts combine to a
217 /// type larger then ValueVT then AssertOp can be used to specify whether the
218 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
219 /// ValueVT (ISD::AssertSext).
220 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
221 const SDValue *Parts, unsigned NumParts,
222 MVT PartVT, EVT ValueVT, const Value *V) {
223 assert(ValueVT.isVector() && "Not a vector value");
224 assert(NumParts > 0 && "No parts to assemble!");
225 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
226 SDValue Val = Parts[0];
228 // Handle a multi-element vector.
232 unsigned NumIntermediates;
234 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
235 NumIntermediates, RegisterVT);
236 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
237 NumParts = NumRegs; // Silence a compiler warning.
238 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
239 assert(RegisterVT == Parts[0].getSimpleValueType() &&
240 "Part type doesn't match part!");
242 // Assemble the parts into intermediate operands.
243 SmallVector<SDValue, 8> Ops(NumIntermediates);
244 if (NumIntermediates == NumParts) {
245 // If the register was not expanded, truncate or copy the value,
247 for (unsigned i = 0; i != NumParts; ++i)
248 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
249 PartVT, IntermediateVT, V);
250 } else if (NumParts > 0) {
251 // If the intermediate type was expanded, build the intermediate
252 // operands from the parts.
253 assert(NumParts % NumIntermediates == 0 &&
254 "Must expand into a divisible number of parts!");
255 unsigned Factor = NumParts / NumIntermediates;
256 for (unsigned i = 0; i != NumIntermediates; ++i)
257 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
258 PartVT, IntermediateVT, V);
261 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
262 // intermediate operands.
263 Val = DAG.getNode(IntermediateVT.isVector() ?
264 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL,
265 ValueVT, &Ops[0], NumIntermediates);
268 // There is now one part, held in Val. Correct it to match ValueVT.
269 EVT PartEVT = Val.getValueType();
271 if (PartEVT == ValueVT)
274 if (PartEVT.isVector()) {
275 // If the element type of the source/dest vectors are the same, but the
276 // parts vector has more elements than the value vector, then we have a
277 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
279 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
280 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
281 "Cannot narrow, it would be a lossy transformation");
282 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
283 DAG.getIntPtrConstant(0));
286 // Vector/Vector bitcast.
287 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
288 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
290 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
291 "Cannot handle this kind of promotion");
292 // Promoted vector extract
293 bool Smaller = ValueVT.bitsLE(PartEVT);
294 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
299 // Trivial bitcast if the types are the same size and the destination
300 // vector type is legal.
301 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
302 TLI.isTypeLegal(ValueVT))
303 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
305 // Handle cases such as i8 -> <1 x i1>
306 if (ValueVT.getVectorNumElements() != 1) {
307 LLVMContext &Ctx = *DAG.getContext();
308 Twine ErrMsg("non-trivial scalar-to-vector conversion");
309 if (const Instruction *I = dyn_cast_or_null<Instruction>(V)) {
310 if (const CallInst *CI = dyn_cast<CallInst>(I))
311 if (isa<InlineAsm>(CI->getCalledValue()))
312 ErrMsg = ErrMsg + ", possible invalid constraint for vector type";
313 Ctx.emitError(I, ErrMsg);
315 Ctx.emitError(ErrMsg);
317 return DAG.getUNDEF(ValueVT);
320 if (ValueVT.getVectorNumElements() == 1 &&
321 ValueVT.getVectorElementType() != PartEVT) {
322 bool Smaller = ValueVT.bitsLE(PartEVT);
323 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
324 DL, ValueVT.getScalarType(), Val);
327 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
330 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl,
331 SDValue Val, SDValue *Parts, unsigned NumParts,
332 MVT PartVT, const Value *V);
334 /// getCopyToParts - Create a series of nodes that contain the specified value
335 /// split into legal parts. If the parts contain more bits than Val, then, for
336 /// integers, ExtendKind can be used to specify how to generate the extra bits.
337 static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL,
338 SDValue Val, SDValue *Parts, unsigned NumParts,
339 MVT PartVT, const Value *V,
340 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
341 EVT ValueVT = Val.getValueType();
343 // Handle the vector case separately.
344 if (ValueVT.isVector())
345 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
347 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
348 unsigned PartBits = PartVT.getSizeInBits();
349 unsigned OrigNumParts = NumParts;
350 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
355 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
356 EVT PartEVT = PartVT;
357 if (PartEVT == ValueVT) {
358 assert(NumParts == 1 && "No-op copy with multiple parts!");
363 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
364 // If the parts cover more bits than the value has, promote the value.
365 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
366 assert(NumParts == 1 && "Do not know what to promote to!");
367 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
369 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
370 ValueVT.isInteger() &&
371 "Unknown mismatch!");
372 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
373 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
374 if (PartVT == MVT::x86mmx)
375 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
377 } else if (PartBits == ValueVT.getSizeInBits()) {
378 // Different types of the same size.
379 assert(NumParts == 1 && PartEVT != ValueVT);
380 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
381 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
382 // If the parts cover less bits than value has, truncate the value.
383 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
384 ValueVT.isInteger() &&
385 "Unknown mismatch!");
386 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
387 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
388 if (PartVT == MVT::x86mmx)
389 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
392 // The value may have changed - recompute ValueVT.
393 ValueVT = Val.getValueType();
394 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
395 "Failed to tile the value with PartVT!");
398 if (PartEVT != ValueVT) {
399 LLVMContext &Ctx = *DAG.getContext();
400 Twine ErrMsg("scalar-to-vector conversion failed");
401 if (const Instruction *I = dyn_cast_or_null<Instruction>(V)) {
402 if (const CallInst *CI = dyn_cast<CallInst>(I))
403 if (isa<InlineAsm>(CI->getCalledValue()))
404 ErrMsg = ErrMsg + ", possible invalid constraint for vector type";
405 Ctx.emitError(I, ErrMsg);
407 Ctx.emitError(ErrMsg);
415 // Expand the value into multiple parts.
416 if (NumParts & (NumParts - 1)) {
417 // The number of parts is not a power of 2. Split off and copy the tail.
418 assert(PartVT.isInteger() && ValueVT.isInteger() &&
419 "Do not know what to expand to!");
420 unsigned RoundParts = 1 << Log2_32(NumParts);
421 unsigned RoundBits = RoundParts * PartBits;
422 unsigned OddParts = NumParts - RoundParts;
423 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
424 DAG.getIntPtrConstant(RoundBits));
425 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
427 if (TLI.isBigEndian())
428 // The odd parts were reversed by getCopyToParts - unreverse them.
429 std::reverse(Parts + RoundParts, Parts + NumParts);
431 NumParts = RoundParts;
432 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
433 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
436 // The number of parts is a power of 2. Repeatedly bisect the value using
438 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
439 EVT::getIntegerVT(*DAG.getContext(),
440 ValueVT.getSizeInBits()),
443 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
444 for (unsigned i = 0; i < NumParts; i += StepSize) {
445 unsigned ThisBits = StepSize * PartBits / 2;
446 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
447 SDValue &Part0 = Parts[i];
448 SDValue &Part1 = Parts[i+StepSize/2];
450 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
451 ThisVT, Part0, DAG.getIntPtrConstant(1));
452 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
453 ThisVT, Part0, DAG.getIntPtrConstant(0));
455 if (ThisBits == PartBits && ThisVT != PartVT) {
456 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
457 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
462 if (TLI.isBigEndian())
463 std::reverse(Parts, Parts + OrigNumParts);
467 /// getCopyToPartsVector - Create a series of nodes that contain the specified
468 /// value split into legal parts.
469 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL,
470 SDValue Val, SDValue *Parts, unsigned NumParts,
471 MVT PartVT, const Value *V) {
472 EVT ValueVT = Val.getValueType();
473 assert(ValueVT.isVector() && "Not a vector");
474 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
477 EVT PartEVT = PartVT;
478 if (PartEVT == ValueVT) {
480 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
481 // Bitconvert vector->vector case.
482 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
483 } else if (PartVT.isVector() &&
484 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
485 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
486 EVT ElementVT = PartVT.getVectorElementType();
487 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
489 SmallVector<SDValue, 16> Ops;
490 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
491 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
492 ElementVT, Val, DAG.getIntPtrConstant(i)));
494 for (unsigned i = ValueVT.getVectorNumElements(),
495 e = PartVT.getVectorNumElements(); i != e; ++i)
496 Ops.push_back(DAG.getUNDEF(ElementVT));
498 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size());
500 // FIXME: Use CONCAT for 2x -> 4x.
502 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
503 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
504 } else if (PartVT.isVector() &&
505 PartEVT.getVectorElementType().bitsGE(
506 ValueVT.getVectorElementType()) &&
507 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
509 // Promoted vector extract
510 bool Smaller = PartEVT.bitsLE(ValueVT);
511 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
514 // Vector -> scalar conversion.
515 assert(ValueVT.getVectorNumElements() == 1 &&
516 "Only trivial vector-to-scalar conversions should get here!");
517 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
518 PartVT, Val, DAG.getIntPtrConstant(0));
520 bool Smaller = ValueVT.bitsLE(PartVT);
521 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
529 // Handle a multi-element vector.
532 unsigned NumIntermediates;
533 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
535 NumIntermediates, RegisterVT);
536 unsigned NumElements = ValueVT.getVectorNumElements();
538 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
539 NumParts = NumRegs; // Silence a compiler warning.
540 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
542 // Split the vector into intermediate operands.
543 SmallVector<SDValue, 8> Ops(NumIntermediates);
544 for (unsigned i = 0; i != NumIntermediates; ++i) {
545 if (IntermediateVT.isVector())
546 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
548 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates)));
550 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
551 IntermediateVT, Val, DAG.getIntPtrConstant(i));
554 // Split the intermediate operands into legal parts.
555 if (NumParts == NumIntermediates) {
556 // If the register was not expanded, promote or copy the value,
558 for (unsigned i = 0; i != NumParts; ++i)
559 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
560 } else if (NumParts > 0) {
561 // If the intermediate type was expanded, split each the value into
563 assert(NumParts % NumIntermediates == 0 &&
564 "Must expand into a divisible number of parts!");
565 unsigned Factor = NumParts / NumIntermediates;
566 for (unsigned i = 0; i != NumIntermediates; ++i)
567 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
572 /// RegsForValue - This struct represents the registers (physical or virtual)
573 /// that a particular set of values is assigned, and the type information
574 /// about the value. The most common situation is to represent one value at a
575 /// time, but struct or array values are handled element-wise as multiple
576 /// values. The splitting of aggregates is performed recursively, so that we
577 /// never have aggregate-typed registers. The values at this point do not
578 /// necessarily have legal types, so each value may require one or more
579 /// registers of some legal type.
581 struct RegsForValue {
582 /// ValueVTs - The value types of the values, which may not be legal, and
583 /// may need be promoted or synthesized from one or more registers.
585 SmallVector<EVT, 4> ValueVTs;
587 /// RegVTs - The value types of the registers. This is the same size as
588 /// ValueVTs and it records, for each value, what the type of the assigned
589 /// register or registers are. (Individual values are never synthesized
590 /// from more than one type of register.)
592 /// With virtual registers, the contents of RegVTs is redundant with TLI's
593 /// getRegisterType member function, however when with physical registers
594 /// it is necessary to have a separate record of the types.
596 SmallVector<MVT, 4> RegVTs;
598 /// Regs - This list holds the registers assigned to the values.
599 /// Each legal or promoted value requires one register, and each
600 /// expanded value requires multiple registers.
602 SmallVector<unsigned, 4> Regs;
606 RegsForValue(const SmallVector<unsigned, 4> ®s,
607 MVT regvt, EVT valuevt)
608 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
610 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
611 unsigned Reg, Type *Ty) {
612 ComputeValueVTs(tli, Ty, ValueVTs);
614 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
615 EVT ValueVT = ValueVTs[Value];
616 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
617 MVT RegisterVT = tli.getRegisterType(Context, ValueVT);
618 for (unsigned i = 0; i != NumRegs; ++i)
619 Regs.push_back(Reg + i);
620 RegVTs.push_back(RegisterVT);
625 /// areValueTypesLegal - Return true if types of all the values are legal.
626 bool areValueTypesLegal(const TargetLowering &TLI) {
627 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
628 MVT RegisterVT = RegVTs[Value];
629 if (!TLI.isTypeLegal(RegisterVT))
635 /// append - Add the specified values to this one.
636 void append(const RegsForValue &RHS) {
637 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
638 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
639 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
642 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
643 /// this value and returns the result as a ValueVTs value. This uses
644 /// Chain/Flag as the input and updates them for the output Chain/Flag.
645 /// If the Flag pointer is NULL, no flag is used.
646 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
648 SDValue &Chain, SDValue *Flag,
649 const Value *V = 0) const;
651 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
652 /// specified value into the registers specified by this object. This uses
653 /// Chain/Flag as the input and updates them for the output Chain/Flag.
654 /// If the Flag pointer is NULL, no flag is used.
655 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
656 SDValue &Chain, SDValue *Flag, const Value *V) const;
658 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
659 /// operand list. This adds the code marker, matching input operand index
660 /// (if applicable), and includes the number of values added into it.
661 void AddInlineAsmOperands(unsigned Kind,
662 bool HasMatching, unsigned MatchingIdx,
664 std::vector<SDValue> &Ops) const;
668 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
669 /// this value and returns the result as a ValueVT value. This uses
670 /// Chain/Flag as the input and updates them for the output Chain/Flag.
671 /// If the Flag pointer is NULL, no flag is used.
672 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
673 FunctionLoweringInfo &FuncInfo,
675 SDValue &Chain, SDValue *Flag,
676 const Value *V) const {
677 // A Value with type {} or [0 x %t] needs no registers.
678 if (ValueVTs.empty())
681 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
683 // Assemble the legal parts into the final values.
684 SmallVector<SDValue, 4> Values(ValueVTs.size());
685 SmallVector<SDValue, 8> Parts;
686 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
687 // Copy the legal parts from the registers.
688 EVT ValueVT = ValueVTs[Value];
689 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
690 MVT RegisterVT = RegVTs[Value];
692 Parts.resize(NumRegs);
693 for (unsigned i = 0; i != NumRegs; ++i) {
696 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
698 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
699 *Flag = P.getValue(2);
702 Chain = P.getValue(1);
705 // If the source register was virtual and if we know something about it,
706 // add an assert node.
707 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
708 !RegisterVT.isInteger() || RegisterVT.isVector())
711 const FunctionLoweringInfo::LiveOutInfo *LOI =
712 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
716 unsigned RegSize = RegisterVT.getSizeInBits();
717 unsigned NumSignBits = LOI->NumSignBits;
718 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
720 // FIXME: We capture more information than the dag can represent. For
721 // now, just use the tightest assertzext/assertsext possible.
723 EVT FromVT(MVT::Other);
724 if (NumSignBits == RegSize)
725 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
726 else if (NumZeroBits >= RegSize-1)
727 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
728 else if (NumSignBits > RegSize-8)
729 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
730 else if (NumZeroBits >= RegSize-8)
731 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
732 else if (NumSignBits > RegSize-16)
733 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
734 else if (NumZeroBits >= RegSize-16)
735 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
736 else if (NumSignBits > RegSize-32)
737 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
738 else if (NumZeroBits >= RegSize-32)
739 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
743 // Add an assertion node.
744 assert(FromVT != MVT::Other);
745 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
746 RegisterVT, P, DAG.getValueType(FromVT));
749 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
750 NumRegs, RegisterVT, ValueVT, V);
755 return DAG.getNode(ISD::MERGE_VALUES, dl,
756 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
757 &Values[0], ValueVTs.size());
760 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
761 /// specified value into the registers specified by this object. This uses
762 /// Chain/Flag as the input and updates them for the output Chain/Flag.
763 /// If the Flag pointer is NULL, no flag is used.
764 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
765 SDValue &Chain, SDValue *Flag,
766 const Value *V) const {
767 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
769 // Get the list of the values's legal parts.
770 unsigned NumRegs = Regs.size();
771 SmallVector<SDValue, 8> Parts(NumRegs);
772 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
773 EVT ValueVT = ValueVTs[Value];
774 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
775 MVT RegisterVT = RegVTs[Value];
776 ISD::NodeType ExtendKind =
777 TLI.isZExtFree(Val, RegisterVT)? ISD::ZERO_EXTEND: ISD::ANY_EXTEND;
779 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
780 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
784 // Copy the parts into the registers.
785 SmallVector<SDValue, 8> Chains(NumRegs);
786 for (unsigned i = 0; i != NumRegs; ++i) {
789 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
791 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
792 *Flag = Part.getValue(1);
795 Chains[i] = Part.getValue(0);
798 if (NumRegs == 1 || Flag)
799 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
800 // flagged to it. That is the CopyToReg nodes and the user are considered
801 // a single scheduling unit. If we create a TokenFactor and return it as
802 // chain, then the TokenFactor is both a predecessor (operand) of the
803 // user as well as a successor (the TF operands are flagged to the user).
804 // c1, f1 = CopyToReg
805 // c2, f2 = CopyToReg
806 // c3 = TokenFactor c1, c2
809 Chain = Chains[NumRegs-1];
811 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
814 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
815 /// operand list. This adds the code marker and includes the number of
816 /// values added into it.
817 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
818 unsigned MatchingIdx,
820 std::vector<SDValue> &Ops) const {
821 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
823 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
825 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
826 else if (!Regs.empty() &&
827 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
828 // Put the register class of the virtual registers in the flag word. That
829 // way, later passes can recompute register class constraints for inline
830 // assembly as well as normal instructions.
831 // Don't do this for tied operands that can use the regclass information
833 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
834 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
835 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
838 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
841 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
842 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
843 MVT RegisterVT = RegVTs[Value];
844 for (unsigned i = 0; i != NumRegs; ++i) {
845 assert(Reg < Regs.size() && "Mismatch in # registers expected");
846 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
851 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
852 const TargetLibraryInfo *li) {
856 TD = DAG.getTarget().getDataLayout();
857 Context = DAG.getContext();
858 LPadToCallSiteMap.clear();
861 /// clear - Clear out the current SelectionDAG and the associated
862 /// state and prepare this SelectionDAGBuilder object to be used
863 /// for a new block. This doesn't clear out information about
864 /// additional blocks that are needed to complete switch lowering
865 /// or PHI node updating; that information is cleared out as it is
867 void SelectionDAGBuilder::clear() {
869 UnusedArgNodeMap.clear();
870 PendingLoads.clear();
871 PendingExports.clear();
872 CurDebugLoc = DebugLoc();
876 /// clearDanglingDebugInfo - Clear the dangling debug information
877 /// map. This function is separated from the clear so that debug
878 /// information that is dangling in a basic block can be properly
879 /// resolved in a different basic block. This allows the
880 /// SelectionDAG to resolve dangling debug information attached
882 void SelectionDAGBuilder::clearDanglingDebugInfo() {
883 DanglingDebugInfoMap.clear();
886 /// getRoot - Return the current virtual root of the Selection DAG,
887 /// flushing any PendingLoad items. This must be done before emitting
888 /// a store or any other node that may need to be ordered after any
889 /// prior load instructions.
891 SDValue SelectionDAGBuilder::getRoot() {
892 if (PendingLoads.empty())
893 return DAG.getRoot();
895 if (PendingLoads.size() == 1) {
896 SDValue Root = PendingLoads[0];
898 PendingLoads.clear();
902 // Otherwise, we have to make a token factor node.
903 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
904 &PendingLoads[0], PendingLoads.size());
905 PendingLoads.clear();
910 /// getControlRoot - Similar to getRoot, but instead of flushing all the
911 /// PendingLoad items, flush all the PendingExports items. It is necessary
912 /// to do this before emitting a terminator instruction.
914 SDValue SelectionDAGBuilder::getControlRoot() {
915 SDValue Root = DAG.getRoot();
917 if (PendingExports.empty())
920 // Turn all of the CopyToReg chains into one factored node.
921 if (Root.getOpcode() != ISD::EntryToken) {
922 unsigned i = 0, e = PendingExports.size();
923 for (; i != e; ++i) {
924 assert(PendingExports[i].getNode()->getNumOperands() > 1);
925 if (PendingExports[i].getNode()->getOperand(0) == Root)
926 break; // Don't add the root if we already indirectly depend on it.
930 PendingExports.push_back(Root);
933 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
935 PendingExports.size());
936 PendingExports.clear();
941 void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) {
942 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering.
943 DAG.AssignOrdering(Node, SDNodeOrder);
945 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I)
946 AssignOrderingToNode(Node->getOperand(I).getNode());
949 void SelectionDAGBuilder::visit(const Instruction &I) {
950 // Set up outgoing PHI node register values before emitting the terminator.
951 if (isa<TerminatorInst>(&I))
952 HandlePHINodesInSuccessorBlocks(I.getParent());
954 CurDebugLoc = I.getDebugLoc();
956 visit(I.getOpcode(), I);
958 if (!isa<TerminatorInst>(&I) && !HasTailCall)
959 CopyToExportRegsIfNeeded(&I);
961 CurDebugLoc = DebugLoc();
964 void SelectionDAGBuilder::visitPHI(const PHINode &) {
965 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
968 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
969 // Note: this doesn't use InstVisitor, because it has to work with
970 // ConstantExpr's in addition to instructions.
972 default: llvm_unreachable("Unknown instruction type encountered!");
973 // Build the switch statement using the Instruction.def file.
974 #define HANDLE_INST(NUM, OPCODE, CLASS) \
975 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
976 #include "llvm/IR/Instruction.def"
979 // Assign the ordering to the freshly created DAG nodes.
980 if (NodeMap.count(&I)) {
982 AssignOrderingToNode(getValue(&I).getNode());
986 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
987 // generate the debug data structures now that we've seen its definition.
988 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
990 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
992 const DbgValueInst *DI = DDI.getDI();
993 DebugLoc dl = DDI.getdl();
994 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
995 MDNode *Variable = DI->getVariable();
996 uint64_t Offset = DI->getOffset();
999 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) {
1000 SDV = DAG.getDbgValue(Variable, Val.getNode(),
1001 Val.getResNo(), Offset, dl, DbgSDNodeOrder);
1002 DAG.AddDbgValue(SDV, Val.getNode(), false);
1005 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
1006 DanglingDebugInfoMap[V] = DanglingDebugInfo();
1010 /// getValue - Return an SDValue for the given Value.
1011 SDValue SelectionDAGBuilder::getValue(const Value *V) {
1012 // If we already have an SDValue for this value, use it. It's important
1013 // to do this first, so that we don't create a CopyFromReg if we already
1014 // have a regular SDValue.
1015 SDValue &N = NodeMap[V];
1016 if (N.getNode()) return N;
1018 // If there's a virtual register allocated and initialized for this
1020 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
1021 if (It != FuncInfo.ValueMap.end()) {
1022 unsigned InReg = It->second;
1023 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
1024 SDValue Chain = DAG.getEntryNode();
1025 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL, V);
1026 resolveDanglingDebugInfo(V, N);
1030 // Otherwise create a new SDValue and remember it.
1031 SDValue Val = getValueImpl(V);
1033 resolveDanglingDebugInfo(V, Val);
1037 /// getNonRegisterValue - Return an SDValue for the given Value, but
1038 /// don't look in FuncInfo.ValueMap for a virtual register.
1039 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1040 // If we already have an SDValue for this value, use it.
1041 SDValue &N = NodeMap[V];
1042 if (N.getNode()) return N;
1044 // Otherwise create a new SDValue and remember it.
1045 SDValue Val = getValueImpl(V);
1047 resolveDanglingDebugInfo(V, Val);
1051 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1052 /// Create an SDValue for the given value.
1053 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1054 if (const Constant *C = dyn_cast<Constant>(V)) {
1055 EVT VT = TLI.getValueType(V->getType(), true);
1057 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1058 return DAG.getConstant(*CI, VT);
1060 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1061 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT);
1063 if (isa<ConstantPointerNull>(C))
1064 return DAG.getConstant(0, TLI.getPointerTy());
1066 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1067 return DAG.getConstantFP(*CFP, VT);
1069 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1070 return DAG.getUNDEF(VT);
1072 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1073 visit(CE->getOpcode(), *CE);
1074 SDValue N1 = NodeMap[V];
1075 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1079 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1080 SmallVector<SDValue, 4> Constants;
1081 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1083 SDNode *Val = getValue(*OI).getNode();
1084 // If the operand is an empty aggregate, there are no values.
1086 // Add each leaf value from the operand to the Constants list
1087 // to form a flattened list of all the values.
1088 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1089 Constants.push_back(SDValue(Val, i));
1092 return DAG.getMergeValues(&Constants[0], Constants.size(),
1096 if (const ConstantDataSequential *CDS =
1097 dyn_cast<ConstantDataSequential>(C)) {
1098 SmallVector<SDValue, 4> Ops;
1099 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1100 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1101 // Add each leaf value from the operand to the Constants list
1102 // to form a flattened list of all the values.
1103 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1104 Ops.push_back(SDValue(Val, i));
1107 if (isa<ArrayType>(CDS->getType()))
1108 return DAG.getMergeValues(&Ops[0], Ops.size(), getCurDebugLoc());
1109 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
1110 VT, &Ops[0], Ops.size());
1113 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1114 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1115 "Unknown struct or array constant!");
1117 SmallVector<EVT, 4> ValueVTs;
1118 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1119 unsigned NumElts = ValueVTs.size();
1121 return SDValue(); // empty struct
1122 SmallVector<SDValue, 4> Constants(NumElts);
1123 for (unsigned i = 0; i != NumElts; ++i) {
1124 EVT EltVT = ValueVTs[i];
1125 if (isa<UndefValue>(C))
1126 Constants[i] = DAG.getUNDEF(EltVT);
1127 else if (EltVT.isFloatingPoint())
1128 Constants[i] = DAG.getConstantFP(0, EltVT);
1130 Constants[i] = DAG.getConstant(0, EltVT);
1133 return DAG.getMergeValues(&Constants[0], NumElts,
1137 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1138 return DAG.getBlockAddress(BA, VT);
1140 VectorType *VecTy = cast<VectorType>(V->getType());
1141 unsigned NumElements = VecTy->getNumElements();
1143 // Now that we know the number and type of the elements, get that number of
1144 // elements into the Ops array based on what kind of constant it is.
1145 SmallVector<SDValue, 16> Ops;
1146 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1147 for (unsigned i = 0; i != NumElements; ++i)
1148 Ops.push_back(getValue(CV->getOperand(i)));
1150 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1151 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1154 if (EltVT.isFloatingPoint())
1155 Op = DAG.getConstantFP(0, EltVT);
1157 Op = DAG.getConstant(0, EltVT);
1158 Ops.assign(NumElements, Op);
1161 // Create a BUILD_VECTOR node.
1162 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
1163 VT, &Ops[0], Ops.size());
1166 // If this is a static alloca, generate it as the frameindex instead of
1168 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1169 DenseMap<const AllocaInst*, int>::iterator SI =
1170 FuncInfo.StaticAllocaMap.find(AI);
1171 if (SI != FuncInfo.StaticAllocaMap.end())
1172 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1175 // If this is an instruction which fast-isel has deferred, select it now.
1176 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1177 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1178 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1179 SDValue Chain = DAG.getEntryNode();
1180 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL, V);
1183 llvm_unreachable("Can't get register for value!");
1186 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1187 SDValue Chain = getControlRoot();
1188 SmallVector<ISD::OutputArg, 8> Outs;
1189 SmallVector<SDValue, 8> OutVals;
1191 if (!FuncInfo.CanLowerReturn) {
1192 unsigned DemoteReg = FuncInfo.DemoteRegister;
1193 const Function *F = I.getParent()->getParent();
1195 // Emit a store of the return value through the virtual register.
1196 // Leave Outs empty so that LowerReturn won't try to load return
1197 // registers the usual way.
1198 SmallVector<EVT, 1> PtrValueVTs;
1199 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1202 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1203 SDValue RetOp = getValue(I.getOperand(0));
1205 SmallVector<EVT, 4> ValueVTs;
1206 SmallVector<uint64_t, 4> Offsets;
1207 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1208 unsigned NumValues = ValueVTs.size();
1210 SmallVector<SDValue, 4> Chains(NumValues);
1211 for (unsigned i = 0; i != NumValues; ++i) {
1212 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(),
1213 RetPtr.getValueType(), RetPtr,
1214 DAG.getIntPtrConstant(Offsets[i]));
1216 DAG.getStore(Chain, getCurDebugLoc(),
1217 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1218 // FIXME: better loc info would be nice.
1219 Add, MachinePointerInfo(), false, false, 0);
1222 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
1223 MVT::Other, &Chains[0], NumValues);
1224 } else if (I.getNumOperands() != 0) {
1225 SmallVector<EVT, 4> ValueVTs;
1226 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1227 unsigned NumValues = ValueVTs.size();
1229 SDValue RetOp = getValue(I.getOperand(0));
1230 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1231 EVT VT = ValueVTs[j];
1233 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1235 const Function *F = I.getParent()->getParent();
1236 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1238 ExtendKind = ISD::SIGN_EXTEND;
1239 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1241 ExtendKind = ISD::ZERO_EXTEND;
1243 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1244 VT = TLI.getTypeForExtArgOrReturn(VT.getSimpleVT(), ExtendKind);
1246 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
1247 MVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
1248 SmallVector<SDValue, 4> Parts(NumParts);
1249 getCopyToParts(DAG, getCurDebugLoc(),
1250 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1251 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1253 // 'inreg' on function refers to return value
1254 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1255 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1259 // Propagate extension type if any
1260 if (ExtendKind == ISD::SIGN_EXTEND)
1262 else if (ExtendKind == ISD::ZERO_EXTEND)
1265 for (unsigned i = 0; i < NumParts; ++i) {
1266 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1267 /*isfixed=*/true, 0, 0));
1268 OutVals.push_back(Parts[i]);
1274 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1275 CallingConv::ID CallConv =
1276 DAG.getMachineFunction().getFunction()->getCallingConv();
1277 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
1278 Outs, OutVals, getCurDebugLoc(), DAG);
1280 // Verify that the target's LowerReturn behaved as expected.
1281 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1282 "LowerReturn didn't return a valid chain!");
1284 // Update the DAG with the new chain value resulting from return lowering.
1288 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1289 /// created for it, emit nodes to copy the value into the virtual
1291 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1293 if (V->getType()->isEmptyTy())
1296 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1297 if (VMI != FuncInfo.ValueMap.end()) {
1298 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1299 CopyValueToVirtualRegister(V, VMI->second);
1303 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1304 /// the current basic block, add it to ValueMap now so that we'll get a
1306 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1307 // No need to export constants.
1308 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1310 // Already exported?
1311 if (FuncInfo.isExportedInst(V)) return;
1313 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1314 CopyValueToVirtualRegister(V, Reg);
1317 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1318 const BasicBlock *FromBB) {
1319 // The operands of the setcc have to be in this block. We don't know
1320 // how to export them from some other block.
1321 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1322 // Can export from current BB.
1323 if (VI->getParent() == FromBB)
1326 // Is already exported, noop.
1327 return FuncInfo.isExportedInst(V);
1330 // If this is an argument, we can export it if the BB is the entry block or
1331 // if it is already exported.
1332 if (isa<Argument>(V)) {
1333 if (FromBB == &FromBB->getParent()->getEntryBlock())
1336 // Otherwise, can only export this if it is already exported.
1337 return FuncInfo.isExportedInst(V);
1340 // Otherwise, constants can always be exported.
1344 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1345 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1346 const MachineBasicBlock *Dst) const {
1347 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1350 const BasicBlock *SrcBB = Src->getBasicBlock();
1351 const BasicBlock *DstBB = Dst->getBasicBlock();
1352 return BPI->getEdgeWeight(SrcBB, DstBB);
1355 void SelectionDAGBuilder::
1356 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1357 uint32_t Weight /* = 0 */) {
1359 Weight = getEdgeWeight(Src, Dst);
1360 Src->addSuccessor(Dst, Weight);
1364 static bool InBlock(const Value *V, const BasicBlock *BB) {
1365 if (const Instruction *I = dyn_cast<Instruction>(V))
1366 return I->getParent() == BB;
1370 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1371 /// This function emits a branch and is used at the leaves of an OR or an
1372 /// AND operator tree.
1375 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1376 MachineBasicBlock *TBB,
1377 MachineBasicBlock *FBB,
1378 MachineBasicBlock *CurBB,
1379 MachineBasicBlock *SwitchBB) {
1380 const BasicBlock *BB = CurBB->getBasicBlock();
1382 // If the leaf of the tree is a comparison, merge the condition into
1384 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1385 // The operands of the cmp have to be in this block. We don't know
1386 // how to export them from some other block. If this is the first block
1387 // of the sequence, no exporting is needed.
1388 if (CurBB == SwitchBB ||
1389 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1390 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1391 ISD::CondCode Condition;
1392 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1393 Condition = getICmpCondCode(IC->getPredicate());
1394 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1395 Condition = getFCmpCondCode(FC->getPredicate());
1396 if (TM.Options.NoNaNsFPMath)
1397 Condition = getFCmpCodeWithoutNaN(Condition);
1399 Condition = ISD::SETEQ; // silence warning.
1400 llvm_unreachable("Unknown compare instruction");
1403 CaseBlock CB(Condition, BOp->getOperand(0),
1404 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1405 SwitchCases.push_back(CB);
1410 // Create a CaseBlock record representing this branch.
1411 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1412 NULL, TBB, FBB, CurBB);
1413 SwitchCases.push_back(CB);
1416 /// FindMergedConditions - If Cond is an expression like
1417 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1418 MachineBasicBlock *TBB,
1419 MachineBasicBlock *FBB,
1420 MachineBasicBlock *CurBB,
1421 MachineBasicBlock *SwitchBB,
1423 // If this node is not part of the or/and tree, emit it as a branch.
1424 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1425 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1426 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1427 BOp->getParent() != CurBB->getBasicBlock() ||
1428 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1429 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1430 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB);
1434 // Create TmpBB after CurBB.
1435 MachineFunction::iterator BBI = CurBB;
1436 MachineFunction &MF = DAG.getMachineFunction();
1437 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1438 CurBB->getParent()->insert(++BBI, TmpBB);
1440 if (Opc == Instruction::Or) {
1441 // Codegen X | Y as:
1449 // Emit the LHS condition.
1450 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc);
1452 // Emit the RHS condition into TmpBB.
1453 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1455 assert(Opc == Instruction::And && "Unknown merge op!");
1456 // Codegen X & Y as:
1463 // This requires creation of TmpBB after CurBB.
1465 // Emit the LHS condition.
1466 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc);
1468 // Emit the RHS condition into TmpBB.
1469 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1473 /// If the set of cases should be emitted as a series of branches, return true.
1474 /// If we should emit this as a bunch of and/or'd together conditions, return
1477 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1478 if (Cases.size() != 2) return true;
1480 // If this is two comparisons of the same values or'd or and'd together, they
1481 // will get folded into a single comparison, so don't emit two blocks.
1482 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1483 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1484 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1485 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1489 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1490 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1491 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1492 Cases[0].CC == Cases[1].CC &&
1493 isa<Constant>(Cases[0].CmpRHS) &&
1494 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1495 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1497 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1504 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1505 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1507 // Update machine-CFG edges.
1508 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1510 // Figure out which block is immediately after the current one.
1511 MachineBasicBlock *NextBlock = 0;
1512 MachineFunction::iterator BBI = BrMBB;
1513 if (++BBI != FuncInfo.MF->end())
1516 if (I.isUnconditional()) {
1517 // Update machine-CFG edges.
1518 BrMBB->addSuccessor(Succ0MBB);
1520 // If this is not a fall-through branch, emit the branch.
1521 if (Succ0MBB != NextBlock)
1522 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1523 MVT::Other, getControlRoot(),
1524 DAG.getBasicBlock(Succ0MBB)));
1529 // If this condition is one of the special cases we handle, do special stuff
1531 const Value *CondVal = I.getCondition();
1532 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1534 // If this is a series of conditions that are or'd or and'd together, emit
1535 // this as a sequence of branches instead of setcc's with and/or operations.
1536 // As long as jumps are not expensive, this should improve performance.
1537 // For example, instead of something like:
1550 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1551 if (!TLI.isJumpExpensive() &&
1553 (BOp->getOpcode() == Instruction::And ||
1554 BOp->getOpcode() == Instruction::Or)) {
1555 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1557 // If the compares in later blocks need to use values not currently
1558 // exported from this block, export them now. This block should always
1559 // be the first entry.
1560 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1562 // Allow some cases to be rejected.
1563 if (ShouldEmitAsBranches(SwitchCases)) {
1564 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1565 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1566 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1569 // Emit the branch for this block.
1570 visitSwitchCase(SwitchCases[0], BrMBB);
1571 SwitchCases.erase(SwitchCases.begin());
1575 // Okay, we decided not to do this, remove any inserted MBB's and clear
1577 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1578 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1580 SwitchCases.clear();
1584 // Create a CaseBlock record representing this branch.
1585 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1586 NULL, Succ0MBB, Succ1MBB, BrMBB);
1588 // Use visitSwitchCase to actually insert the fast branch sequence for this
1590 visitSwitchCase(CB, BrMBB);
1593 /// visitSwitchCase - Emits the necessary code to represent a single node in
1594 /// the binary search tree resulting from lowering a switch instruction.
1595 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1596 MachineBasicBlock *SwitchBB) {
1598 SDValue CondLHS = getValue(CB.CmpLHS);
1599 DebugLoc dl = getCurDebugLoc();
1601 // Build the setcc now.
1602 if (CB.CmpMHS == NULL) {
1603 // Fold "(X == true)" to X and "(X == false)" to !X to
1604 // handle common cases produced by branch lowering.
1605 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1606 CB.CC == ISD::SETEQ)
1608 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1609 CB.CC == ISD::SETEQ) {
1610 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1611 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1613 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1615 assert(CB.CC == ISD::SETCC_INVALID &&
1616 "Condition is undefined for to-the-range belonging check.");
1618 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1619 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1621 SDValue CmpOp = getValue(CB.CmpMHS);
1622 EVT VT = CmpOp.getValueType();
1624 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(false)) {
1625 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1628 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1629 VT, CmpOp, DAG.getConstant(Low, VT));
1630 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1631 DAG.getConstant(High-Low, VT), ISD::SETULE);
1635 // Update successor info
1636 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1637 // TrueBB and FalseBB are always different unless the incoming IR is
1638 // degenerate. This only happens when running llc on weird IR.
1639 if (CB.TrueBB != CB.FalseBB)
1640 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1642 // Set NextBlock to be the MBB immediately after the current one, if any.
1643 // This is used to avoid emitting unnecessary branches to the next block.
1644 MachineBasicBlock *NextBlock = 0;
1645 MachineFunction::iterator BBI = SwitchBB;
1646 if (++BBI != FuncInfo.MF->end())
1649 // If the lhs block is the next block, invert the condition so that we can
1650 // fall through to the lhs instead of the rhs block.
1651 if (CB.TrueBB == NextBlock) {
1652 std::swap(CB.TrueBB, CB.FalseBB);
1653 SDValue True = DAG.getConstant(1, Cond.getValueType());
1654 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1657 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1658 MVT::Other, getControlRoot(), Cond,
1659 DAG.getBasicBlock(CB.TrueBB));
1661 // Insert the false branch. Do this even if it's a fall through branch,
1662 // this makes it easier to do DAG optimizations which require inverting
1663 // the branch condition.
1664 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1665 DAG.getBasicBlock(CB.FalseBB));
1667 DAG.setRoot(BrCond);
1670 /// visitJumpTable - Emit JumpTable node in the current MBB
1671 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1672 // Emit the code for the jump table
1673 assert(JT.Reg != -1U && "Should lower JT Header first!");
1674 EVT PTy = TLI.getPointerTy();
1675 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1677 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1678 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1679 MVT::Other, Index.getValue(1),
1681 DAG.setRoot(BrJumpTable);
1684 /// visitJumpTableHeader - This function emits necessary code to produce index
1685 /// in the JumpTable from switch case.
1686 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1687 JumpTableHeader &JTH,
1688 MachineBasicBlock *SwitchBB) {
1689 // Subtract the lowest switch case value from the value being switched on and
1690 // conditional branch to default mbb if the result is greater than the
1691 // difference between smallest and largest cases.
1692 SDValue SwitchOp = getValue(JTH.SValue);
1693 EVT VT = SwitchOp.getValueType();
1694 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1695 DAG.getConstant(JTH.First, VT));
1697 // The SDNode we just created, which holds the value being switched on minus
1698 // the smallest case value, needs to be copied to a virtual register so it
1699 // can be used as an index into the jump table in a subsequent basic block.
1700 // This value may be smaller or larger than the target's pointer type, and
1701 // therefore require extension or truncating.
1702 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy());
1704 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1705 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1706 JumpTableReg, SwitchOp);
1707 JT.Reg = JumpTableReg;
1709 // Emit the range check for the jump table, and branch to the default block
1710 // for the switch statement if the value being switched on exceeds the largest
1711 // case in the switch.
1712 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1713 TLI.getSetCCResultType(Sub.getValueType()), Sub,
1714 DAG.getConstant(JTH.Last-JTH.First,VT),
1717 // Set NextBlock to be the MBB immediately after the current one, if any.
1718 // This is used to avoid emitting unnecessary branches to the next block.
1719 MachineBasicBlock *NextBlock = 0;
1720 MachineFunction::iterator BBI = SwitchBB;
1722 if (++BBI != FuncInfo.MF->end())
1725 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1726 MVT::Other, CopyTo, CMP,
1727 DAG.getBasicBlock(JT.Default));
1729 if (JT.MBB != NextBlock)
1730 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1731 DAG.getBasicBlock(JT.MBB));
1733 DAG.setRoot(BrCond);
1736 /// visitBitTestHeader - This function emits necessary code to produce value
1737 /// suitable for "bit tests"
1738 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1739 MachineBasicBlock *SwitchBB) {
1740 // Subtract the minimum value
1741 SDValue SwitchOp = getValue(B.SValue);
1742 EVT VT = SwitchOp.getValueType();
1743 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1744 DAG.getConstant(B.First, VT));
1747 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1748 TLI.getSetCCResultType(Sub.getValueType()),
1749 Sub, DAG.getConstant(B.Range, VT),
1752 // Determine the type of the test operands.
1753 bool UsePtrType = false;
1754 if (!TLI.isTypeLegal(VT))
1757 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1758 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1759 // Switch table case range are encoded into series of masks.
1760 // Just use pointer type, it's guaranteed to fit.
1766 VT = TLI.getPointerTy();
1767 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT);
1770 B.RegVT = VT.getSimpleVT();
1771 B.Reg = FuncInfo.CreateReg(B.RegVT);
1772 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1775 // Set NextBlock to be the MBB immediately after the current one, if any.
1776 // This is used to avoid emitting unnecessary branches to the next block.
1777 MachineBasicBlock *NextBlock = 0;
1778 MachineFunction::iterator BBI = SwitchBB;
1779 if (++BBI != FuncInfo.MF->end())
1782 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1784 addSuccessorWithWeight(SwitchBB, B.Default);
1785 addSuccessorWithWeight(SwitchBB, MBB);
1787 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1788 MVT::Other, CopyTo, RangeCmp,
1789 DAG.getBasicBlock(B.Default));
1791 if (MBB != NextBlock)
1792 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1793 DAG.getBasicBlock(MBB));
1795 DAG.setRoot(BrRange);
1798 /// visitBitTestCase - this function produces one "bit test"
1799 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1800 MachineBasicBlock* NextMBB,
1801 uint32_t BranchWeightToNext,
1804 MachineBasicBlock *SwitchBB) {
1806 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1809 unsigned PopCount = CountPopulation_64(B.Mask);
1810 if (PopCount == 1) {
1811 // Testing for a single bit; just compare the shift count with what it
1812 // would need to be to shift a 1 bit in that position.
1813 Cmp = DAG.getSetCC(getCurDebugLoc(),
1814 TLI.getSetCCResultType(VT),
1816 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT),
1818 } else if (PopCount == BB.Range) {
1819 // There is only one zero bit in the range, test for it directly.
1820 Cmp = DAG.getSetCC(getCurDebugLoc(),
1821 TLI.getSetCCResultType(VT),
1823 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT),
1826 // Make desired shift
1827 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT,
1828 DAG.getConstant(1, VT), ShiftOp);
1830 // Emit bit tests and jumps
1831 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1832 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1833 Cmp = DAG.getSetCC(getCurDebugLoc(),
1834 TLI.getSetCCResultType(VT),
1835 AndOp, DAG.getConstant(0, VT),
1839 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1840 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1841 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1842 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1844 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1845 MVT::Other, getControlRoot(),
1846 Cmp, DAG.getBasicBlock(B.TargetBB));
1848 // Set NextBlock to be the MBB immediately after the current one, if any.
1849 // This is used to avoid emitting unnecessary branches to the next block.
1850 MachineBasicBlock *NextBlock = 0;
1851 MachineFunction::iterator BBI = SwitchBB;
1852 if (++BBI != FuncInfo.MF->end())
1855 if (NextMBB != NextBlock)
1856 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1857 DAG.getBasicBlock(NextMBB));
1862 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1863 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1865 // Retrieve successors.
1866 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1867 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1869 const Value *Callee(I.getCalledValue());
1870 const Function *Fn = dyn_cast<Function>(Callee);
1871 if (isa<InlineAsm>(Callee))
1873 else if (Fn && Fn->isIntrinsic()) {
1874 assert(Fn->getIntrinsicID() == Intrinsic::donothing);
1875 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
1877 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1879 // If the value of the invoke is used outside of its defining block, make it
1880 // available as a virtual register.
1881 CopyToExportRegsIfNeeded(&I);
1883 // Update successor info
1884 addSuccessorWithWeight(InvokeMBB, Return);
1885 addSuccessorWithWeight(InvokeMBB, LandingPad);
1887 // Drop into normal successor.
1888 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1889 MVT::Other, getControlRoot(),
1890 DAG.getBasicBlock(Return)));
1893 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
1894 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
1897 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
1898 assert(FuncInfo.MBB->isLandingPad() &&
1899 "Call to landingpad not in landing pad!");
1901 MachineBasicBlock *MBB = FuncInfo.MBB;
1902 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
1903 AddLandingPadInfo(LP, MMI, MBB);
1905 // If there aren't registers to copy the values into (e.g., during SjLj
1906 // exceptions), then don't bother to create these DAG nodes.
1907 if (TLI.getExceptionPointerRegister() == 0 &&
1908 TLI.getExceptionSelectorRegister() == 0)
1911 SmallVector<EVT, 2> ValueVTs;
1912 ComputeValueVTs(TLI, LP.getType(), ValueVTs);
1913 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
1915 // Get the two live-in registers as SDValues. The physregs have already been
1916 // copied into virtual registers.
1918 Ops[0] = DAG.getZExtOrTrunc(
1919 DAG.getCopyFromReg(DAG.getEntryNode(), getCurDebugLoc(),
1920 FuncInfo.ExceptionPointerVirtReg, TLI.getPointerTy()),
1921 getCurDebugLoc(), ValueVTs[0]);
1922 Ops[1] = DAG.getZExtOrTrunc(
1923 DAG.getCopyFromReg(DAG.getEntryNode(), getCurDebugLoc(),
1924 FuncInfo.ExceptionSelectorVirtReg, TLI.getPointerTy()),
1925 getCurDebugLoc(), ValueVTs[1]);
1928 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
1929 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
1934 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1935 /// small case ranges).
1936 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
1937 CaseRecVector& WorkList,
1939 MachineBasicBlock *Default,
1940 MachineBasicBlock *SwitchBB) {
1941 // Size is the number of Cases represented by this range.
1942 size_t Size = CR.Range.second - CR.Range.first;
1946 // Get the MachineFunction which holds the current MBB. This is used when
1947 // inserting any additional MBBs necessary to represent the switch.
1948 MachineFunction *CurMF = FuncInfo.MF;
1950 // Figure out which block is immediately after the current one.
1951 MachineBasicBlock *NextBlock = 0;
1952 MachineFunction::iterator BBI = CR.CaseBB;
1954 if (++BBI != FuncInfo.MF->end())
1957 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1958 // If any two of the cases has the same destination, and if one value
1959 // is the same as the other, but has one bit unset that the other has set,
1960 // use bit manipulation to do two compares at once. For example:
1961 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1962 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
1963 // TODO: Handle cases where CR.CaseBB != SwitchBB.
1964 if (Size == 2 && CR.CaseBB == SwitchBB) {
1965 Case &Small = *CR.Range.first;
1966 Case &Big = *(CR.Range.second-1);
1968 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
1969 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
1970 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
1972 // Check that there is only one bit different.
1973 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
1974 (SmallValue | BigValue) == BigValue) {
1975 // Isolate the common bit.
1976 APInt CommonBit = BigValue & ~SmallValue;
1977 assert((SmallValue | CommonBit) == BigValue &&
1978 CommonBit.countPopulation() == 1 && "Not a common bit?");
1980 SDValue CondLHS = getValue(SV);
1981 EVT VT = CondLHS.getValueType();
1982 DebugLoc DL = getCurDebugLoc();
1984 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
1985 DAG.getConstant(CommonBit, VT));
1986 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
1987 Or, DAG.getConstant(BigValue, VT),
1990 // Update successor info.
1991 // Both Small and Big will jump to Small.BB, so we sum up the weights.
1992 addSuccessorWithWeight(SwitchBB, Small.BB,
1993 Small.ExtraWeight + Big.ExtraWeight);
1994 addSuccessorWithWeight(SwitchBB, Default,
1995 // The default destination is the first successor in IR.
1996 BPI ? BPI->getEdgeWeight(SwitchBB->getBasicBlock(), (unsigned)0) : 0);
1998 // Insert the true branch.
1999 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
2000 getControlRoot(), Cond,
2001 DAG.getBasicBlock(Small.BB));
2003 // Insert the false branch.
2004 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
2005 DAG.getBasicBlock(Default));
2007 DAG.setRoot(BrCond);
2013 // Order cases by weight so the most likely case will be checked first.
2014 uint32_t UnhandledWeights = 0;
2016 for (CaseItr I = CR.Range.first, IE = CR.Range.second; I != IE; ++I) {
2017 uint32_t IWeight = I->ExtraWeight;
2018 UnhandledWeights += IWeight;
2019 for (CaseItr J = CR.Range.first; J < I; ++J) {
2020 uint32_t JWeight = J->ExtraWeight;
2021 if (IWeight > JWeight)
2026 // Rearrange the case blocks so that the last one falls through if possible.
2027 Case &BackCase = *(CR.Range.second-1);
2029 NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
2030 // The last case block won't fall through into 'NextBlock' if we emit the
2031 // branches in this order. See if rearranging a case value would help.
2032 // We start at the bottom as it's the case with the least weight.
2033 for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I){
2034 if (I->BB == NextBlock) {
2035 std::swap(*I, BackCase);
2041 // Create a CaseBlock record representing a conditional branch to
2042 // the Case's target mbb if the value being switched on SV is equal
2044 MachineBasicBlock *CurBlock = CR.CaseBB;
2045 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2046 MachineBasicBlock *FallThrough;
2048 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
2049 CurMF->insert(BBI, FallThrough);
2051 // Put SV in a virtual register to make it available from the new blocks.
2052 ExportFromCurrentBlock(SV);
2054 // If the last case doesn't match, go to the default block.
2055 FallThrough = Default;
2058 const Value *RHS, *LHS, *MHS;
2060 if (I->High == I->Low) {
2061 // This is just small small case range :) containing exactly 1 case
2063 LHS = SV; RHS = I->High; MHS = NULL;
2065 CC = ISD::SETCC_INVALID;
2066 LHS = I->Low; MHS = SV; RHS = I->High;
2069 // The false weight should be sum of all un-handled cases.
2070 UnhandledWeights -= I->ExtraWeight;
2071 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough,
2073 /* trueweight */ I->ExtraWeight,
2074 /* falseweight */ UnhandledWeights);
2076 // If emitting the first comparison, just call visitSwitchCase to emit the
2077 // code into the current block. Otherwise, push the CaseBlock onto the
2078 // vector to be later processed by SDISel, and insert the node's MBB
2079 // before the next MBB.
2080 if (CurBlock == SwitchBB)
2081 visitSwitchCase(CB, SwitchBB);
2083 SwitchCases.push_back(CB);
2085 CurBlock = FallThrough;
2091 static inline bool areJTsAllowed(const TargetLowering &TLI) {
2092 return TLI.supportJumpTables() &&
2093 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
2094 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
2097 static APInt ComputeRange(const APInt &First, const APInt &Last) {
2098 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
2099 APInt LastExt = Last.zext(BitWidth), FirstExt = First.zext(BitWidth);
2100 return (LastExt - FirstExt + 1ULL);
2103 /// handleJTSwitchCase - Emit jumptable for current switch case range
2104 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR,
2105 CaseRecVector &WorkList,
2107 MachineBasicBlock *Default,
2108 MachineBasicBlock *SwitchBB) {
2109 Case& FrontCase = *CR.Range.first;
2110 Case& BackCase = *(CR.Range.second-1);
2112 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2113 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2115 APInt TSize(First.getBitWidth(), 0);
2116 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I)
2119 if (!areJTsAllowed(TLI) || TSize.ult(TLI.getMinimumJumpTableEntries()))
2122 APInt Range = ComputeRange(First, Last);
2123 // The density is TSize / Range. Require at least 40%.
2124 // It should not be possible for IntTSize to saturate for sane code, but make
2125 // sure we handle Range saturation correctly.
2126 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10);
2127 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10);
2128 if (IntTSize * 10 < IntRange * 4)
2131 DEBUG(dbgs() << "Lowering jump table\n"
2132 << "First entry: " << First << ". Last entry: " << Last << '\n'
2133 << "Range: " << Range << ". Size: " << TSize << ".\n\n");
2135 // Get the MachineFunction which holds the current MBB. This is used when
2136 // inserting any additional MBBs necessary to represent the switch.
2137 MachineFunction *CurMF = FuncInfo.MF;
2139 // Figure out which block is immediately after the current one.
2140 MachineFunction::iterator BBI = CR.CaseBB;
2143 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2145 // Create a new basic block to hold the code for loading the address
2146 // of the jump table, and jumping to it. Update successor information;
2147 // we will either branch to the default case for the switch, or the jump
2149 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2150 CurMF->insert(BBI, JumpTableBB);
2152 addSuccessorWithWeight(CR.CaseBB, Default);
2153 addSuccessorWithWeight(CR.CaseBB, JumpTableBB);
2155 // Build a vector of destination BBs, corresponding to each target
2156 // of the jump table. If the value of the jump table slot corresponds to
2157 // a case statement, push the case's BB onto the vector, otherwise, push
2159 std::vector<MachineBasicBlock*> DestBBs;
2161 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
2162 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
2163 const APInt &High = cast<ConstantInt>(I->High)->getValue();
2165 if (Low.ule(TEI) && TEI.ule(High)) {
2166 DestBBs.push_back(I->BB);
2170 DestBBs.push_back(Default);
2174 // Calculate weight for each unique destination in CR.
2175 DenseMap<MachineBasicBlock*, uint32_t> DestWeights;
2177 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2178 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2179 DestWeights.find(I->BB);
2180 if (Itr != DestWeights.end())
2181 Itr->second += I->ExtraWeight;
2183 DestWeights[I->BB] = I->ExtraWeight;
2186 // Update successor info. Add one edge to each unique successor.
2187 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2188 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
2189 E = DestBBs.end(); I != E; ++I) {
2190 if (!SuccsHandled[(*I)->getNumber()]) {
2191 SuccsHandled[(*I)->getNumber()] = true;
2192 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2193 DestWeights.find(*I);
2194 addSuccessorWithWeight(JumpTableBB, *I,
2195 Itr != DestWeights.end() ? Itr->second : 0);
2199 // Create a jump table index for this jump table.
2200 unsigned JTEncoding = TLI.getJumpTableEncoding();
2201 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
2202 ->createJumpTableIndex(DestBBs);
2204 // Set the jump table information so that we can codegen it as a second
2205 // MachineBasicBlock
2206 JumpTable JT(-1U, JTI, JumpTableBB, Default);
2207 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
2208 if (CR.CaseBB == SwitchBB)
2209 visitJumpTableHeader(JT, JTH, SwitchBB);
2211 JTCases.push_back(JumpTableBlock(JTH, JT));
2215 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2217 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
2218 CaseRecVector& WorkList,
2220 MachineBasicBlock *Default,
2221 MachineBasicBlock *SwitchBB) {
2222 // Get the MachineFunction which holds the current MBB. This is used when
2223 // inserting any additional MBBs necessary to represent the switch.
2224 MachineFunction *CurMF = FuncInfo.MF;
2226 // Figure out which block is immediately after the current one.
2227 MachineFunction::iterator BBI = CR.CaseBB;
2230 Case& FrontCase = *CR.Range.first;
2231 Case& BackCase = *(CR.Range.second-1);
2232 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2234 // Size is the number of Cases represented by this range.
2235 unsigned Size = CR.Range.second - CR.Range.first;
2237 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2238 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2240 CaseItr Pivot = CR.Range.first + Size/2;
2242 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2243 // (heuristically) allow us to emit JumpTable's later.
2244 APInt TSize(First.getBitWidth(), 0);
2245 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2249 APInt LSize = FrontCase.size();
2250 APInt RSize = TSize-LSize;
2251 DEBUG(dbgs() << "Selecting best pivot: \n"
2252 << "First: " << First << ", Last: " << Last <<'\n'
2253 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2254 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2256 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2257 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2258 APInt Range = ComputeRange(LEnd, RBegin);
2259 assert((Range - 2ULL).isNonNegative() &&
2260 "Invalid case distance");
2261 // Use volatile double here to avoid excess precision issues on some hosts,
2262 // e.g. that use 80-bit X87 registers.
2263 volatile double LDensity =
2264 (double)LSize.roundToDouble() /
2265 (LEnd - First + 1ULL).roundToDouble();
2266 volatile double RDensity =
2267 (double)RSize.roundToDouble() /
2268 (Last - RBegin + 1ULL).roundToDouble();
2269 double Metric = Range.logBase2()*(LDensity+RDensity);
2270 // Should always split in some non-trivial place
2271 DEBUG(dbgs() <<"=>Step\n"
2272 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2273 << "LDensity: " << LDensity
2274 << ", RDensity: " << RDensity << '\n'
2275 << "Metric: " << Metric << '\n');
2276 if (FMetric < Metric) {
2279 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2285 if (areJTsAllowed(TLI)) {
2286 // If our case is dense we *really* should handle it earlier!
2287 assert((FMetric > 0) && "Should handle dense range earlier!");
2289 Pivot = CR.Range.first + Size/2;
2292 CaseRange LHSR(CR.Range.first, Pivot);
2293 CaseRange RHSR(Pivot, CR.Range.second);
2294 const Constant *C = Pivot->Low;
2295 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2297 // We know that we branch to the LHS if the Value being switched on is
2298 // less than the Pivot value, C. We use this to optimize our binary
2299 // tree a bit, by recognizing that if SV is greater than or equal to the
2300 // LHS's Case Value, and that Case Value is exactly one less than the
2301 // Pivot's Value, then we can branch directly to the LHS's Target,
2302 // rather than creating a leaf node for it.
2303 if ((LHSR.second - LHSR.first) == 1 &&
2304 LHSR.first->High == CR.GE &&
2305 cast<ConstantInt>(C)->getValue() ==
2306 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2307 TrueBB = LHSR.first->BB;
2309 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2310 CurMF->insert(BBI, TrueBB);
2311 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2313 // Put SV in a virtual register to make it available from the new blocks.
2314 ExportFromCurrentBlock(SV);
2317 // Similar to the optimization above, if the Value being switched on is
2318 // known to be less than the Constant CR.LT, and the current Case Value
2319 // is CR.LT - 1, then we can branch directly to the target block for
2320 // the current Case Value, rather than emitting a RHS leaf node for it.
2321 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2322 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2323 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2324 FalseBB = RHSR.first->BB;
2326 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2327 CurMF->insert(BBI, FalseBB);
2328 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2330 // Put SV in a virtual register to make it available from the new blocks.
2331 ExportFromCurrentBlock(SV);
2334 // Create a CaseBlock record representing a conditional branch to
2335 // the LHS node if the value being switched on SV is less than C.
2336 // Otherwise, branch to LHS.
2337 CaseBlock CB(ISD::SETULT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
2339 if (CR.CaseBB == SwitchBB)
2340 visitSwitchCase(CB, SwitchBB);
2342 SwitchCases.push_back(CB);
2347 /// handleBitTestsSwitchCase - if current case range has few destination and
2348 /// range span less, than machine word bitwidth, encode case range into series
2349 /// of masks and emit bit tests with these masks.
2350 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2351 CaseRecVector& WorkList,
2353 MachineBasicBlock* Default,
2354 MachineBasicBlock *SwitchBB){
2355 EVT PTy = TLI.getPointerTy();
2356 unsigned IntPtrBits = PTy.getSizeInBits();
2358 Case& FrontCase = *CR.Range.first;
2359 Case& BackCase = *(CR.Range.second-1);
2361 // Get the MachineFunction which holds the current MBB. This is used when
2362 // inserting any additional MBBs necessary to represent the switch.
2363 MachineFunction *CurMF = FuncInfo.MF;
2365 // If target does not have legal shift left, do not emit bit tests at all.
2366 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy()))
2370 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2372 // Single case counts one, case range - two.
2373 numCmps += (I->Low == I->High ? 1 : 2);
2376 // Count unique destinations
2377 SmallSet<MachineBasicBlock*, 4> Dests;
2378 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2379 Dests.insert(I->BB);
2380 if (Dests.size() > 3)
2381 // Don't bother the code below, if there are too much unique destinations
2384 DEBUG(dbgs() << "Total number of unique destinations: "
2385 << Dests.size() << '\n'
2386 << "Total number of comparisons: " << numCmps << '\n');
2388 // Compute span of values.
2389 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2390 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2391 APInt cmpRange = maxValue - minValue;
2393 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2394 << "Low bound: " << minValue << '\n'
2395 << "High bound: " << maxValue << '\n');
2397 if (cmpRange.uge(IntPtrBits) ||
2398 (!(Dests.size() == 1 && numCmps >= 3) &&
2399 !(Dests.size() == 2 && numCmps >= 5) &&
2400 !(Dests.size() >= 3 && numCmps >= 6)))
2403 DEBUG(dbgs() << "Emitting bit tests\n");
2404 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2406 // Optimize the case where all the case values fit in a
2407 // word without having to subtract minValue. In this case,
2408 // we can optimize away the subtraction.
2409 if (maxValue.ult(IntPtrBits)) {
2410 cmpRange = maxValue;
2412 lowBound = minValue;
2415 CaseBitsVector CasesBits;
2416 unsigned i, count = 0;
2418 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2419 MachineBasicBlock* Dest = I->BB;
2420 for (i = 0; i < count; ++i)
2421 if (Dest == CasesBits[i].BB)
2425 assert((count < 3) && "Too much destinations to test!");
2426 CasesBits.push_back(CaseBits(0, Dest, 0, 0/*Weight*/));
2430 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2431 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2433 uint64_t lo = (lowValue - lowBound).getZExtValue();
2434 uint64_t hi = (highValue - lowBound).getZExtValue();
2435 CasesBits[i].ExtraWeight += I->ExtraWeight;
2437 for (uint64_t j = lo; j <= hi; j++) {
2438 CasesBits[i].Mask |= 1ULL << j;
2439 CasesBits[i].Bits++;
2443 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2447 // Figure out which block is immediately after the current one.
2448 MachineFunction::iterator BBI = CR.CaseBB;
2451 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2453 DEBUG(dbgs() << "Cases:\n");
2454 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2455 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2456 << ", Bits: " << CasesBits[i].Bits
2457 << ", BB: " << CasesBits[i].BB << '\n');
2459 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2460 CurMF->insert(BBI, CaseBB);
2461 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2463 CasesBits[i].BB, CasesBits[i].ExtraWeight));
2465 // Put SV in a virtual register to make it available from the new blocks.
2466 ExportFromCurrentBlock(SV);
2469 BitTestBlock BTB(lowBound, cmpRange, SV,
2470 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2471 CR.CaseBB, Default, BTC);
2473 if (CR.CaseBB == SwitchBB)
2474 visitBitTestHeader(BTB, SwitchBB);
2476 BitTestCases.push_back(BTB);
2481 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2482 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2483 const SwitchInst& SI) {
2485 /// Use a shorter form of declaration, and also
2486 /// show the we want to use CRSBuilder as Clusterifier.
2487 typedef IntegersSubsetMapping<MachineBasicBlock> Clusterifier;
2489 Clusterifier TheClusterifier;
2491 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2492 // Start with "simple" cases
2493 for (SwitchInst::ConstCaseIt i = SI.case_begin(), e = SI.case_end();
2495 const BasicBlock *SuccBB = i.getCaseSuccessor();
2496 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB];
2498 TheClusterifier.add(i.getCaseValueEx(), SMBB,
2499 BPI ? BPI->getEdgeWeight(SI.getParent(), i.getSuccessorIndex()) : 0);
2502 TheClusterifier.optimize();
2505 for (Clusterifier::RangeIterator i = TheClusterifier.begin(),
2506 e = TheClusterifier.end(); i != e; ++i, ++numCmps) {
2507 Clusterifier::Cluster &C = *i;
2508 // Update edge weight for the cluster.
2509 unsigned W = C.first.Weight;
2511 // FIXME: Currently work with ConstantInt based numbers.
2512 // Changing it to APInt based is a pretty heavy for this commit.
2513 Cases.push_back(Case(C.first.getLow().toConstantInt(),
2514 C.first.getHigh().toConstantInt(), C.second, W));
2516 if (C.first.getLow() != C.first.getHigh())
2517 // A range counts double, since it requires two compares.
2524 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2525 MachineBasicBlock *Last) {
2527 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2528 if (JTCases[i].first.HeaderBB == First)
2529 JTCases[i].first.HeaderBB = Last;
2531 // Update BitTestCases.
2532 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2533 if (BitTestCases[i].Parent == First)
2534 BitTestCases[i].Parent = Last;
2537 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2538 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2540 // Figure out which block is immediately after the current one.
2541 MachineBasicBlock *NextBlock = 0;
2542 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2544 // If there is only the default destination, branch to it if it is not the
2545 // next basic block. Otherwise, just fall through.
2546 if (!SI.getNumCases()) {
2547 // Update machine-CFG edges.
2549 // If this is not a fall-through branch, emit the branch.
2550 SwitchMBB->addSuccessor(Default);
2551 if (Default != NextBlock)
2552 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2553 MVT::Other, getControlRoot(),
2554 DAG.getBasicBlock(Default)));
2559 // If there are any non-default case statements, create a vector of Cases
2560 // representing each one, and sort the vector so that we can efficiently
2561 // create a binary search tree from them.
2563 size_t numCmps = Clusterify(Cases, SI);
2564 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2565 << ". Total compares: " << numCmps << '\n');
2568 // Get the Value to be switched on and default basic blocks, which will be
2569 // inserted into CaseBlock records, representing basic blocks in the binary
2571 const Value *SV = SI.getCondition();
2573 // Push the initial CaseRec onto the worklist
2574 CaseRecVector WorkList;
2575 WorkList.push_back(CaseRec(SwitchMBB,0,0,
2576 CaseRange(Cases.begin(),Cases.end())));
2578 while (!WorkList.empty()) {
2579 // Grab a record representing a case range to process off the worklist
2580 CaseRec CR = WorkList.back();
2581 WorkList.pop_back();
2583 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2586 // If the range has few cases (two or less) emit a series of specific
2588 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2591 // If the switch has more than N blocks, and is at least 40% dense, and the
2592 // target supports indirect branches, then emit a jump table rather than
2593 // lowering the switch to a binary tree of conditional branches.
2594 // N defaults to 4 and is controlled via TLS.getMinimumJumpTableEntries().
2595 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2598 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2599 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2600 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2604 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2605 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2607 // Update machine-CFG edges with unique successors.
2608 SmallSet<BasicBlock*, 32> Done;
2609 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2610 BasicBlock *BB = I.getSuccessor(i);
2611 bool Inserted = Done.insert(BB);
2615 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2616 addSuccessorWithWeight(IndirectBrMBB, Succ);
2619 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(),
2620 MVT::Other, getControlRoot(),
2621 getValue(I.getAddress())));
2624 void SelectionDAGBuilder::visitFSub(const User &I) {
2625 // -0.0 - X --> fneg
2626 Type *Ty = I.getType();
2627 if (isa<Constant>(I.getOperand(0)) &&
2628 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2629 SDValue Op2 = getValue(I.getOperand(1));
2630 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2631 Op2.getValueType(), Op2));
2635 visitBinary(I, ISD::FSUB);
2638 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2639 SDValue Op1 = getValue(I.getOperand(0));
2640 SDValue Op2 = getValue(I.getOperand(1));
2641 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2642 Op1.getValueType(), Op1, Op2));
2645 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2646 SDValue Op1 = getValue(I.getOperand(0));
2647 SDValue Op2 = getValue(I.getOperand(1));
2649 EVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType());
2651 // Coerce the shift amount to the right type if we can.
2652 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2653 unsigned ShiftSize = ShiftTy.getSizeInBits();
2654 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2655 DebugLoc DL = getCurDebugLoc();
2657 // If the operand is smaller than the shift count type, promote it.
2658 if (ShiftSize > Op2Size)
2659 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2661 // If the operand is larger than the shift count type but the shift
2662 // count type has enough bits to represent any shift value, truncate
2663 // it now. This is a common case and it exposes the truncate to
2664 // optimization early.
2665 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2666 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2667 // Otherwise we'll need to temporarily settle for some other convenient
2668 // type. Type legalization will make adjustments once the shiftee is split.
2670 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2673 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2674 Op1.getValueType(), Op1, Op2));
2677 void SelectionDAGBuilder::visitSDiv(const User &I) {
2678 SDValue Op1 = getValue(I.getOperand(0));
2679 SDValue Op2 = getValue(I.getOperand(1));
2681 // Turn exact SDivs into multiplications.
2682 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2684 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2685 !isa<ConstantSDNode>(Op1) &&
2686 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2687 setValue(&I, TLI.BuildExactSDIV(Op1, Op2, getCurDebugLoc(), DAG));
2689 setValue(&I, DAG.getNode(ISD::SDIV, getCurDebugLoc(), Op1.getValueType(),
2693 void SelectionDAGBuilder::visitICmp(const User &I) {
2694 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2695 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2696 predicate = IC->getPredicate();
2697 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2698 predicate = ICmpInst::Predicate(IC->getPredicate());
2699 SDValue Op1 = getValue(I.getOperand(0));
2700 SDValue Op2 = getValue(I.getOperand(1));
2701 ISD::CondCode Opcode = getICmpCondCode(predicate);
2703 EVT DestVT = TLI.getValueType(I.getType());
2704 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
2707 void SelectionDAGBuilder::visitFCmp(const User &I) {
2708 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2709 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2710 predicate = FC->getPredicate();
2711 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2712 predicate = FCmpInst::Predicate(FC->getPredicate());
2713 SDValue Op1 = getValue(I.getOperand(0));
2714 SDValue Op2 = getValue(I.getOperand(1));
2715 ISD::CondCode Condition = getFCmpCondCode(predicate);
2716 if (TM.Options.NoNaNsFPMath)
2717 Condition = getFCmpCodeWithoutNaN(Condition);
2718 EVT DestVT = TLI.getValueType(I.getType());
2719 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2722 void SelectionDAGBuilder::visitSelect(const User &I) {
2723 SmallVector<EVT, 4> ValueVTs;
2724 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2725 unsigned NumValues = ValueVTs.size();
2726 if (NumValues == 0) return;
2728 SmallVector<SDValue, 4> Values(NumValues);
2729 SDValue Cond = getValue(I.getOperand(0));
2730 SDValue TrueVal = getValue(I.getOperand(1));
2731 SDValue FalseVal = getValue(I.getOperand(2));
2732 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2733 ISD::VSELECT : ISD::SELECT;
2735 for (unsigned i = 0; i != NumValues; ++i)
2736 Values[i] = DAG.getNode(OpCode, getCurDebugLoc(),
2737 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2739 SDValue(TrueVal.getNode(),
2740 TrueVal.getResNo() + i),
2741 SDValue(FalseVal.getNode(),
2742 FalseVal.getResNo() + i));
2744 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2745 DAG.getVTList(&ValueVTs[0], NumValues),
2746 &Values[0], NumValues));
2749 void SelectionDAGBuilder::visitTrunc(const User &I) {
2750 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2751 SDValue N = getValue(I.getOperand(0));
2752 EVT DestVT = TLI.getValueType(I.getType());
2753 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2756 void SelectionDAGBuilder::visitZExt(const User &I) {
2757 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2758 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2759 SDValue N = getValue(I.getOperand(0));
2760 EVT DestVT = TLI.getValueType(I.getType());
2761 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2764 void SelectionDAGBuilder::visitSExt(const User &I) {
2765 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2766 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2767 SDValue N = getValue(I.getOperand(0));
2768 EVT DestVT = TLI.getValueType(I.getType());
2769 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2772 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2773 // FPTrunc is never a no-op cast, no need to check
2774 SDValue N = getValue(I.getOperand(0));
2775 EVT DestVT = TLI.getValueType(I.getType());
2776 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2778 DAG.getTargetConstant(0, TLI.getPointerTy())));
2781 void SelectionDAGBuilder::visitFPExt(const User &I){
2782 // FPExt is never a no-op cast, no need to check
2783 SDValue N = getValue(I.getOperand(0));
2784 EVT DestVT = TLI.getValueType(I.getType());
2785 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2788 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2789 // FPToUI is never a no-op cast, no need to check
2790 SDValue N = getValue(I.getOperand(0));
2791 EVT DestVT = TLI.getValueType(I.getType());
2792 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2795 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2796 // FPToSI is never a no-op cast, no need to check
2797 SDValue N = getValue(I.getOperand(0));
2798 EVT DestVT = TLI.getValueType(I.getType());
2799 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2802 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2803 // UIToFP is never a no-op cast, no need to check
2804 SDValue N = getValue(I.getOperand(0));
2805 EVT DestVT = TLI.getValueType(I.getType());
2806 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2809 void SelectionDAGBuilder::visitSIToFP(const User &I){
2810 // SIToFP is never a no-op cast, no need to check
2811 SDValue N = getValue(I.getOperand(0));
2812 EVT DestVT = TLI.getValueType(I.getType());
2813 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2816 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2817 // What to do depends on the size of the integer and the size of the pointer.
2818 // We can either truncate, zero extend, or no-op, accordingly.
2819 SDValue N = getValue(I.getOperand(0));
2820 EVT DestVT = TLI.getValueType(I.getType());
2821 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2824 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2825 // What to do depends on the size of the integer and the size of the pointer.
2826 // We can either truncate, zero extend, or no-op, accordingly.
2827 SDValue N = getValue(I.getOperand(0));
2828 EVT DestVT = TLI.getValueType(I.getType());
2829 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2832 void SelectionDAGBuilder::visitBitCast(const User &I) {
2833 SDValue N = getValue(I.getOperand(0));
2834 EVT DestVT = TLI.getValueType(I.getType());
2836 // BitCast assures us that source and destination are the same size so this is
2837 // either a BITCAST or a no-op.
2838 if (DestVT != N.getValueType())
2839 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
2840 DestVT, N)); // convert types.
2842 setValue(&I, N); // noop cast.
2845 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2846 SDValue InVec = getValue(I.getOperand(0));
2847 SDValue InVal = getValue(I.getOperand(1));
2848 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2850 getValue(I.getOperand(2)));
2851 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2852 TLI.getValueType(I.getType()),
2853 InVec, InVal, InIdx));
2856 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2857 SDValue InVec = getValue(I.getOperand(0));
2858 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2860 getValue(I.getOperand(1)));
2861 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2862 TLI.getValueType(I.getType()), InVec, InIdx));
2865 // Utility for visitShuffleVector - Return true if every element in Mask,
2866 // beginning from position Pos and ending in Pos+Size, falls within the
2867 // specified sequential range [L, L+Pos). or is undef.
2868 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2869 unsigned Pos, unsigned Size, int Low) {
2870 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2871 if (Mask[i] >= 0 && Mask[i] != Low)
2876 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2877 SDValue Src1 = getValue(I.getOperand(0));
2878 SDValue Src2 = getValue(I.getOperand(1));
2880 SmallVector<int, 8> Mask;
2881 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2882 unsigned MaskNumElts = Mask.size();
2884 EVT VT = TLI.getValueType(I.getType());
2885 EVT SrcVT = Src1.getValueType();
2886 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2888 if (SrcNumElts == MaskNumElts) {
2889 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2894 // Normalize the shuffle vector since mask and vector length don't match.
2895 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2896 // Mask is longer than the source vectors and is a multiple of the source
2897 // vectors. We can use concatenate vector to make the mask and vectors
2899 if (SrcNumElts*2 == MaskNumElts) {
2900 // First check for Src1 in low and Src2 in high
2901 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2902 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2903 // The shuffle is concatenating two vectors together.
2904 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2908 // Then check for Src2 in low and Src1 in high
2909 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2910 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2911 // The shuffle is concatenating two vectors together.
2912 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2918 // Pad both vectors with undefs to make them the same length as the mask.
2919 unsigned NumConcat = MaskNumElts / SrcNumElts;
2920 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2921 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2922 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2924 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2925 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2929 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2930 getCurDebugLoc(), VT,
2931 &MOps1[0], NumConcat);
2932 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2933 getCurDebugLoc(), VT,
2934 &MOps2[0], NumConcat);
2936 // Readjust mask for new input vector length.
2937 SmallVector<int, 8> MappedOps;
2938 for (unsigned i = 0; i != MaskNumElts; ++i) {
2940 if (Idx >= (int)SrcNumElts)
2941 Idx -= SrcNumElts - MaskNumElts;
2942 MappedOps.push_back(Idx);
2945 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2950 if (SrcNumElts > MaskNumElts) {
2951 // Analyze the access pattern of the vector to see if we can extract
2952 // two subvectors and do the shuffle. The analysis is done by calculating
2953 // the range of elements the mask access on both vectors.
2954 int MinRange[2] = { static_cast<int>(SrcNumElts),
2955 static_cast<int>(SrcNumElts)};
2956 int MaxRange[2] = {-1, -1};
2958 for (unsigned i = 0; i != MaskNumElts; ++i) {
2964 if (Idx >= (int)SrcNumElts) {
2968 if (Idx > MaxRange[Input])
2969 MaxRange[Input] = Idx;
2970 if (Idx < MinRange[Input])
2971 MinRange[Input] = Idx;
2974 // Check if the access is smaller than the vector size and can we find
2975 // a reasonable extract index.
2976 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2978 int StartIdx[2]; // StartIdx to extract from
2979 for (unsigned Input = 0; Input < 2; ++Input) {
2980 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2981 RangeUse[Input] = 0; // Unused
2982 StartIdx[Input] = 0;
2986 // Find a good start index that is a multiple of the mask length. Then
2987 // see if the rest of the elements are in range.
2988 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2989 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2990 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2991 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2994 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2995 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2998 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
2999 // Extract appropriate subvector and generate a vector shuffle
3000 for (unsigned Input = 0; Input < 2; ++Input) {
3001 SDValue &Src = Input == 0 ? Src1 : Src2;
3002 if (RangeUse[Input] == 0)
3003 Src = DAG.getUNDEF(VT);
3005 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
3006 Src, DAG.getIntPtrConstant(StartIdx[Input]));
3009 // Calculate new mask.
3010 SmallVector<int, 8> MappedOps;
3011 for (unsigned i = 0; i != MaskNumElts; ++i) {
3014 if (Idx < (int)SrcNumElts)
3017 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
3019 MappedOps.push_back(Idx);
3022 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
3028 // We can't use either concat vectors or extract subvectors so fall back to
3029 // replacing the shuffle with extract and build vector.
3030 // to insert and build vector.
3031 EVT EltVT = VT.getVectorElementType();
3032 EVT PtrVT = TLI.getPointerTy();
3033 SmallVector<SDValue,8> Ops;
3034 for (unsigned i = 0; i != MaskNumElts; ++i) {
3039 Res = DAG.getUNDEF(EltVT);
3041 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
3042 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
3044 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
3045 EltVT, Src, DAG.getConstant(Idx, PtrVT));
3051 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
3052 VT, &Ops[0], Ops.size()));
3055 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
3056 const Value *Op0 = I.getOperand(0);
3057 const Value *Op1 = I.getOperand(1);
3058 Type *AggTy = I.getType();
3059 Type *ValTy = Op1->getType();
3060 bool IntoUndef = isa<UndefValue>(Op0);
3061 bool FromUndef = isa<UndefValue>(Op1);
3063 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3065 SmallVector<EVT, 4> AggValueVTs;
3066 ComputeValueVTs(TLI, AggTy, AggValueVTs);
3067 SmallVector<EVT, 4> ValValueVTs;
3068 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3070 unsigned NumAggValues = AggValueVTs.size();
3071 unsigned NumValValues = ValValueVTs.size();
3072 SmallVector<SDValue, 4> Values(NumAggValues);
3074 SDValue Agg = getValue(Op0);
3076 // Copy the beginning value(s) from the original aggregate.
3077 for (; i != LinearIndex; ++i)
3078 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3079 SDValue(Agg.getNode(), Agg.getResNo() + i);
3080 // Copy values from the inserted value(s).
3082 SDValue Val = getValue(Op1);
3083 for (; i != LinearIndex + NumValValues; ++i)
3084 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3085 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3087 // Copy remaining value(s) from the original aggregate.
3088 for (; i != NumAggValues; ++i)
3089 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3090 SDValue(Agg.getNode(), Agg.getResNo() + i);
3092 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3093 DAG.getVTList(&AggValueVTs[0], NumAggValues),
3094 &Values[0], NumAggValues));
3097 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
3098 const Value *Op0 = I.getOperand(0);
3099 Type *AggTy = Op0->getType();
3100 Type *ValTy = I.getType();
3101 bool OutOfUndef = isa<UndefValue>(Op0);
3103 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3105 SmallVector<EVT, 4> ValValueVTs;
3106 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3108 unsigned NumValValues = ValValueVTs.size();
3110 // Ignore a extractvalue that produces an empty object
3111 if (!NumValValues) {
3112 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3116 SmallVector<SDValue, 4> Values(NumValValues);
3118 SDValue Agg = getValue(Op0);
3119 // Copy out the selected value(s).
3120 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3121 Values[i - LinearIndex] =
3123 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3124 SDValue(Agg.getNode(), Agg.getResNo() + i);
3126 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3127 DAG.getVTList(&ValValueVTs[0], NumValValues),
3128 &Values[0], NumValValues));
3131 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3132 SDValue N = getValue(I.getOperand(0));
3133 // Note that the pointer operand may be a vector of pointers. Take the scalar
3134 // element which holds a pointer.
3135 Type *Ty = I.getOperand(0)->getType()->getScalarType();
3137 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
3139 const Value *Idx = *OI;
3140 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
3141 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
3144 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
3145 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
3146 DAG.getConstant(Offset, N.getValueType()));
3149 Ty = StTy->getElementType(Field);
3151 Ty = cast<SequentialType>(Ty)->getElementType();
3153 // If this is a constant subscript, handle it quickly.
3154 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3155 if (CI->isZero()) continue;
3157 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
3159 EVT PTy = TLI.getPointerTy();
3160 unsigned PtrBits = PTy.getSizeInBits();
3162 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
3164 DAG.getConstant(Offs, MVT::i64));
3166 OffsVal = DAG.getIntPtrConstant(Offs);
3168 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
3173 // N = N + Idx * ElementSize;
3174 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(),
3175 TD->getTypeAllocSize(Ty));
3176 SDValue IdxN = getValue(Idx);
3178 // If the index is smaller or larger than intptr_t, truncate or extend
3180 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType());
3182 // If this is a multiply by a power of two, turn it into a shl
3183 // immediately. This is a very common case.
3184 if (ElementSize != 1) {
3185 if (ElementSize.isPowerOf2()) {
3186 unsigned Amt = ElementSize.logBase2();
3187 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
3188 N.getValueType(), IdxN,
3189 DAG.getConstant(Amt, IdxN.getValueType()));
3191 SDValue Scale = DAG.getConstant(ElementSize, IdxN.getValueType());
3192 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
3193 N.getValueType(), IdxN, Scale);
3197 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3198 N.getValueType(), N, IdxN);
3205 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3206 // If this is a fixed sized alloca in the entry block of the function,
3207 // allocate it statically on the stack.
3208 if (FuncInfo.StaticAllocaMap.count(&I))
3209 return; // getValue will auto-populate this.
3211 Type *Ty = I.getAllocatedType();
3212 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
3214 std::max((unsigned)TLI.getDataLayout()->getPrefTypeAlignment(Ty),
3217 SDValue AllocSize = getValue(I.getArraySize());
3219 EVT IntPtr = TLI.getPointerTy();
3220 if (AllocSize.getValueType() != IntPtr)
3221 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr);
3223 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr,
3225 DAG.getConstant(TySize, IntPtr));
3227 // Handle alignment. If the requested alignment is less than or equal to
3228 // the stack alignment, ignore it. If the size is greater than or equal to
3229 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3230 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
3231 if (Align <= StackAlign)
3234 // Round the size of the allocation up to the stack alignment size
3235 // by add SA-1 to the size.
3236 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3237 AllocSize.getValueType(), AllocSize,
3238 DAG.getIntPtrConstant(StackAlign-1));
3240 // Mask out the low bits for alignment purposes.
3241 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
3242 AllocSize.getValueType(), AllocSize,
3243 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
3245 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
3246 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3247 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
3250 DAG.setRoot(DSA.getValue(1));
3252 // Inform the Frame Information that we have just allocated a variable-sized
3254 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1);
3257 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3259 return visitAtomicLoad(I);
3261 const Value *SV = I.getOperand(0);
3262 SDValue Ptr = getValue(SV);
3264 Type *Ty = I.getType();
3266 bool isVolatile = I.isVolatile();
3267 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3268 bool isInvariant = I.getMetadata("invariant.load") != 0;
3269 unsigned Alignment = I.getAlignment();
3270 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3271 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3273 SmallVector<EVT, 4> ValueVTs;
3274 SmallVector<uint64_t, 4> Offsets;
3275 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
3276 unsigned NumValues = ValueVTs.size();
3281 bool ConstantMemory = false;
3282 if (I.isVolatile() || NumValues > MaxParallelChains)
3283 // Serialize volatile loads with other side effects.
3285 else if (AA->pointsToConstantMemory(
3286 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) {
3287 // Do not serialize (non-volatile) loads of constant memory with anything.
3288 Root = DAG.getEntryNode();
3289 ConstantMemory = true;
3291 // Do not serialize non-volatile loads against each other.
3292 Root = DAG.getRoot();
3295 SmallVector<SDValue, 4> Values(NumValues);
3296 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3298 EVT PtrVT = Ptr.getValueType();
3299 unsigned ChainI = 0;
3300 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3301 // Serializing loads here may result in excessive register pressure, and
3302 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3303 // could recover a bit by hoisting nodes upward in the chain by recognizing
3304 // they are side-effect free or do not alias. The optimizer should really
3305 // avoid this case by converting large object/array copies to llvm.memcpy
3306 // (MaxParallelChains should always remain as failsafe).
3307 if (ChainI == MaxParallelChains) {
3308 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3309 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3310 MVT::Other, &Chains[0], ChainI);
3314 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3316 DAG.getConstant(Offsets[i], PtrVT));
3317 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
3318 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3319 isNonTemporal, isInvariant, Alignment, TBAAInfo,
3323 Chains[ChainI] = L.getValue(1);
3326 if (!ConstantMemory) {
3327 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3328 MVT::Other, &Chains[0], ChainI);
3332 PendingLoads.push_back(Chain);
3335 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3336 DAG.getVTList(&ValueVTs[0], NumValues),
3337 &Values[0], NumValues));
3340 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3342 return visitAtomicStore(I);
3344 const Value *SrcV = I.getOperand(0);
3345 const Value *PtrV = I.getOperand(1);
3347 SmallVector<EVT, 4> ValueVTs;
3348 SmallVector<uint64_t, 4> Offsets;
3349 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
3350 unsigned NumValues = ValueVTs.size();
3354 // Get the lowered operands. Note that we do this after
3355 // checking if NumResults is zero, because with zero results
3356 // the operands won't have values in the map.
3357 SDValue Src = getValue(SrcV);
3358 SDValue Ptr = getValue(PtrV);
3360 SDValue Root = getRoot();
3361 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3363 EVT PtrVT = Ptr.getValueType();
3364 bool isVolatile = I.isVolatile();
3365 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3366 unsigned Alignment = I.getAlignment();
3367 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3369 unsigned ChainI = 0;
3370 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3371 // See visitLoad comments.
3372 if (ChainI == MaxParallelChains) {
3373 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3374 MVT::Other, &Chains[0], ChainI);
3378 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr,
3379 DAG.getConstant(Offsets[i], PtrVT));
3380 SDValue St = DAG.getStore(Root, getCurDebugLoc(),
3381 SDValue(Src.getNode(), Src.getResNo() + i),
3382 Add, MachinePointerInfo(PtrV, Offsets[i]),
3383 isVolatile, isNonTemporal, Alignment, TBAAInfo);
3384 Chains[ChainI] = St;
3387 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3388 MVT::Other, &Chains[0], ChainI);
3390 AssignOrderingToNode(StoreNode.getNode());
3391 DAG.setRoot(StoreNode);
3394 static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order,
3395 SynchronizationScope Scope,
3396 bool Before, DebugLoc dl,
3398 const TargetLowering &TLI) {
3399 // Fence, if necessary
3401 if (Order == AcquireRelease || Order == SequentiallyConsistent)
3403 else if (Order == Acquire || Order == Monotonic)
3406 if (Order == AcquireRelease)
3408 else if (Order == Release || Order == Monotonic)
3413 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy());
3414 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy());
3415 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3);
3418 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3419 DebugLoc dl = getCurDebugLoc();
3420 AtomicOrdering Order = I.getOrdering();
3421 SynchronizationScope Scope = I.getSynchScope();
3423 SDValue InChain = getRoot();
3425 if (TLI.getInsertFencesForAtomic())
3426 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3430 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
3431 getValue(I.getCompareOperand()).getValueType().getSimpleVT(),
3433 getValue(I.getPointerOperand()),
3434 getValue(I.getCompareOperand()),
3435 getValue(I.getNewValOperand()),
3436 MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */,
3437 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3440 SDValue OutChain = L.getValue(1);
3442 if (TLI.getInsertFencesForAtomic())
3443 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3447 DAG.setRoot(OutChain);
3450 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3451 DebugLoc dl = getCurDebugLoc();
3453 switch (I.getOperation()) {
3454 default: llvm_unreachable("Unknown atomicrmw operation");
3455 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3456 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3457 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3458 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3459 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3460 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3461 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3462 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3463 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3464 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3465 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3467 AtomicOrdering Order = I.getOrdering();
3468 SynchronizationScope Scope = I.getSynchScope();
3470 SDValue InChain = getRoot();
3472 if (TLI.getInsertFencesForAtomic())
3473 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3477 DAG.getAtomic(NT, dl,
3478 getValue(I.getValOperand()).getValueType().getSimpleVT(),
3480 getValue(I.getPointerOperand()),
3481 getValue(I.getValOperand()),
3482 I.getPointerOperand(), 0 /* Alignment */,
3483 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3486 SDValue OutChain = L.getValue(1);
3488 if (TLI.getInsertFencesForAtomic())
3489 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3493 DAG.setRoot(OutChain);
3496 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3497 DebugLoc dl = getCurDebugLoc();
3500 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy());
3501 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy());
3502 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3));
3505 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3506 DebugLoc dl = getCurDebugLoc();
3507 AtomicOrdering Order = I.getOrdering();
3508 SynchronizationScope Scope = I.getSynchScope();
3510 SDValue InChain = getRoot();
3512 EVT VT = TLI.getValueType(I.getType());
3514 if (I.getAlignment() < VT.getSizeInBits() / 8)
3515 report_fatal_error("Cannot generate unaligned atomic load");
3518 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3519 getValue(I.getPointerOperand()),
3520 I.getPointerOperand(), I.getAlignment(),
3521 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3524 SDValue OutChain = L.getValue(1);
3526 if (TLI.getInsertFencesForAtomic())
3527 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3531 DAG.setRoot(OutChain);
3534 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3535 DebugLoc dl = getCurDebugLoc();
3537 AtomicOrdering Order = I.getOrdering();
3538 SynchronizationScope Scope = I.getSynchScope();
3540 SDValue InChain = getRoot();
3542 EVT VT = TLI.getValueType(I.getValueOperand()->getType());
3544 if (I.getAlignment() < VT.getSizeInBits() / 8)
3545 report_fatal_error("Cannot generate unaligned atomic store");
3547 if (TLI.getInsertFencesForAtomic())
3548 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3552 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3554 getValue(I.getPointerOperand()),
3555 getValue(I.getValueOperand()),
3556 I.getPointerOperand(), I.getAlignment(),
3557 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3560 if (TLI.getInsertFencesForAtomic())
3561 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3564 DAG.setRoot(OutChain);
3567 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3569 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3570 unsigned Intrinsic) {
3571 bool HasChain = !I.doesNotAccessMemory();
3572 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3574 // Build the operand list.
3575 SmallVector<SDValue, 8> Ops;
3576 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3578 // We don't need to serialize loads against other loads.
3579 Ops.push_back(DAG.getRoot());
3581 Ops.push_back(getRoot());
3585 // Info is set by getTgtMemInstrinsic
3586 TargetLowering::IntrinsicInfo Info;
3587 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3589 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3590 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3591 Info.opc == ISD::INTRINSIC_W_CHAIN)
3592 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI.getPointerTy()));
3594 // Add all operands of the call to the operand list.
3595 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3596 SDValue Op = getValue(I.getArgOperand(i));
3600 SmallVector<EVT, 4> ValueVTs;
3601 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3604 ValueVTs.push_back(MVT::Other);
3606 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
3610 if (IsTgtIntrinsic) {
3611 // This is target intrinsic that touches memory
3612 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
3613 VTs, &Ops[0], Ops.size(),
3615 MachinePointerInfo(Info.ptrVal, Info.offset),
3616 Info.align, Info.vol,
3617 Info.readMem, Info.writeMem);
3618 } else if (!HasChain) {
3619 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
3620 VTs, &Ops[0], Ops.size());
3621 } else if (!I.getType()->isVoidTy()) {
3622 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
3623 VTs, &Ops[0], Ops.size());
3625 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
3626 VTs, &Ops[0], Ops.size());
3630 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3632 PendingLoads.push_back(Chain);
3637 if (!I.getType()->isVoidTy()) {
3638 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3639 EVT VT = TLI.getValueType(PTy);
3640 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result);
3643 setValue(&I, Result);
3645 // Assign order to result here. If the intrinsic does not produce a result,
3646 // it won't be mapped to a SDNode and visit() will not assign it an order
3649 AssignOrderingToNode(Result.getNode());
3653 /// GetSignificand - Get the significand and build it into a floating-point
3654 /// number with exponent of 1:
3656 /// Op = (Op & 0x007fffff) | 0x3f800000;
3658 /// where Op is the hexadecimal representation of floating point value.
3660 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3661 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3662 DAG.getConstant(0x007fffff, MVT::i32));
3663 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3664 DAG.getConstant(0x3f800000, MVT::i32));
3665 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3668 /// GetExponent - Get the exponent:
3670 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3672 /// where Op is the hexadecimal representation of floating point value.
3674 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3676 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3677 DAG.getConstant(0x7f800000, MVT::i32));
3678 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3679 DAG.getConstant(23, TLI.getPointerTy()));
3680 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3681 DAG.getConstant(127, MVT::i32));
3682 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3685 /// getF32Constant - Get 32-bit floating point constant.
3687 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3688 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)),
3692 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3693 /// limited-precision mode.
3694 static SDValue expandExp(DebugLoc dl, SDValue Op, SelectionDAG &DAG,
3695 const TargetLowering &TLI) {
3696 if (Op.getValueType() == MVT::f32 &&
3697 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3699 // Put the exponent in the right bit position for later addition to the
3702 // #define LOG2OFe 1.4426950f
3703 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3704 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3705 getF32Constant(DAG, 0x3fb8aa3b));
3706 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3708 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3709 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3710 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3712 // IntegerPartOfX <<= 23;
3713 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3714 DAG.getConstant(23, TLI.getPointerTy()));
3716 SDValue TwoToFracPartOfX;
3717 if (LimitFloatPrecision <= 6) {
3718 // For floating-point precision of 6:
3720 // TwoToFractionalPartOfX =
3722 // (0.735607626f + 0.252464424f * x) * x;
3724 // error 0.0144103317, which is 6 bits
3725 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3726 getF32Constant(DAG, 0x3e814304));
3727 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3728 getF32Constant(DAG, 0x3f3c50c8));
3729 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3730 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3731 getF32Constant(DAG, 0x3f7f5e7e));
3732 } else if (LimitFloatPrecision <= 12) {
3733 // For floating-point precision of 12:
3735 // TwoToFractionalPartOfX =
3738 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3740 // 0.000107046256 error, which is 13 to 14 bits
3741 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3742 getF32Constant(DAG, 0x3da235e3));
3743 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3744 getF32Constant(DAG, 0x3e65b8f3));
3745 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3746 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3747 getF32Constant(DAG, 0x3f324b07));
3748 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3749 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3750 getF32Constant(DAG, 0x3f7ff8fd));
3751 } else { // LimitFloatPrecision <= 18
3752 // For floating-point precision of 18:
3754 // TwoToFractionalPartOfX =
3758 // (0.554906021e-1f +
3759 // (0.961591928e-2f +
3760 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3762 // error 2.47208000*10^(-7), which is better than 18 bits
3763 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3764 getF32Constant(DAG, 0x3924b03e));
3765 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3766 getF32Constant(DAG, 0x3ab24b87));
3767 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3768 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3769 getF32Constant(DAG, 0x3c1d8c17));
3770 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3771 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3772 getF32Constant(DAG, 0x3d634a1d));
3773 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3774 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3775 getF32Constant(DAG, 0x3e75fe14));
3776 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3777 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3778 getF32Constant(DAG, 0x3f317234));
3779 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3780 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3781 getF32Constant(DAG, 0x3f800000));
3784 // Add the exponent into the result in integer domain.
3785 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFracPartOfX);
3786 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3787 DAG.getNode(ISD::ADD, dl, MVT::i32,
3788 t13, IntegerPartOfX));
3791 // No special expansion.
3792 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3795 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3796 /// limited-precision mode.
3797 static SDValue expandLog(DebugLoc dl, SDValue Op, SelectionDAG &DAG,
3798 const TargetLowering &TLI) {
3799 if (Op.getValueType() == MVT::f32 &&
3800 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3801 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3803 // Scale the exponent by log(2) [0.69314718f].
3804 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3805 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3806 getF32Constant(DAG, 0x3f317218));
3808 // Get the significand and build it into a floating-point number with
3810 SDValue X = GetSignificand(DAG, Op1, dl);
3812 SDValue LogOfMantissa;
3813 if (LimitFloatPrecision <= 6) {
3814 // For floating-point precision of 6:
3818 // (1.4034025f - 0.23903021f * x) * x;
3820 // error 0.0034276066, which is better than 8 bits
3821 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3822 getF32Constant(DAG, 0xbe74c456));
3823 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3824 getF32Constant(DAG, 0x3fb3a2b1));
3825 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3826 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3827 getF32Constant(DAG, 0x3f949a29));
3828 } else if (LimitFloatPrecision <= 12) {
3829 // For floating-point precision of 12:
3835 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3837 // error 0.000061011436, which is 14 bits
3838 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3839 getF32Constant(DAG, 0xbd67b6d6));
3840 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3841 getF32Constant(DAG, 0x3ee4f4b8));
3842 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3843 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3844 getF32Constant(DAG, 0x3fbc278b));
3845 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3846 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3847 getF32Constant(DAG, 0x40348e95));
3848 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3849 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3850 getF32Constant(DAG, 0x3fdef31a));
3851 } else { // LimitFloatPrecision <= 18
3852 // For floating-point precision of 18:
3860 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3862 // error 0.0000023660568, which is better than 18 bits
3863 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3864 getF32Constant(DAG, 0xbc91e5ac));
3865 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3866 getF32Constant(DAG, 0x3e4350aa));
3867 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3868 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3869 getF32Constant(DAG, 0x3f60d3e3));
3870 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3871 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3872 getF32Constant(DAG, 0x4011cdf0));
3873 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3874 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3875 getF32Constant(DAG, 0x406cfd1c));
3876 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3877 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3878 getF32Constant(DAG, 0x408797cb));
3879 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3880 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3881 getF32Constant(DAG, 0x4006dcab));
3884 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
3887 // No special expansion.
3888 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
3891 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
3892 /// limited-precision mode.
3893 static SDValue expandLog2(DebugLoc dl, SDValue Op, SelectionDAG &DAG,
3894 const TargetLowering &TLI) {
3895 if (Op.getValueType() == MVT::f32 &&
3896 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3897 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3899 // Get the exponent.
3900 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3902 // Get the significand and build it into a floating-point number with
3904 SDValue X = GetSignificand(DAG, Op1, dl);
3906 // Different possible minimax approximations of significand in
3907 // floating-point for various degrees of accuracy over [1,2].
3908 SDValue Log2ofMantissa;
3909 if (LimitFloatPrecision <= 6) {
3910 // For floating-point precision of 6:
3912 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3914 // error 0.0049451742, which is more than 7 bits
3915 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3916 getF32Constant(DAG, 0xbeb08fe0));
3917 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3918 getF32Constant(DAG, 0x40019463));
3919 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3920 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3921 getF32Constant(DAG, 0x3fd6633d));
3922 } else if (LimitFloatPrecision <= 12) {
3923 // For floating-point precision of 12:
3929 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3931 // error 0.0000876136000, which is better than 13 bits
3932 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3933 getF32Constant(DAG, 0xbda7262e));
3934 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3935 getF32Constant(DAG, 0x3f25280b));
3936 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3937 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3938 getF32Constant(DAG, 0x4007b923));
3939 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3940 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3941 getF32Constant(DAG, 0x40823e2f));
3942 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3943 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3944 getF32Constant(DAG, 0x4020d29c));
3945 } else { // LimitFloatPrecision <= 18
3946 // For floating-point precision of 18:
3955 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3957 // error 0.0000018516, which is better than 18 bits
3958 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3959 getF32Constant(DAG, 0xbcd2769e));
3960 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3961 getF32Constant(DAG, 0x3e8ce0b9));
3962 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3963 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3964 getF32Constant(DAG, 0x3fa22ae7));
3965 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3966 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3967 getF32Constant(DAG, 0x40525723));
3968 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3969 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3970 getF32Constant(DAG, 0x40aaf200));
3971 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3972 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3973 getF32Constant(DAG, 0x40c39dad));
3974 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3975 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3976 getF32Constant(DAG, 0x4042902c));
3979 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
3982 // No special expansion.
3983 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
3986 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
3987 /// limited-precision mode.
3988 static SDValue expandLog10(DebugLoc dl, SDValue Op, SelectionDAG &DAG,
3989 const TargetLowering &TLI) {
3990 if (Op.getValueType() == MVT::f32 &&
3991 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3992 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3994 // Scale the exponent by log10(2) [0.30102999f].
3995 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3996 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3997 getF32Constant(DAG, 0x3e9a209a));
3999 // Get the significand and build it into a floating-point number with
4001 SDValue X = GetSignificand(DAG, Op1, dl);
4003 SDValue Log10ofMantissa;
4004 if (LimitFloatPrecision <= 6) {
4005 // For floating-point precision of 6:
4007 // Log10ofMantissa =
4009 // (0.60948995f - 0.10380950f * x) * x;
4011 // error 0.0014886165, which is 6 bits
4012 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4013 getF32Constant(DAG, 0xbdd49a13));
4014 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4015 getF32Constant(DAG, 0x3f1c0789));
4016 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4017 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4018 getF32Constant(DAG, 0x3f011300));
4019 } else if (LimitFloatPrecision <= 12) {
4020 // For floating-point precision of 12:
4022 // Log10ofMantissa =
4025 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4027 // error 0.00019228036, which is better than 12 bits
4028 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4029 getF32Constant(DAG, 0x3d431f31));
4030 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4031 getF32Constant(DAG, 0x3ea21fb2));
4032 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4033 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4034 getF32Constant(DAG, 0x3f6ae232));
4035 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4036 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4037 getF32Constant(DAG, 0x3f25f7c3));
4038 } else { // LimitFloatPrecision <= 18
4039 // For floating-point precision of 18:
4041 // Log10ofMantissa =
4046 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4048 // error 0.0000037995730, which is better than 18 bits
4049 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4050 getF32Constant(DAG, 0x3c5d51ce));
4051 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4052 getF32Constant(DAG, 0x3e00685a));
4053 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4054 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4055 getF32Constant(DAG, 0x3efb6798));
4056 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4057 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4058 getF32Constant(DAG, 0x3f88d192));
4059 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4060 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4061 getF32Constant(DAG, 0x3fc4316c));
4062 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4063 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4064 getF32Constant(DAG, 0x3f57ce70));
4067 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4070 // No special expansion.
4071 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4074 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4075 /// limited-precision mode.
4076 static SDValue expandExp2(DebugLoc dl, SDValue Op, SelectionDAG &DAG,
4077 const TargetLowering &TLI) {
4078 if (Op.getValueType() == MVT::f32 &&
4079 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4080 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
4082 // FractionalPartOfX = x - (float)IntegerPartOfX;
4083 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4084 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
4086 // IntegerPartOfX <<= 23;
4087 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4088 DAG.getConstant(23, TLI.getPointerTy()));
4090 SDValue TwoToFractionalPartOfX;
4091 if (LimitFloatPrecision <= 6) {
4092 // For floating-point precision of 6:
4094 // TwoToFractionalPartOfX =
4096 // (0.735607626f + 0.252464424f * x) * x;
4098 // error 0.0144103317, which is 6 bits
4099 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4100 getF32Constant(DAG, 0x3e814304));
4101 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4102 getF32Constant(DAG, 0x3f3c50c8));
4103 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4104 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4105 getF32Constant(DAG, 0x3f7f5e7e));
4106 } else if (LimitFloatPrecision <= 12) {
4107 // For floating-point precision of 12:
4109 // TwoToFractionalPartOfX =
4112 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4114 // error 0.000107046256, which is 13 to 14 bits
4115 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4116 getF32Constant(DAG, 0x3da235e3));
4117 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4118 getF32Constant(DAG, 0x3e65b8f3));
4119 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4120 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4121 getF32Constant(DAG, 0x3f324b07));
4122 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4123 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4124 getF32Constant(DAG, 0x3f7ff8fd));
4125 } else { // LimitFloatPrecision <= 18
4126 // For floating-point precision of 18:
4128 // TwoToFractionalPartOfX =
4132 // (0.554906021e-1f +
4133 // (0.961591928e-2f +
4134 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4135 // error 2.47208000*10^(-7), which is better than 18 bits
4136 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4137 getF32Constant(DAG, 0x3924b03e));
4138 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4139 getF32Constant(DAG, 0x3ab24b87));
4140 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4141 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4142 getF32Constant(DAG, 0x3c1d8c17));
4143 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4144 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4145 getF32Constant(DAG, 0x3d634a1d));
4146 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4147 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4148 getF32Constant(DAG, 0x3e75fe14));
4149 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4150 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4151 getF32Constant(DAG, 0x3f317234));
4152 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4153 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4154 getF32Constant(DAG, 0x3f800000));
4157 // Add the exponent into the result in integer domain.
4158 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32,
4159 TwoToFractionalPartOfX);
4160 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4161 DAG.getNode(ISD::ADD, dl, MVT::i32,
4162 t13, IntegerPartOfX));
4165 // No special expansion.
4166 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4169 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4170 /// limited-precision mode with x == 10.0f.
4171 static SDValue expandPow(DebugLoc dl, SDValue LHS, SDValue RHS,
4172 SelectionDAG &DAG, const TargetLowering &TLI) {
4173 bool IsExp10 = false;
4174 if (LHS.getValueType() == MVT::f32 && LHS.getValueType() == MVT::f32 &&
4175 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4176 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4178 IsExp10 = LHSC->isExactlyValue(Ten);
4183 // Put the exponent in the right bit position for later addition to the
4186 // #define LOG2OF10 3.3219281f
4187 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
4188 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4189 getF32Constant(DAG, 0x40549a78));
4190 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4192 // FractionalPartOfX = x - (float)IntegerPartOfX;
4193 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4194 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4196 // IntegerPartOfX <<= 23;
4197 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4198 DAG.getConstant(23, TLI.getPointerTy()));
4200 SDValue TwoToFractionalPartOfX;
4201 if (LimitFloatPrecision <= 6) {
4202 // For floating-point precision of 6:
4204 // twoToFractionalPartOfX =
4206 // (0.735607626f + 0.252464424f * x) * x;
4208 // error 0.0144103317, which is 6 bits
4209 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4210 getF32Constant(DAG, 0x3e814304));
4211 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4212 getF32Constant(DAG, 0x3f3c50c8));
4213 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4214 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4215 getF32Constant(DAG, 0x3f7f5e7e));
4216 } else if (LimitFloatPrecision <= 12) {
4217 // For floating-point precision of 12:
4219 // TwoToFractionalPartOfX =
4222 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4224 // error 0.000107046256, which is 13 to 14 bits
4225 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4226 getF32Constant(DAG, 0x3da235e3));
4227 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4228 getF32Constant(DAG, 0x3e65b8f3));
4229 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4230 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4231 getF32Constant(DAG, 0x3f324b07));
4232 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4233 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4234 getF32Constant(DAG, 0x3f7ff8fd));
4235 } else { // LimitFloatPrecision <= 18
4236 // For floating-point precision of 18:
4238 // TwoToFractionalPartOfX =
4242 // (0.554906021e-1f +
4243 // (0.961591928e-2f +
4244 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4245 // error 2.47208000*10^(-7), which is better than 18 bits
4246 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4247 getF32Constant(DAG, 0x3924b03e));
4248 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4249 getF32Constant(DAG, 0x3ab24b87));
4250 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4251 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4252 getF32Constant(DAG, 0x3c1d8c17));
4253 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4254 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4255 getF32Constant(DAG, 0x3d634a1d));
4256 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4257 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4258 getF32Constant(DAG, 0x3e75fe14));
4259 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4260 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4261 getF32Constant(DAG, 0x3f317234));
4262 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4263 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4264 getF32Constant(DAG, 0x3f800000));
4267 SDValue t13 = DAG.getNode(ISD::BITCAST, dl,MVT::i32,TwoToFractionalPartOfX);
4268 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4269 DAG.getNode(ISD::ADD, dl, MVT::i32,
4270 t13, IntegerPartOfX));
4273 // No special expansion.
4274 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4278 /// ExpandPowI - Expand a llvm.powi intrinsic.
4279 static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS,
4280 SelectionDAG &DAG) {
4281 // If RHS is a constant, we can expand this out to a multiplication tree,
4282 // otherwise we end up lowering to a call to __powidf2 (for example). When
4283 // optimizing for size, we only want to do this if the expansion would produce
4284 // a small number of multiplies, otherwise we do the full expansion.
4285 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4286 // Get the exponent as a positive value.
4287 unsigned Val = RHSC->getSExtValue();
4288 if ((int)Val < 0) Val = -Val;
4290 // powi(x, 0) -> 1.0
4292 return DAG.getConstantFP(1.0, LHS.getValueType());
4294 const Function *F = DAG.getMachineFunction().getFunction();
4295 if (!F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
4296 Attribute::OptimizeForSize) ||
4297 // If optimizing for size, don't insert too many multiplies. This
4298 // inserts up to 5 multiplies.
4299 CountPopulation_32(Val)+Log2_32(Val) < 7) {
4300 // We use the simple binary decomposition method to generate the multiply
4301 // sequence. There are more optimal ways to do this (for example,
4302 // powi(x,15) generates one more multiply than it should), but this has
4303 // the benefit of being both really simple and much better than a libcall.
4304 SDValue Res; // Logically starts equal to 1.0
4305 SDValue CurSquare = LHS;
4309 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4311 Res = CurSquare; // 1.0*CurSquare.
4314 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4315 CurSquare, CurSquare);
4319 // If the original was negative, invert the result, producing 1/(x*x*x).
4320 if (RHSC->getSExtValue() < 0)
4321 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4322 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4327 // Otherwise, expand to a libcall.
4328 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4331 // getTruncatedArgReg - Find underlying register used for an truncated
4333 static unsigned getTruncatedArgReg(const SDValue &N) {
4334 if (N.getOpcode() != ISD::TRUNCATE)
4337 const SDValue &Ext = N.getOperand(0);
4338 if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){
4339 const SDValue &CFR = Ext.getOperand(0);
4340 if (CFR.getOpcode() == ISD::CopyFromReg)
4341 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4342 if (CFR.getOpcode() == ISD::TRUNCATE)
4343 return getTruncatedArgReg(CFR);
4348 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4349 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4350 /// At the end of instruction selection, they will be inserted to the entry BB.
4352 SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
4355 const Argument *Arg = dyn_cast<Argument>(V);
4359 MachineFunction &MF = DAG.getMachineFunction();
4360 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo();
4361 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4363 // Ignore inlined function arguments here.
4364 DIVariable DV(Variable);
4365 if (DV.isInlinedFnArgument(MF.getFunction()))
4369 // Some arguments' frame index is recorded during argument lowering.
4370 Offset = FuncInfo.getArgumentFrameIndex(Arg);
4372 Reg = TRI->getFrameRegister(MF);
4374 if (!Reg && N.getNode()) {
4375 if (N.getOpcode() == ISD::CopyFromReg)
4376 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4378 Reg = getTruncatedArgReg(N);
4379 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4380 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4381 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4388 // Check if ValueMap has reg number.
4389 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4390 if (VMI != FuncInfo.ValueMap.end())
4394 if (!Reg && N.getNode()) {
4395 // Check if frame index is available.
4396 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4397 if (FrameIndexSDNode *FINode =
4398 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) {
4399 Reg = TRI->getFrameRegister(MF);
4400 Offset = FINode->getIndex();
4407 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(),
4408 TII->get(TargetOpcode::DBG_VALUE))
4409 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable);
4410 FuncInfo.ArgDbgValues.push_back(&*MIB);
4414 // VisualStudio defines setjmp as _setjmp
4415 #if defined(_MSC_VER) && defined(setjmp) && \
4416 !defined(setjmp_undefined_for_msvc)
4417 # pragma push_macro("setjmp")
4419 # define setjmp_undefined_for_msvc
4422 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4423 /// we want to emit this as a call to a named external function, return the name
4424 /// otherwise lower it and return null.
4426 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4427 DebugLoc dl = getCurDebugLoc();
4430 switch (Intrinsic) {
4432 // By default, turn this into a target intrinsic node.
4433 visitTargetIntrinsic(I, Intrinsic);
4435 case Intrinsic::vastart: visitVAStart(I); return 0;
4436 case Intrinsic::vaend: visitVAEnd(I); return 0;
4437 case Intrinsic::vacopy: visitVACopy(I); return 0;
4438 case Intrinsic::returnaddress:
4439 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
4440 getValue(I.getArgOperand(0))));
4442 case Intrinsic::frameaddress:
4443 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
4444 getValue(I.getArgOperand(0))));
4446 case Intrinsic::setjmp:
4447 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4448 case Intrinsic::longjmp:
4449 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4450 case Intrinsic::memcpy: {
4451 // Assert for address < 256 since we support only user defined address
4453 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4455 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4457 "Unknown address space");
4458 SDValue Op1 = getValue(I.getArgOperand(0));
4459 SDValue Op2 = getValue(I.getArgOperand(1));
4460 SDValue Op3 = getValue(I.getArgOperand(2));
4461 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4463 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4464 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4465 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false,
4466 MachinePointerInfo(I.getArgOperand(0)),
4467 MachinePointerInfo(I.getArgOperand(1))));
4470 case Intrinsic::memset: {
4471 // Assert for address < 256 since we support only user defined address
4473 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4475 "Unknown address space");
4476 SDValue Op1 = getValue(I.getArgOperand(0));
4477 SDValue Op2 = getValue(I.getArgOperand(1));
4478 SDValue Op3 = getValue(I.getArgOperand(2));
4479 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4481 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4482 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4483 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4484 MachinePointerInfo(I.getArgOperand(0))));
4487 case Intrinsic::memmove: {
4488 // Assert for address < 256 since we support only user defined address
4490 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4492 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4494 "Unknown address space");
4495 SDValue Op1 = getValue(I.getArgOperand(0));
4496 SDValue Op2 = getValue(I.getArgOperand(1));
4497 SDValue Op3 = getValue(I.getArgOperand(2));
4498 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4500 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4501 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4502 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4503 MachinePointerInfo(I.getArgOperand(0)),
4504 MachinePointerInfo(I.getArgOperand(1))));
4507 case Intrinsic::dbg_declare: {
4508 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4509 MDNode *Variable = DI.getVariable();
4510 const Value *Address = DI.getAddress();
4511 if (!Address || !DIVariable(Variable).Verify()) {
4512 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4516 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4517 // but do not always have a corresponding SDNode built. The SDNodeOrder
4518 // absolute, but not relative, values are different depending on whether
4519 // debug info exists.
4522 // Check if address has undef value.
4523 if (isa<UndefValue>(Address) ||
4524 (Address->use_empty() && !isa<Argument>(Address))) {
4525 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4529 SDValue &N = NodeMap[Address];
4530 if (!N.getNode() && isa<Argument>(Address))
4531 // Check unused arguments map.
4532 N = UnusedArgNodeMap[Address];
4535 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4536 Address = BCI->getOperand(0);
4537 // Parameters are handled specially.
4539 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable ||
4540 isa<Argument>(Address));
4542 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4544 if (isParameter && !AI) {
4545 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4547 // Byval parameter. We have a frame index at this point.
4548 SDV = DAG.getDbgValue(Variable, FINode->getIndex(),
4549 0, dl, SDNodeOrder);
4551 // Address is an argument, so try to emit its dbg value using
4552 // virtual register info from the FuncInfo.ValueMap.
4553 EmitFuncArgumentDbgValue(Address, Variable, 0, N);
4557 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(),
4558 0, dl, SDNodeOrder);
4560 // Can't do anything with other non-AI cases yet.
4561 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4562 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4563 DEBUG(Address->dump());
4566 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4568 // If Address is an argument then try to emit its dbg value using
4569 // virtual register info from the FuncInfo.ValueMap.
4570 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) {
4571 // If variable is pinned by a alloca in dominating bb then
4572 // use StaticAllocaMap.
4573 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4574 if (AI->getParent() != DI.getParent()) {
4575 DenseMap<const AllocaInst*, int>::iterator SI =
4576 FuncInfo.StaticAllocaMap.find(AI);
4577 if (SI != FuncInfo.StaticAllocaMap.end()) {
4578 SDV = DAG.getDbgValue(Variable, SI->second,
4579 0, dl, SDNodeOrder);
4580 DAG.AddDbgValue(SDV, 0, false);
4585 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4590 case Intrinsic::dbg_value: {
4591 const DbgValueInst &DI = cast<DbgValueInst>(I);
4592 if (!DIVariable(DI.getVariable()).Verify())
4595 MDNode *Variable = DI.getVariable();
4596 uint64_t Offset = DI.getOffset();
4597 const Value *V = DI.getValue();
4601 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4602 // but do not always have a corresponding SDNode built. The SDNodeOrder
4603 // absolute, but not relative, values are different depending on whether
4604 // debug info exists.
4607 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4608 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder);
4609 DAG.AddDbgValue(SDV, 0, false);
4611 // Do not use getValue() in here; we don't want to generate code at
4612 // this point if it hasn't been done yet.
4613 SDValue N = NodeMap[V];
4614 if (!N.getNode() && isa<Argument>(V))
4615 // Check unused arguments map.
4616 N = UnusedArgNodeMap[V];
4618 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) {
4619 SDV = DAG.getDbgValue(Variable, N.getNode(),
4620 N.getResNo(), Offset, dl, SDNodeOrder);
4621 DAG.AddDbgValue(SDV, N.getNode(), false);
4623 } else if (!V->use_empty() ) {
4624 // Do not call getValue(V) yet, as we don't want to generate code.
4625 // Remember it for later.
4626 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4627 DanglingDebugInfoMap[V] = DDI;
4629 // We may expand this to cover more cases. One case where we have no
4630 // data available is an unreferenced parameter.
4631 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4635 // Build a debug info table entry.
4636 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4637 V = BCI->getOperand(0);
4638 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4639 // Don't handle byval struct arguments or VLAs, for example.
4641 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4642 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4645 DenseMap<const AllocaInst*, int>::iterator SI =
4646 FuncInfo.StaticAllocaMap.find(AI);
4647 if (SI == FuncInfo.StaticAllocaMap.end())
4649 int FI = SI->second;
4651 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4652 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
4653 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
4657 case Intrinsic::eh_typeid_for: {
4658 // Find the type id for the given typeinfo.
4659 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0));
4660 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4661 Res = DAG.getConstant(TypeID, MVT::i32);
4666 case Intrinsic::eh_return_i32:
4667 case Intrinsic::eh_return_i64:
4668 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4669 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4672 getValue(I.getArgOperand(0)),
4673 getValue(I.getArgOperand(1))));
4675 case Intrinsic::eh_unwind_init:
4676 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4678 case Intrinsic::eh_dwarf_cfa: {
4679 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl,
4680 TLI.getPointerTy());
4681 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4683 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4684 TLI.getPointerTy()),
4686 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl,
4688 DAG.getConstant(0, TLI.getPointerTy()));
4689 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
4693 case Intrinsic::eh_sjlj_callsite: {
4694 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4695 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4696 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4697 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4699 MMI.setCurrentCallSite(CI->getZExtValue());
4702 case Intrinsic::eh_sjlj_functioncontext: {
4703 // Get and store the index of the function context.
4704 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4706 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4707 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4708 MFI->setFunctionContextIndex(FI);
4711 case Intrinsic::eh_sjlj_setjmp: {
4714 Ops[1] = getValue(I.getArgOperand(0));
4715 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, dl,
4716 DAG.getVTList(MVT::i32, MVT::Other),
4718 setValue(&I, Op.getValue(0));
4719 DAG.setRoot(Op.getValue(1));
4722 case Intrinsic::eh_sjlj_longjmp: {
4723 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other,
4724 getRoot(), getValue(I.getArgOperand(0))));
4728 case Intrinsic::x86_mmx_pslli_w:
4729 case Intrinsic::x86_mmx_pslli_d:
4730 case Intrinsic::x86_mmx_pslli_q:
4731 case Intrinsic::x86_mmx_psrli_w:
4732 case Intrinsic::x86_mmx_psrli_d:
4733 case Intrinsic::x86_mmx_psrli_q:
4734 case Intrinsic::x86_mmx_psrai_w:
4735 case Intrinsic::x86_mmx_psrai_d: {
4736 SDValue ShAmt = getValue(I.getArgOperand(1));
4737 if (isa<ConstantSDNode>(ShAmt)) {
4738 visitTargetIntrinsic(I, Intrinsic);
4741 unsigned NewIntrinsic = 0;
4742 EVT ShAmtVT = MVT::v2i32;
4743 switch (Intrinsic) {
4744 case Intrinsic::x86_mmx_pslli_w:
4745 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4747 case Intrinsic::x86_mmx_pslli_d:
4748 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4750 case Intrinsic::x86_mmx_pslli_q:
4751 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4753 case Intrinsic::x86_mmx_psrli_w:
4754 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4756 case Intrinsic::x86_mmx_psrli_d:
4757 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4759 case Intrinsic::x86_mmx_psrli_q:
4760 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4762 case Intrinsic::x86_mmx_psrai_w:
4763 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4765 case Intrinsic::x86_mmx_psrai_d:
4766 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4768 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4771 // The vector shift intrinsics with scalars uses 32b shift amounts but
4772 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4774 // We must do this early because v2i32 is not a legal type.
4777 ShOps[1] = DAG.getConstant(0, MVT::i32);
4778 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
4779 EVT DestVT = TLI.getValueType(I.getType());
4780 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt);
4781 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
4782 DAG.getConstant(NewIntrinsic, MVT::i32),
4783 getValue(I.getArgOperand(0)), ShAmt);
4787 case Intrinsic::x86_avx_vinsertf128_pd_256:
4788 case Intrinsic::x86_avx_vinsertf128_ps_256:
4789 case Intrinsic::x86_avx_vinsertf128_si_256:
4790 case Intrinsic::x86_avx2_vinserti128: {
4791 EVT DestVT = TLI.getValueType(I.getType());
4792 EVT ElVT = TLI.getValueType(I.getArgOperand(1)->getType());
4793 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) *
4794 ElVT.getVectorNumElements();
4795 Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, DestVT,
4796 getValue(I.getArgOperand(0)),
4797 getValue(I.getArgOperand(1)),
4798 DAG.getIntPtrConstant(Idx));
4802 case Intrinsic::x86_avx_vextractf128_pd_256:
4803 case Intrinsic::x86_avx_vextractf128_ps_256:
4804 case Intrinsic::x86_avx_vextractf128_si_256:
4805 case Intrinsic::x86_avx2_vextracti128: {
4806 EVT DestVT = TLI.getValueType(I.getType());
4807 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(1))->getZExtValue() & 1) *
4808 DestVT.getVectorNumElements();
4809 Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT,
4810 getValue(I.getArgOperand(0)),
4811 DAG.getIntPtrConstant(Idx));
4815 case Intrinsic::convertff:
4816 case Intrinsic::convertfsi:
4817 case Intrinsic::convertfui:
4818 case Intrinsic::convertsif:
4819 case Intrinsic::convertuif:
4820 case Intrinsic::convertss:
4821 case Intrinsic::convertsu:
4822 case Intrinsic::convertus:
4823 case Intrinsic::convertuu: {
4824 ISD::CvtCode Code = ISD::CVT_INVALID;
4825 switch (Intrinsic) {
4826 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4827 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4828 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4829 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4830 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4831 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4832 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4833 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4834 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4835 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4837 EVT DestVT = TLI.getValueType(I.getType());
4838 const Value *Op1 = I.getArgOperand(0);
4839 Res = DAG.getConvertRndSat(DestVT, dl, getValue(Op1),
4840 DAG.getValueType(DestVT),
4841 DAG.getValueType(getValue(Op1).getValueType()),
4842 getValue(I.getArgOperand(1)),
4843 getValue(I.getArgOperand(2)),
4848 case Intrinsic::powi:
4849 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)),
4850 getValue(I.getArgOperand(1)), DAG));
4852 case Intrinsic::log:
4853 setValue(&I, expandLog(dl, getValue(I.getArgOperand(0)), DAG, TLI));
4855 case Intrinsic::log2:
4856 setValue(&I, expandLog2(dl, getValue(I.getArgOperand(0)), DAG, TLI));
4858 case Intrinsic::log10:
4859 setValue(&I, expandLog10(dl, getValue(I.getArgOperand(0)), DAG, TLI));
4861 case Intrinsic::exp:
4862 setValue(&I, expandExp(dl, getValue(I.getArgOperand(0)), DAG, TLI));
4864 case Intrinsic::exp2:
4865 setValue(&I, expandExp2(dl, getValue(I.getArgOperand(0)), DAG, TLI));
4867 case Intrinsic::pow:
4868 setValue(&I, expandPow(dl, getValue(I.getArgOperand(0)),
4869 getValue(I.getArgOperand(1)), DAG, TLI));
4871 case Intrinsic::sqrt:
4872 case Intrinsic::fabs:
4873 case Intrinsic::sin:
4874 case Intrinsic::cos:
4875 case Intrinsic::floor:
4876 case Intrinsic::ceil:
4877 case Intrinsic::trunc:
4878 case Intrinsic::rint:
4879 case Intrinsic::nearbyint: {
4881 switch (Intrinsic) {
4882 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4883 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4884 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4885 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4886 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4887 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
4888 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
4889 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
4890 case Intrinsic::rint: Opcode = ISD::FRINT; break;
4891 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
4894 setValue(&I, DAG.getNode(Opcode, dl,
4895 getValue(I.getArgOperand(0)).getValueType(),
4896 getValue(I.getArgOperand(0))));
4899 case Intrinsic::fma:
4900 setValue(&I, DAG.getNode(ISD::FMA, dl,
4901 getValue(I.getArgOperand(0)).getValueType(),
4902 getValue(I.getArgOperand(0)),
4903 getValue(I.getArgOperand(1)),
4904 getValue(I.getArgOperand(2))));
4906 case Intrinsic::fmuladd: {
4907 EVT VT = TLI.getValueType(I.getType());
4908 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
4909 TLI.isFMAFasterThanMulAndAdd(VT)){
4910 setValue(&I, DAG.getNode(ISD::FMA, dl,
4911 getValue(I.getArgOperand(0)).getValueType(),
4912 getValue(I.getArgOperand(0)),
4913 getValue(I.getArgOperand(1)),
4914 getValue(I.getArgOperand(2))));
4916 SDValue Mul = DAG.getNode(ISD::FMUL, dl,
4917 getValue(I.getArgOperand(0)).getValueType(),
4918 getValue(I.getArgOperand(0)),
4919 getValue(I.getArgOperand(1)));
4920 SDValue Add = DAG.getNode(ISD::FADD, dl,
4921 getValue(I.getArgOperand(0)).getValueType(),
4923 getValue(I.getArgOperand(2)));
4928 case Intrinsic::convert_to_fp16:
4929 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl,
4930 MVT::i16, getValue(I.getArgOperand(0))));
4932 case Intrinsic::convert_from_fp16:
4933 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl,
4934 MVT::f32, getValue(I.getArgOperand(0))));
4936 case Intrinsic::pcmarker: {
4937 SDValue Tmp = getValue(I.getArgOperand(0));
4938 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4941 case Intrinsic::readcyclecounter: {
4942 SDValue Op = getRoot();
4943 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4944 DAG.getVTList(MVT::i64, MVT::Other),
4947 DAG.setRoot(Res.getValue(1));
4950 case Intrinsic::bswap:
4951 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4952 getValue(I.getArgOperand(0)).getValueType(),
4953 getValue(I.getArgOperand(0))));
4955 case Intrinsic::cttz: {
4956 SDValue Arg = getValue(I.getArgOperand(0));
4957 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4958 EVT Ty = Arg.getValueType();
4959 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4963 case Intrinsic::ctlz: {
4964 SDValue Arg = getValue(I.getArgOperand(0));
4965 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4966 EVT Ty = Arg.getValueType();
4967 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4971 case Intrinsic::ctpop: {
4972 SDValue Arg = getValue(I.getArgOperand(0));
4973 EVT Ty = Arg.getValueType();
4974 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg));
4977 case Intrinsic::stacksave: {
4978 SDValue Op = getRoot();
4979 Res = DAG.getNode(ISD::STACKSAVE, dl,
4980 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4982 DAG.setRoot(Res.getValue(1));
4985 case Intrinsic::stackrestore: {
4986 Res = getValue(I.getArgOperand(0));
4987 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res));
4990 case Intrinsic::stackprotector: {
4991 // Emit code into the DAG to store the stack guard onto the stack.
4992 MachineFunction &MF = DAG.getMachineFunction();
4993 MachineFrameInfo *MFI = MF.getFrameInfo();
4994 EVT PtrTy = TLI.getPointerTy();
4996 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value.
4997 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4999 int FI = FuncInfo.StaticAllocaMap[Slot];
5000 MFI->setStackProtectorIndex(FI);
5002 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
5004 // Store the stack protector onto the stack.
5005 Res = DAG.getStore(getRoot(), dl, Src, FIN,
5006 MachinePointerInfo::getFixedStack(FI),
5012 case Intrinsic::objectsize: {
5013 // If we don't know by now, we're never going to know.
5014 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
5016 assert(CI && "Non-constant type in __builtin_object_size?");
5018 SDValue Arg = getValue(I.getCalledValue());
5019 EVT Ty = Arg.getValueType();
5022 Res = DAG.getConstant(-1ULL, Ty);
5024 Res = DAG.getConstant(0, Ty);
5029 case Intrinsic::annotation:
5030 case Intrinsic::ptr_annotation:
5031 // Drop the intrinsic, but forward the value
5032 setValue(&I, getValue(I.getOperand(0)));
5034 case Intrinsic::var_annotation:
5035 // Discard annotate attributes
5038 case Intrinsic::init_trampoline: {
5039 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5043 Ops[1] = getValue(I.getArgOperand(0));
5044 Ops[2] = getValue(I.getArgOperand(1));
5045 Ops[3] = getValue(I.getArgOperand(2));
5046 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5047 Ops[5] = DAG.getSrcValue(F);
5049 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, dl, MVT::Other, Ops, 6);
5054 case Intrinsic::adjust_trampoline: {
5055 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, dl,
5057 getValue(I.getArgOperand(0))));
5060 case Intrinsic::gcroot:
5062 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5063 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5065 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5066 GFI->addStackRoot(FI->getIndex(), TypeMap);
5069 case Intrinsic::gcread:
5070 case Intrinsic::gcwrite:
5071 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5072 case Intrinsic::flt_rounds:
5073 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
5076 case Intrinsic::expect: {
5077 // Just replace __builtin_expect(exp, c) with EXP.
5078 setValue(&I, getValue(I.getArgOperand(0)));
5082 case Intrinsic::debugtrap:
5083 case Intrinsic::trap: {
5084 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
5085 if (TrapFuncName.empty()) {
5086 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
5087 ISD::TRAP : ISD::DEBUGTRAP;
5088 DAG.setRoot(DAG.getNode(Op, dl,MVT::Other, getRoot()));
5091 TargetLowering::ArgListTy Args;
5093 CallLoweringInfo CLI(getRoot(), I.getType(),
5094 false, false, false, false, 0, CallingConv::C,
5095 /*isTailCall=*/false,
5096 /*doesNotRet=*/false, /*isReturnValueUsed=*/true,
5097 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()),
5099 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5100 DAG.setRoot(Result.second);
5104 case Intrinsic::uadd_with_overflow:
5105 case Intrinsic::sadd_with_overflow:
5106 case Intrinsic::usub_with_overflow:
5107 case Intrinsic::ssub_with_overflow:
5108 case Intrinsic::umul_with_overflow:
5109 case Intrinsic::smul_with_overflow: {
5111 switch (Intrinsic) {
5112 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5113 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5114 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5115 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5116 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5117 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5118 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5120 SDValue Op1 = getValue(I.getArgOperand(0));
5121 SDValue Op2 = getValue(I.getArgOperand(1));
5123 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5124 setValue(&I, DAG.getNode(Op, dl, VTs, Op1, Op2));
5127 case Intrinsic::prefetch: {
5129 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5131 Ops[1] = getValue(I.getArgOperand(0));
5132 Ops[2] = getValue(I.getArgOperand(1));
5133 Ops[3] = getValue(I.getArgOperand(2));
5134 Ops[4] = getValue(I.getArgOperand(3));
5135 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl,
5136 DAG.getVTList(MVT::Other),
5138 EVT::getIntegerVT(*Context, 8),
5139 MachinePointerInfo(I.getArgOperand(0)),
5141 false, /* volatile */
5143 rw==1)); /* write */
5146 case Intrinsic::lifetime_start:
5147 case Intrinsic::lifetime_end: {
5148 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5149 // Stack coloring is not enabled in O0, discard region information.
5150 if (TM.getOptLevel() == CodeGenOpt::None)
5153 SmallVector<Value *, 4> Allocas;
5154 GetUnderlyingObjects(I.getArgOperand(1), Allocas, TD);
5156 for (SmallVector<Value*, 4>::iterator Object = Allocas.begin(),
5157 E = Allocas.end(); Object != E; ++Object) {
5158 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5160 // Could not find an Alloca.
5161 if (!LifetimeObject)
5164 int FI = FuncInfo.StaticAllocaMap[LifetimeObject];
5168 Ops[1] = DAG.getFrameIndex(FI, TLI.getPointerTy(), true);
5169 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5171 Res = DAG.getNode(Opcode, dl, MVT::Other, Ops, 2);
5176 case Intrinsic::invariant_start:
5177 // Discard region information.
5178 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
5180 case Intrinsic::invariant_end:
5181 // Discard region information.
5183 case Intrinsic::donothing:
5189 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5191 MachineBasicBlock *LandingPad) {
5192 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5193 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5194 Type *RetTy = FTy->getReturnType();
5195 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5196 MCSymbol *BeginLabel = 0;
5198 TargetLowering::ArgListTy Args;
5199 TargetLowering::ArgListEntry Entry;
5200 Args.reserve(CS.arg_size());
5202 // Check whether the function can return without sret-demotion.
5203 SmallVector<ISD::OutputArg, 4> Outs;
5204 GetReturnInfo(RetTy, CS.getAttributes(), Outs, TLI);
5206 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
5207 DAG.getMachineFunction(),
5208 FTy->isVarArg(), Outs,
5211 SDValue DemoteStackSlot;
5212 int DemoteStackIdx = -100;
5214 if (!CanLowerReturn) {
5215 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(
5216 FTy->getReturnType());
5217 unsigned Align = TLI.getDataLayout()->getPrefTypeAlignment(
5218 FTy->getReturnType());
5219 MachineFunction &MF = DAG.getMachineFunction();
5220 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5221 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
5223 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy());
5224 Entry.Node = DemoteStackSlot;
5225 Entry.Ty = StackSlotPtrType;
5226 Entry.isSExt = false;
5227 Entry.isZExt = false;
5228 Entry.isInReg = false;
5229 Entry.isSRet = true;
5230 Entry.isNest = false;
5231 Entry.isByVal = false;
5232 Entry.isReturned = false;
5233 Entry.Alignment = Align;
5234 Args.push_back(Entry);
5235 RetTy = Type::getVoidTy(FTy->getContext());
5238 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5240 const Value *V = *i;
5243 if (V->getType()->isEmptyTy())
5246 SDValue ArgNode = getValue(V);
5247 Entry.Node = ArgNode; Entry.Ty = V->getType();
5249 unsigned attrInd = i - CS.arg_begin() + 1;
5250 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
5251 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
5252 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
5253 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
5254 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
5255 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
5256 Entry.isReturned = CS.paramHasAttr(attrInd, Attribute::Returned);
5257 Entry.Alignment = CS.getParamAlignment(attrInd);
5258 Args.push_back(Entry);
5262 // Insert a label before the invoke call to mark the try range. This can be
5263 // used to detect deletion of the invoke via the MachineModuleInfo.
5264 BeginLabel = MMI.getContext().CreateTempSymbol();
5266 // For SjLj, keep track of which landing pads go with which invokes
5267 // so as to maintain the ordering of pads in the LSDA.
5268 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5269 if (CallSiteIndex) {
5270 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5271 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5273 // Now that the call site is handled, stop tracking it.
5274 MMI.setCurrentCallSite(0);
5277 // Both PendingLoads and PendingExports must be flushed here;
5278 // this call might not return.
5280 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel));
5283 // Check if target-independent constraints permit a tail call here.
5284 // Target-dependent constraints are checked within TLI.LowerCallTo.
5285 if (isTailCall && !isInTailCallPosition(CS, TLI))
5289 CallLoweringInfo CLI(getRoot(), RetTy, FTy, isTailCall, Callee, Args, DAG,
5290 getCurDebugLoc(), CS);
5291 std::pair<SDValue,SDValue> Result = TLI.LowerCallTo(CLI);
5292 assert((isTailCall || Result.second.getNode()) &&
5293 "Non-null chain expected with non-tail call!");
5294 assert((Result.second.getNode() || !Result.first.getNode()) &&
5295 "Null value expected with tail call!");
5296 if (Result.first.getNode()) {
5297 setValue(CS.getInstruction(), Result.first);
5298 } else if (!CanLowerReturn && Result.second.getNode()) {
5299 // The instruction result is the result of loading from the
5300 // hidden sret parameter.
5301 SmallVector<EVT, 1> PVTs;
5302 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
5304 ComputeValueVTs(TLI, PtrRetTy, PVTs);
5305 assert(PVTs.size() == 1 && "Pointers should fit in one register");
5306 EVT PtrVT = PVTs[0];
5308 SmallVector<EVT, 4> RetTys;
5309 SmallVector<uint64_t, 4> Offsets;
5310 RetTy = FTy->getReturnType();
5311 ComputeValueVTs(TLI, RetTy, RetTys, &Offsets);
5313 unsigned NumValues = RetTys.size();
5314 SmallVector<SDValue, 4> Values(NumValues);
5315 SmallVector<SDValue, 4> Chains(NumValues);
5317 for (unsigned i = 0; i < NumValues; ++i) {
5318 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT,
5320 DAG.getConstant(Offsets[i], PtrVT));
5321 SDValue L = DAG.getLoad(RetTys[i], getCurDebugLoc(), Result.second, Add,
5322 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]),
5323 false, false, false, 1);
5325 Chains[i] = L.getValue(1);
5328 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
5329 MVT::Other, &Chains[0], NumValues);
5330 PendingLoads.push_back(Chain);
5332 setValue(CS.getInstruction(),
5333 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
5334 DAG.getVTList(&RetTys[0], RetTys.size()),
5335 &Values[0], Values.size()));
5338 // Assign order to nodes here. If the call does not produce a result, it won't
5339 // be mapped to a SDNode and visit() will not assign it an order number.
5340 if (!Result.second.getNode()) {
5341 // As a special case, a null chain means that a tail call has been emitted and
5342 // the DAG root is already updated.
5345 AssignOrderingToNode(DAG.getRoot().getNode());
5347 DAG.setRoot(Result.second);
5349 AssignOrderingToNode(Result.second.getNode());
5353 // Insert a label at the end of the invoke call to mark the try range. This
5354 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5355 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
5356 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel));
5358 // Inform MachineModuleInfo of range.
5359 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5363 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5364 /// value is equal or not-equal to zero.
5365 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5366 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end();
5368 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI))
5369 if (IC->isEquality())
5370 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5371 if (C->isNullValue())
5373 // Unknown instruction.
5379 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5381 SelectionDAGBuilder &Builder) {
5383 // Check to see if this load can be trivially constant folded, e.g. if the
5384 // input is from a string literal.
5385 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5386 // Cast pointer to the type we really want to load.
5387 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5388 PointerType::getUnqual(LoadTy));
5390 if (const Constant *LoadCst =
5391 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
5393 return Builder.getValue(LoadCst);
5396 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5397 // still constant memory, the input chain can be the entry node.
5399 bool ConstantMemory = false;
5401 // Do not serialize (non-volatile) loads of constant memory with anything.
5402 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5403 Root = Builder.DAG.getEntryNode();
5404 ConstantMemory = true;
5406 // Do not serialize non-volatile loads against each other.
5407 Root = Builder.DAG.getRoot();
5410 SDValue Ptr = Builder.getValue(PtrVal);
5411 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root,
5412 Ptr, MachinePointerInfo(PtrVal),
5414 false /*nontemporal*/,
5415 false /*isinvariant*/, 1 /* align=1 */);
5417 if (!ConstantMemory)
5418 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5423 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5424 /// If so, return true and lower it, otherwise return false and it will be
5425 /// lowered like a normal call.
5426 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5427 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5428 if (I.getNumArgOperands() != 3)
5431 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5432 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5433 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5434 !I.getType()->isIntegerTy())
5437 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2));
5439 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5440 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5441 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) {
5442 bool ActuallyDoIt = true;
5445 switch (Size->getZExtValue()) {
5447 LoadVT = MVT::Other;
5449 ActuallyDoIt = false;
5453 LoadTy = Type::getInt16Ty(Size->getContext());
5457 LoadTy = Type::getInt32Ty(Size->getContext());
5461 LoadTy = Type::getInt64Ty(Size->getContext());
5465 LoadVT = MVT::v4i32;
5466 LoadTy = Type::getInt32Ty(Size->getContext());
5467 LoadTy = VectorType::get(LoadTy, 4);
5472 // This turns into unaligned loads. We only do this if the target natively
5473 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5474 // we'll only produce a small number of byte loads.
5476 // Require that we can find a legal MVT, and only do this if the target
5477 // supports unaligned loads of that type. Expanding into byte loads would
5479 if (ActuallyDoIt && Size->getZExtValue() > 4) {
5480 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5481 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5482 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT))
5483 ActuallyDoIt = false;
5487 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5488 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5490 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal,
5492 EVT CallVT = TLI.getValueType(I.getType(), true);
5493 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT));
5502 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5503 /// operation (as expected), translate it to an SDNode with the specified opcode
5504 /// and return true.
5505 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5507 // Sanity check that it really is a unary floating-point call.
5508 if (I.getNumArgOperands() != 1 ||
5509 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5510 I.getType() != I.getArgOperand(0)->getType() ||
5511 !I.onlyReadsMemory())
5514 SDValue Tmp = getValue(I.getArgOperand(0));
5515 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), Tmp.getValueType(), Tmp));
5519 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5520 // Handle inline assembly differently.
5521 if (isa<InlineAsm>(I.getCalledValue())) {
5526 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5527 ComputeUsesVAFloatArgument(I, &MMI);
5529 const char *RenameFn = 0;
5530 if (Function *F = I.getCalledFunction()) {
5531 if (F->isDeclaration()) {
5532 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5533 if (unsigned IID = II->getIntrinsicID(F)) {
5534 RenameFn = visitIntrinsicCall(I, IID);
5539 if (unsigned IID = F->getIntrinsicID()) {
5540 RenameFn = visitIntrinsicCall(I, IID);
5546 // Check for well-known libc/libm calls. If the function is internal, it
5547 // can't be a library call.
5549 if (!F->hasLocalLinkage() && F->hasName() &&
5550 LibInfo->getLibFunc(F->getName(), Func) &&
5551 LibInfo->hasOptimizedCodeGen(Func)) {
5554 case LibFunc::copysign:
5555 case LibFunc::copysignf:
5556 case LibFunc::copysignl:
5557 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5558 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5559 I.getType() == I.getArgOperand(0)->getType() &&
5560 I.getType() == I.getArgOperand(1)->getType() &&
5561 I.onlyReadsMemory()) {
5562 SDValue LHS = getValue(I.getArgOperand(0));
5563 SDValue RHS = getValue(I.getArgOperand(1));
5564 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
5565 LHS.getValueType(), LHS, RHS));
5570 case LibFunc::fabsf:
5571 case LibFunc::fabsl:
5572 if (visitUnaryFloatCall(I, ISD::FABS))
5578 if (visitUnaryFloatCall(I, ISD::FSIN))
5584 if (visitUnaryFloatCall(I, ISD::FCOS))
5588 case LibFunc::sqrtf:
5589 case LibFunc::sqrtl:
5590 if (visitUnaryFloatCall(I, ISD::FSQRT))
5593 case LibFunc::floor:
5594 case LibFunc::floorf:
5595 case LibFunc::floorl:
5596 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5599 case LibFunc::nearbyint:
5600 case LibFunc::nearbyintf:
5601 case LibFunc::nearbyintl:
5602 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5606 case LibFunc::ceilf:
5607 case LibFunc::ceill:
5608 if (visitUnaryFloatCall(I, ISD::FCEIL))
5612 case LibFunc::rintf:
5613 case LibFunc::rintl:
5614 if (visitUnaryFloatCall(I, ISD::FRINT))
5617 case LibFunc::trunc:
5618 case LibFunc::truncf:
5619 case LibFunc::truncl:
5620 if (visitUnaryFloatCall(I, ISD::FTRUNC))
5624 case LibFunc::log2f:
5625 case LibFunc::log2l:
5626 if (visitUnaryFloatCall(I, ISD::FLOG2))
5630 case LibFunc::exp2f:
5631 case LibFunc::exp2l:
5632 if (visitUnaryFloatCall(I, ISD::FEXP2))
5635 case LibFunc::memcmp:
5636 if (visitMemCmpCall(I))
5645 Callee = getValue(I.getCalledValue());
5647 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
5649 // Check if we can potentially perform a tail call. More detailed checking is
5650 // be done within LowerCallTo, after more information about the call is known.
5651 LowerCallTo(&I, Callee, I.isTailCall());
5656 /// AsmOperandInfo - This contains information for each constraint that we are
5658 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5660 /// CallOperand - If this is the result output operand or a clobber
5661 /// this is null, otherwise it is the incoming operand to the CallInst.
5662 /// This gets modified as the asm is processed.
5663 SDValue CallOperand;
5665 /// AssignedRegs - If this is a register or register class operand, this
5666 /// contains the set of register corresponding to the operand.
5667 RegsForValue AssignedRegs;
5669 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5670 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
5673 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5674 /// corresponds to. If there is no Value* for this operand, it returns
5676 EVT getCallOperandValEVT(LLVMContext &Context,
5677 const TargetLowering &TLI,
5678 const DataLayout *TD) const {
5679 if (CallOperandVal == 0) return MVT::Other;
5681 if (isa<BasicBlock>(CallOperandVal))
5682 return TLI.getPointerTy();
5684 llvm::Type *OpTy = CallOperandVal->getType();
5686 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5687 // If this is an indirect operand, the operand is a pointer to the
5690 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5692 report_fatal_error("Indirect operand for inline asm not a pointer!");
5693 OpTy = PtrTy->getElementType();
5696 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5697 if (StructType *STy = dyn_cast<StructType>(OpTy))
5698 if (STy->getNumElements() == 1)
5699 OpTy = STy->getElementType(0);
5701 // If OpTy is not a single value, it may be a struct/union that we
5702 // can tile with integers.
5703 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5704 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
5713 OpTy = IntegerType::get(Context, BitSize);
5718 return TLI.getValueType(OpTy, true);
5722 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5724 } // end anonymous namespace
5726 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5727 /// specified operand. We prefer to assign virtual registers, to allow the
5728 /// register allocator to handle the assignment process. However, if the asm
5729 /// uses features that we can't model on machineinstrs, we have SDISel do the
5730 /// allocation. This produces generally horrible, but correct, code.
5732 /// OpInfo describes the operand.
5734 static void GetRegistersForValue(SelectionDAG &DAG,
5735 const TargetLowering &TLI,
5737 SDISelAsmOperandInfo &OpInfo) {
5738 LLVMContext &Context = *DAG.getContext();
5740 MachineFunction &MF = DAG.getMachineFunction();
5741 SmallVector<unsigned, 4> Regs;
5743 // If this is a constraint for a single physreg, or a constraint for a
5744 // register class, find it.
5745 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
5746 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5747 OpInfo.ConstraintVT);
5749 unsigned NumRegs = 1;
5750 if (OpInfo.ConstraintVT != MVT::Other) {
5751 // If this is a FP input in an integer register (or visa versa) insert a bit
5752 // cast of the input value. More generally, handle any case where the input
5753 // value disagrees with the register class we plan to stick this in.
5754 if (OpInfo.Type == InlineAsm::isInput &&
5755 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5756 // Try to convert to the first EVT that the reg class contains. If the
5757 // types are identical size, use a bitcast to convert (e.g. two differing
5759 MVT RegVT = *PhysReg.second->vt_begin();
5760 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
5761 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5762 RegVT, OpInfo.CallOperand);
5763 OpInfo.ConstraintVT = RegVT;
5764 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5765 // If the input is a FP value and we want it in FP registers, do a
5766 // bitcast to the corresponding integer type. This turns an f64 value
5767 // into i64, which can be passed with two i32 values on a 32-bit
5769 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
5770 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5771 RegVT, OpInfo.CallOperand);
5772 OpInfo.ConstraintVT = RegVT;
5776 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5780 EVT ValueVT = OpInfo.ConstraintVT;
5782 // If this is a constraint for a specific physical register, like {r17},
5784 if (unsigned AssignedReg = PhysReg.first) {
5785 const TargetRegisterClass *RC = PhysReg.second;
5786 if (OpInfo.ConstraintVT == MVT::Other)
5787 ValueVT = *RC->vt_begin();
5789 // Get the actual register value type. This is important, because the user
5790 // may have asked for (e.g.) the AX register in i32 type. We need to
5791 // remember that AX is actually i16 to get the right extension.
5792 RegVT = *RC->vt_begin();
5794 // This is a explicit reference to a physical register.
5795 Regs.push_back(AssignedReg);
5797 // If this is an expanded reference, add the rest of the regs to Regs.
5799 TargetRegisterClass::iterator I = RC->begin();
5800 for (; *I != AssignedReg; ++I)
5801 assert(I != RC->end() && "Didn't find reg!");
5803 // Already added the first reg.
5805 for (; NumRegs; --NumRegs, ++I) {
5806 assert(I != RC->end() && "Ran out of registers to allocate!");
5811 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5815 // Otherwise, if this was a reference to an LLVM register class, create vregs
5816 // for this reference.
5817 if (const TargetRegisterClass *RC = PhysReg.second) {
5818 RegVT = *RC->vt_begin();
5819 if (OpInfo.ConstraintVT == MVT::Other)
5822 // Create the appropriate number of virtual registers.
5823 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5824 for (; NumRegs; --NumRegs)
5825 Regs.push_back(RegInfo.createVirtualRegister(RC));
5827 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5831 // Otherwise, we couldn't allocate enough registers for this.
5834 /// visitInlineAsm - Handle a call to an InlineAsm object.
5836 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5837 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5839 /// ConstraintOperands - Information about all of the constraints.
5840 SDISelAsmOperandInfoVector ConstraintOperands;
5842 TargetLowering::AsmOperandInfoVector
5843 TargetConstraints = TLI.ParseConstraints(CS);
5845 bool hasMemory = false;
5847 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5848 unsigned ResNo = 0; // ResNo - The result number of the next output.
5849 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5850 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5851 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5853 MVT OpVT = MVT::Other;
5855 // Compute the value type for each operand.
5856 switch (OpInfo.Type) {
5857 case InlineAsm::isOutput:
5858 // Indirect outputs just consume an argument.
5859 if (OpInfo.isIndirect) {
5860 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5864 // The return value of the call is this value. As such, there is no
5865 // corresponding argument.
5866 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5867 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
5868 OpVT = TLI.getSimpleValueType(STy->getElementType(ResNo));
5870 assert(ResNo == 0 && "Asm only has one result!");
5871 OpVT = TLI.getSimpleValueType(CS.getType());
5875 case InlineAsm::isInput:
5876 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5878 case InlineAsm::isClobber:
5883 // If this is an input or an indirect output, process the call argument.
5884 // BasicBlocks are labels, currently appearing only in asm's.
5885 if (OpInfo.CallOperandVal) {
5886 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5887 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5889 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5892 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD).
5896 OpInfo.ConstraintVT = OpVT;
5898 // Indirect operand accesses access memory.
5899 if (OpInfo.isIndirect)
5902 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
5903 TargetLowering::ConstraintType
5904 CType = TLI.getConstraintType(OpInfo.Codes[j]);
5905 if (CType == TargetLowering::C_Memory) {
5913 SDValue Chain, Flag;
5915 // We won't need to flush pending loads if this asm doesn't touch
5916 // memory and is nonvolatile.
5917 if (hasMemory || IA->hasSideEffects())
5920 Chain = DAG.getRoot();
5922 // Second pass over the constraints: compute which constraint option to use
5923 // and assign registers to constraints that want a specific physreg.
5924 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5925 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5927 // If this is an output operand with a matching input operand, look up the
5928 // matching input. If their types mismatch, e.g. one is an integer, the
5929 // other is floating point, or their sizes are different, flag it as an
5931 if (OpInfo.hasMatchingInput()) {
5932 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5934 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5935 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
5936 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5937 OpInfo.ConstraintVT);
5938 std::pair<unsigned, const TargetRegisterClass*> InputRC =
5939 TLI.getRegForInlineAsmConstraint(Input.ConstraintCode,
5940 Input.ConstraintVT);
5941 if ((OpInfo.ConstraintVT.isInteger() !=
5942 Input.ConstraintVT.isInteger()) ||
5943 (MatchRC.second != InputRC.second)) {
5944 report_fatal_error("Unsupported asm: input constraint"
5945 " with a matching output constraint of"
5946 " incompatible type!");
5948 Input.ConstraintVT = OpInfo.ConstraintVT;
5952 // Compute the constraint code and ConstraintType to use.
5953 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
5955 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5956 OpInfo.Type == InlineAsm::isClobber)
5959 // If this is a memory input, and if the operand is not indirect, do what we
5960 // need to to provide an address for the memory input.
5961 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5962 !OpInfo.isIndirect) {
5963 assert((OpInfo.isMultipleAlternative ||
5964 (OpInfo.Type == InlineAsm::isInput)) &&
5965 "Can only indirectify direct input operands!");
5967 // Memory operands really want the address of the value. If we don't have
5968 // an indirect input, put it in the constpool if we can, otherwise spill
5969 // it to a stack slot.
5970 // TODO: This isn't quite right. We need to handle these according to
5971 // the addressing mode that the constraint wants. Also, this may take
5972 // an additional register for the computation and we don't want that
5975 // If the operand is a float, integer, or vector constant, spill to a
5976 // constant pool entry to get its address.
5977 const Value *OpVal = OpInfo.CallOperandVal;
5978 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5979 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
5980 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5981 TLI.getPointerTy());
5983 // Otherwise, create a stack slot and emit a store to it before the
5985 Type *Ty = OpVal->getType();
5986 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
5987 unsigned Align = TLI.getDataLayout()->getPrefTypeAlignment(Ty);
5988 MachineFunction &MF = DAG.getMachineFunction();
5989 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5990 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5991 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5992 OpInfo.CallOperand, StackSlot,
5993 MachinePointerInfo::getFixedStack(SSFI),
5995 OpInfo.CallOperand = StackSlot;
5998 // There is no longer a Value* corresponding to this operand.
5999 OpInfo.CallOperandVal = 0;
6001 // It is now an indirect operand.
6002 OpInfo.isIndirect = true;
6005 // If this constraint is for a specific register, allocate it before
6007 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6008 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo);
6011 // Second pass - Loop over all of the operands, assigning virtual or physregs
6012 // to register class operands.
6013 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6014 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6016 // C_Register operands have already been allocated, Other/Memory don't need
6018 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6019 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo);
6022 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6023 std::vector<SDValue> AsmNodeOperands;
6024 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6025 AsmNodeOperands.push_back(
6026 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
6027 TLI.getPointerTy()));
6029 // If we have a !srcloc metadata node associated with it, we want to attach
6030 // this to the ultimately generated inline asm machineinstr. To do this, we
6031 // pass in the third operand as this (potentially null) inline asm MDNode.
6032 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6033 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6035 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6036 // bits as operand 3.
6037 unsigned ExtraInfo = 0;
6038 if (IA->hasSideEffects())
6039 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6040 if (IA->isAlignStack())
6041 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6042 // Set the asm dialect.
6043 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6045 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6046 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6047 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6049 // Compute the constraint code and ConstraintType to use.
6050 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6052 // Ideally, we would only check against memory constraints. However, the
6053 // meaning of an other constraint can be target-specific and we can't easily
6054 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6055 // for other constriants as well.
6056 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6057 OpInfo.ConstraintType == TargetLowering::C_Other) {
6058 if (OpInfo.Type == InlineAsm::isInput)
6059 ExtraInfo |= InlineAsm::Extra_MayLoad;
6060 else if (OpInfo.Type == InlineAsm::isOutput)
6061 ExtraInfo |= InlineAsm::Extra_MayStore;
6062 else if (OpInfo.Type == InlineAsm::isClobber)
6063 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6067 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
6068 TLI.getPointerTy()));
6070 // Loop over all of the inputs, copying the operand values into the
6071 // appropriate registers and processing the output regs.
6072 RegsForValue RetValRegs;
6074 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6075 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6077 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6078 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6080 switch (OpInfo.Type) {
6081 case InlineAsm::isOutput: {
6082 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6083 OpInfo.ConstraintType != TargetLowering::C_Register) {
6084 // Memory output, or 'other' output (e.g. 'X' constraint).
6085 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6087 // Add information to the INLINEASM node to know about this output.
6088 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6089 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
6090 TLI.getPointerTy()));
6091 AsmNodeOperands.push_back(OpInfo.CallOperand);
6095 // Otherwise, this is a register or register class output.
6097 // Copy the output from the appropriate register. Find a register that
6099 if (OpInfo.AssignedRegs.Regs.empty()) {
6100 LLVMContext &Ctx = *DAG.getContext();
6101 Ctx.emitError(CS.getInstruction(),
6102 "couldn't allocate output register for constraint '" +
6103 Twine(OpInfo.ConstraintCode) + "'");
6107 // If this is an indirect operand, store through the pointer after the
6109 if (OpInfo.isIndirect) {
6110 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6111 OpInfo.CallOperandVal));
6113 // This is the result value of the call.
6114 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6115 // Concatenate this output onto the outputs list.
6116 RetValRegs.append(OpInfo.AssignedRegs);
6119 // Add information to the INLINEASM node to know that this register is
6121 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
6122 InlineAsm::Kind_RegDefEarlyClobber :
6123 InlineAsm::Kind_RegDef,
6130 case InlineAsm::isInput: {
6131 SDValue InOperandVal = OpInfo.CallOperand;
6133 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6134 // If this is required to match an output register we have already set,
6135 // just use its register.
6136 unsigned OperandNo = OpInfo.getMatchedOperand();
6138 // Scan until we find the definition we already emitted of this operand.
6139 // When we find it, create a RegsForValue operand.
6140 unsigned CurOp = InlineAsm::Op_FirstOperand;
6141 for (; OperandNo; --OperandNo) {
6142 // Advance to the next operand.
6144 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6145 assert((InlineAsm::isRegDefKind(OpFlag) ||
6146 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6147 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6148 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6152 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6153 if (InlineAsm::isRegDefKind(OpFlag) ||
6154 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6155 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6156 if (OpInfo.isIndirect) {
6157 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6158 LLVMContext &Ctx = *DAG.getContext();
6159 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6160 " don't know how to handle tied "
6161 "indirect register inputs");
6162 report_fatal_error("Cannot handle indirect register inputs!");
6165 RegsForValue MatchedRegs;
6166 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6167 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6168 MatchedRegs.RegVTs.push_back(RegVT);
6169 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6170 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6172 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6173 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6175 LLVMContext &Ctx = *DAG.getContext();
6176 Ctx.emitError(CS.getInstruction(), "inline asm error: This value"
6177 " type register class is not natively supported!");
6178 report_fatal_error("inline asm error: This value type register "
6179 "class is not natively supported!");
6182 // Use the produced MatchedRegs object to
6183 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
6184 Chain, &Flag, CS.getInstruction());
6185 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6186 true, OpInfo.getMatchedOperand(),
6187 DAG, AsmNodeOperands);
6191 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6192 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6193 "Unexpected number of operands");
6194 // Add information to the INLINEASM node to know about this input.
6195 // See InlineAsm.h isUseOperandTiedToDef.
6196 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6197 OpInfo.getMatchedOperand());
6198 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
6199 TLI.getPointerTy()));
6200 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6204 // Treat indirect 'X' constraint as memory.
6205 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6207 OpInfo.ConstraintType = TargetLowering::C_Memory;
6209 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6210 std::vector<SDValue> Ops;
6211 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6214 LLVMContext &Ctx = *DAG.getContext();
6215 Ctx.emitError(CS.getInstruction(),
6216 "invalid operand for inline asm constraint '" +
6217 Twine(OpInfo.ConstraintCode) + "'");
6221 // Add information to the INLINEASM node to know about this input.
6222 unsigned ResOpType =
6223 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6224 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6225 TLI.getPointerTy()));
6226 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6230 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6231 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6232 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
6233 "Memory operands expect pointer values");
6235 // Add information to the INLINEASM node to know about this input.
6236 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6237 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6238 TLI.getPointerTy()));
6239 AsmNodeOperands.push_back(InOperandVal);
6243 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6244 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6245 "Unknown constraint type!");
6247 // TODO: Support this.
6248 if (OpInfo.isIndirect) {
6249 LLVMContext &Ctx = *DAG.getContext();
6250 Ctx.emitError(CS.getInstruction(),
6251 "Don't know how to handle indirect register inputs yet "
6252 "for constraint '" + Twine(OpInfo.ConstraintCode) + "'");
6256 // Copy the input into the appropriate registers.
6257 if (OpInfo.AssignedRegs.Regs.empty()) {
6258 LLVMContext &Ctx = *DAG.getContext();
6259 Ctx.emitError(CS.getInstruction(),
6260 "couldn't allocate input reg for constraint '" +
6261 Twine(OpInfo.ConstraintCode) + "'");
6265 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
6266 Chain, &Flag, CS.getInstruction());
6268 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6269 DAG, AsmNodeOperands);
6272 case InlineAsm::isClobber: {
6273 // Add the clobbered value to the operand list, so that the register
6274 // allocator is aware that the physreg got clobbered.
6275 if (!OpInfo.AssignedRegs.Regs.empty())
6276 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6284 // Finish up input operands. Set the input chain and add the flag last.
6285 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6286 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6288 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
6289 DAG.getVTList(MVT::Other, MVT::Glue),
6290 &AsmNodeOperands[0], AsmNodeOperands.size());
6291 Flag = Chain.getValue(1);
6293 // If this asm returns a register value, copy the result from that register
6294 // and set it as the value of the call.
6295 if (!RetValRegs.Regs.empty()) {
6296 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
6297 Chain, &Flag, CS.getInstruction());
6299 // FIXME: Why don't we do this for inline asms with MRVs?
6300 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6301 EVT ResultType = TLI.getValueType(CS.getType());
6303 // If any of the results of the inline asm is a vector, it may have the
6304 // wrong width/num elts. This can happen for register classes that can
6305 // contain multiple different value types. The preg or vreg allocated may
6306 // not have the same VT as was expected. Convert it to the right type
6307 // with bit_convert.
6308 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6309 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
6312 } else if (ResultType != Val.getValueType() &&
6313 ResultType.isInteger() && Val.getValueType().isInteger()) {
6314 // If a result value was tied to an input value, the computed result may
6315 // have a wider width than the expected result. Extract the relevant
6317 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
6320 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6323 setValue(CS.getInstruction(), Val);
6324 // Don't need to use this as a chain in this case.
6325 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6329 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6331 // Process indirect outputs, first output all of the flagged copies out of
6333 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6334 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6335 const Value *Ptr = IndirectStoresToEmit[i].second;
6336 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
6338 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6341 // Emit the non-flagged stores from the physregs.
6342 SmallVector<SDValue, 8> OutChains;
6343 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6344 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(),
6345 StoresToEmit[i].first,
6346 getValue(StoresToEmit[i].second),
6347 MachinePointerInfo(StoresToEmit[i].second),
6349 OutChains.push_back(Val);
6352 if (!OutChains.empty())
6353 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
6354 &OutChains[0], OutChains.size());
6359 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6360 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
6361 MVT::Other, getRoot(),
6362 getValue(I.getArgOperand(0)),
6363 DAG.getSrcValue(I.getArgOperand(0))));
6366 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6367 const DataLayout &TD = *TLI.getDataLayout();
6368 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
6369 getRoot(), getValue(I.getOperand(0)),
6370 DAG.getSrcValue(I.getOperand(0)),
6371 TD.getABITypeAlignment(I.getType()));
6373 DAG.setRoot(V.getValue(1));
6376 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6377 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
6378 MVT::Other, getRoot(),
6379 getValue(I.getArgOperand(0)),
6380 DAG.getSrcValue(I.getArgOperand(0))));
6383 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6384 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
6385 MVT::Other, getRoot(),
6386 getValue(I.getArgOperand(0)),
6387 getValue(I.getArgOperand(1)),
6388 DAG.getSrcValue(I.getArgOperand(0)),
6389 DAG.getSrcValue(I.getArgOperand(1))));
6392 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6393 /// implementation, which just calls LowerCall.
6394 /// FIXME: When all targets are
6395 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6396 std::pair<SDValue, SDValue>
6397 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
6398 // Handle the incoming return values from the call.
6400 SmallVector<EVT, 4> RetTys;
6401 ComputeValueVTs(*this, CLI.RetTy, RetTys);
6402 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6404 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6405 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6406 for (unsigned i = 0; i != NumRegs; ++i) {
6407 ISD::InputArg MyFlags;
6408 MyFlags.VT = RegisterVT;
6409 MyFlags.Used = CLI.IsReturnValueUsed;
6411 MyFlags.Flags.setSExt();
6413 MyFlags.Flags.setZExt();
6415 MyFlags.Flags.setInReg();
6416 CLI.Ins.push_back(MyFlags);
6420 // Handle all of the outgoing arguments.
6422 CLI.OutVals.clear();
6423 ArgListTy &Args = CLI.Args;
6424 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6425 SmallVector<EVT, 4> ValueVTs;
6426 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
6427 for (unsigned Value = 0, NumValues = ValueVTs.size();
6428 Value != NumValues; ++Value) {
6429 EVT VT = ValueVTs[Value];
6430 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
6431 SDValue Op = SDValue(Args[i].Node.getNode(),
6432 Args[i].Node.getResNo() + Value);
6433 ISD::ArgFlagsTy Flags;
6434 unsigned OriginalAlignment =
6435 getDataLayout()->getABITypeAlignment(ArgTy);
6441 if (Args[i].isInReg)
6445 if (Args[i].isByVal) {
6447 PointerType *Ty = cast<PointerType>(Args[i].Ty);
6448 Type *ElementTy = Ty->getElementType();
6449 Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy));
6450 // For ByVal, alignment should come from FE. BE will guess if this
6451 // info is not there but there are cases it cannot get right.
6452 unsigned FrameAlign;
6453 if (Args[i].Alignment)
6454 FrameAlign = Args[i].Alignment;
6456 FrameAlign = getByValTypeAlignment(ElementTy);
6457 Flags.setByValAlign(FrameAlign);
6461 Flags.setOrigAlign(OriginalAlignment);
6463 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
6464 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
6465 SmallVector<SDValue, 4> Parts(NumParts);
6466 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6469 ExtendKind = ISD::SIGN_EXTEND;
6470 else if (Args[i].isZExt)
6471 ExtendKind = ISD::ZERO_EXTEND;
6473 // Conservatively only handle 'returned' on non-vectors for now
6474 if (Args[i].isReturned && !Op.getValueType().isVector()) {
6475 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
6476 "unexpected use of 'returned'");
6477 // Before passing 'returned' to the target lowering code, ensure that
6478 // either the register MVT and the actual EVT are the same size or that
6479 // the return value and argument are extended in the same way; in these
6480 // cases it's safe to pass the argument register value unchanged as the
6481 // return register value (although it's at the target's option whether
6483 // TODO: allow code generation to take advantage of partially preserved
6484 // registers rather than clobbering the entire register when the
6485 // parameter extension method is not compatible with the return
6487 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
6488 (ExtendKind != ISD::ANY_EXTEND &&
6489 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
6490 Flags.setReturned();
6493 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts,
6494 PartVT, CLI.CS ? CLI.CS->getInstruction() : 0, ExtendKind);
6496 for (unsigned j = 0; j != NumParts; ++j) {
6497 // if it isn't first piece, alignment must be 1
6498 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(),
6499 i < CLI.NumFixedArgs,
6500 i, j*Parts[j].getValueType().getStoreSize());
6501 if (NumParts > 1 && j == 0)
6502 MyFlags.Flags.setSplit();
6504 MyFlags.Flags.setOrigAlign(1);
6506 CLI.Outs.push_back(MyFlags);
6507 CLI.OutVals.push_back(Parts[j]);
6512 SmallVector<SDValue, 4> InVals;
6513 CLI.Chain = LowerCall(CLI, InVals);
6515 // Verify that the target's LowerCall behaved as expected.
6516 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
6517 "LowerCall didn't return a valid chain!");
6518 assert((!CLI.IsTailCall || InVals.empty()) &&
6519 "LowerCall emitted a return value for a tail call!");
6520 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
6521 "LowerCall didn't emit the correct number of values!");
6523 // For a tail call, the return value is merely live-out and there aren't
6524 // any nodes in the DAG representing it. Return a special value to
6525 // indicate that a tail call has been emitted and no more Instructions
6526 // should be processed in the current block.
6527 if (CLI.IsTailCall) {
6528 CLI.DAG.setRoot(CLI.Chain);
6529 return std::make_pair(SDValue(), SDValue());
6532 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
6533 assert(InVals[i].getNode() &&
6534 "LowerCall emitted a null value!");
6535 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
6536 "LowerCall emitted a value with the wrong type!");
6539 // Collect the legal value parts into potentially illegal values
6540 // that correspond to the original function's return values.
6541 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6543 AssertOp = ISD::AssertSext;
6544 else if (CLI.RetZExt)
6545 AssertOp = ISD::AssertZext;
6546 SmallVector<SDValue, 4> ReturnValues;
6547 unsigned CurReg = 0;
6548 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6550 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6551 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6553 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
6554 NumRegs, RegisterVT, VT, NULL,
6559 // For a function returning void, there is no return value. We can't create
6560 // such a node, so we just return a null return value in that case. In
6561 // that case, nothing will actually look at the value.
6562 if (ReturnValues.empty())
6563 return std::make_pair(SDValue(), CLI.Chain);
6565 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
6566 CLI.DAG.getVTList(&RetTys[0], RetTys.size()),
6567 &ReturnValues[0], ReturnValues.size());
6568 return std::make_pair(Res, CLI.Chain);
6571 void TargetLowering::LowerOperationWrapper(SDNode *N,
6572 SmallVectorImpl<SDValue> &Results,
6573 SelectionDAG &DAG) const {
6574 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
6576 Results.push_back(Res);
6579 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6580 llvm_unreachable("LowerOperation not implemented for this target!");
6584 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
6585 SDValue Op = getNonRegisterValue(V);
6586 assert((Op.getOpcode() != ISD::CopyFromReg ||
6587 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
6588 "Copy from a reg to the same reg!");
6589 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
6591 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
6592 SDValue Chain = DAG.getEntryNode();
6593 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0, V);
6594 PendingExports.push_back(Chain);
6597 #include "llvm/CodeGen/SelectionDAGISel.h"
6599 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
6600 /// entry block, return true. This includes arguments used by switches, since
6601 /// the switch may expand into multiple basic blocks.
6602 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
6603 // With FastISel active, we may be splitting blocks, so force creation
6604 // of virtual registers for all non-dead arguments.
6606 return A->use_empty();
6608 const BasicBlock *Entry = A->getParent()->begin();
6609 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end();
6611 const User *U = *UI;
6612 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
6613 return false; // Use not in entry block.
6618 void SelectionDAGISel::LowerArguments(const Function &F) {
6619 SelectionDAG &DAG = SDB->DAG;
6620 DebugLoc dl = SDB->getCurDebugLoc();
6621 const DataLayout *TD = TLI.getDataLayout();
6622 SmallVector<ISD::InputArg, 16> Ins;
6624 if (!FuncInfo->CanLowerReturn) {
6625 // Put in an sret pointer parameter before all the other parameters.
6626 SmallVector<EVT, 1> ValueVTs;
6627 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6629 // NOTE: Assuming that a pointer will never break down to more than one VT
6631 ISD::ArgFlagsTy Flags;
6633 MVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]);
6634 ISD::InputArg RetArg(Flags, RegisterVT, true, 0, 0);
6635 Ins.push_back(RetArg);
6638 // Set up the incoming argument description vector.
6640 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
6641 I != E; ++I, ++Idx) {
6642 SmallVector<EVT, 4> ValueVTs;
6643 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6644 bool isArgValueUsed = !I->use_empty();
6645 for (unsigned Value = 0, NumValues = ValueVTs.size();
6646 Value != NumValues; ++Value) {
6647 EVT VT = ValueVTs[Value];
6648 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
6649 ISD::ArgFlagsTy Flags;
6650 unsigned OriginalAlignment =
6651 TD->getABITypeAlignment(ArgTy);
6653 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
6655 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
6657 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
6659 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
6661 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal)) {
6663 PointerType *Ty = cast<PointerType>(I->getType());
6664 Type *ElementTy = Ty->getElementType();
6665 Flags.setByValSize(TD->getTypeAllocSize(ElementTy));
6666 // For ByVal, alignment should be passed from FE. BE will guess if
6667 // this info is not there but there are cases it cannot get right.
6668 unsigned FrameAlign;
6669 if (F.getParamAlignment(Idx))
6670 FrameAlign = F.getParamAlignment(Idx);
6672 FrameAlign = TLI.getByValTypeAlignment(ElementTy);
6673 Flags.setByValAlign(FrameAlign);
6675 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
6677 Flags.setOrigAlign(OriginalAlignment);
6679 MVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6680 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6681 for (unsigned i = 0; i != NumRegs; ++i) {
6682 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed,
6683 Idx-1, i*RegisterVT.getStoreSize());
6684 if (NumRegs > 1 && i == 0)
6685 MyFlags.Flags.setSplit();
6686 // if it isn't first piece, alignment must be 1
6688 MyFlags.Flags.setOrigAlign(1);
6689 Ins.push_back(MyFlags);
6694 // Call the target to set up the argument values.
6695 SmallVector<SDValue, 8> InVals;
6696 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
6700 // Verify that the target's LowerFormalArguments behaved as expected.
6701 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
6702 "LowerFormalArguments didn't return a valid chain!");
6703 assert(InVals.size() == Ins.size() &&
6704 "LowerFormalArguments didn't emit the correct number of values!");
6706 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6707 assert(InVals[i].getNode() &&
6708 "LowerFormalArguments emitted a null value!");
6709 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6710 "LowerFormalArguments emitted a value with the wrong type!");
6714 // Update the DAG with the new chain value resulting from argument lowering.
6715 DAG.setRoot(NewRoot);
6717 // Set up the argument values.
6720 if (!FuncInfo->CanLowerReturn) {
6721 // Create a virtual register for the sret pointer, and put in a copy
6722 // from the sret argument into it.
6723 SmallVector<EVT, 1> ValueVTs;
6724 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6725 MVT VT = ValueVTs[0].getSimpleVT();
6726 MVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6727 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6728 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
6729 RegVT, VT, NULL, AssertOp);
6731 MachineFunction& MF = SDB->DAG.getMachineFunction();
6732 MachineRegisterInfo& RegInfo = MF.getRegInfo();
6733 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT));
6734 FuncInfo->DemoteRegister = SRetReg;
6735 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(),
6737 DAG.setRoot(NewRoot);
6739 // i indexes lowered arguments. Bump it past the hidden sret argument.
6740 // Idx indexes LLVM arguments. Don't touch it.
6744 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
6746 SmallVector<SDValue, 4> ArgValues;
6747 SmallVector<EVT, 4> ValueVTs;
6748 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6749 unsigned NumValues = ValueVTs.size();
6751 // If this argument is unused then remember its value. It is used to generate
6752 // debugging information.
6753 if (I->use_empty() && NumValues)
6754 SDB->setUnusedArgValue(I, InVals[i]);
6756 for (unsigned Val = 0; Val != NumValues; ++Val) {
6757 EVT VT = ValueVTs[Val];
6758 MVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6759 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6761 if (!I->use_empty()) {
6762 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6763 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
6764 AssertOp = ISD::AssertSext;
6765 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
6766 AssertOp = ISD::AssertZext;
6768 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
6769 NumParts, PartVT, VT,
6776 // We don't need to do anything else for unused arguments.
6777 if (ArgValues.empty())
6780 // Note down frame index.
6781 if (FrameIndexSDNode *FI =
6782 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
6783 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
6785 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues,
6786 SDB->getCurDebugLoc());
6788 SDB->setValue(I, Res);
6789 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
6790 if (LoadSDNode *LNode =
6791 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
6792 if (FrameIndexSDNode *FI =
6793 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
6794 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
6797 // If this argument is live outside of the entry block, insert a copy from
6798 // wherever we got it to the vreg that other BB's will reference it as.
6799 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
6800 // If we can, though, try to skip creating an unnecessary vreg.
6801 // FIXME: This isn't very clean... it would be nice to make this more
6802 // general. It's also subtly incompatible with the hacks FastISel
6804 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
6805 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
6806 FuncInfo->ValueMap[I] = Reg;
6810 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
6811 FuncInfo->InitializeRegForValue(I);
6812 SDB->CopyToExportRegsIfNeeded(I);
6816 assert(i == InVals.size() && "Argument register count mismatch!");
6818 // Finally, if the target has anything special to do, allow it to do so.
6819 // FIXME: this should insert code into the DAG!
6820 EmitFunctionEntryCode();
6823 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
6824 /// ensure constants are generated when needed. Remember the virtual registers
6825 /// that need to be added to the Machine PHI nodes as input. We cannot just
6826 /// directly add them, because expansion might result in multiple MBB's for one
6827 /// BB. As such, the start of the BB might correspond to a different MBB than
6831 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
6832 const TerminatorInst *TI = LLVMBB->getTerminator();
6834 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6836 // Check successor nodes' PHI nodes that expect a constant to be available
6838 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6839 const BasicBlock *SuccBB = TI->getSuccessor(succ);
6840 if (!isa<PHINode>(SuccBB->begin())) continue;
6841 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
6843 // If this terminator has multiple identical successors (common for
6844 // switches), only handle each succ once.
6845 if (!SuccsHandled.insert(SuccMBB)) continue;
6847 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6849 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6850 // nodes and Machine PHI nodes, but the incoming operands have not been
6852 for (BasicBlock::const_iterator I = SuccBB->begin();
6853 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
6854 // Ignore dead phi's.
6855 if (PN->use_empty()) continue;
6858 if (PN->getType()->isEmptyTy())
6862 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6864 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
6865 unsigned &RegOut = ConstantsOut[C];
6867 RegOut = FuncInfo.CreateRegs(C->getType());
6868 CopyValueToVirtualRegister(C, RegOut);
6872 DenseMap<const Value *, unsigned>::iterator I =
6873 FuncInfo.ValueMap.find(PHIOp);
6874 if (I != FuncInfo.ValueMap.end())
6877 assert(isa<AllocaInst>(PHIOp) &&
6878 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
6879 "Didn't codegen value into a register!??");
6880 Reg = FuncInfo.CreateRegs(PHIOp->getType());
6881 CopyValueToVirtualRegister(PHIOp, Reg);
6885 // Remember that this register needs to added to the machine PHI node as
6886 // the input for this MBB.
6887 SmallVector<EVT, 4> ValueVTs;
6888 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
6889 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
6890 EVT VT = ValueVTs[vti];
6891 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
6892 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
6893 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
6894 Reg += NumRegisters;
6898 ConstantsOut.clear();