1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/Loads.h"
24 #include "llvm/Analysis/TargetLibraryInfo.h"
25 #include "llvm/Analysis/ValueTracking.h"
26 #include "llvm/Analysis/VectorUtils.h"
27 #include "llvm/CodeGen/Analysis.h"
28 #include "llvm/CodeGen/FastISel.h"
29 #include "llvm/CodeGen/FunctionLoweringInfo.h"
30 #include "llvm/CodeGen/GCMetadata.h"
31 #include "llvm/CodeGen/GCStrategy.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/SelectionDAG.h"
39 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
40 #include "llvm/CodeGen/StackMaps.h"
41 #include "llvm/CodeGen/WinEHFuncInfo.h"
42 #include "llvm/IR/CallingConv.h"
43 #include "llvm/IR/ConstantRange.h"
44 #include "llvm/IR/Constants.h"
45 #include "llvm/IR/DataLayout.h"
46 #include "llvm/IR/DebugInfo.h"
47 #include "llvm/IR/DerivedTypes.h"
48 #include "llvm/IR/Function.h"
49 #include "llvm/IR/GetElementPtrTypeIterator.h"
50 #include "llvm/IR/GlobalVariable.h"
51 #include "llvm/IR/InlineAsm.h"
52 #include "llvm/IR/Instructions.h"
53 #include "llvm/IR/IntrinsicInst.h"
54 #include "llvm/IR/Intrinsics.h"
55 #include "llvm/IR/LLVMContext.h"
56 #include "llvm/IR/Module.h"
57 #include "llvm/IR/Statepoint.h"
58 #include "llvm/MC/MCSymbol.h"
59 #include "llvm/Support/CommandLine.h"
60 #include "llvm/Support/Debug.h"
61 #include "llvm/Support/ErrorHandling.h"
62 #include "llvm/Support/MathExtras.h"
63 #include "llvm/Support/raw_ostream.h"
64 #include "llvm/Target/TargetFrameLowering.h"
65 #include "llvm/Target/TargetInstrInfo.h"
66 #include "llvm/Target/TargetIntrinsicInfo.h"
67 #include "llvm/Target/TargetLowering.h"
68 #include "llvm/Target/TargetOptions.h"
69 #include "llvm/Target/TargetSubtargetInfo.h"
74 #define DEBUG_TYPE "isel"
76 /// LimitFloatPrecision - Generate low-precision inline sequences for
77 /// some float libcalls (6, 8 or 12 bits).
78 static unsigned LimitFloatPrecision;
80 static cl::opt<unsigned, true>
81 LimitFPPrecision("limit-float-precision",
82 cl::desc("Generate low-precision inline sequences "
83 "for some float libcalls"),
84 cl::location(LimitFloatPrecision),
88 EnableFMFInDAG("enable-fmf-dag", cl::init(true), cl::Hidden,
89 cl::desc("Enable fast-math-flags for DAG nodes"));
91 /// Minimum jump table density for normal functions.
92 static cl::opt<unsigned>
93 JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden,
94 cl::desc("Minimum density for building a jump table in "
95 "a normal function"));
97 /// Minimum jump table density for -Os or -Oz functions.
98 static cl::opt<unsigned>
99 OptsizeJumpTableDensity("optsize-jump-table-density", cl::init(40), cl::Hidden,
100 cl::desc("Minimum density for building a jump table in "
101 "an optsize function"));
104 // Limit the width of DAG chains. This is important in general to prevent
105 // DAG-based analysis from blowing up. For example, alias analysis and
106 // load clustering may not complete in reasonable time. It is difficult to
107 // recognize and avoid this situation within each individual analysis, and
108 // future analyses are likely to have the same behavior. Limiting DAG width is
109 // the safe approach and will be especially important with global DAGs.
111 // MaxParallelChains default is arbitrarily high to avoid affecting
112 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
113 // sequence over this should have been converted to llvm.memcpy by the
114 // frontend. It is easy to induce this behavior with .ll code such as:
115 // %buffer = alloca [4096 x i8]
116 // %data = load [4096 x i8]* %argPtr
117 // store [4096 x i8] %data, [4096 x i8]* %buffer
118 static const unsigned MaxParallelChains = 64;
120 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL,
121 const SDValue *Parts, unsigned NumParts,
122 MVT PartVT, EVT ValueVT, const Value *V);
124 /// getCopyFromParts - Create a value that contains the specified legal parts
125 /// combined into the value they represent. If the parts combine to a type
126 /// larger than ValueVT then AssertOp can be used to specify whether the extra
127 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
128 /// (ISD::AssertSext).
129 static SDValue getCopyFromParts(SelectionDAG &DAG, const SDLoc &DL,
130 const SDValue *Parts, unsigned NumParts,
131 MVT PartVT, EVT ValueVT, const Value *V,
132 Optional<ISD::NodeType> AssertOp = None) {
133 if (ValueVT.isVector())
134 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
137 assert(NumParts > 0 && "No parts to assemble!");
138 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
139 SDValue Val = Parts[0];
142 // Assemble the value from multiple parts.
143 if (ValueVT.isInteger()) {
144 unsigned PartBits = PartVT.getSizeInBits();
145 unsigned ValueBits = ValueVT.getSizeInBits();
147 // Assemble the power of 2 part.
148 unsigned RoundParts = NumParts & (NumParts - 1) ?
149 1 << Log2_32(NumParts) : NumParts;
150 unsigned RoundBits = PartBits * RoundParts;
151 EVT RoundVT = RoundBits == ValueBits ?
152 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
155 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
157 if (RoundParts > 2) {
158 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
160 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
161 RoundParts / 2, PartVT, HalfVT, V);
163 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
164 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
167 if (DAG.getDataLayout().isBigEndian())
170 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
172 if (RoundParts < NumParts) {
173 // Assemble the trailing non-power-of-2 part.
174 unsigned OddParts = NumParts - RoundParts;
175 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
176 Hi = getCopyFromParts(DAG, DL,
177 Parts + RoundParts, OddParts, PartVT, OddVT, V);
179 // Combine the round and odd parts.
181 if (DAG.getDataLayout().isBigEndian())
183 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
184 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
186 DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
187 DAG.getConstant(Lo.getValueSizeInBits(), DL,
188 TLI.getPointerTy(DAG.getDataLayout())));
189 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
190 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
192 } else if (PartVT.isFloatingPoint()) {
193 // FP split into multiple FP parts (for ppcf128)
194 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
197 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
198 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
199 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout()))
201 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
203 // FP split into integer parts (soft fp)
204 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
205 !PartVT.isVector() && "Unexpected split");
206 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
207 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
211 // There is now one part, held in Val. Correct it to match ValueVT.
212 // PartEVT is the type of the register class that holds the value.
213 // ValueVT is the type of the inline asm operation.
214 EVT PartEVT = Val.getValueType();
216 if (PartEVT == ValueVT)
219 if (PartEVT.isInteger() && ValueVT.isFloatingPoint() &&
220 ValueVT.bitsLT(PartEVT)) {
221 // For an FP value in an integer part, we need to truncate to the right
223 PartEVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
224 Val = DAG.getNode(ISD::TRUNCATE, DL, PartEVT, Val);
227 // Handle types that have the same size.
228 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
229 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
231 // Handle types with different sizes.
232 if (PartEVT.isInteger() && ValueVT.isInteger()) {
233 if (ValueVT.bitsLT(PartEVT)) {
234 // For a truncate, see if we have any information to
235 // indicate whether the truncated bits will always be
236 // zero or sign-extension.
237 if (AssertOp.hasValue())
238 Val = DAG.getNode(*AssertOp, DL, PartEVT, Val,
239 DAG.getValueType(ValueVT));
240 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
242 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
245 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
246 // FP_ROUND's are always exact here.
247 if (ValueVT.bitsLT(Val.getValueType()))
249 ISD::FP_ROUND, DL, ValueVT, Val,
250 DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout())));
252 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
255 llvm_unreachable("Unknown mismatch!");
258 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
259 const Twine &ErrMsg) {
260 const Instruction *I = dyn_cast_or_null<Instruction>(V);
262 return Ctx.emitError(ErrMsg);
264 const char *AsmError = ", possible invalid constraint for vector type";
265 if (const CallInst *CI = dyn_cast<CallInst>(I))
266 if (isa<InlineAsm>(CI->getCalledValue()))
267 return Ctx.emitError(I, ErrMsg + AsmError);
269 return Ctx.emitError(I, ErrMsg);
272 /// getCopyFromPartsVector - Create a value that contains the specified legal
273 /// parts combined into the value they represent. If the parts combine to a
274 /// type larger than ValueVT then AssertOp can be used to specify whether the
275 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
276 /// ValueVT (ISD::AssertSext).
277 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL,
278 const SDValue *Parts, unsigned NumParts,
279 MVT PartVT, EVT ValueVT, const Value *V) {
280 assert(ValueVT.isVector() && "Not a vector value");
281 assert(NumParts > 0 && "No parts to assemble!");
282 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
283 SDValue Val = Parts[0];
285 // Handle a multi-element vector.
289 unsigned NumIntermediates;
291 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
292 NumIntermediates, RegisterVT);
293 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
294 NumParts = NumRegs; // Silence a compiler warning.
295 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
296 assert(RegisterVT.getSizeInBits() ==
297 Parts[0].getSimpleValueType().getSizeInBits() &&
298 "Part type sizes don't match!");
300 // Assemble the parts into intermediate operands.
301 SmallVector<SDValue, 8> Ops(NumIntermediates);
302 if (NumIntermediates == NumParts) {
303 // If the register was not expanded, truncate or copy the value,
305 for (unsigned i = 0; i != NumParts; ++i)
306 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
307 PartVT, IntermediateVT, V);
308 } else if (NumParts > 0) {
309 // If the intermediate type was expanded, build the intermediate
310 // operands from the parts.
311 assert(NumParts % NumIntermediates == 0 &&
312 "Must expand into a divisible number of parts!");
313 unsigned Factor = NumParts / NumIntermediates;
314 for (unsigned i = 0; i != NumIntermediates; ++i)
315 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
316 PartVT, IntermediateVT, V);
319 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
320 // intermediate operands.
321 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
326 // There is now one part, held in Val. Correct it to match ValueVT.
327 EVT PartEVT = Val.getValueType();
329 if (PartEVT == ValueVT)
332 if (PartEVT.isVector()) {
333 // If the element type of the source/dest vectors are the same, but the
334 // parts vector has more elements than the value vector, then we have a
335 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
337 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
338 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
339 "Cannot narrow, it would be a lossy transformation");
341 ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
342 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
345 // Vector/Vector bitcast.
346 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
347 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
349 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
350 "Cannot handle this kind of promotion");
351 // Promoted vector extract
352 return DAG.getAnyExtOrTrunc(Val, DL, ValueVT);
356 // Trivial bitcast if the types are the same size and the destination
357 // vector type is legal.
358 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
359 TLI.isTypeLegal(ValueVT))
360 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
362 // Handle cases such as i8 -> <1 x i1>
363 if (ValueVT.getVectorNumElements() != 1) {
364 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
365 "non-trivial scalar-to-vector conversion");
366 return DAG.getUNDEF(ValueVT);
369 if (ValueVT.getVectorNumElements() == 1 &&
370 ValueVT.getVectorElementType() != PartEVT)
371 Val = DAG.getAnyExtOrTrunc(Val, DL, ValueVT.getScalarType());
373 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
376 static void getCopyToPartsVector(SelectionDAG &DAG, const SDLoc &dl,
377 SDValue Val, SDValue *Parts, unsigned NumParts,
378 MVT PartVT, const Value *V);
380 /// getCopyToParts - Create a series of nodes that contain the specified value
381 /// split into legal parts. If the parts contain more bits than Val, then, for
382 /// integers, ExtendKind can be used to specify how to generate the extra bits.
383 static void getCopyToParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val,
384 SDValue *Parts, unsigned NumParts, MVT PartVT,
386 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
387 EVT ValueVT = Val.getValueType();
389 // Handle the vector case separately.
390 if (ValueVT.isVector())
391 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
393 unsigned PartBits = PartVT.getSizeInBits();
394 unsigned OrigNumParts = NumParts;
395 assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) &&
396 "Copying to an illegal type!");
401 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
402 EVT PartEVT = PartVT;
403 if (PartEVT == ValueVT) {
404 assert(NumParts == 1 && "No-op copy with multiple parts!");
409 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
410 // If the parts cover more bits than the value has, promote the value.
411 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
412 assert(NumParts == 1 && "Do not know what to promote to!");
413 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
415 if (ValueVT.isFloatingPoint()) {
416 // FP values need to be bitcast, then extended if they are being put
417 // into a larger container.
418 ValueVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
419 Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
421 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
422 ValueVT.isInteger() &&
423 "Unknown mismatch!");
424 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
425 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
426 if (PartVT == MVT::x86mmx)
427 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
429 } else if (PartBits == ValueVT.getSizeInBits()) {
430 // Different types of the same size.
431 assert(NumParts == 1 && PartEVT != ValueVT);
432 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
433 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
434 // If the parts cover less bits than value has, truncate the value.
435 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
436 ValueVT.isInteger() &&
437 "Unknown mismatch!");
438 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
439 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
440 if (PartVT == MVT::x86mmx)
441 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
444 // The value may have changed - recompute ValueVT.
445 ValueVT = Val.getValueType();
446 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
447 "Failed to tile the value with PartVT!");
450 if (PartEVT != ValueVT) {
451 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
452 "scalar-to-vector conversion failed");
453 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
460 // Expand the value into multiple parts.
461 if (NumParts & (NumParts - 1)) {
462 // The number of parts is not a power of 2. Split off and copy the tail.
463 assert(PartVT.isInteger() && ValueVT.isInteger() &&
464 "Do not know what to expand to!");
465 unsigned RoundParts = 1 << Log2_32(NumParts);
466 unsigned RoundBits = RoundParts * PartBits;
467 unsigned OddParts = NumParts - RoundParts;
468 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
469 DAG.getIntPtrConstant(RoundBits, DL));
470 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
472 if (DAG.getDataLayout().isBigEndian())
473 // The odd parts were reversed by getCopyToParts - unreverse them.
474 std::reverse(Parts + RoundParts, Parts + NumParts);
476 NumParts = RoundParts;
477 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
478 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
481 // The number of parts is a power of 2. Repeatedly bisect the value using
483 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
484 EVT::getIntegerVT(*DAG.getContext(),
485 ValueVT.getSizeInBits()),
488 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
489 for (unsigned i = 0; i < NumParts; i += StepSize) {
490 unsigned ThisBits = StepSize * PartBits / 2;
491 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
492 SDValue &Part0 = Parts[i];
493 SDValue &Part1 = Parts[i+StepSize/2];
495 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
496 ThisVT, Part0, DAG.getIntPtrConstant(1, DL));
497 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
498 ThisVT, Part0, DAG.getIntPtrConstant(0, DL));
500 if (ThisBits == PartBits && ThisVT != PartVT) {
501 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
502 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
507 if (DAG.getDataLayout().isBigEndian())
508 std::reverse(Parts, Parts + OrigNumParts);
512 /// getCopyToPartsVector - Create a series of nodes that contain the specified
513 /// value split into legal parts.
514 static void getCopyToPartsVector(SelectionDAG &DAG, const SDLoc &DL,
515 SDValue Val, SDValue *Parts, unsigned NumParts,
516 MVT PartVT, const Value *V) {
517 EVT ValueVT = Val.getValueType();
518 assert(ValueVT.isVector() && "Not a vector");
519 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
522 EVT PartEVT = PartVT;
523 if (PartEVT == ValueVT) {
525 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
526 // Bitconvert vector->vector case.
527 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
528 } else if (PartVT.isVector() &&
529 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
530 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
531 EVT ElementVT = PartVT.getVectorElementType();
532 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
534 SmallVector<SDValue, 16> Ops;
535 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
536 Ops.push_back(DAG.getNode(
537 ISD::EXTRACT_VECTOR_ELT, DL, ElementVT, Val,
538 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))));
540 for (unsigned i = ValueVT.getVectorNumElements(),
541 e = PartVT.getVectorNumElements(); i != e; ++i)
542 Ops.push_back(DAG.getUNDEF(ElementVT));
544 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
546 // FIXME: Use CONCAT for 2x -> 4x.
548 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
549 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
550 } else if (PartVT.isVector() &&
551 PartEVT.getVectorElementType().bitsGE(
552 ValueVT.getVectorElementType()) &&
553 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
555 // Promoted vector extract
556 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
558 // Vector -> scalar conversion.
559 assert(ValueVT.getVectorNumElements() == 1 &&
560 "Only trivial vector-to-scalar conversions should get here!");
562 ISD::EXTRACT_VECTOR_ELT, DL, PartVT, Val,
563 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
565 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
572 // Handle a multi-element vector.
575 unsigned NumIntermediates;
576 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
578 NumIntermediates, RegisterVT);
579 unsigned NumElements = ValueVT.getVectorNumElements();
581 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
582 NumParts = NumRegs; // Silence a compiler warning.
583 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
585 // Split the vector into intermediate operands.
586 SmallVector<SDValue, 8> Ops(NumIntermediates);
587 for (unsigned i = 0; i != NumIntermediates; ++i) {
588 if (IntermediateVT.isVector())
590 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val,
591 DAG.getConstant(i * (NumElements / NumIntermediates), DL,
592 TLI.getVectorIdxTy(DAG.getDataLayout())));
594 Ops[i] = DAG.getNode(
595 ISD::EXTRACT_VECTOR_ELT, DL, IntermediateVT, Val,
596 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
599 // Split the intermediate operands into legal parts.
600 if (NumParts == NumIntermediates) {
601 // If the register was not expanded, promote or copy the value,
603 for (unsigned i = 0; i != NumParts; ++i)
604 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
605 } else if (NumParts > 0) {
606 // If the intermediate type was expanded, split each the value into
608 assert(NumIntermediates != 0 && "division by zero");
609 assert(NumParts % NumIntermediates == 0 &&
610 "Must expand into a divisible number of parts!");
611 unsigned Factor = NumParts / NumIntermediates;
612 for (unsigned i = 0; i != NumIntermediates; ++i)
613 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
617 RegsForValue::RegsForValue() {}
619 RegsForValue::RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt,
621 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
623 RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &TLI,
624 const DataLayout &DL, unsigned Reg, Type *Ty) {
625 ComputeValueVTs(TLI, DL, Ty, ValueVTs);
627 for (EVT ValueVT : ValueVTs) {
628 unsigned NumRegs = TLI.getNumRegisters(Context, ValueVT);
629 MVT RegisterVT = TLI.getRegisterType(Context, ValueVT);
630 for (unsigned i = 0; i != NumRegs; ++i)
631 Regs.push_back(Reg + i);
632 RegVTs.push_back(RegisterVT);
637 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
638 /// this value and returns the result as a ValueVT value. This uses
639 /// Chain/Flag as the input and updates them for the output Chain/Flag.
640 /// If the Flag pointer is NULL, no flag is used.
641 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
642 FunctionLoweringInfo &FuncInfo,
643 const SDLoc &dl, SDValue &Chain,
644 SDValue *Flag, const Value *V) const {
645 // A Value with type {} or [0 x %t] needs no registers.
646 if (ValueVTs.empty())
649 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
651 // Assemble the legal parts into the final values.
652 SmallVector<SDValue, 4> Values(ValueVTs.size());
653 SmallVector<SDValue, 8> Parts;
654 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
655 // Copy the legal parts from the registers.
656 EVT ValueVT = ValueVTs[Value];
657 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
658 MVT RegisterVT = RegVTs[Value];
660 Parts.resize(NumRegs);
661 for (unsigned i = 0; i != NumRegs; ++i) {
664 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
666 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
667 *Flag = P.getValue(2);
670 Chain = P.getValue(1);
673 // If the source register was virtual and if we know something about it,
674 // add an assert node.
675 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
676 !RegisterVT.isInteger() || RegisterVT.isVector())
679 const FunctionLoweringInfo::LiveOutInfo *LOI =
680 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
684 unsigned RegSize = RegisterVT.getSizeInBits();
685 unsigned NumSignBits = LOI->NumSignBits;
686 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
688 if (NumZeroBits == RegSize) {
689 // The current value is a zero.
690 // Explicitly express that as it would be easier for
691 // optimizations to kick in.
692 Parts[i] = DAG.getConstant(0, dl, RegisterVT);
696 // FIXME: We capture more information than the dag can represent. For
697 // now, just use the tightest assertzext/assertsext possible.
699 EVT FromVT(MVT::Other);
700 if (NumSignBits == RegSize) {
701 isSExt = true; // ASSERT SEXT 1
703 } else if (NumZeroBits >= RegSize - 1) {
704 isSExt = false; // ASSERT ZEXT 1
706 } else if (NumSignBits > RegSize - 8) {
707 isSExt = true; // ASSERT SEXT 8
709 } else if (NumZeroBits >= RegSize - 8) {
710 isSExt = false; // ASSERT ZEXT 8
712 } else if (NumSignBits > RegSize - 16) {
713 isSExt = true; // ASSERT SEXT 16
715 } else if (NumZeroBits >= RegSize - 16) {
716 isSExt = false; // ASSERT ZEXT 16
718 } else if (NumSignBits > RegSize - 32) {
719 isSExt = true; // ASSERT SEXT 32
721 } else if (NumZeroBits >= RegSize - 32) {
722 isSExt = false; // ASSERT ZEXT 32
727 // Add an assertion node.
728 assert(FromVT != MVT::Other);
729 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
730 RegisterVT, P, DAG.getValueType(FromVT));
733 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
734 NumRegs, RegisterVT, ValueVT, V);
739 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
742 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
743 /// specified value into the registers specified by this object. This uses
744 /// Chain/Flag as the input and updates them for the output Chain/Flag.
745 /// If the Flag pointer is NULL, no flag is used.
746 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG,
747 const SDLoc &dl, SDValue &Chain, SDValue *Flag,
749 ISD::NodeType PreferredExtendType) const {
750 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
751 ISD::NodeType ExtendKind = PreferredExtendType;
753 // Get the list of the values's legal parts.
754 unsigned NumRegs = Regs.size();
755 SmallVector<SDValue, 8> Parts(NumRegs);
756 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
757 EVT ValueVT = ValueVTs[Value];
758 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
759 MVT RegisterVT = RegVTs[Value];
761 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
762 ExtendKind = ISD::ZERO_EXTEND;
764 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
765 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
769 // Copy the parts into the registers.
770 SmallVector<SDValue, 8> Chains(NumRegs);
771 for (unsigned i = 0; i != NumRegs; ++i) {
774 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
776 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
777 *Flag = Part.getValue(1);
780 Chains[i] = Part.getValue(0);
783 if (NumRegs == 1 || Flag)
784 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
785 // flagged to it. That is the CopyToReg nodes and the user are considered
786 // a single scheduling unit. If we create a TokenFactor and return it as
787 // chain, then the TokenFactor is both a predecessor (operand) of the
788 // user as well as a successor (the TF operands are flagged to the user).
789 // c1, f1 = CopyToReg
790 // c2, f2 = CopyToReg
791 // c3 = TokenFactor c1, c2
794 Chain = Chains[NumRegs-1];
796 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
799 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
800 /// operand list. This adds the code marker and includes the number of
801 /// values added into it.
802 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
803 unsigned MatchingIdx, const SDLoc &dl,
805 std::vector<SDValue> &Ops) const {
806 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
808 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
810 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
811 else if (!Regs.empty() &&
812 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
813 // Put the register class of the virtual registers in the flag word. That
814 // way, later passes can recompute register class constraints for inline
815 // assembly as well as normal instructions.
816 // Don't do this for tied operands that can use the regclass information
818 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
819 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
820 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
823 SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32);
826 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
827 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
828 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
829 MVT RegisterVT = RegVTs[Value];
830 for (unsigned i = 0; i != NumRegs; ++i) {
831 assert(Reg < Regs.size() && "Mismatch in # registers expected");
832 unsigned TheReg = Regs[Reg++];
833 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
835 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
836 // If we clobbered the stack pointer, MFI should know about it.
837 assert(DAG.getMachineFunction().getFrameInfo().hasOpaqueSPAdjustment());
843 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
844 const TargetLibraryInfo *li) {
848 DL = &DAG.getDataLayout();
849 Context = DAG.getContext();
850 LPadToCallSiteMap.clear();
853 /// clear - Clear out the current SelectionDAG and the associated
854 /// state and prepare this SelectionDAGBuilder object to be used
855 /// for a new block. This doesn't clear out information about
856 /// additional blocks that are needed to complete switch lowering
857 /// or PHI node updating; that information is cleared out as it is
859 void SelectionDAGBuilder::clear() {
861 UnusedArgNodeMap.clear();
862 PendingLoads.clear();
863 PendingExports.clear();
866 SDNodeOrder = LowestSDNodeOrder;
867 StatepointLowering.clear();
870 /// clearDanglingDebugInfo - Clear the dangling debug information
871 /// map. This function is separated from the clear so that debug
872 /// information that is dangling in a basic block can be properly
873 /// resolved in a different basic block. This allows the
874 /// SelectionDAG to resolve dangling debug information attached
876 void SelectionDAGBuilder::clearDanglingDebugInfo() {
877 DanglingDebugInfoMap.clear();
880 /// getRoot - Return the current virtual root of the Selection DAG,
881 /// flushing any PendingLoad items. This must be done before emitting
882 /// a store or any other node that may need to be ordered after any
883 /// prior load instructions.
885 SDValue SelectionDAGBuilder::getRoot() {
886 if (PendingLoads.empty())
887 return DAG.getRoot();
889 if (PendingLoads.size() == 1) {
890 SDValue Root = PendingLoads[0];
892 PendingLoads.clear();
896 // Otherwise, we have to make a token factor node.
897 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
899 PendingLoads.clear();
904 /// getControlRoot - Similar to getRoot, but instead of flushing all the
905 /// PendingLoad items, flush all the PendingExports items. It is necessary
906 /// to do this before emitting a terminator instruction.
908 SDValue SelectionDAGBuilder::getControlRoot() {
909 SDValue Root = DAG.getRoot();
911 if (PendingExports.empty())
914 // Turn all of the CopyToReg chains into one factored node.
915 if (Root.getOpcode() != ISD::EntryToken) {
916 unsigned i = 0, e = PendingExports.size();
917 for (; i != e; ++i) {
918 assert(PendingExports[i].getNode()->getNumOperands() > 1);
919 if (PendingExports[i].getNode()->getOperand(0) == Root)
920 break; // Don't add the root if we already indirectly depend on it.
924 PendingExports.push_back(Root);
927 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
929 PendingExports.clear();
934 void SelectionDAGBuilder::visit(const Instruction &I) {
935 // Set up outgoing PHI node register values before emitting the terminator.
936 if (isa<TerminatorInst>(&I)) {
937 HandlePHINodesInSuccessorBlocks(I.getParent());
944 visit(I.getOpcode(), I);
946 if (!isa<TerminatorInst>(&I) && !HasTailCall &&
947 !isStatepoint(&I)) // statepoints handle their exports internally
948 CopyToExportRegsIfNeeded(&I);
953 void SelectionDAGBuilder::visitPHI(const PHINode &) {
954 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
957 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
958 // Note: this doesn't use InstVisitor, because it has to work with
959 // ConstantExpr's in addition to instructions.
961 default: llvm_unreachable("Unknown instruction type encountered!");
962 // Build the switch statement using the Instruction.def file.
963 #define HANDLE_INST(NUM, OPCODE, CLASS) \
964 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
965 #include "llvm/IR/Instruction.def"
969 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
970 // generate the debug data structures now that we've seen its definition.
971 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
973 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
975 const DbgValueInst *DI = DDI.getDI();
976 DebugLoc dl = DDI.getdl();
977 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
978 DILocalVariable *Variable = DI->getVariable();
979 DIExpression *Expr = DI->getExpression();
980 assert(Variable->isValidLocationForIntrinsic(dl) &&
981 "Expected inlined-at fields to agree");
982 uint64_t Offset = DI->getOffset();
985 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, Offset, false,
987 SDV = getDbgValue(Val, Variable, Expr, Offset, dl, DbgSDNodeOrder);
988 DAG.AddDbgValue(SDV, Val.getNode(), false);
991 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
992 DanglingDebugInfoMap[V] = DanglingDebugInfo();
996 /// getCopyFromRegs - If there was virtual register allocated for the value V
997 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
998 SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
999 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
1002 if (It != FuncInfo.ValueMap.end()) {
1003 unsigned InReg = It->second;
1004 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(),
1005 DAG.getDataLayout(), InReg, Ty);
1006 SDValue Chain = DAG.getEntryNode();
1007 Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1008 resolveDanglingDebugInfo(V, Result);
1014 /// getValue - Return an SDValue for the given Value.
1015 SDValue SelectionDAGBuilder::getValue(const Value *V) {
1016 // If we already have an SDValue for this value, use it. It's important
1017 // to do this first, so that we don't create a CopyFromReg if we already
1018 // have a regular SDValue.
1019 SDValue &N = NodeMap[V];
1020 if (N.getNode()) return N;
1022 // If there's a virtual register allocated and initialized for this
1024 if (SDValue copyFromReg = getCopyFromRegs(V, V->getType()))
1027 // Otherwise create a new SDValue and remember it.
1028 SDValue Val = getValueImpl(V);
1030 resolveDanglingDebugInfo(V, Val);
1034 // Return true if SDValue exists for the given Value
1035 bool SelectionDAGBuilder::findValue(const Value *V) const {
1036 return (NodeMap.find(V) != NodeMap.end()) ||
1037 (FuncInfo.ValueMap.find(V) != FuncInfo.ValueMap.end());
1040 /// getNonRegisterValue - Return an SDValue for the given Value, but
1041 /// don't look in FuncInfo.ValueMap for a virtual register.
1042 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1043 // If we already have an SDValue for this value, use it.
1044 SDValue &N = NodeMap[V];
1046 if (isa<ConstantSDNode>(N) || isa<ConstantFPSDNode>(N)) {
1047 // Remove the debug location from the node as the node is about to be used
1048 // in a location which may differ from the original debug location. This
1049 // is relevant to Constant and ConstantFP nodes because they can appear
1050 // as constant expressions inside PHI nodes.
1051 N->setDebugLoc(DebugLoc());
1056 // Otherwise create a new SDValue and remember it.
1057 SDValue Val = getValueImpl(V);
1059 resolveDanglingDebugInfo(V, Val);
1063 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1064 /// Create an SDValue for the given value.
1065 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1066 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1068 if (const Constant *C = dyn_cast<Constant>(V)) {
1069 EVT VT = TLI.getValueType(DAG.getDataLayout(), V->getType(), true);
1071 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1072 return DAG.getConstant(*CI, getCurSDLoc(), VT);
1074 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1075 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1077 if (isa<ConstantPointerNull>(C)) {
1078 unsigned AS = V->getType()->getPointerAddressSpace();
1079 return DAG.getConstant(0, getCurSDLoc(),
1080 TLI.getPointerTy(DAG.getDataLayout(), AS));
1083 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1084 return DAG.getConstantFP(*CFP, getCurSDLoc(), VT);
1086 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1087 return DAG.getUNDEF(VT);
1089 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1090 visit(CE->getOpcode(), *CE);
1091 SDValue N1 = NodeMap[V];
1092 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1096 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1097 SmallVector<SDValue, 4> Constants;
1098 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1100 SDNode *Val = getValue(*OI).getNode();
1101 // If the operand is an empty aggregate, there are no values.
1103 // Add each leaf value from the operand to the Constants list
1104 // to form a flattened list of all the values.
1105 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1106 Constants.push_back(SDValue(Val, i));
1109 return DAG.getMergeValues(Constants, getCurSDLoc());
1112 if (const ConstantDataSequential *CDS =
1113 dyn_cast<ConstantDataSequential>(C)) {
1114 SmallVector<SDValue, 4> Ops;
1115 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1116 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1117 // Add each leaf value from the operand to the Constants list
1118 // to form a flattened list of all the values.
1119 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1120 Ops.push_back(SDValue(Val, i));
1123 if (isa<ArrayType>(CDS->getType()))
1124 return DAG.getMergeValues(Ops, getCurSDLoc());
1125 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1129 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1130 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1131 "Unknown struct or array constant!");
1133 SmallVector<EVT, 4> ValueVTs;
1134 ComputeValueVTs(TLI, DAG.getDataLayout(), C->getType(), ValueVTs);
1135 unsigned NumElts = ValueVTs.size();
1137 return SDValue(); // empty struct
1138 SmallVector<SDValue, 4> Constants(NumElts);
1139 for (unsigned i = 0; i != NumElts; ++i) {
1140 EVT EltVT = ValueVTs[i];
1141 if (isa<UndefValue>(C))
1142 Constants[i] = DAG.getUNDEF(EltVT);
1143 else if (EltVT.isFloatingPoint())
1144 Constants[i] = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1146 Constants[i] = DAG.getConstant(0, getCurSDLoc(), EltVT);
1149 return DAG.getMergeValues(Constants, getCurSDLoc());
1152 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1153 return DAG.getBlockAddress(BA, VT);
1155 VectorType *VecTy = cast<VectorType>(V->getType());
1156 unsigned NumElements = VecTy->getNumElements();
1158 // Now that we know the number and type of the elements, get that number of
1159 // elements into the Ops array based on what kind of constant it is.
1160 SmallVector<SDValue, 16> Ops;
1161 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1162 for (unsigned i = 0; i != NumElements; ++i)
1163 Ops.push_back(getValue(CV->getOperand(i)));
1165 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1167 TLI.getValueType(DAG.getDataLayout(), VecTy->getElementType());
1170 if (EltVT.isFloatingPoint())
1171 Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1173 Op = DAG.getConstant(0, getCurSDLoc(), EltVT);
1174 Ops.assign(NumElements, Op);
1177 // Create a BUILD_VECTOR node.
1178 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1181 // If this is a static alloca, generate it as the frameindex instead of
1183 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1184 DenseMap<const AllocaInst*, int>::iterator SI =
1185 FuncInfo.StaticAllocaMap.find(AI);
1186 if (SI != FuncInfo.StaticAllocaMap.end())
1187 return DAG.getFrameIndex(SI->second,
1188 TLI.getPointerTy(DAG.getDataLayout()));
1191 // If this is an instruction which fast-isel has deferred, select it now.
1192 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1193 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1194 RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg,
1196 SDValue Chain = DAG.getEntryNode();
1197 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1200 llvm_unreachable("Can't get register for value!");
1203 void SelectionDAGBuilder::visitCatchPad(const CatchPadInst &I) {
1204 auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1205 bool IsMSVCCXX = Pers == EHPersonality::MSVC_CXX;
1206 bool IsCoreCLR = Pers == EHPersonality::CoreCLR;
1207 MachineBasicBlock *CatchPadMBB = FuncInfo.MBB;
1208 // In MSVC C++ and CoreCLR, catchblocks are funclets and need prologues.
1209 if (IsMSVCCXX || IsCoreCLR)
1210 CatchPadMBB->setIsEHFuncletEntry();
1212 DAG.setRoot(DAG.getNode(ISD::CATCHPAD, getCurSDLoc(), MVT::Other, getControlRoot()));
1215 void SelectionDAGBuilder::visitCatchRet(const CatchReturnInst &I) {
1216 // Update machine-CFG edge.
1217 MachineBasicBlock *TargetMBB = FuncInfo.MBBMap[I.getSuccessor()];
1218 FuncInfo.MBB->addSuccessor(TargetMBB);
1220 auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1221 bool IsSEH = isAsynchronousEHPersonality(Pers);
1223 // If this is not a fall-through branch or optimizations are switched off,
1225 if (TargetMBB != NextBlock(FuncInfo.MBB) ||
1226 TM.getOptLevel() == CodeGenOpt::None)
1227 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
1228 getControlRoot(), DAG.getBasicBlock(TargetMBB)));
1232 // Figure out the funclet membership for the catchret's successor.
1233 // This will be used by the FuncletLayout pass to determine how to order the
1235 // A 'catchret' returns to the outer scope's color.
1236 Value *ParentPad = I.getCatchSwitchParentPad();
1237 const BasicBlock *SuccessorColor;
1238 if (isa<ConstantTokenNone>(ParentPad))
1239 SuccessorColor = &FuncInfo.Fn->getEntryBlock();
1241 SuccessorColor = cast<Instruction>(ParentPad)->getParent();
1242 assert(SuccessorColor && "No parent funclet for catchret!");
1243 MachineBasicBlock *SuccessorColorMBB = FuncInfo.MBBMap[SuccessorColor];
1244 assert(SuccessorColorMBB && "No MBB for SuccessorColor!");
1246 // Create the terminator node.
1247 SDValue Ret = DAG.getNode(ISD::CATCHRET, getCurSDLoc(), MVT::Other,
1248 getControlRoot(), DAG.getBasicBlock(TargetMBB),
1249 DAG.getBasicBlock(SuccessorColorMBB));
1253 void SelectionDAGBuilder::visitCleanupPad(const CleanupPadInst &CPI) {
1254 // Don't emit any special code for the cleanuppad instruction. It just marks
1255 // the start of a funclet.
1256 FuncInfo.MBB->setIsEHFuncletEntry();
1257 FuncInfo.MBB->setIsCleanupFuncletEntry();
1260 /// When an invoke or a cleanupret unwinds to the next EH pad, there are
1261 /// many places it could ultimately go. In the IR, we have a single unwind
1262 /// destination, but in the machine CFG, we enumerate all the possible blocks.
1263 /// This function skips over imaginary basic blocks that hold catchswitch
1264 /// instructions, and finds all the "real" machine
1265 /// basic block destinations. As those destinations may not be successors of
1266 /// EHPadBB, here we also calculate the edge probability to those destinations.
1267 /// The passed-in Prob is the edge probability to EHPadBB.
1268 static void findUnwindDestinations(
1269 FunctionLoweringInfo &FuncInfo, const BasicBlock *EHPadBB,
1270 BranchProbability Prob,
1271 SmallVectorImpl<std::pair<MachineBasicBlock *, BranchProbability>>
1273 EHPersonality Personality =
1274 classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1275 bool IsMSVCCXX = Personality == EHPersonality::MSVC_CXX;
1276 bool IsCoreCLR = Personality == EHPersonality::CoreCLR;
1279 const Instruction *Pad = EHPadBB->getFirstNonPHI();
1280 BasicBlock *NewEHPadBB = nullptr;
1281 if (isa<LandingPadInst>(Pad)) {
1282 // Stop on landingpads. They are not funclets.
1283 UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob);
1285 } else if (isa<CleanupPadInst>(Pad)) {
1286 // Stop on cleanup pads. Cleanups are always funclet entries for all known
1288 UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob);
1289 UnwindDests.back().first->setIsEHFuncletEntry();
1291 } else if (auto *CatchSwitch = dyn_cast<CatchSwitchInst>(Pad)) {
1292 // Add the catchpad handlers to the possible destinations.
1293 for (const BasicBlock *CatchPadBB : CatchSwitch->handlers()) {
1294 UnwindDests.emplace_back(FuncInfo.MBBMap[CatchPadBB], Prob);
1295 // For MSVC++ and the CLR, catchblocks are funclets and need prologues.
1296 if (IsMSVCCXX || IsCoreCLR)
1297 UnwindDests.back().first->setIsEHFuncletEntry();
1299 NewEHPadBB = CatchSwitch->getUnwindDest();
1304 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1305 if (BPI && NewEHPadBB)
1306 Prob *= BPI->getEdgeProbability(EHPadBB, NewEHPadBB);
1307 EHPadBB = NewEHPadBB;
1311 void SelectionDAGBuilder::visitCleanupRet(const CleanupReturnInst &I) {
1312 // Update successor info.
1313 SmallVector<std::pair<MachineBasicBlock *, BranchProbability>, 1> UnwindDests;
1314 auto UnwindDest = I.getUnwindDest();
1315 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1316 BranchProbability UnwindDestProb =
1318 ? BPI->getEdgeProbability(FuncInfo.MBB->getBasicBlock(), UnwindDest)
1319 : BranchProbability::getZero();
1320 findUnwindDestinations(FuncInfo, UnwindDest, UnwindDestProb, UnwindDests);
1321 for (auto &UnwindDest : UnwindDests) {
1322 UnwindDest.first->setIsEHPad();
1323 addSuccessorWithProb(FuncInfo.MBB, UnwindDest.first, UnwindDest.second);
1325 FuncInfo.MBB->normalizeSuccProbs();
1327 // Create the terminator node.
1329 DAG.getNode(ISD::CLEANUPRET, getCurSDLoc(), MVT::Other, getControlRoot());
1333 void SelectionDAGBuilder::visitCatchSwitch(const CatchSwitchInst &CSI) {
1334 report_fatal_error("visitCatchSwitch not yet implemented!");
1337 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1338 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1339 auto &DL = DAG.getDataLayout();
1340 SDValue Chain = getControlRoot();
1341 SmallVector<ISD::OutputArg, 8> Outs;
1342 SmallVector<SDValue, 8> OutVals;
1344 // Calls to @llvm.experimental.deoptimize don't generate a return value, so
1347 // %val = call <ty> @llvm.experimental.deoptimize()
1351 if (I.getParent()->getTerminatingDeoptimizeCall()) {
1352 LowerDeoptimizingReturn();
1356 if (!FuncInfo.CanLowerReturn) {
1357 unsigned DemoteReg = FuncInfo.DemoteRegister;
1358 const Function *F = I.getParent()->getParent();
1360 // Emit a store of the return value through the virtual register.
1361 // Leave Outs empty so that LowerReturn won't try to load return
1362 // registers the usual way.
1363 SmallVector<EVT, 1> PtrValueVTs;
1364 ComputeValueVTs(TLI, DL, PointerType::getUnqual(F->getReturnType()),
1367 SDValue RetPtr = DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
1368 DemoteReg, PtrValueVTs[0]);
1369 SDValue RetOp = getValue(I.getOperand(0));
1371 SmallVector<EVT, 4> ValueVTs;
1372 SmallVector<uint64_t, 4> Offsets;
1373 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1374 unsigned NumValues = ValueVTs.size();
1376 // An aggregate return value cannot wrap around the address space, so
1377 // offsets to its parts don't wrap either.
1379 Flags.setNoUnsignedWrap(true);
1381 SmallVector<SDValue, 4> Chains(NumValues);
1382 for (unsigned i = 0; i != NumValues; ++i) {
1383 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1384 RetPtr.getValueType(), RetPtr,
1385 DAG.getIntPtrConstant(Offsets[i],
1388 Chains[i] = DAG.getStore(Chain, getCurSDLoc(),
1389 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1390 // FIXME: better loc info would be nice.
1391 Add, MachinePointerInfo());
1394 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1395 MVT::Other, Chains);
1396 } else if (I.getNumOperands() != 0) {
1397 SmallVector<EVT, 4> ValueVTs;
1398 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs);
1399 unsigned NumValues = ValueVTs.size();
1401 SDValue RetOp = getValue(I.getOperand(0));
1403 const Function *F = I.getParent()->getParent();
1405 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1406 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1408 ExtendKind = ISD::SIGN_EXTEND;
1409 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1411 ExtendKind = ISD::ZERO_EXTEND;
1413 LLVMContext &Context = F->getContext();
1414 bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1417 for (unsigned j = 0; j != NumValues; ++j) {
1418 EVT VT = ValueVTs[j];
1420 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1421 VT = TLI.getTypeForExtReturn(Context, VT, ExtendKind);
1423 unsigned NumParts = TLI.getNumRegisters(Context, VT);
1424 MVT PartVT = TLI.getRegisterType(Context, VT);
1425 SmallVector<SDValue, 4> Parts(NumParts);
1426 getCopyToParts(DAG, getCurSDLoc(),
1427 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1428 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1430 // 'inreg' on function refers to return value
1431 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1435 // Propagate extension type if any
1436 if (ExtendKind == ISD::SIGN_EXTEND)
1438 else if (ExtendKind == ISD::ZERO_EXTEND)
1441 for (unsigned i = 0; i < NumParts; ++i) {
1442 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1443 VT, /*isfixed=*/true, 0, 0));
1444 OutVals.push_back(Parts[i]);
1450 // Push in swifterror virtual register as the last element of Outs. This makes
1451 // sure swifterror virtual register will be returned in the swifterror
1452 // physical register.
1453 const Function *F = I.getParent()->getParent();
1454 if (TLI.supportSwiftError() &&
1455 F->getAttributes().hasAttrSomewhere(Attribute::SwiftError)) {
1456 assert(FuncInfo.SwiftErrorArg && "Need a swift error argument");
1457 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1458 Flags.setSwiftError();
1459 Outs.push_back(ISD::OutputArg(Flags, EVT(TLI.getPointerTy(DL)) /*vt*/,
1460 EVT(TLI.getPointerTy(DL)) /*argvt*/,
1461 true /*isfixed*/, 1 /*origidx*/,
1463 // Create SDNode for the swifterror virtual register.
1464 OutVals.push_back(DAG.getRegister(FuncInfo.getOrCreateSwiftErrorVReg(
1465 FuncInfo.MBB, FuncInfo.SwiftErrorArg),
1466 EVT(TLI.getPointerTy(DL))));
1469 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1470 CallingConv::ID CallConv =
1471 DAG.getMachineFunction().getFunction()->getCallingConv();
1472 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1473 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1475 // Verify that the target's LowerReturn behaved as expected.
1476 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1477 "LowerReturn didn't return a valid chain!");
1479 // Update the DAG with the new chain value resulting from return lowering.
1483 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1484 /// created for it, emit nodes to copy the value into the virtual
1486 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1488 if (V->getType()->isEmptyTy())
1491 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1492 if (VMI != FuncInfo.ValueMap.end()) {
1493 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1494 CopyValueToVirtualRegister(V, VMI->second);
1498 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1499 /// the current basic block, add it to ValueMap now so that we'll get a
1501 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1502 // No need to export constants.
1503 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1505 // Already exported?
1506 if (FuncInfo.isExportedInst(V)) return;
1508 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1509 CopyValueToVirtualRegister(V, Reg);
1512 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1513 const BasicBlock *FromBB) {
1514 // The operands of the setcc have to be in this block. We don't know
1515 // how to export them from some other block.
1516 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1517 // Can export from current BB.
1518 if (VI->getParent() == FromBB)
1521 // Is already exported, noop.
1522 return FuncInfo.isExportedInst(V);
1525 // If this is an argument, we can export it if the BB is the entry block or
1526 // if it is already exported.
1527 if (isa<Argument>(V)) {
1528 if (FromBB == &FromBB->getParent()->getEntryBlock())
1531 // Otherwise, can only export this if it is already exported.
1532 return FuncInfo.isExportedInst(V);
1535 // Otherwise, constants can always be exported.
1539 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1541 SelectionDAGBuilder::getEdgeProbability(const MachineBasicBlock *Src,
1542 const MachineBasicBlock *Dst) const {
1543 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1544 const BasicBlock *SrcBB = Src->getBasicBlock();
1545 const BasicBlock *DstBB = Dst->getBasicBlock();
1547 // If BPI is not available, set the default probability as 1 / N, where N is
1548 // the number of successors.
1549 auto SuccSize = std::max<uint32_t>(
1550 std::distance(succ_begin(SrcBB), succ_end(SrcBB)), 1);
1551 return BranchProbability(1, SuccSize);
1553 return BPI->getEdgeProbability(SrcBB, DstBB);
1556 void SelectionDAGBuilder::addSuccessorWithProb(MachineBasicBlock *Src,
1557 MachineBasicBlock *Dst,
1558 BranchProbability Prob) {
1560 Src->addSuccessorWithoutProb(Dst);
1562 if (Prob.isUnknown())
1563 Prob = getEdgeProbability(Src, Dst);
1564 Src->addSuccessor(Dst, Prob);
1568 static bool InBlock(const Value *V, const BasicBlock *BB) {
1569 if (const Instruction *I = dyn_cast<Instruction>(V))
1570 return I->getParent() == BB;
1574 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1575 /// This function emits a branch and is used at the leaves of an OR or an
1576 /// AND operator tree.
1579 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1580 MachineBasicBlock *TBB,
1581 MachineBasicBlock *FBB,
1582 MachineBasicBlock *CurBB,
1583 MachineBasicBlock *SwitchBB,
1584 BranchProbability TProb,
1585 BranchProbability FProb) {
1586 const BasicBlock *BB = CurBB->getBasicBlock();
1588 // If the leaf of the tree is a comparison, merge the condition into
1590 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1591 // The operands of the cmp have to be in this block. We don't know
1592 // how to export them from some other block. If this is the first block
1593 // of the sequence, no exporting is needed.
1594 if (CurBB == SwitchBB ||
1595 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1596 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1597 ISD::CondCode Condition;
1598 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1599 Condition = getICmpCondCode(IC->getPredicate());
1601 const FCmpInst *FC = cast<FCmpInst>(Cond);
1602 Condition = getFCmpCondCode(FC->getPredicate());
1603 if (TM.Options.NoNaNsFPMath)
1604 Condition = getFCmpCodeWithoutNaN(Condition);
1607 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1608 TBB, FBB, CurBB, TProb, FProb);
1609 SwitchCases.push_back(CB);
1614 // Create a CaseBlock record representing this branch.
1615 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1616 nullptr, TBB, FBB, CurBB, TProb, FProb);
1617 SwitchCases.push_back(CB);
1620 /// FindMergedConditions - If Cond is an expression like
1621 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1622 MachineBasicBlock *TBB,
1623 MachineBasicBlock *FBB,
1624 MachineBasicBlock *CurBB,
1625 MachineBasicBlock *SwitchBB,
1626 Instruction::BinaryOps Opc,
1627 BranchProbability TProb,
1628 BranchProbability FProb) {
1629 // If this node is not part of the or/and tree, emit it as a branch.
1630 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1631 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1632 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1633 BOp->getParent() != CurBB->getBasicBlock() ||
1634 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1635 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1636 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1641 // Create TmpBB after CurBB.
1642 MachineFunction::iterator BBI(CurBB);
1643 MachineFunction &MF = DAG.getMachineFunction();
1644 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1645 CurBB->getParent()->insert(++BBI, TmpBB);
1647 if (Opc == Instruction::Or) {
1648 // Codegen X | Y as:
1657 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1658 // The requirement is that
1659 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1660 // = TrueProb for original BB.
1661 // Assuming the original probabilities are A and B, one choice is to set
1662 // BB1's probabilities to A/2 and A/2+B, and set TmpBB's probabilities to
1663 // A/(1+B) and 2B/(1+B). This choice assumes that
1664 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1665 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1666 // TmpBB, but the math is more complicated.
1668 auto NewTrueProb = TProb / 2;
1669 auto NewFalseProb = TProb / 2 + FProb;
1670 // Emit the LHS condition.
1671 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1672 NewTrueProb, NewFalseProb);
1674 // Normalize A/2 and B to get A/(1+B) and 2B/(1+B).
1675 SmallVector<BranchProbability, 2> Probs{TProb / 2, FProb};
1676 BranchProbability::normalizeProbabilities(Probs.begin(), Probs.end());
1677 // Emit the RHS condition into TmpBB.
1678 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1679 Probs[0], Probs[1]);
1681 assert(Opc == Instruction::And && "Unknown merge op!");
1682 // Codegen X & Y as:
1690 // This requires creation of TmpBB after CurBB.
1692 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1693 // The requirement is that
1694 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1695 // = FalseProb for original BB.
1696 // Assuming the original probabilities are A and B, one choice is to set
1697 // BB1's probabilities to A+B/2 and B/2, and set TmpBB's probabilities to
1698 // 2A/(1+A) and B/(1+A). This choice assumes that FalseProb for BB1 ==
1699 // TrueProb for BB1 * FalseProb for TmpBB.
1701 auto NewTrueProb = TProb + FProb / 2;
1702 auto NewFalseProb = FProb / 2;
1703 // Emit the LHS condition.
1704 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1705 NewTrueProb, NewFalseProb);
1707 // Normalize A and B/2 to get 2A/(1+A) and B/(1+A).
1708 SmallVector<BranchProbability, 2> Probs{TProb, FProb / 2};
1709 BranchProbability::normalizeProbabilities(Probs.begin(), Probs.end());
1710 // Emit the RHS condition into TmpBB.
1711 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1712 Probs[0], Probs[1]);
1716 /// If the set of cases should be emitted as a series of branches, return true.
1717 /// If we should emit this as a bunch of and/or'd together conditions, return
1720 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1721 if (Cases.size() != 2) return true;
1723 // If this is two comparisons of the same values or'd or and'd together, they
1724 // will get folded into a single comparison, so don't emit two blocks.
1725 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1726 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1727 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1728 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1732 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1733 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1734 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1735 Cases[0].CC == Cases[1].CC &&
1736 isa<Constant>(Cases[0].CmpRHS) &&
1737 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1738 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1740 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1747 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1748 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1750 // Update machine-CFG edges.
1751 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1753 if (I.isUnconditional()) {
1754 // Update machine-CFG edges.
1755 BrMBB->addSuccessor(Succ0MBB);
1757 // If this is not a fall-through branch or optimizations are switched off,
1759 if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None)
1760 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1761 MVT::Other, getControlRoot(),
1762 DAG.getBasicBlock(Succ0MBB)));
1767 // If this condition is one of the special cases we handle, do special stuff
1769 const Value *CondVal = I.getCondition();
1770 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1772 // If this is a series of conditions that are or'd or and'd together, emit
1773 // this as a sequence of branches instead of setcc's with and/or operations.
1774 // As long as jumps are not expensive, this should improve performance.
1775 // For example, instead of something like:
1788 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1789 Instruction::BinaryOps Opcode = BOp->getOpcode();
1790 if (!DAG.getTargetLoweringInfo().isJumpExpensive() && BOp->hasOneUse() &&
1791 !I.getMetadata(LLVMContext::MD_unpredictable) &&
1792 (Opcode == Instruction::And || Opcode == Instruction::Or)) {
1793 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1795 getEdgeProbability(BrMBB, Succ0MBB),
1796 getEdgeProbability(BrMBB, Succ1MBB));
1797 // If the compares in later blocks need to use values not currently
1798 // exported from this block, export them now. This block should always
1799 // be the first entry.
1800 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1802 // Allow some cases to be rejected.
1803 if (ShouldEmitAsBranches(SwitchCases)) {
1804 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1805 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1806 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1809 // Emit the branch for this block.
1810 visitSwitchCase(SwitchCases[0], BrMBB);
1811 SwitchCases.erase(SwitchCases.begin());
1815 // Okay, we decided not to do this, remove any inserted MBB's and clear
1817 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1818 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1820 SwitchCases.clear();
1824 // Create a CaseBlock record representing this branch.
1825 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1826 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1828 // Use visitSwitchCase to actually insert the fast branch sequence for this
1830 visitSwitchCase(CB, BrMBB);
1833 /// visitSwitchCase - Emits the necessary code to represent a single node in
1834 /// the binary search tree resulting from lowering a switch instruction.
1835 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1836 MachineBasicBlock *SwitchBB) {
1838 SDValue CondLHS = getValue(CB.CmpLHS);
1839 SDLoc dl = getCurSDLoc();
1841 // Build the setcc now.
1843 // Fold "(X == true)" to X and "(X == false)" to !X to
1844 // handle common cases produced by branch lowering.
1845 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1846 CB.CC == ISD::SETEQ)
1848 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1849 CB.CC == ISD::SETEQ) {
1850 SDValue True = DAG.getConstant(1, dl, CondLHS.getValueType());
1851 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1853 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1855 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1857 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1858 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1860 SDValue CmpOp = getValue(CB.CmpMHS);
1861 EVT VT = CmpOp.getValueType();
1863 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1864 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT),
1867 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1868 VT, CmpOp, DAG.getConstant(Low, dl, VT));
1869 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1870 DAG.getConstant(High-Low, dl, VT), ISD::SETULE);
1874 // Update successor info
1875 addSuccessorWithProb(SwitchBB, CB.TrueBB, CB.TrueProb);
1876 // TrueBB and FalseBB are always different unless the incoming IR is
1877 // degenerate. This only happens when running llc on weird IR.
1878 if (CB.TrueBB != CB.FalseBB)
1879 addSuccessorWithProb(SwitchBB, CB.FalseBB, CB.FalseProb);
1880 SwitchBB->normalizeSuccProbs();
1882 // If the lhs block is the next block, invert the condition so that we can
1883 // fall through to the lhs instead of the rhs block.
1884 if (CB.TrueBB == NextBlock(SwitchBB)) {
1885 std::swap(CB.TrueBB, CB.FalseBB);
1886 SDValue True = DAG.getConstant(1, dl, Cond.getValueType());
1887 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1890 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1891 MVT::Other, getControlRoot(), Cond,
1892 DAG.getBasicBlock(CB.TrueBB));
1894 // Insert the false branch. Do this even if it's a fall through branch,
1895 // this makes it easier to do DAG optimizations which require inverting
1896 // the branch condition.
1897 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1898 DAG.getBasicBlock(CB.FalseBB));
1900 DAG.setRoot(BrCond);
1903 /// visitJumpTable - Emit JumpTable node in the current MBB
1904 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1905 // Emit the code for the jump table
1906 assert(JT.Reg != -1U && "Should lower JT Header first!");
1907 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
1908 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1910 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1911 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1912 MVT::Other, Index.getValue(1),
1914 DAG.setRoot(BrJumpTable);
1917 /// visitJumpTableHeader - This function emits necessary code to produce index
1918 /// in the JumpTable from switch case.
1919 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1920 JumpTableHeader &JTH,
1921 MachineBasicBlock *SwitchBB) {
1922 SDLoc dl = getCurSDLoc();
1924 // Subtract the lowest switch case value from the value being switched on and
1925 // conditional branch to default mbb if the result is greater than the
1926 // difference between smallest and largest cases.
1927 SDValue SwitchOp = getValue(JTH.SValue);
1928 EVT VT = SwitchOp.getValueType();
1929 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1930 DAG.getConstant(JTH.First, dl, VT));
1932 // The SDNode we just created, which holds the value being switched on minus
1933 // the smallest case value, needs to be copied to a virtual register so it
1934 // can be used as an index into the jump table in a subsequent basic block.
1935 // This value may be smaller or larger than the target's pointer type, and
1936 // therefore require extension or truncating.
1937 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1938 SwitchOp = DAG.getZExtOrTrunc(Sub, dl, TLI.getPointerTy(DAG.getDataLayout()));
1940 unsigned JumpTableReg =
1941 FuncInfo.CreateReg(TLI.getPointerTy(DAG.getDataLayout()));
1942 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl,
1943 JumpTableReg, SwitchOp);
1944 JT.Reg = JumpTableReg;
1946 // Emit the range check for the jump table, and branch to the default block
1947 // for the switch statement if the value being switched on exceeds the largest
1948 // case in the switch.
1949 SDValue CMP = DAG.getSetCC(
1950 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1951 Sub.getValueType()),
1952 Sub, DAG.getConstant(JTH.Last - JTH.First, dl, VT), ISD::SETUGT);
1954 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1955 MVT::Other, CopyTo, CMP,
1956 DAG.getBasicBlock(JT.Default));
1958 // Avoid emitting unnecessary branches to the next block.
1959 if (JT.MBB != NextBlock(SwitchBB))
1960 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1961 DAG.getBasicBlock(JT.MBB));
1963 DAG.setRoot(BrCond);
1966 /// Create a LOAD_STACK_GUARD node, and let it carry the target specific global
1967 /// variable if there exists one.
1968 static SDValue getLoadStackGuard(SelectionDAG &DAG, const SDLoc &DL,
1970 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1971 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
1972 MachineFunction &MF = DAG.getMachineFunction();
1973 Value *Global = TLI.getSDagStackGuard(*MF.getFunction()->getParent());
1974 MachineSDNode *Node =
1975 DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD, DL, PtrTy, Chain);
1977 MachinePointerInfo MPInfo(Global);
1978 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
1979 auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant |
1980 MachineMemOperand::MODereferenceable;
1981 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags, PtrTy.getSizeInBits() / 8,
1982 DAG.getEVTAlignment(PtrTy));
1983 Node->setMemRefs(MemRefs, MemRefs + 1);
1985 return SDValue(Node, 0);
1988 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1989 /// tail spliced into a stack protector check success bb.
1991 /// For a high level explanation of how this fits into the stack protector
1992 /// generation see the comment on the declaration of class
1993 /// StackProtectorDescriptor.
1994 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1995 MachineBasicBlock *ParentBB) {
1997 // First create the loads to the guard/stack slot for the comparison.
1998 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1999 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
2001 MachineFrameInfo &MFI = ParentBB->getParent()->getFrameInfo();
2002 int FI = MFI.getStackProtectorIndex();
2005 SDLoc dl = getCurSDLoc();
2006 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
2007 const Module &M = *ParentBB->getParent()->getFunction()->getParent();
2008 unsigned Align = DL->getPrefTypeAlignment(Type::getInt8PtrTy(M.getContext()));
2010 // Generate code to load the content of the guard slot.
2011 SDValue StackSlot = DAG.getLoad(
2012 PtrTy, dl, DAG.getEntryNode(), StackSlotPtr,
2013 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), Align,
2014 MachineMemOperand::MOVolatile);
2016 // Retrieve guard check function, nullptr if instrumentation is inlined.
2017 if (const Value *GuardCheck = TLI.getSSPStackGuardCheck(M)) {
2018 // The target provides a guard check function to validate the guard value.
2019 // Generate a call to that function with the content of the guard slot as
2021 auto *Fn = cast<Function>(GuardCheck);
2022 FunctionType *FnTy = Fn->getFunctionType();
2023 assert(FnTy->getNumParams() == 1 && "Invalid function signature");
2025 TargetLowering::ArgListTy Args;
2026 TargetLowering::ArgListEntry Entry;
2027 Entry.Node = StackSlot;
2028 Entry.Ty = FnTy->getParamType(0);
2029 if (Fn->hasAttribute(1, Attribute::AttrKind::InReg))
2030 Entry.isInReg = true;
2031 Args.push_back(Entry);
2033 TargetLowering::CallLoweringInfo CLI(DAG);
2034 CLI.setDebugLoc(getCurSDLoc())
2035 .setChain(DAG.getEntryNode())
2036 .setCallee(Fn->getCallingConv(), FnTy->getReturnType(),
2037 getValue(GuardCheck), std::move(Args));
2039 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
2040 DAG.setRoot(Result.second);
2044 // If useLoadStackGuardNode returns true, generate LOAD_STACK_GUARD.
2045 // Otherwise, emit a volatile load to retrieve the stack guard value.
2046 SDValue Chain = DAG.getEntryNode();
2047 if (TLI.useLoadStackGuardNode()) {
2048 Guard = getLoadStackGuard(DAG, dl, Chain);
2050 const Value *IRGuard = TLI.getSDagStackGuard(M);
2051 SDValue GuardPtr = getValue(IRGuard);
2054 DAG.getLoad(PtrTy, dl, Chain, GuardPtr, MachinePointerInfo(IRGuard, 0),
2055 Align, MachineMemOperand::MOVolatile);
2058 // Perform the comparison via a subtract/getsetcc.
2059 EVT VT = Guard.getValueType();
2060 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Guard, StackSlot);
2062 SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(DAG.getDataLayout(),
2064 Sub.getValueType()),
2065 Sub, DAG.getConstant(0, dl, VT), ISD::SETNE);
2067 // If the sub is not 0, then we know the guard/stackslot do not equal, so
2068 // branch to failure MBB.
2069 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
2070 MVT::Other, StackSlot.getOperand(0),
2071 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
2072 // Otherwise branch to success MBB.
2073 SDValue Br = DAG.getNode(ISD::BR, dl,
2075 DAG.getBasicBlock(SPD.getSuccessMBB()));
2080 /// Codegen the failure basic block for a stack protector check.
2082 /// A failure stack protector machine basic block consists simply of a call to
2083 /// __stack_chk_fail().
2085 /// For a high level explanation of how this fits into the stack protector
2086 /// generation see the comment on the declaration of class
2087 /// StackProtectorDescriptor.
2089 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
2090 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2092 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
2093 None, false, getCurSDLoc(), false, false).second;
2097 /// visitBitTestHeader - This function emits necessary code to produce value
2098 /// suitable for "bit tests"
2099 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
2100 MachineBasicBlock *SwitchBB) {
2101 SDLoc dl = getCurSDLoc();
2103 // Subtract the minimum value
2104 SDValue SwitchOp = getValue(B.SValue);
2105 EVT VT = SwitchOp.getValueType();
2106 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
2107 DAG.getConstant(B.First, dl, VT));
2110 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2111 SDValue RangeCmp = DAG.getSetCC(
2112 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
2113 Sub.getValueType()),
2114 Sub, DAG.getConstant(B.Range, dl, VT), ISD::SETUGT);
2116 // Determine the type of the test operands.
2117 bool UsePtrType = false;
2118 if (!TLI.isTypeLegal(VT))
2121 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
2122 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
2123 // Switch table case range are encoded into series of masks.
2124 // Just use pointer type, it's guaranteed to fit.
2130 VT = TLI.getPointerTy(DAG.getDataLayout());
2131 Sub = DAG.getZExtOrTrunc(Sub, dl, VT);
2134 B.RegVT = VT.getSimpleVT();
2135 B.Reg = FuncInfo.CreateReg(B.RegVT);
2136 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub);
2138 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
2140 addSuccessorWithProb(SwitchBB, B.Default, B.DefaultProb);
2141 addSuccessorWithProb(SwitchBB, MBB, B.Prob);
2142 SwitchBB->normalizeSuccProbs();
2144 SDValue BrRange = DAG.getNode(ISD::BRCOND, dl,
2145 MVT::Other, CopyTo, RangeCmp,
2146 DAG.getBasicBlock(B.Default));
2148 // Avoid emitting unnecessary branches to the next block.
2149 if (MBB != NextBlock(SwitchBB))
2150 BrRange = DAG.getNode(ISD::BR, dl, MVT::Other, BrRange,
2151 DAG.getBasicBlock(MBB));
2153 DAG.setRoot(BrRange);
2156 /// visitBitTestCase - this function produces one "bit test"
2157 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
2158 MachineBasicBlock* NextMBB,
2159 BranchProbability BranchProbToNext,
2162 MachineBasicBlock *SwitchBB) {
2163 SDLoc dl = getCurSDLoc();
2165 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT);
2167 unsigned PopCount = countPopulation(B.Mask);
2168 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2169 if (PopCount == 1) {
2170 // Testing for a single bit; just compare the shift count with what it
2171 // would need to be to shift a 1 bit in that position.
2173 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2174 ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT),
2176 } else if (PopCount == BB.Range) {
2177 // There is only one zero bit in the range, test for it directly.
2179 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2180 ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT),
2183 // Make desired shift
2184 SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT,
2185 DAG.getConstant(1, dl, VT), ShiftOp);
2187 // Emit bit tests and jumps
2188 SDValue AndOp = DAG.getNode(ISD::AND, dl,
2189 VT, SwitchVal, DAG.getConstant(B.Mask, dl, VT));
2191 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2192 AndOp, DAG.getConstant(0, dl, VT), ISD::SETNE);
2195 // The branch probability from SwitchBB to B.TargetBB is B.ExtraProb.
2196 addSuccessorWithProb(SwitchBB, B.TargetBB, B.ExtraProb);
2197 // The branch probability from SwitchBB to NextMBB is BranchProbToNext.
2198 addSuccessorWithProb(SwitchBB, NextMBB, BranchProbToNext);
2199 // It is not guaranteed that the sum of B.ExtraProb and BranchProbToNext is
2200 // one as they are relative probabilities (and thus work more like weights),
2201 // and hence we need to normalize them to let the sum of them become one.
2202 SwitchBB->normalizeSuccProbs();
2204 SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl,
2205 MVT::Other, getControlRoot(),
2206 Cmp, DAG.getBasicBlock(B.TargetBB));
2208 // Avoid emitting unnecessary branches to the next block.
2209 if (NextMBB != NextBlock(SwitchBB))
2210 BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd,
2211 DAG.getBasicBlock(NextMBB));
2216 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
2217 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
2219 // Retrieve successors. Look through artificial IR level blocks like
2220 // catchswitch for successors.
2221 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
2222 const BasicBlock *EHPadBB = I.getSuccessor(1);
2224 // Deopt bundles are lowered in LowerCallSiteWithDeoptBundle, and we don't
2225 // have to do anything here to lower funclet bundles.
2226 assert(!I.hasOperandBundlesOtherThan(
2227 {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) &&
2228 "Cannot lower invokes with arbitrary operand bundles yet!");
2230 const Value *Callee(I.getCalledValue());
2231 const Function *Fn = dyn_cast<Function>(Callee);
2232 if (isa<InlineAsm>(Callee))
2234 else if (Fn && Fn->isIntrinsic()) {
2235 switch (Fn->getIntrinsicID()) {
2237 llvm_unreachable("Cannot invoke this intrinsic");
2238 case Intrinsic::donothing:
2239 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2241 case Intrinsic::experimental_patchpoint_void:
2242 case Intrinsic::experimental_patchpoint_i64:
2243 visitPatchpoint(&I, EHPadBB);
2245 case Intrinsic::experimental_gc_statepoint:
2246 LowerStatepoint(ImmutableStatepoint(&I), EHPadBB);
2249 } else if (I.countOperandBundlesOfType(LLVMContext::OB_deopt)) {
2250 // Currently we do not lower any intrinsic calls with deopt operand bundles.
2251 // Eventually we will support lowering the @llvm.experimental.deoptimize
2252 // intrinsic, and right now there are no plans to support other intrinsics
2253 // with deopt state.
2254 LowerCallSiteWithDeoptBundle(&I, getValue(Callee), EHPadBB);
2256 LowerCallTo(&I, getValue(Callee), false, EHPadBB);
2259 // If the value of the invoke is used outside of its defining block, make it
2260 // available as a virtual register.
2261 // We already took care of the exported value for the statepoint instruction
2262 // during call to the LowerStatepoint.
2263 if (!isStatepoint(I)) {
2264 CopyToExportRegsIfNeeded(&I);
2267 SmallVector<std::pair<MachineBasicBlock *, BranchProbability>, 1> UnwindDests;
2268 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2269 BranchProbability EHPadBBProb =
2270 BPI ? BPI->getEdgeProbability(InvokeMBB->getBasicBlock(), EHPadBB)
2271 : BranchProbability::getZero();
2272 findUnwindDestinations(FuncInfo, EHPadBB, EHPadBBProb, UnwindDests);
2274 // Update successor info.
2275 addSuccessorWithProb(InvokeMBB, Return);
2276 for (auto &UnwindDest : UnwindDests) {
2277 UnwindDest.first->setIsEHPad();
2278 addSuccessorWithProb(InvokeMBB, UnwindDest.first, UnwindDest.second);
2280 InvokeMBB->normalizeSuccProbs();
2282 // Drop into normal successor.
2283 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2284 MVT::Other, getControlRoot(),
2285 DAG.getBasicBlock(Return)));
2288 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2289 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2292 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2293 assert(FuncInfo.MBB->isEHPad() &&
2294 "Call to landingpad not in landing pad!");
2296 MachineBasicBlock *MBB = FuncInfo.MBB;
2297 addLandingPadInfo(LP, *MBB);
2299 // If there aren't registers to copy the values into (e.g., during SjLj
2300 // exceptions), then don't bother to create these DAG nodes.
2301 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2302 const Constant *PersonalityFn = FuncInfo.Fn->getPersonalityFn();
2303 if (TLI.getExceptionPointerRegister(PersonalityFn) == 0 &&
2304 TLI.getExceptionSelectorRegister(PersonalityFn) == 0)
2307 // If landingpad's return type is token type, we don't create DAG nodes
2308 // for its exception pointer and selector value. The extraction of exception
2309 // pointer or selector value from token type landingpads is not currently
2311 if (LP.getType()->isTokenTy())
2314 SmallVector<EVT, 2> ValueVTs;
2315 SDLoc dl = getCurSDLoc();
2316 ComputeValueVTs(TLI, DAG.getDataLayout(), LP.getType(), ValueVTs);
2317 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2319 // Get the two live-in registers as SDValues. The physregs have already been
2320 // copied into virtual registers.
2322 if (FuncInfo.ExceptionPointerVirtReg) {
2323 Ops[0] = DAG.getZExtOrTrunc(
2324 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2325 FuncInfo.ExceptionPointerVirtReg,
2326 TLI.getPointerTy(DAG.getDataLayout())),
2329 Ops[0] = DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout()));
2331 Ops[1] = DAG.getZExtOrTrunc(
2332 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2333 FuncInfo.ExceptionSelectorVirtReg,
2334 TLI.getPointerTy(DAG.getDataLayout())),
2338 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
2339 DAG.getVTList(ValueVTs), Ops);
2343 void SelectionDAGBuilder::sortAndRangeify(CaseClusterVector &Clusters) {
2345 for (const CaseCluster &CC : Clusters)
2346 assert(CC.Low == CC.High && "Input clusters must be single-case");
2349 std::sort(Clusters.begin(), Clusters.end(),
2350 [](const CaseCluster &a, const CaseCluster &b) {
2351 return a.Low->getValue().slt(b.Low->getValue());
2354 // Merge adjacent clusters with the same destination.
2355 const unsigned N = Clusters.size();
2356 unsigned DstIndex = 0;
2357 for (unsigned SrcIndex = 0; SrcIndex < N; ++SrcIndex) {
2358 CaseCluster &CC = Clusters[SrcIndex];
2359 const ConstantInt *CaseVal = CC.Low;
2360 MachineBasicBlock *Succ = CC.MBB;
2362 if (DstIndex != 0 && Clusters[DstIndex - 1].MBB == Succ &&
2363 (CaseVal->getValue() - Clusters[DstIndex - 1].High->getValue()) == 1) {
2364 // If this case has the same successor and is a neighbour, merge it into
2365 // the previous cluster.
2366 Clusters[DstIndex - 1].High = CaseVal;
2367 Clusters[DstIndex - 1].Prob += CC.Prob;
2369 std::memmove(&Clusters[DstIndex++], &Clusters[SrcIndex],
2370 sizeof(Clusters[SrcIndex]));
2373 Clusters.resize(DstIndex);
2376 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2377 MachineBasicBlock *Last) {
2379 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2380 if (JTCases[i].first.HeaderBB == First)
2381 JTCases[i].first.HeaderBB = Last;
2383 // Update BitTestCases.
2384 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2385 if (BitTestCases[i].Parent == First)
2386 BitTestCases[i].Parent = Last;
2389 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2390 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2392 // Update machine-CFG edges with unique successors.
2393 SmallSet<BasicBlock*, 32> Done;
2394 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2395 BasicBlock *BB = I.getSuccessor(i);
2396 bool Inserted = Done.insert(BB).second;
2400 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2401 addSuccessorWithProb(IndirectBrMBB, Succ);
2403 IndirectBrMBB->normalizeSuccProbs();
2405 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2406 MVT::Other, getControlRoot(),
2407 getValue(I.getAddress())));
2410 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2411 if (DAG.getTarget().Options.TrapUnreachable)
2413 DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2416 void SelectionDAGBuilder::visitFSub(const User &I) {
2417 // -0.0 - X --> fneg
2418 Type *Ty = I.getType();
2419 if (isa<Constant>(I.getOperand(0)) &&
2420 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2421 SDValue Op2 = getValue(I.getOperand(1));
2422 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2423 Op2.getValueType(), Op2));
2427 visitBinary(I, ISD::FSUB);
2430 /// Checks if the given instruction performs a vector reduction, in which case
2431 /// we have the freedom to alter the elements in the result as long as the
2432 /// reduction of them stays unchanged.
2433 static bool isVectorReductionOp(const User *I) {
2434 const Instruction *Inst = dyn_cast<Instruction>(I);
2435 if (!Inst || !Inst->getType()->isVectorTy())
2438 auto OpCode = Inst->getOpcode();
2440 case Instruction::Add:
2441 case Instruction::Mul:
2442 case Instruction::And:
2443 case Instruction::Or:
2444 case Instruction::Xor:
2446 case Instruction::FAdd:
2447 case Instruction::FMul:
2448 if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(Inst))
2449 if (FPOp->getFastMathFlags().unsafeAlgebra())
2456 unsigned ElemNum = Inst->getType()->getVectorNumElements();
2457 unsigned ElemNumToReduce = ElemNum;
2459 // Do DFS search on the def-use chain from the given instruction. We only
2460 // allow four kinds of operations during the search until we reach the
2461 // instruction that extracts the first element from the vector:
2463 // 1. The reduction operation of the same opcode as the given instruction.
2467 // 3. ShuffleVector instruction together with a reduction operation that
2468 // does a partial reduction.
2470 // 4. ExtractElement that extracts the first element from the vector, and we
2471 // stop searching the def-use chain here.
2473 // 3 & 4 above perform a reduction on all elements of the vector. We push defs
2474 // from 1-3 to the stack to continue the DFS. The given instruction is not
2475 // a reduction operation if we meet any other instructions other than those
2478 SmallVector<const User *, 16> UsersToVisit{Inst};
2479 SmallPtrSet<const User *, 16> Visited;
2480 bool ReduxExtracted = false;
2482 while (!UsersToVisit.empty()) {
2483 auto User = UsersToVisit.back();
2484 UsersToVisit.pop_back();
2485 if (!Visited.insert(User).second)
2488 for (const auto &U : User->users()) {
2489 auto Inst = dyn_cast<Instruction>(U);
2493 if (Inst->getOpcode() == OpCode || isa<PHINode>(U)) {
2494 if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(Inst))
2495 if (!isa<PHINode>(FPOp) && !FPOp->getFastMathFlags().unsafeAlgebra())
2497 UsersToVisit.push_back(U);
2498 } else if (const ShuffleVectorInst *ShufInst =
2499 dyn_cast<ShuffleVectorInst>(U)) {
2500 // Detect the following pattern: A ShuffleVector instruction together
2501 // with a reduction that do partial reduction on the first and second
2502 // ElemNumToReduce / 2 elements, and store the result in
2503 // ElemNumToReduce / 2 elements in another vector.
2505 unsigned ResultElements = ShufInst->getType()->getVectorNumElements();
2506 if (ResultElements < ElemNum)
2509 if (ElemNumToReduce == 1)
2511 if (!isa<UndefValue>(U->getOperand(1)))
2513 for (unsigned i = 0; i < ElemNumToReduce / 2; ++i)
2514 if (ShufInst->getMaskValue(i) != int(i + ElemNumToReduce / 2))
2516 for (unsigned i = ElemNumToReduce / 2; i < ElemNum; ++i)
2517 if (ShufInst->getMaskValue(i) != -1)
2520 // There is only one user of this ShuffleVector instruction, which
2521 // must be a reduction operation.
2522 if (!U->hasOneUse())
2525 auto U2 = dyn_cast<Instruction>(*U->user_begin());
2526 if (!U2 || U2->getOpcode() != OpCode)
2529 // Check operands of the reduction operation.
2530 if ((U2->getOperand(0) == U->getOperand(0) && U2->getOperand(1) == U) ||
2531 (U2->getOperand(1) == U->getOperand(0) && U2->getOperand(0) == U)) {
2532 UsersToVisit.push_back(U2);
2533 ElemNumToReduce /= 2;
2536 } else if (isa<ExtractElementInst>(U)) {
2537 // At this moment we should have reduced all elements in the vector.
2538 if (ElemNumToReduce != 1)
2541 const ConstantInt *Val = dyn_cast<ConstantInt>(U->getOperand(1));
2542 if (!Val || Val->getZExtValue() != 0)
2545 ReduxExtracted = true;
2550 return ReduxExtracted;
2553 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2554 SDValue Op1 = getValue(I.getOperand(0));
2555 SDValue Op2 = getValue(I.getOperand(1));
2560 bool vec_redux = false;
2563 if (const OverflowingBinaryOperator *OFBinOp =
2564 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2565 nuw = OFBinOp->hasNoUnsignedWrap();
2566 nsw = OFBinOp->hasNoSignedWrap();
2568 if (const PossiblyExactOperator *ExactOp =
2569 dyn_cast<const PossiblyExactOperator>(&I))
2570 exact = ExactOp->isExact();
2571 if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(&I))
2572 FMF = FPOp->getFastMathFlags();
2574 if (isVectorReductionOp(&I)) {
2576 DEBUG(dbgs() << "Detected a reduction operation:" << I << "\n");
2580 Flags.setExact(exact);
2581 Flags.setNoSignedWrap(nsw);
2582 Flags.setNoUnsignedWrap(nuw);
2583 Flags.setVectorReduction(vec_redux);
2584 if (EnableFMFInDAG) {
2585 Flags.setAllowReciprocal(FMF.allowReciprocal());
2586 Flags.setNoInfs(FMF.noInfs());
2587 Flags.setNoNaNs(FMF.noNaNs());
2588 Flags.setNoSignedZeros(FMF.noSignedZeros());
2589 Flags.setUnsafeAlgebra(FMF.unsafeAlgebra());
2591 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2593 setValue(&I, BinNodeValue);
2596 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2597 SDValue Op1 = getValue(I.getOperand(0));
2598 SDValue Op2 = getValue(I.getOperand(1));
2600 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy(
2601 Op2.getValueType(), DAG.getDataLayout());
2603 // Coerce the shift amount to the right type if we can.
2604 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2605 unsigned ShiftSize = ShiftTy.getSizeInBits();
2606 unsigned Op2Size = Op2.getValueSizeInBits();
2607 SDLoc DL = getCurSDLoc();
2609 // If the operand is smaller than the shift count type, promote it.
2610 if (ShiftSize > Op2Size)
2611 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2613 // If the operand is larger than the shift count type but the shift
2614 // count type has enough bits to represent any shift value, truncate
2615 // it now. This is a common case and it exposes the truncate to
2616 // optimization early.
2617 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueSizeInBits()))
2618 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2619 // Otherwise we'll need to temporarily settle for some other convenient
2620 // type. Type legalization will make adjustments once the shiftee is split.
2622 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2629 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2631 if (const OverflowingBinaryOperator *OFBinOp =
2632 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2633 nuw = OFBinOp->hasNoUnsignedWrap();
2634 nsw = OFBinOp->hasNoSignedWrap();
2636 if (const PossiblyExactOperator *ExactOp =
2637 dyn_cast<const PossiblyExactOperator>(&I))
2638 exact = ExactOp->isExact();
2641 Flags.setExact(exact);
2642 Flags.setNoSignedWrap(nsw);
2643 Flags.setNoUnsignedWrap(nuw);
2644 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2649 void SelectionDAGBuilder::visitSDiv(const User &I) {
2650 SDValue Op1 = getValue(I.getOperand(0));
2651 SDValue Op2 = getValue(I.getOperand(1));
2654 Flags.setExact(isa<PossiblyExactOperator>(&I) &&
2655 cast<PossiblyExactOperator>(&I)->isExact());
2656 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(), Op1,
2660 void SelectionDAGBuilder::visitICmp(const User &I) {
2661 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2662 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2663 predicate = IC->getPredicate();
2664 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2665 predicate = ICmpInst::Predicate(IC->getPredicate());
2666 SDValue Op1 = getValue(I.getOperand(0));
2667 SDValue Op2 = getValue(I.getOperand(1));
2668 ISD::CondCode Opcode = getICmpCondCode(predicate);
2670 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2672 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2675 void SelectionDAGBuilder::visitFCmp(const User &I) {
2676 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2677 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2678 predicate = FC->getPredicate();
2679 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2680 predicate = FCmpInst::Predicate(FC->getPredicate());
2681 SDValue Op1 = getValue(I.getOperand(0));
2682 SDValue Op2 = getValue(I.getOperand(1));
2683 ISD::CondCode Condition = getFCmpCondCode(predicate);
2685 // FIXME: Fcmp instructions have fast-math-flags in IR, so we should use them.
2686 // FIXME: We should propagate the fast-math-flags to the DAG node itself for
2687 // further optimization, but currently FMF is only applicable to binary nodes.
2688 if (TM.Options.NoNaNsFPMath)
2689 Condition = getFCmpCodeWithoutNaN(Condition);
2690 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2692 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2695 // Check if the condition of the select has one use or two users that are both
2696 // selects with the same condition.
2697 static bool hasOnlySelectUsers(const Value *Cond) {
2698 return all_of(Cond->users(), [](const Value *V) {
2699 return isa<SelectInst>(V);
2703 void SelectionDAGBuilder::visitSelect(const User &I) {
2704 SmallVector<EVT, 4> ValueVTs;
2705 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(),
2707 unsigned NumValues = ValueVTs.size();
2708 if (NumValues == 0) return;
2710 SmallVector<SDValue, 4> Values(NumValues);
2711 SDValue Cond = getValue(I.getOperand(0));
2712 SDValue LHSVal = getValue(I.getOperand(1));
2713 SDValue RHSVal = getValue(I.getOperand(2));
2714 auto BaseOps = {Cond};
2715 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2716 ISD::VSELECT : ISD::SELECT;
2718 // Min/max matching is only viable if all output VTs are the same.
2719 if (std::equal(ValueVTs.begin(), ValueVTs.end(), ValueVTs.begin())) {
2720 EVT VT = ValueVTs[0];
2721 LLVMContext &Ctx = *DAG.getContext();
2722 auto &TLI = DAG.getTargetLoweringInfo();
2724 // We care about the legality of the operation after it has been type
2726 while (TLI.getTypeAction(Ctx, VT) != TargetLoweringBase::TypeLegal &&
2727 VT != TLI.getTypeToTransformTo(Ctx, VT))
2728 VT = TLI.getTypeToTransformTo(Ctx, VT);
2730 // If the vselect is legal, assume we want to leave this as a vector setcc +
2731 // vselect. Otherwise, if this is going to be scalarized, we want to see if
2732 // min/max is legal on the scalar type.
2733 bool UseScalarMinMax = VT.isVector() &&
2734 !TLI.isOperationLegalOrCustom(ISD::VSELECT, VT);
2737 auto SPR = matchSelectPattern(const_cast<User*>(&I), LHS, RHS);
2738 ISD::NodeType Opc = ISD::DELETED_NODE;
2739 switch (SPR.Flavor) {
2740 case SPF_UMAX: Opc = ISD::UMAX; break;
2741 case SPF_UMIN: Opc = ISD::UMIN; break;
2742 case SPF_SMAX: Opc = ISD::SMAX; break;
2743 case SPF_SMIN: Opc = ISD::SMIN; break;
2745 switch (SPR.NaNBehavior) {
2746 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2747 case SPNB_RETURNS_NAN: Opc = ISD::FMINNAN; break;
2748 case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break;
2749 case SPNB_RETURNS_ANY: {
2750 if (TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT))
2752 else if (TLI.isOperationLegalOrCustom(ISD::FMINNAN, VT))
2754 else if (UseScalarMinMax)
2755 Opc = TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT.getScalarType()) ?
2756 ISD::FMINNUM : ISD::FMINNAN;
2762 switch (SPR.NaNBehavior) {
2763 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2764 case SPNB_RETURNS_NAN: Opc = ISD::FMAXNAN; break;
2765 case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break;
2766 case SPNB_RETURNS_ANY:
2768 if (TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT))
2770 else if (TLI.isOperationLegalOrCustom(ISD::FMAXNAN, VT))
2772 else if (UseScalarMinMax)
2773 Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT.getScalarType()) ?
2774 ISD::FMAXNUM : ISD::FMAXNAN;
2781 if (Opc != ISD::DELETED_NODE &&
2782 (TLI.isOperationLegalOrCustom(Opc, VT) ||
2784 TLI.isOperationLegalOrCustom(Opc, VT.getScalarType()))) &&
2785 // If the underlying comparison instruction is used by any other
2786 // instruction, the consumed instructions won't be destroyed, so it is
2787 // not profitable to convert to a min/max.
2788 hasOnlySelectUsers(cast<SelectInst>(I).getCondition())) {
2790 LHSVal = getValue(LHS);
2791 RHSVal = getValue(RHS);
2796 for (unsigned i = 0; i != NumValues; ++i) {
2797 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end());
2798 Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i));
2799 Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i));
2800 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2801 LHSVal.getNode()->getValueType(LHSVal.getResNo()+i),
2805 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2806 DAG.getVTList(ValueVTs), Values));
2809 void SelectionDAGBuilder::visitTrunc(const User &I) {
2810 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2811 SDValue N = getValue(I.getOperand(0));
2812 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2814 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2817 void SelectionDAGBuilder::visitZExt(const User &I) {
2818 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2819 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2820 SDValue N = getValue(I.getOperand(0));
2821 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2823 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2826 void SelectionDAGBuilder::visitSExt(const User &I) {
2827 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2828 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2829 SDValue N = getValue(I.getOperand(0));
2830 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2832 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2835 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2836 // FPTrunc is never a no-op cast, no need to check
2837 SDValue N = getValue(I.getOperand(0));
2838 SDLoc dl = getCurSDLoc();
2839 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2840 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2841 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N,
2842 DAG.getTargetConstant(
2843 0, dl, TLI.getPointerTy(DAG.getDataLayout()))));
2846 void SelectionDAGBuilder::visitFPExt(const User &I) {
2847 // FPExt is never a no-op cast, no need to check
2848 SDValue N = getValue(I.getOperand(0));
2849 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2851 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2854 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2855 // FPToUI is never a no-op cast, no need to check
2856 SDValue N = getValue(I.getOperand(0));
2857 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2859 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2862 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2863 // FPToSI is never a no-op cast, no need to check
2864 SDValue N = getValue(I.getOperand(0));
2865 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2867 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2870 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2871 // UIToFP is never a no-op cast, no need to check
2872 SDValue N = getValue(I.getOperand(0));
2873 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2875 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2878 void SelectionDAGBuilder::visitSIToFP(const User &I) {
2879 // SIToFP is never a no-op cast, no need to check
2880 SDValue N = getValue(I.getOperand(0));
2881 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2883 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2886 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2887 // What to do depends on the size of the integer and the size of the pointer.
2888 // We can either truncate, zero extend, or no-op, accordingly.
2889 SDValue N = getValue(I.getOperand(0));
2890 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2892 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2895 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2896 // What to do depends on the size of the integer and the size of the pointer.
2897 // We can either truncate, zero extend, or no-op, accordingly.
2898 SDValue N = getValue(I.getOperand(0));
2899 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2901 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2904 void SelectionDAGBuilder::visitBitCast(const User &I) {
2905 SDValue N = getValue(I.getOperand(0));
2906 SDLoc dl = getCurSDLoc();
2907 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2910 // BitCast assures us that source and destination are the same size so this is
2911 // either a BITCAST or a no-op.
2912 if (DestVT != N.getValueType())
2913 setValue(&I, DAG.getNode(ISD::BITCAST, dl,
2914 DestVT, N)); // convert types.
2915 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
2916 // might fold any kind of constant expression to an integer constant and that
2917 // is not what we are looking for. Only regcognize a bitcast of a genuine
2918 // constant integer as an opaque constant.
2919 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
2920 setValue(&I, DAG.getConstant(C->getValue(), dl, DestVT, /*isTarget=*/false,
2923 setValue(&I, N); // noop cast.
2926 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
2927 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2928 const Value *SV = I.getOperand(0);
2929 SDValue N = getValue(SV);
2930 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2932 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
2933 unsigned DestAS = I.getType()->getPointerAddressSpace();
2935 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
2936 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
2941 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2942 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2943 SDValue InVec = getValue(I.getOperand(0));
2944 SDValue InVal = getValue(I.getOperand(1));
2945 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)), getCurSDLoc(),
2946 TLI.getVectorIdxTy(DAG.getDataLayout()));
2947 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
2948 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2949 InVec, InVal, InIdx));
2952 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2953 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2954 SDValue InVec = getValue(I.getOperand(0));
2955 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), getCurSDLoc(),
2956 TLI.getVectorIdxTy(DAG.getDataLayout()));
2957 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
2958 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2962 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2963 SDValue Src1 = getValue(I.getOperand(0));
2964 SDValue Src2 = getValue(I.getOperand(1));
2965 SDLoc DL = getCurSDLoc();
2967 SmallVector<int, 8> Mask;
2968 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2969 unsigned MaskNumElts = Mask.size();
2971 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2972 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2973 EVT SrcVT = Src1.getValueType();
2974 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2976 if (SrcNumElts == MaskNumElts) {
2977 setValue(&I, DAG.getVectorShuffle(VT, DL, Src1, Src2, Mask));
2981 // Normalize the shuffle vector since mask and vector length don't match.
2982 if (SrcNumElts < MaskNumElts) {
2983 // Mask is longer than the source vectors. We can use concatenate vector to
2984 // make the mask and vectors lengths match.
2986 if (MaskNumElts % SrcNumElts == 0) {
2987 // Mask length is a multiple of the source vector length.
2988 // Check if the shuffle is some kind of concatenation of the input
2990 unsigned NumConcat = MaskNumElts / SrcNumElts;
2991 bool IsConcat = true;
2992 SmallVector<int, 8> ConcatSrcs(NumConcat, -1);
2993 for (unsigned i = 0; i != MaskNumElts; ++i) {
2997 // Ensure the indices in each SrcVT sized piece are sequential and that
2998 // the same source is used for the whole piece.
2999 if ((Idx % SrcNumElts != (i % SrcNumElts)) ||
3000 (ConcatSrcs[i / SrcNumElts] >= 0 &&
3001 ConcatSrcs[i / SrcNumElts] != (int)(Idx / SrcNumElts))) {
3005 // Remember which source this index came from.
3006 ConcatSrcs[i / SrcNumElts] = Idx / SrcNumElts;
3009 // The shuffle is concatenating multiple vectors together. Just emit
3010 // a CONCAT_VECTORS operation.
3012 SmallVector<SDValue, 8> ConcatOps;
3013 for (auto Src : ConcatSrcs) {
3015 ConcatOps.push_back(DAG.getUNDEF(SrcVT));
3017 ConcatOps.push_back(Src1);
3019 ConcatOps.push_back(Src2);
3021 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ConcatOps));
3026 unsigned PaddedMaskNumElts = alignTo(MaskNumElts, SrcNumElts);
3027 unsigned NumConcat = PaddedMaskNumElts / SrcNumElts;
3028 EVT PaddedVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(),
3031 // Pad both vectors with undefs to make them the same length as the mask.
3032 SDValue UndefVal = DAG.getUNDEF(SrcVT);
3034 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
3035 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
3039 Src1 = Src1.isUndef()
3040 ? DAG.getUNDEF(PaddedVT)
3041 : DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps1);
3042 Src2 = Src2.isUndef()
3043 ? DAG.getUNDEF(PaddedVT)
3044 : DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps2);
3046 // Readjust mask for new input vector length.
3047 SmallVector<int, 8> MappedOps(PaddedMaskNumElts, -1);
3048 for (unsigned i = 0; i != MaskNumElts; ++i) {
3050 if (Idx >= (int)SrcNumElts)
3051 Idx -= SrcNumElts - PaddedMaskNumElts;
3055 SDValue Result = DAG.getVectorShuffle(PaddedVT, DL, Src1, Src2, MappedOps);
3057 // If the concatenated vector was padded, extract a subvector with the
3058 // correct number of elements.
3059 if (MaskNumElts != PaddedMaskNumElts)
3060 Result = DAG.getNode(
3061 ISD::EXTRACT_SUBVECTOR, DL, VT, Result,
3062 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
3064 setValue(&I, Result);
3068 if (SrcNumElts > MaskNumElts) {
3069 // Analyze the access pattern of the vector to see if we can extract
3070 // two subvectors and do the shuffle. The analysis is done by calculating
3071 // the range of elements the mask access on both vectors.
3072 int MinRange[2] = { static_cast<int>(SrcNumElts),
3073 static_cast<int>(SrcNumElts)};
3074 int MaxRange[2] = {-1, -1};
3076 for (unsigned i = 0; i != MaskNumElts; ++i) {
3082 if (Idx >= (int)SrcNumElts) {
3086 if (Idx > MaxRange[Input])
3087 MaxRange[Input] = Idx;
3088 if (Idx < MinRange[Input])
3089 MinRange[Input] = Idx;
3092 // Check if the access is smaller than the vector size and can we find
3093 // a reasonable extract index.
3094 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
3096 int StartIdx[2]; // StartIdx to extract from
3097 for (unsigned Input = 0; Input < 2; ++Input) {
3098 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
3099 RangeUse[Input] = 0; // Unused
3100 StartIdx[Input] = 0;
3104 // Find a good start index that is a multiple of the mask length. Then
3105 // see if the rest of the elements are in range.
3106 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
3107 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
3108 StartIdx[Input] + MaskNumElts <= SrcNumElts)
3109 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
3112 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
3113 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
3116 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
3117 // Extract appropriate subvector and generate a vector shuffle
3118 for (unsigned Input = 0; Input < 2; ++Input) {
3119 SDValue &Src = Input == 0 ? Src1 : Src2;
3120 if (RangeUse[Input] == 0)
3121 Src = DAG.getUNDEF(VT);
3124 ISD::EXTRACT_SUBVECTOR, DL, VT, Src,
3125 DAG.getConstant(StartIdx[Input], DL,
3126 TLI.getVectorIdxTy(DAG.getDataLayout())));
3130 // Calculate new mask.
3131 SmallVector<int, 8> MappedOps;
3132 for (unsigned i = 0; i != MaskNumElts; ++i) {
3135 if (Idx < (int)SrcNumElts)
3138 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
3140 MappedOps.push_back(Idx);
3143 setValue(&I, DAG.getVectorShuffle(VT, DL, Src1, Src2, MappedOps));
3148 // We can't use either concat vectors or extract subvectors so fall back to
3149 // replacing the shuffle with extract and build vector.
3150 // to insert and build vector.
3151 EVT EltVT = VT.getVectorElementType();
3152 EVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout());
3153 SmallVector<SDValue,8> Ops;
3154 for (unsigned i = 0; i != MaskNumElts; ++i) {
3159 Res = DAG.getUNDEF(EltVT);
3161 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
3162 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
3164 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
3165 EltVT, Src, DAG.getConstant(Idx, DL, IdxVT));
3171 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Ops));
3174 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
3175 const Value *Op0 = I.getOperand(0);
3176 const Value *Op1 = I.getOperand(1);
3177 Type *AggTy = I.getType();
3178 Type *ValTy = Op1->getType();
3179 bool IntoUndef = isa<UndefValue>(Op0);
3180 bool FromUndef = isa<UndefValue>(Op1);
3182 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3184 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3185 SmallVector<EVT, 4> AggValueVTs;
3186 ComputeValueVTs(TLI, DAG.getDataLayout(), AggTy, AggValueVTs);
3187 SmallVector<EVT, 4> ValValueVTs;
3188 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
3190 unsigned NumAggValues = AggValueVTs.size();
3191 unsigned NumValValues = ValValueVTs.size();
3192 SmallVector<SDValue, 4> Values(NumAggValues);
3194 // Ignore an insertvalue that produces an empty object
3195 if (!NumAggValues) {
3196 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3200 SDValue Agg = getValue(Op0);
3202 // Copy the beginning value(s) from the original aggregate.
3203 for (; i != LinearIndex; ++i)
3204 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3205 SDValue(Agg.getNode(), Agg.getResNo() + i);
3206 // Copy values from the inserted value(s).
3208 SDValue Val = getValue(Op1);
3209 for (; i != LinearIndex + NumValValues; ++i)
3210 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3211 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3213 // Copy remaining value(s) from the original aggregate.
3214 for (; i != NumAggValues; ++i)
3215 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3216 SDValue(Agg.getNode(), Agg.getResNo() + i);
3218 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3219 DAG.getVTList(AggValueVTs), Values));
3222 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
3223 const Value *Op0 = I.getOperand(0);
3224 Type *AggTy = Op0->getType();
3225 Type *ValTy = I.getType();
3226 bool OutOfUndef = isa<UndefValue>(Op0);
3228 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3230 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3231 SmallVector<EVT, 4> ValValueVTs;
3232 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
3234 unsigned NumValValues = ValValueVTs.size();
3236 // Ignore a extractvalue that produces an empty object
3237 if (!NumValValues) {
3238 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3242 SmallVector<SDValue, 4> Values(NumValValues);
3244 SDValue Agg = getValue(Op0);
3245 // Copy out the selected value(s).
3246 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3247 Values[i - LinearIndex] =
3249 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3250 SDValue(Agg.getNode(), Agg.getResNo() + i);
3252 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3253 DAG.getVTList(ValValueVTs), Values));
3256 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3257 Value *Op0 = I.getOperand(0);
3258 // Note that the pointer operand may be a vector of pointers. Take the scalar
3259 // element which holds a pointer.
3260 unsigned AS = Op0->getType()->getScalarType()->getPointerAddressSpace();
3261 SDValue N = getValue(Op0);
3262 SDLoc dl = getCurSDLoc();
3264 // Normalize Vector GEP - all scalar operands should be converted to the
3266 unsigned VectorWidth = I.getType()->isVectorTy() ?
3267 cast<VectorType>(I.getType())->getVectorNumElements() : 0;
3269 if (VectorWidth && !N.getValueType().isVector()) {
3270 LLVMContext &Context = *DAG.getContext();
3271 EVT VT = EVT::getVectorVT(Context, N.getValueType(), VectorWidth);
3272 N = DAG.getSplatBuildVector(VT, dl, N);
3275 for (gep_type_iterator GTI = gep_type_begin(&I), E = gep_type_end(&I);
3277 const Value *Idx = GTI.getOperand();
3278 if (StructType *StTy = GTI.getStructTypeOrNull()) {
3279 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
3282 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
3284 // In an inbouds GEP with an offset that is nonnegative even when
3285 // interpreted as signed, assume there is no unsigned overflow.
3287 if (int64_t(Offset) >= 0 && cast<GEPOperator>(I).isInBounds())
3288 Flags.setNoUnsignedWrap(true);
3290 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N,
3291 DAG.getConstant(Offset, dl, N.getValueType()), &Flags);
3295 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout(), AS);
3296 unsigned PtrSize = PtrTy.getSizeInBits();
3297 APInt ElementSize(PtrSize, DL->getTypeAllocSize(GTI.getIndexedType()));
3299 // If this is a scalar constant or a splat vector of constants,
3300 // handle it quickly.
3301 const auto *CI = dyn_cast<ConstantInt>(Idx);
3302 if (!CI && isa<ConstantDataVector>(Idx) &&
3303 cast<ConstantDataVector>(Idx)->getSplatValue())
3304 CI = cast<ConstantInt>(cast<ConstantDataVector>(Idx)->getSplatValue());
3309 APInt Offs = ElementSize * CI->getValue().sextOrTrunc(PtrSize);
3310 LLVMContext &Context = *DAG.getContext();
3311 SDValue OffsVal = VectorWidth ?
3312 DAG.getConstant(Offs, dl, EVT::getVectorVT(Context, PtrTy, VectorWidth)) :
3313 DAG.getConstant(Offs, dl, PtrTy);
3315 // In an inbouds GEP with an offset that is nonnegative even when
3316 // interpreted as signed, assume there is no unsigned overflow.
3318 if (Offs.isNonNegative() && cast<GEPOperator>(I).isInBounds())
3319 Flags.setNoUnsignedWrap(true);
3321 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, OffsVal, &Flags);
3325 // N = N + Idx * ElementSize;
3326 SDValue IdxN = getValue(Idx);
3328 if (!IdxN.getValueType().isVector() && VectorWidth) {
3329 MVT VT = MVT::getVectorVT(IdxN.getValueType().getSimpleVT(), VectorWidth);
3330 IdxN = DAG.getSplatBuildVector(VT, dl, IdxN);
3333 // If the index is smaller or larger than intptr_t, truncate or extend
3335 IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType());
3337 // If this is a multiply by a power of two, turn it into a shl
3338 // immediately. This is a very common case.
3339 if (ElementSize != 1) {
3340 if (ElementSize.isPowerOf2()) {
3341 unsigned Amt = ElementSize.logBase2();
3342 IdxN = DAG.getNode(ISD::SHL, dl,
3343 N.getValueType(), IdxN,
3344 DAG.getConstant(Amt, dl, IdxN.getValueType()));
3346 SDValue Scale = DAG.getConstant(ElementSize, dl, IdxN.getValueType());
3347 IdxN = DAG.getNode(ISD::MUL, dl,
3348 N.getValueType(), IdxN, Scale);
3352 N = DAG.getNode(ISD::ADD, dl,
3353 N.getValueType(), N, IdxN);
3360 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3361 // If this is a fixed sized alloca in the entry block of the function,
3362 // allocate it statically on the stack.
3363 if (FuncInfo.StaticAllocaMap.count(&I))
3364 return; // getValue will auto-populate this.
3366 SDLoc dl = getCurSDLoc();
3367 Type *Ty = I.getAllocatedType();
3368 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3369 auto &DL = DAG.getDataLayout();
3370 uint64_t TySize = DL.getTypeAllocSize(Ty);
3372 std::max((unsigned)DL.getPrefTypeAlignment(Ty), I.getAlignment());
3374 SDValue AllocSize = getValue(I.getArraySize());
3376 EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout());
3377 if (AllocSize.getValueType() != IntPtr)
3378 AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr);
3380 AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr,
3382 DAG.getConstant(TySize, dl, IntPtr));
3384 // Handle alignment. If the requested alignment is less than or equal to
3385 // the stack alignment, ignore it. If the size is greater than or equal to
3386 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3387 unsigned StackAlign =
3388 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
3389 if (Align <= StackAlign)
3392 // Round the size of the allocation up to the stack alignment size
3393 // by add SA-1 to the size. This doesn't overflow because we're computing
3394 // an address inside an alloca.
3396 Flags.setNoUnsignedWrap(true);
3397 AllocSize = DAG.getNode(ISD::ADD, dl,
3398 AllocSize.getValueType(), AllocSize,
3399 DAG.getIntPtrConstant(StackAlign - 1, dl), &Flags);
3401 // Mask out the low bits for alignment purposes.
3402 AllocSize = DAG.getNode(ISD::AND, dl,
3403 AllocSize.getValueType(), AllocSize,
3404 DAG.getIntPtrConstant(~(uint64_t)(StackAlign - 1),
3407 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align, dl) };
3408 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3409 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops);
3411 DAG.setRoot(DSA.getValue(1));
3413 assert(FuncInfo.MF->getFrameInfo().hasVarSizedObjects());
3416 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3418 return visitAtomicLoad(I);
3420 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3421 const Value *SV = I.getOperand(0);
3422 if (TLI.supportSwiftError()) {
3423 // Swifterror values can come from either a function parameter with
3424 // swifterror attribute or an alloca with swifterror attribute.
3425 if (const Argument *Arg = dyn_cast<Argument>(SV)) {
3426 if (Arg->hasSwiftErrorAttr())
3427 return visitLoadFromSwiftError(I);
3430 if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(SV)) {
3431 if (Alloca->isSwiftError())
3432 return visitLoadFromSwiftError(I);
3436 SDValue Ptr = getValue(SV);
3438 Type *Ty = I.getType();
3440 bool isVolatile = I.isVolatile();
3441 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3442 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr;
3443 bool isDereferenceable = isDereferenceablePointer(SV, DAG.getDataLayout());
3444 unsigned Alignment = I.getAlignment();
3447 I.getAAMetadata(AAInfo);
3448 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3450 SmallVector<EVT, 4> ValueVTs;
3451 SmallVector<uint64_t, 4> Offsets;
3452 ComputeValueVTs(TLI, DAG.getDataLayout(), Ty, ValueVTs, &Offsets);
3453 unsigned NumValues = ValueVTs.size();
3458 bool ConstantMemory = false;
3459 if (isVolatile || NumValues > MaxParallelChains)
3460 // Serialize volatile loads with other side effects.
3462 else if (AA->pointsToConstantMemory(MemoryLocation(
3463 SV, DAG.getDataLayout().getTypeStoreSize(Ty), AAInfo))) {
3464 // Do not serialize (non-volatile) loads of constant memory with anything.
3465 Root = DAG.getEntryNode();
3466 ConstantMemory = true;
3468 // Do not serialize non-volatile loads against each other.
3469 Root = DAG.getRoot();
3472 SDLoc dl = getCurSDLoc();
3475 Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG);
3477 // An aggregate load cannot wrap around the address space, so offsets to its
3478 // parts don't wrap either.
3480 Flags.setNoUnsignedWrap(true);
3482 SmallVector<SDValue, 4> Values(NumValues);
3483 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3484 EVT PtrVT = Ptr.getValueType();
3485 unsigned ChainI = 0;
3486 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3487 // Serializing loads here may result in excessive register pressure, and
3488 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3489 // could recover a bit by hoisting nodes upward in the chain by recognizing
3490 // they are side-effect free or do not alias. The optimizer should really
3491 // avoid this case by converting large object/array copies to llvm.memcpy
3492 // (MaxParallelChains should always remain as failsafe).
3493 if (ChainI == MaxParallelChains) {
3494 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3495 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3496 makeArrayRef(Chains.data(), ChainI));
3500 SDValue A = DAG.getNode(ISD::ADD, dl,
3502 DAG.getConstant(Offsets[i], dl, PtrVT),
3504 auto MMOFlags = MachineMemOperand::MONone;
3506 MMOFlags |= MachineMemOperand::MOVolatile;
3508 MMOFlags |= MachineMemOperand::MONonTemporal;
3510 MMOFlags |= MachineMemOperand::MOInvariant;
3511 if (isDereferenceable)
3512 MMOFlags |= MachineMemOperand::MODereferenceable;
3514 SDValue L = DAG.getLoad(ValueVTs[i], dl, Root, A,
3515 MachinePointerInfo(SV, Offsets[i]), Alignment,
3516 MMOFlags, AAInfo, Ranges);
3519 Chains[ChainI] = L.getValue(1);
3522 if (!ConstantMemory) {
3523 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3524 makeArrayRef(Chains.data(), ChainI));
3528 PendingLoads.push_back(Chain);
3531 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl,
3532 DAG.getVTList(ValueVTs), Values));
3535 void SelectionDAGBuilder::visitStoreToSwiftError(const StoreInst &I) {
3536 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3537 assert(TLI.supportSwiftError() &&
3538 "call visitStoreToSwiftError when backend supports swifterror");
3540 SmallVector<EVT, 4> ValueVTs;
3541 SmallVector<uint64_t, 4> Offsets;
3542 const Value *SrcV = I.getOperand(0);
3543 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(),
3544 SrcV->getType(), ValueVTs, &Offsets);
3545 assert(ValueVTs.size() == 1 && Offsets[0] == 0 &&
3546 "expect a single EVT for swifterror");
3548 SDValue Src = getValue(SrcV);
3549 // Create a virtual register, then update the virtual register.
3550 auto &DL = DAG.getDataLayout();
3551 const TargetRegisterClass *RC = TLI.getRegClassFor(TLI.getPointerTy(DL));
3552 unsigned VReg = FuncInfo.MF->getRegInfo().createVirtualRegister(RC);
3553 // Chain, DL, Reg, N or Chain, DL, Reg, N, Glue
3554 // Chain can be getRoot or getControlRoot.
3555 SDValue CopyNode = DAG.getCopyToReg(getRoot(), getCurSDLoc(), VReg,
3556 SDValue(Src.getNode(), Src.getResNo()));
3557 DAG.setRoot(CopyNode);
3558 FuncInfo.setCurrentSwiftErrorVReg(FuncInfo.MBB, I.getOperand(1), VReg);
3561 void SelectionDAGBuilder::visitLoadFromSwiftError(const LoadInst &I) {
3562 assert(DAG.getTargetLoweringInfo().supportSwiftError() &&
3563 "call visitLoadFromSwiftError when backend supports swifterror");
3565 assert(!I.isVolatile() &&
3566 I.getMetadata(LLVMContext::MD_nontemporal) == nullptr &&
3567 I.getMetadata(LLVMContext::MD_invariant_load) == nullptr &&
3568 "Support volatile, non temporal, invariant for load_from_swift_error");
3570 const Value *SV = I.getOperand(0);
3571 Type *Ty = I.getType();
3573 I.getAAMetadata(AAInfo);
3574 assert(!AA->pointsToConstantMemory(MemoryLocation(
3575 SV, DAG.getDataLayout().getTypeStoreSize(Ty), AAInfo)) &&
3576 "load_from_swift_error should not be constant memory");
3578 SmallVector<EVT, 4> ValueVTs;
3579 SmallVector<uint64_t, 4> Offsets;
3580 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), Ty,
3581 ValueVTs, &Offsets);
3582 assert(ValueVTs.size() == 1 && Offsets[0] == 0 &&
3583 "expect a single EVT for swifterror");
3585 // Chain, DL, Reg, VT, Glue or Chain, DL, Reg, VT
3586 SDValue L = DAG.getCopyFromReg(
3587 getRoot(), getCurSDLoc(),
3588 FuncInfo.getOrCreateSwiftErrorVReg(FuncInfo.MBB, SV), ValueVTs[0]);
3593 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3595 return visitAtomicStore(I);
3597 const Value *SrcV = I.getOperand(0);
3598 const Value *PtrV = I.getOperand(1);
3600 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3601 if (TLI.supportSwiftError()) {
3602 // Swifterror values can come from either a function parameter with
3603 // swifterror attribute or an alloca with swifterror attribute.
3604 if (const Argument *Arg = dyn_cast<Argument>(PtrV)) {
3605 if (Arg->hasSwiftErrorAttr())
3606 return visitStoreToSwiftError(I);
3609 if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(PtrV)) {
3610 if (Alloca->isSwiftError())
3611 return visitStoreToSwiftError(I);
3615 SmallVector<EVT, 4> ValueVTs;
3616 SmallVector<uint64_t, 4> Offsets;
3617 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(),
3618 SrcV->getType(), ValueVTs, &Offsets);
3619 unsigned NumValues = ValueVTs.size();
3623 // Get the lowered operands. Note that we do this after
3624 // checking if NumResults is zero, because with zero results
3625 // the operands won't have values in the map.
3626 SDValue Src = getValue(SrcV);
3627 SDValue Ptr = getValue(PtrV);
3629 SDValue Root = getRoot();
3630 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3631 SDLoc dl = getCurSDLoc();
3632 EVT PtrVT = Ptr.getValueType();
3633 unsigned Alignment = I.getAlignment();
3635 I.getAAMetadata(AAInfo);
3637 auto MMOFlags = MachineMemOperand::MONone;
3639 MMOFlags |= MachineMemOperand::MOVolatile;
3640 if (I.getMetadata(LLVMContext::MD_nontemporal) != nullptr)
3641 MMOFlags |= MachineMemOperand::MONonTemporal;
3643 // An aggregate load cannot wrap around the address space, so offsets to its
3644 // parts don't wrap either.
3646 Flags.setNoUnsignedWrap(true);
3648 unsigned ChainI = 0;
3649 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3650 // See visitLoad comments.
3651 if (ChainI == MaxParallelChains) {
3652 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3653 makeArrayRef(Chains.data(), ChainI));
3657 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr,
3658 DAG.getConstant(Offsets[i], dl, PtrVT), &Flags);
3659 SDValue St = DAG.getStore(
3660 Root, dl, SDValue(Src.getNode(), Src.getResNo() + i), Add,
3661 MachinePointerInfo(PtrV, Offsets[i]), Alignment, MMOFlags, AAInfo);
3662 Chains[ChainI] = St;
3665 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3666 makeArrayRef(Chains.data(), ChainI));
3667 DAG.setRoot(StoreNode);
3670 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I,
3671 bool IsCompressing) {
3672 SDLoc sdl = getCurSDLoc();
3674 auto getMaskedStoreOps = [&](Value* &Ptr, Value* &Mask, Value* &Src0,
3675 unsigned& Alignment) {
3676 // llvm.masked.store.*(Src0, Ptr, alignment, Mask)
3677 Src0 = I.getArgOperand(0);
3678 Ptr = I.getArgOperand(1);
3679 Alignment = cast<ConstantInt>(I.getArgOperand(2))->getZExtValue();
3680 Mask = I.getArgOperand(3);
3682 auto getCompressingStoreOps = [&](Value* &Ptr, Value* &Mask, Value* &Src0,
3683 unsigned& Alignment) {
3684 // llvm.masked.compressstore.*(Src0, Ptr, Mask)
3685 Src0 = I.getArgOperand(0);
3686 Ptr = I.getArgOperand(1);
3687 Mask = I.getArgOperand(2);
3691 Value *PtrOperand, *MaskOperand, *Src0Operand;
3694 getCompressingStoreOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
3696 getMaskedStoreOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
3698 SDValue Ptr = getValue(PtrOperand);
3699 SDValue Src0 = getValue(Src0Operand);
3700 SDValue Mask = getValue(MaskOperand);
3702 EVT VT = Src0.getValueType();
3704 Alignment = DAG.getEVTAlignment(VT);
3707 I.getAAMetadata(AAInfo);
3709 MachineMemOperand *MMO =
3710 DAG.getMachineFunction().
3711 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3712 MachineMemOperand::MOStore, VT.getStoreSize(),
3714 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
3715 MMO, false /* Truncating */,
3717 DAG.setRoot(StoreNode);
3718 setValue(&I, StoreNode);
3721 // Get a uniform base for the Gather/Scatter intrinsic.
3722 // The first argument of the Gather/Scatter intrinsic is a vector of pointers.
3723 // We try to represent it as a base pointer + vector of indices.
3724 // Usually, the vector of pointers comes from a 'getelementptr' instruction.
3725 // The first operand of the GEP may be a single pointer or a vector of pointers
3727 // %gep.ptr = getelementptr i32, <8 x i32*> %vptr, <8 x i32> %ind
3729 // %gep.ptr = getelementptr i32, i32* %ptr, <8 x i32> %ind
3730 // %res = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %gep.ptr, ..
3732 // When the first GEP operand is a single pointer - it is the uniform base we
3733 // are looking for. If first operand of the GEP is a splat vector - we
3734 // extract the spalt value and use it as a uniform base.
3735 // In all other cases the function returns 'false'.
3737 static bool getUniformBase(const Value* &Ptr, SDValue& Base, SDValue& Index,
3738 SelectionDAGBuilder* SDB) {
3740 SelectionDAG& DAG = SDB->DAG;
3741 LLVMContext &Context = *DAG.getContext();
3743 assert(Ptr->getType()->isVectorTy() && "Uexpected pointer type");
3744 const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr);
3745 if (!GEP || GEP->getNumOperands() > 2)
3748 const Value *GEPPtr = GEP->getPointerOperand();
3749 if (!GEPPtr->getType()->isVectorTy())
3751 else if (!(Ptr = getSplatValue(GEPPtr)))
3754 Value *IndexVal = GEP->getOperand(1);
3756 // The operands of the GEP may be defined in another basic block.
3757 // In this case we'll not find nodes for the operands.
3758 if (!SDB->findValue(Ptr) || !SDB->findValue(IndexVal))
3761 Base = SDB->getValue(Ptr);
3762 Index = SDB->getValue(IndexVal);
3764 // Suppress sign extension.
3765 if (SExtInst* Sext = dyn_cast<SExtInst>(IndexVal)) {
3766 if (SDB->findValue(Sext->getOperand(0))) {
3767 IndexVal = Sext->getOperand(0);
3768 Index = SDB->getValue(IndexVal);
3771 if (!Index.getValueType().isVector()) {
3772 unsigned GEPWidth = GEP->getType()->getVectorNumElements();
3773 EVT VT = EVT::getVectorVT(Context, Index.getValueType(), GEPWidth);
3774 Index = DAG.getSplatBuildVector(VT, SDLoc(Index), Index);
3779 void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
3780 SDLoc sdl = getCurSDLoc();
3782 // llvm.masked.scatter.*(Src0, Ptrs, alignemt, Mask)
3783 const Value *Ptr = I.getArgOperand(1);
3784 SDValue Src0 = getValue(I.getArgOperand(0));
3785 SDValue Mask = getValue(I.getArgOperand(3));
3786 EVT VT = Src0.getValueType();
3787 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3789 Alignment = DAG.getEVTAlignment(VT);
3790 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3793 I.getAAMetadata(AAInfo);
3797 const Value *BasePtr = Ptr;
3798 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3800 const Value *MemOpBasePtr = UniformBase ? BasePtr : nullptr;
3801 MachineMemOperand *MMO = DAG.getMachineFunction().
3802 getMachineMemOperand(MachinePointerInfo(MemOpBasePtr),
3803 MachineMemOperand::MOStore, VT.getStoreSize(),
3806 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3807 Index = getValue(Ptr);
3809 SDValue Ops[] = { getRoot(), Src0, Mask, Base, Index };
3810 SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl,
3812 DAG.setRoot(Scatter);
3813 setValue(&I, Scatter);
3816 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I, bool IsExpanding) {
3817 SDLoc sdl = getCurSDLoc();
3819 auto getMaskedLoadOps = [&](Value* &Ptr, Value* &Mask, Value* &Src0,
3820 unsigned& Alignment) {
3821 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
3822 Ptr = I.getArgOperand(0);
3823 Alignment = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
3824 Mask = I.getArgOperand(2);
3825 Src0 = I.getArgOperand(3);
3827 auto getExpandingLoadOps = [&](Value* &Ptr, Value* &Mask, Value* &Src0,
3828 unsigned& Alignment) {
3829 // @llvm.masked.expandload.*(Ptr, Mask, Src0)
3830 Ptr = I.getArgOperand(0);
3832 Mask = I.getArgOperand(1);
3833 Src0 = I.getArgOperand(2);
3836 Value *PtrOperand, *MaskOperand, *Src0Operand;
3839 getExpandingLoadOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
3841 getMaskedLoadOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
3843 SDValue Ptr = getValue(PtrOperand);
3844 SDValue Src0 = getValue(Src0Operand);
3845 SDValue Mask = getValue(MaskOperand);
3847 EVT VT = Src0.getValueType();
3849 Alignment = DAG.getEVTAlignment(VT);
3852 I.getAAMetadata(AAInfo);
3853 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3855 // Do not serialize masked loads of constant memory with anything.
3856 bool AddToChain = !AA->pointsToConstantMemory(MemoryLocation(
3857 PtrOperand, DAG.getDataLayout().getTypeStoreSize(I.getType()), AAInfo));
3858 SDValue InChain = AddToChain ? DAG.getRoot() : DAG.getEntryNode();
3860 MachineMemOperand *MMO =
3861 DAG.getMachineFunction().
3862 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3863 MachineMemOperand::MOLoad, VT.getStoreSize(),
3864 Alignment, AAInfo, Ranges);
3866 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
3867 ISD::NON_EXTLOAD, IsExpanding);
3869 SDValue OutChain = Load.getValue(1);
3870 DAG.setRoot(OutChain);
3875 void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
3876 SDLoc sdl = getCurSDLoc();
3878 // @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0)
3879 const Value *Ptr = I.getArgOperand(0);
3880 SDValue Src0 = getValue(I.getArgOperand(3));
3881 SDValue Mask = getValue(I.getArgOperand(2));
3883 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3884 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3885 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3887 Alignment = DAG.getEVTAlignment(VT);
3890 I.getAAMetadata(AAInfo);
3891 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3893 SDValue Root = DAG.getRoot();
3896 const Value *BasePtr = Ptr;
3897 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3898 bool ConstantMemory = false;
3900 AA->pointsToConstantMemory(MemoryLocation(
3901 BasePtr, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3903 // Do not serialize (non-volatile) loads of constant memory with anything.
3904 Root = DAG.getEntryNode();
3905 ConstantMemory = true;
3908 MachineMemOperand *MMO =
3909 DAG.getMachineFunction().
3910 getMachineMemOperand(MachinePointerInfo(UniformBase ? BasePtr : nullptr),
3911 MachineMemOperand::MOLoad, VT.getStoreSize(),
3912 Alignment, AAInfo, Ranges);
3915 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3916 Index = getValue(Ptr);
3918 SDValue Ops[] = { Root, Src0, Mask, Base, Index };
3919 SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl,
3922 SDValue OutChain = Gather.getValue(1);
3923 if (!ConstantMemory)
3924 PendingLoads.push_back(OutChain);
3925 setValue(&I, Gather);
3928 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3929 SDLoc dl = getCurSDLoc();
3930 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3931 AtomicOrdering FailureOrder = I.getFailureOrdering();
3932 SynchronizationScope Scope = I.getSynchScope();
3934 SDValue InChain = getRoot();
3936 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3937 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3938 SDValue L = DAG.getAtomicCmpSwap(
3939 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3940 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3941 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3942 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3944 SDValue OutChain = L.getValue(2);
3947 DAG.setRoot(OutChain);
3950 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3951 SDLoc dl = getCurSDLoc();
3953 switch (I.getOperation()) {
3954 default: llvm_unreachable("Unknown atomicrmw operation");
3955 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3956 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3957 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3958 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3959 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3960 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3961 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3962 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3963 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3964 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3965 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3967 AtomicOrdering Order = I.getOrdering();
3968 SynchronizationScope Scope = I.getSynchScope();
3970 SDValue InChain = getRoot();
3973 DAG.getAtomic(NT, dl,
3974 getValue(I.getValOperand()).getSimpleValueType(),
3976 getValue(I.getPointerOperand()),
3977 getValue(I.getValOperand()),
3978 I.getPointerOperand(),
3979 /* Alignment=*/ 0, Order, Scope);
3981 SDValue OutChain = L.getValue(1);
3984 DAG.setRoot(OutChain);
3987 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3988 SDLoc dl = getCurSDLoc();
3989 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3992 Ops[1] = DAG.getConstant((unsigned)I.getOrdering(), dl,
3993 TLI.getPointerTy(DAG.getDataLayout()));
3994 Ops[2] = DAG.getConstant(I.getSynchScope(), dl,
3995 TLI.getPointerTy(DAG.getDataLayout()));
3996 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3999 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
4000 SDLoc dl = getCurSDLoc();
4001 AtomicOrdering Order = I.getOrdering();
4002 SynchronizationScope Scope = I.getSynchScope();
4004 SDValue InChain = getRoot();
4006 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4007 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4009 if (I.getAlignment() < VT.getSizeInBits() / 8)
4010 report_fatal_error("Cannot generate unaligned atomic load");
4012 MachineMemOperand *MMO =
4013 DAG.getMachineFunction().
4014 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
4015 MachineMemOperand::MOVolatile |
4016 MachineMemOperand::MOLoad,
4018 I.getAlignment() ? I.getAlignment() :
4019 DAG.getEVTAlignment(VT),
4020 AAMDNodes(), nullptr, Scope, Order);
4022 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
4024 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
4025 getValue(I.getPointerOperand()), MMO);
4027 SDValue OutChain = L.getValue(1);
4030 DAG.setRoot(OutChain);
4033 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
4034 SDLoc dl = getCurSDLoc();
4036 AtomicOrdering Order = I.getOrdering();
4037 SynchronizationScope Scope = I.getSynchScope();
4039 SDValue InChain = getRoot();
4041 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4043 TLI.getValueType(DAG.getDataLayout(), I.getValueOperand()->getType());
4045 if (I.getAlignment() < VT.getSizeInBits() / 8)
4046 report_fatal_error("Cannot generate unaligned atomic store");
4049 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
4051 getValue(I.getPointerOperand()),
4052 getValue(I.getValueOperand()),
4053 I.getPointerOperand(), I.getAlignment(),
4056 DAG.setRoot(OutChain);
4059 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
4061 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
4062 unsigned Intrinsic) {
4063 // Ignore the callsite's attributes. A specific call site may be marked with
4064 // readnone, but the lowering code will expect the chain based on the
4066 const Function *F = I.getCalledFunction();
4067 bool HasChain = !F->doesNotAccessMemory();
4068 bool OnlyLoad = HasChain && F->onlyReadsMemory();
4070 // Build the operand list.
4071 SmallVector<SDValue, 8> Ops;
4072 if (HasChain) { // If this intrinsic has side-effects, chainify it.
4074 // We don't need to serialize loads against other loads.
4075 Ops.push_back(DAG.getRoot());
4077 Ops.push_back(getRoot());
4081 // Info is set by getTgtMemInstrinsic
4082 TargetLowering::IntrinsicInfo Info;
4083 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4084 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
4086 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
4087 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
4088 Info.opc == ISD::INTRINSIC_W_CHAIN)
4089 Ops.push_back(DAG.getTargetConstant(Intrinsic, getCurSDLoc(),
4090 TLI.getPointerTy(DAG.getDataLayout())));
4092 // Add all operands of the call to the operand list.
4093 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
4094 SDValue Op = getValue(I.getArgOperand(i));
4098 SmallVector<EVT, 4> ValueVTs;
4099 ComputeValueVTs(TLI, DAG.getDataLayout(), I.getType(), ValueVTs);
4102 ValueVTs.push_back(MVT::Other);
4104 SDVTList VTs = DAG.getVTList(ValueVTs);
4108 if (IsTgtIntrinsic) {
4109 // This is target intrinsic that touches memory
4110 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
4111 VTs, Ops, Info.memVT,
4112 MachinePointerInfo(Info.ptrVal, Info.offset),
4113 Info.align, Info.vol,
4114 Info.readMem, Info.writeMem, Info.size);
4115 } else if (!HasChain) {
4116 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
4117 } else if (!I.getType()->isVoidTy()) {
4118 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
4120 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
4124 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
4126 PendingLoads.push_back(Chain);
4131 if (!I.getType()->isVoidTy()) {
4132 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
4133 EVT VT = TLI.getValueType(DAG.getDataLayout(), PTy);
4134 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
4136 Result = lowerRangeToAssertZExt(DAG, I, Result);
4138 setValue(&I, Result);
4142 /// GetSignificand - Get the significand and build it into a floating-point
4143 /// number with exponent of 1:
4145 /// Op = (Op & 0x007fffff) | 0x3f800000;
4147 /// where Op is the hexadecimal representation of floating point value.
4148 static SDValue GetSignificand(SelectionDAG &DAG, SDValue Op, const SDLoc &dl) {
4149 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
4150 DAG.getConstant(0x007fffff, dl, MVT::i32));
4151 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
4152 DAG.getConstant(0x3f800000, dl, MVT::i32));
4153 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
4156 /// GetExponent - Get the exponent:
4158 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
4160 /// where Op is the hexadecimal representation of floating point value.
4161 static SDValue GetExponent(SelectionDAG &DAG, SDValue Op,
4162 const TargetLowering &TLI, const SDLoc &dl) {
4163 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
4164 DAG.getConstant(0x7f800000, dl, MVT::i32));
4165 SDValue t1 = DAG.getNode(
4166 ISD::SRL, dl, MVT::i32, t0,
4167 DAG.getConstant(23, dl, TLI.getPointerTy(DAG.getDataLayout())));
4168 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
4169 DAG.getConstant(127, dl, MVT::i32));
4170 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
4173 /// getF32Constant - Get 32-bit floating point constant.
4174 static SDValue getF32Constant(SelectionDAG &DAG, unsigned Flt,
4176 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle(), APInt(32, Flt)), dl,
4180 static SDValue getLimitedPrecisionExp2(SDValue t0, const SDLoc &dl,
4181 SelectionDAG &DAG) {
4182 // TODO: What fast-math-flags should be set on the floating-point nodes?
4184 // IntegerPartOfX = ((int32_t)(t0);
4185 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4187 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
4188 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4189 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4191 // IntegerPartOfX <<= 23;
4192 IntegerPartOfX = DAG.getNode(
4193 ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4194 DAG.getConstant(23, dl, DAG.getTargetLoweringInfo().getPointerTy(
4195 DAG.getDataLayout())));
4197 SDValue TwoToFractionalPartOfX;
4198 if (LimitFloatPrecision <= 6) {
4199 // For floating-point precision of 6:
4201 // TwoToFractionalPartOfX =
4203 // (0.735607626f + 0.252464424f * x) * x;
4205 // error 0.0144103317, which is 6 bits
4206 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4207 getF32Constant(DAG, 0x3e814304, dl));
4208 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4209 getF32Constant(DAG, 0x3f3c50c8, dl));
4210 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4211 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4212 getF32Constant(DAG, 0x3f7f5e7e, dl));
4213 } else if (LimitFloatPrecision <= 12) {
4214 // For floating-point precision of 12:
4216 // TwoToFractionalPartOfX =
4219 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4221 // error 0.000107046256, which is 13 to 14 bits
4222 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4223 getF32Constant(DAG, 0x3da235e3, dl));
4224 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4225 getF32Constant(DAG, 0x3e65b8f3, dl));
4226 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4227 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4228 getF32Constant(DAG, 0x3f324b07, dl));
4229 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4230 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4231 getF32Constant(DAG, 0x3f7ff8fd, dl));
4232 } else { // LimitFloatPrecision <= 18
4233 // For floating-point precision of 18:
4235 // TwoToFractionalPartOfX =
4239 // (0.554906021e-1f +
4240 // (0.961591928e-2f +
4241 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4242 // error 2.47208000*10^(-7), which is better than 18 bits
4243 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4244 getF32Constant(DAG, 0x3924b03e, dl));
4245 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4246 getF32Constant(DAG, 0x3ab24b87, dl));
4247 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4248 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4249 getF32Constant(DAG, 0x3c1d8c17, dl));
4250 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4251 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4252 getF32Constant(DAG, 0x3d634a1d, dl));
4253 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4254 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4255 getF32Constant(DAG, 0x3e75fe14, dl));
4256 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4257 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4258 getF32Constant(DAG, 0x3f317234, dl));
4259 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4260 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4261 getF32Constant(DAG, 0x3f800000, dl));
4264 // Add the exponent into the result in integer domain.
4265 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
4266 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4267 DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
4270 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
4271 /// limited-precision mode.
4272 static SDValue expandExp(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
4273 const TargetLowering &TLI) {
4274 if (Op.getValueType() == MVT::f32 &&
4275 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4277 // Put the exponent in the right bit position for later addition to the
4280 // #define LOG2OFe 1.4426950f
4281 // t0 = Op * LOG2OFe
4283 // TODO: What fast-math-flags should be set here?
4284 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
4285 getF32Constant(DAG, 0x3fb8aa3b, dl));
4286 return getLimitedPrecisionExp2(t0, dl, DAG);
4289 // No special expansion.
4290 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
4293 /// expandLog - Lower a log intrinsic. Handles the special sequences for
4294 /// limited-precision mode.
4295 static SDValue expandLog(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
4296 const TargetLowering &TLI) {
4298 // TODO: What fast-math-flags should be set on the floating-point nodes?
4300 if (Op.getValueType() == MVT::f32 &&
4301 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4302 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4304 // Scale the exponent by log(2) [0.69314718f].
4305 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4306 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4307 getF32Constant(DAG, 0x3f317218, dl));
4309 // Get the significand and build it into a floating-point number with
4311 SDValue X = GetSignificand(DAG, Op1, dl);
4313 SDValue LogOfMantissa;
4314 if (LimitFloatPrecision <= 6) {
4315 // For floating-point precision of 6:
4319 // (1.4034025f - 0.23903021f * x) * x;
4321 // error 0.0034276066, which is better than 8 bits
4322 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4323 getF32Constant(DAG, 0xbe74c456, dl));
4324 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4325 getF32Constant(DAG, 0x3fb3a2b1, dl));
4326 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4327 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4328 getF32Constant(DAG, 0x3f949a29, dl));
4329 } else if (LimitFloatPrecision <= 12) {
4330 // For floating-point precision of 12:
4336 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
4338 // error 0.000061011436, which is 14 bits
4339 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4340 getF32Constant(DAG, 0xbd67b6d6, dl));
4341 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4342 getF32Constant(DAG, 0x3ee4f4b8, dl));
4343 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4344 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4345 getF32Constant(DAG, 0x3fbc278b, dl));
4346 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4347 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4348 getF32Constant(DAG, 0x40348e95, dl));
4349 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4350 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4351 getF32Constant(DAG, 0x3fdef31a, dl));
4352 } else { // LimitFloatPrecision <= 18
4353 // For floating-point precision of 18:
4361 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
4363 // error 0.0000023660568, which is better than 18 bits
4364 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4365 getF32Constant(DAG, 0xbc91e5ac, dl));
4366 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4367 getF32Constant(DAG, 0x3e4350aa, dl));
4368 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4369 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4370 getF32Constant(DAG, 0x3f60d3e3, dl));
4371 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4372 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4373 getF32Constant(DAG, 0x4011cdf0, dl));
4374 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4375 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4376 getF32Constant(DAG, 0x406cfd1c, dl));
4377 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4378 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4379 getF32Constant(DAG, 0x408797cb, dl));
4380 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4381 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4382 getF32Constant(DAG, 0x4006dcab, dl));
4385 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
4388 // No special expansion.
4389 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
4392 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
4393 /// limited-precision mode.
4394 static SDValue expandLog2(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
4395 const TargetLowering &TLI) {
4397 // TODO: What fast-math-flags should be set on the floating-point nodes?
4399 if (Op.getValueType() == MVT::f32 &&
4400 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4401 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4403 // Get the exponent.
4404 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
4406 // Get the significand and build it into a floating-point number with
4408 SDValue X = GetSignificand(DAG, Op1, dl);
4410 // Different possible minimax approximations of significand in
4411 // floating-point for various degrees of accuracy over [1,2].
4412 SDValue Log2ofMantissa;
4413 if (LimitFloatPrecision <= 6) {
4414 // For floating-point precision of 6:
4416 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
4418 // error 0.0049451742, which is more than 7 bits
4419 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4420 getF32Constant(DAG, 0xbeb08fe0, dl));
4421 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4422 getF32Constant(DAG, 0x40019463, dl));
4423 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4424 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4425 getF32Constant(DAG, 0x3fd6633d, dl));
4426 } else if (LimitFloatPrecision <= 12) {
4427 // For floating-point precision of 12:
4433 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
4435 // error 0.0000876136000, which is better than 13 bits
4436 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4437 getF32Constant(DAG, 0xbda7262e, dl));
4438 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4439 getF32Constant(DAG, 0x3f25280b, dl));
4440 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4441 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4442 getF32Constant(DAG, 0x4007b923, dl));
4443 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4444 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4445 getF32Constant(DAG, 0x40823e2f, dl));
4446 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4447 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4448 getF32Constant(DAG, 0x4020d29c, dl));
4449 } else { // LimitFloatPrecision <= 18
4450 // For floating-point precision of 18:
4459 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
4461 // error 0.0000018516, which is better than 18 bits
4462 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4463 getF32Constant(DAG, 0xbcd2769e, dl));
4464 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4465 getF32Constant(DAG, 0x3e8ce0b9, dl));
4466 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4467 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4468 getF32Constant(DAG, 0x3fa22ae7, dl));
4469 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4470 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4471 getF32Constant(DAG, 0x40525723, dl));
4472 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4473 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4474 getF32Constant(DAG, 0x40aaf200, dl));
4475 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4476 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4477 getF32Constant(DAG, 0x40c39dad, dl));
4478 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4479 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4480 getF32Constant(DAG, 0x4042902c, dl));
4483 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
4486 // No special expansion.
4487 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
4490 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
4491 /// limited-precision mode.
4492 static SDValue expandLog10(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
4493 const TargetLowering &TLI) {
4495 // TODO: What fast-math-flags should be set on the floating-point nodes?
4497 if (Op.getValueType() == MVT::f32 &&
4498 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4499 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4501 // Scale the exponent by log10(2) [0.30102999f].
4502 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4503 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4504 getF32Constant(DAG, 0x3e9a209a, dl));
4506 // Get the significand and build it into a floating-point number with
4508 SDValue X = GetSignificand(DAG, Op1, dl);
4510 SDValue Log10ofMantissa;
4511 if (LimitFloatPrecision <= 6) {
4512 // For floating-point precision of 6:
4514 // Log10ofMantissa =
4516 // (0.60948995f - 0.10380950f * x) * x;
4518 // error 0.0014886165, which is 6 bits
4519 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4520 getF32Constant(DAG, 0xbdd49a13, dl));
4521 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4522 getF32Constant(DAG, 0x3f1c0789, dl));
4523 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4524 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4525 getF32Constant(DAG, 0x3f011300, dl));
4526 } else if (LimitFloatPrecision <= 12) {
4527 // For floating-point precision of 12:
4529 // Log10ofMantissa =
4532 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4534 // error 0.00019228036, which is better than 12 bits
4535 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4536 getF32Constant(DAG, 0x3d431f31, dl));
4537 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4538 getF32Constant(DAG, 0x3ea21fb2, dl));
4539 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4540 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4541 getF32Constant(DAG, 0x3f6ae232, dl));
4542 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4543 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4544 getF32Constant(DAG, 0x3f25f7c3, dl));
4545 } else { // LimitFloatPrecision <= 18
4546 // For floating-point precision of 18:
4548 // Log10ofMantissa =
4553 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4555 // error 0.0000037995730, which is better than 18 bits
4556 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4557 getF32Constant(DAG, 0x3c5d51ce, dl));
4558 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4559 getF32Constant(DAG, 0x3e00685a, dl));
4560 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4561 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4562 getF32Constant(DAG, 0x3efb6798, dl));
4563 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4564 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4565 getF32Constant(DAG, 0x3f88d192, dl));
4566 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4567 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4568 getF32Constant(DAG, 0x3fc4316c, dl));
4569 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4570 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4571 getF32Constant(DAG, 0x3f57ce70, dl));
4574 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4577 // No special expansion.
4578 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4581 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4582 /// limited-precision mode.
4583 static SDValue expandExp2(const SDLoc &dl, SDValue Op, SelectionDAG &DAG,
4584 const TargetLowering &TLI) {
4585 if (Op.getValueType() == MVT::f32 &&
4586 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
4587 return getLimitedPrecisionExp2(Op, dl, DAG);
4589 // No special expansion.
4590 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4593 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4594 /// limited-precision mode with x == 10.0f.
4595 static SDValue expandPow(const SDLoc &dl, SDValue LHS, SDValue RHS,
4596 SelectionDAG &DAG, const TargetLowering &TLI) {
4597 bool IsExp10 = false;
4598 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
4599 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4600 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4602 IsExp10 = LHSC->isExactlyValue(Ten);
4606 // TODO: What fast-math-flags should be set on the FMUL node?
4608 // Put the exponent in the right bit position for later addition to the
4611 // #define LOG2OF10 3.3219281f
4612 // t0 = Op * LOG2OF10;
4613 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4614 getF32Constant(DAG, 0x40549a78, dl));
4615 return getLimitedPrecisionExp2(t0, dl, DAG);
4618 // No special expansion.
4619 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4623 /// ExpandPowI - Expand a llvm.powi intrinsic.
4624 static SDValue ExpandPowI(const SDLoc &DL, SDValue LHS, SDValue RHS,
4625 SelectionDAG &DAG) {
4626 // If RHS is a constant, we can expand this out to a multiplication tree,
4627 // otherwise we end up lowering to a call to __powidf2 (for example). When
4628 // optimizing for size, we only want to do this if the expansion would produce
4629 // a small number of multiplies, otherwise we do the full expansion.
4630 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4631 // Get the exponent as a positive value.
4632 unsigned Val = RHSC->getSExtValue();
4633 if ((int)Val < 0) Val = -Val;
4635 // powi(x, 0) -> 1.0
4637 return DAG.getConstantFP(1.0, DL, LHS.getValueType());
4639 const Function *F = DAG.getMachineFunction().getFunction();
4640 if (!F->optForSize() ||
4641 // If optimizing for size, don't insert too many multiplies.
4642 // This inserts up to 5 multiplies.
4643 countPopulation(Val) + Log2_32(Val) < 7) {
4644 // We use the simple binary decomposition method to generate the multiply
4645 // sequence. There are more optimal ways to do this (for example,
4646 // powi(x,15) generates one more multiply than it should), but this has
4647 // the benefit of being both really simple and much better than a libcall.
4648 SDValue Res; // Logically starts equal to 1.0
4649 SDValue CurSquare = LHS;
4650 // TODO: Intrinsics should have fast-math-flags that propagate to these
4655 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4657 Res = CurSquare; // 1.0*CurSquare.
4660 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4661 CurSquare, CurSquare);
4665 // If the original was negative, invert the result, producing 1/(x*x*x).
4666 if (RHSC->getSExtValue() < 0)
4667 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4668 DAG.getConstantFP(1.0, DL, LHS.getValueType()), Res);
4673 // Otherwise, expand to a libcall.
4674 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4677 // getUnderlyingArgReg - Find underlying register used for a truncated or
4678 // bitcasted argument.
4679 static unsigned getUnderlyingArgReg(const SDValue &N) {
4680 switch (N.getOpcode()) {
4681 case ISD::CopyFromReg:
4682 return cast<RegisterSDNode>(N.getOperand(1))->getReg();
4684 case ISD::AssertZext:
4685 case ISD::AssertSext:
4687 return getUnderlyingArgReg(N.getOperand(0));
4693 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4694 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4695 /// At the end of instruction selection, they will be inserted to the entry BB.
4696 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
4697 const Value *V, DILocalVariable *Variable, DIExpression *Expr,
4698 DILocation *DL, int64_t Offset, bool IsIndirect, const SDValue &N) {
4699 const Argument *Arg = dyn_cast<Argument>(V);
4703 MachineFunction &MF = DAG.getMachineFunction();
4704 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4706 // Ignore inlined function arguments here.
4708 // FIXME: Should we be checking DL->inlinedAt() to determine this?
4709 if (!Variable->getScope()->getSubprogram()->describes(MF.getFunction()))
4712 Optional<MachineOperand> Op;
4713 // Some arguments' frame index is recorded during argument lowering.
4714 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4715 Op = MachineOperand::CreateFI(FI);
4717 if (!Op && N.getNode()) {
4718 unsigned Reg = getUnderlyingArgReg(N);
4719 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4720 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4721 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4726 Op = MachineOperand::CreateReg(Reg, false);
4730 // Check if ValueMap has reg number.
4731 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4732 if (VMI != FuncInfo.ValueMap.end())
4733 Op = MachineOperand::CreateReg(VMI->second, false);
4736 if (!Op && N.getNode())
4737 // Check if frame index is available.
4738 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4739 if (FrameIndexSDNode *FINode =
4740 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4741 Op = MachineOperand::CreateFI(FINode->getIndex());
4746 assert(Variable->isValidLocationForIntrinsic(DL) &&
4747 "Expected inlined-at fields to agree");
4749 FuncInfo.ArgDbgValues.push_back(
4750 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
4751 Op->getReg(), Offset, Variable, Expr));
4753 FuncInfo.ArgDbgValues.push_back(
4754 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE))
4757 .addMetadata(Variable)
4758 .addMetadata(Expr));
4763 /// Return the appropriate SDDbgValue based on N.
4764 SDDbgValue *SelectionDAGBuilder::getDbgValue(SDValue N,
4765 DILocalVariable *Variable,
4766 DIExpression *Expr, int64_t Offset,
4768 unsigned DbgSDNodeOrder) {
4770 auto *FISDN = dyn_cast<FrameIndexSDNode>(N.getNode());
4771 if (FISDN && Expr->startsWithDeref()) {
4772 // Construct a FrameIndexDbgValue for FrameIndexSDNodes so we can describe
4773 // stack slot locations as such instead of as indirectly addressed
4775 ArrayRef<uint64_t> TrailingElements(Expr->elements_begin() + 1,
4776 Expr->elements_end());
4777 DIExpression *DerefedDIExpr =
4778 DIExpression::get(*DAG.getContext(), TrailingElements);
4779 int FI = FISDN->getIndex();
4780 SDV = DAG.getFrameIndexDbgValue(Variable, DerefedDIExpr, FI, 0, dl,
4783 SDV = DAG.getDbgValue(Variable, Expr, N.getNode(), N.getResNo(), false,
4784 Offset, dl, DbgSDNodeOrder);
4789 // VisualStudio defines setjmp as _setjmp
4790 #if defined(_MSC_VER) && defined(setjmp) && \
4791 !defined(setjmp_undefined_for_msvc)
4792 # pragma push_macro("setjmp")
4794 # define setjmp_undefined_for_msvc
4797 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4798 /// we want to emit this as a call to a named external function, return the name
4799 /// otherwise lower it and return null.
4801 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4802 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4803 SDLoc sdl = getCurSDLoc();
4804 DebugLoc dl = getCurDebugLoc();
4807 switch (Intrinsic) {
4809 // By default, turn this into a target intrinsic node.
4810 visitTargetIntrinsic(I, Intrinsic);
4812 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4813 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4814 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4815 case Intrinsic::returnaddress:
4816 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl,
4817 TLI.getPointerTy(DAG.getDataLayout()),
4818 getValue(I.getArgOperand(0))));
4820 case Intrinsic::addressofreturnaddress:
4821 setValue(&I, DAG.getNode(ISD::ADDROFRETURNADDR, sdl,
4822 TLI.getPointerTy(DAG.getDataLayout())));
4824 case Intrinsic::frameaddress:
4825 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl,
4826 TLI.getPointerTy(DAG.getDataLayout()),
4827 getValue(I.getArgOperand(0))));
4829 case Intrinsic::read_register: {
4830 Value *Reg = I.getArgOperand(0);
4831 SDValue Chain = getRoot();
4833 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4834 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4835 Res = DAG.getNode(ISD::READ_REGISTER, sdl,
4836 DAG.getVTList(VT, MVT::Other), Chain, RegName);
4838 DAG.setRoot(Res.getValue(1));
4841 case Intrinsic::write_register: {
4842 Value *Reg = I.getArgOperand(0);
4843 Value *RegValue = I.getArgOperand(1);
4844 SDValue Chain = getRoot();
4846 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4847 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4848 RegName, getValue(RegValue)));
4851 case Intrinsic::setjmp:
4852 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4853 case Intrinsic::longjmp:
4854 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4855 case Intrinsic::memcpy: {
4856 SDValue Op1 = getValue(I.getArgOperand(0));
4857 SDValue Op2 = getValue(I.getArgOperand(1));
4858 SDValue Op3 = getValue(I.getArgOperand(2));
4859 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4861 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4862 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4863 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4864 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4866 MachinePointerInfo(I.getArgOperand(0)),
4867 MachinePointerInfo(I.getArgOperand(1)));
4868 updateDAGForMaybeTailCall(MC);
4871 case Intrinsic::memset: {
4872 SDValue Op1 = getValue(I.getArgOperand(0));
4873 SDValue Op2 = getValue(I.getArgOperand(1));
4874 SDValue Op3 = getValue(I.getArgOperand(2));
4875 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4877 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4878 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4879 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4880 SDValue MS = DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4881 isTC, MachinePointerInfo(I.getArgOperand(0)));
4882 updateDAGForMaybeTailCall(MS);
4885 case Intrinsic::memmove: {
4886 SDValue Op1 = getValue(I.getArgOperand(0));
4887 SDValue Op2 = getValue(I.getArgOperand(1));
4888 SDValue Op3 = getValue(I.getArgOperand(2));
4889 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4891 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4892 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4893 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4894 SDValue MM = DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4895 isTC, MachinePointerInfo(I.getArgOperand(0)),
4896 MachinePointerInfo(I.getArgOperand(1)));
4897 updateDAGForMaybeTailCall(MM);
4900 case Intrinsic::memcpy_element_atomic: {
4901 SDValue Dst = getValue(I.getArgOperand(0));
4902 SDValue Src = getValue(I.getArgOperand(1));
4903 SDValue NumElements = getValue(I.getArgOperand(2));
4904 SDValue ElementSize = getValue(I.getArgOperand(3));
4906 // Emit a library call.
4907 TargetLowering::ArgListTy Args;
4908 TargetLowering::ArgListEntry Entry;
4909 Entry.Ty = DAG.getDataLayout().getIntPtrType(*DAG.getContext());
4911 Args.push_back(Entry);
4914 Args.push_back(Entry);
4916 Entry.Ty = I.getArgOperand(2)->getType();
4917 Entry.Node = NumElements;
4918 Args.push_back(Entry);
4920 Entry.Ty = Type::getInt32Ty(*DAG.getContext());
4921 Entry.Node = ElementSize;
4922 Args.push_back(Entry);
4924 uint64_t ElementSizeConstant =
4925 cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4926 RTLIB::Libcall LibraryCall =
4927 RTLIB::getMEMCPY_ELEMENT_ATOMIC(ElementSizeConstant);
4928 if (LibraryCall == RTLIB::UNKNOWN_LIBCALL)
4929 report_fatal_error("Unsupported element size");
4931 TargetLowering::CallLoweringInfo CLI(DAG);
4932 CLI.setDebugLoc(sdl)
4933 .setChain(getRoot())
4934 .setCallee(TLI.getLibcallCallingConv(LibraryCall),
4935 Type::getVoidTy(*DAG.getContext()),
4936 DAG.getExternalSymbol(
4937 TLI.getLibcallName(LibraryCall),
4938 TLI.getPointerTy(DAG.getDataLayout())),
4941 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
4942 DAG.setRoot(CallResult.second);
4945 case Intrinsic::dbg_declare: {
4946 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4947 DILocalVariable *Variable = DI.getVariable();
4948 DIExpression *Expression = DI.getExpression();
4949 const Value *Address = DI.getAddress();
4950 assert(Variable && "Missing variable");
4952 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4956 // Check if address has undef value.
4957 if (isa<UndefValue>(Address) ||
4958 (Address->use_empty() && !isa<Argument>(Address))) {
4959 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4963 SDValue &N = NodeMap[Address];
4964 if (!N.getNode() && isa<Argument>(Address))
4965 // Check unused arguments map.
4966 N = UnusedArgNodeMap[Address];
4969 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4970 Address = BCI->getOperand(0);
4971 // Parameters are handled specially.
4972 bool isParameter = Variable->isParameter() || isa<Argument>(Address);
4973 auto FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4974 if (isParameter && FINode) {
4975 // Byval parameter. We have a frame index at this point.
4976 SDV = DAG.getFrameIndexDbgValue(Variable, Expression,
4977 FINode->getIndex(), 0, dl, SDNodeOrder);
4978 } else if (isa<Argument>(Address)) {
4979 // Address is an argument, so try to emit its dbg value using
4980 // virtual register info from the FuncInfo.ValueMap.
4981 EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4985 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4986 true, 0, dl, SDNodeOrder);
4988 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4990 // If Address is an argument then try to emit its dbg value using
4991 // virtual register info from the FuncInfo.ValueMap.
4992 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4994 // If variable is pinned by a alloca in dominating bb then
4995 // use StaticAllocaMap.
4996 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4997 if (AI->getParent() != DI.getParent()) {
4998 DenseMap<const AllocaInst*, int>::iterator SI =
4999 FuncInfo.StaticAllocaMap.find(AI);
5000 if (SI != FuncInfo.StaticAllocaMap.end()) {
5001 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
5002 0, dl, SDNodeOrder);
5003 DAG.AddDbgValue(SDV, nullptr, false);
5008 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
5013 case Intrinsic::dbg_value: {
5014 const DbgValueInst &DI = cast<DbgValueInst>(I);
5015 assert(DI.getVariable() && "Missing variable");
5017 DILocalVariable *Variable = DI.getVariable();
5018 DIExpression *Expression = DI.getExpression();
5019 uint64_t Offset = DI.getOffset();
5020 const Value *V = DI.getValue();
5025 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
5026 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
5028 DAG.AddDbgValue(SDV, nullptr, false);
5030 // Do not use getValue() in here; we don't want to generate code at
5031 // this point if it hasn't been done yet.
5032 SDValue N = NodeMap[V];
5033 if (!N.getNode() && isa<Argument>(V))
5034 // Check unused arguments map.
5035 N = UnusedArgNodeMap[V];
5037 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, dl, Offset,
5039 SDV = getDbgValue(N, Variable, Expression, Offset, dl, SDNodeOrder);
5040 DAG.AddDbgValue(SDV, N.getNode(), false);
5042 } else if (!V->use_empty() ) {
5043 // Do not call getValue(V) yet, as we don't want to generate code.
5044 // Remember it for later.
5045 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
5046 DanglingDebugInfoMap[V] = DDI;
5048 // We may expand this to cover more cases. One case where we have no
5049 // data available is an unreferenced parameter.
5050 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
5054 // Build a debug info table entry.
5055 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
5056 V = BCI->getOperand(0);
5057 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
5058 // Don't handle byval struct arguments or VLAs, for example.
5060 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
5061 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
5064 DenseMap<const AllocaInst*, int>::iterator SI =
5065 FuncInfo.StaticAllocaMap.find(AI);
5066 if (SI == FuncInfo.StaticAllocaMap.end())
5067 return nullptr; // VLAs.
5071 case Intrinsic::eh_typeid_for: {
5072 // Find the type id for the given typeinfo.
5073 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
5074 unsigned TypeID = DAG.getMachineFunction().getTypeIDFor(GV);
5075 Res = DAG.getConstant(TypeID, sdl, MVT::i32);
5080 case Intrinsic::eh_return_i32:
5081 case Intrinsic::eh_return_i64:
5082 DAG.getMachineFunction().setCallsEHReturn(true);
5083 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
5086 getValue(I.getArgOperand(0)),
5087 getValue(I.getArgOperand(1))));
5089 case Intrinsic::eh_unwind_init:
5090 DAG.getMachineFunction().setCallsUnwindInit(true);
5092 case Intrinsic::eh_dwarf_cfa: {
5093 setValue(&I, DAG.getNode(ISD::EH_DWARF_CFA, sdl,
5094 TLI.getPointerTy(DAG.getDataLayout()),
5095 getValue(I.getArgOperand(0))));
5098 case Intrinsic::eh_sjlj_callsite: {
5099 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5100 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
5101 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
5102 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
5104 MMI.setCurrentCallSite(CI->getZExtValue());
5107 case Intrinsic::eh_sjlj_functioncontext: {
5108 // Get and store the index of the function context.
5109 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
5111 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
5112 int FI = FuncInfo.StaticAllocaMap[FnCtx];
5113 MFI.setFunctionContextIndex(FI);
5116 case Intrinsic::eh_sjlj_setjmp: {
5119 Ops[1] = getValue(I.getArgOperand(0));
5120 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
5121 DAG.getVTList(MVT::i32, MVT::Other), Ops);
5122 setValue(&I, Op.getValue(0));
5123 DAG.setRoot(Op.getValue(1));
5126 case Intrinsic::eh_sjlj_longjmp: {
5127 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
5128 getRoot(), getValue(I.getArgOperand(0))));
5131 case Intrinsic::eh_sjlj_setup_dispatch: {
5132 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_SETUP_DISPATCH, sdl, MVT::Other,
5137 case Intrinsic::masked_gather:
5138 visitMaskedGather(I);
5140 case Intrinsic::masked_load:
5143 case Intrinsic::masked_scatter:
5144 visitMaskedScatter(I);
5146 case Intrinsic::masked_store:
5147 visitMaskedStore(I);
5149 case Intrinsic::masked_expandload:
5150 visitMaskedLoad(I, true /* IsExpanding */);
5152 case Intrinsic::masked_compressstore:
5153 visitMaskedStore(I, true /* IsCompressing */);
5155 case Intrinsic::x86_mmx_pslli_w:
5156 case Intrinsic::x86_mmx_pslli_d:
5157 case Intrinsic::x86_mmx_pslli_q:
5158 case Intrinsic::x86_mmx_psrli_w:
5159 case Intrinsic::x86_mmx_psrli_d:
5160 case Intrinsic::x86_mmx_psrli_q:
5161 case Intrinsic::x86_mmx_psrai_w:
5162 case Intrinsic::x86_mmx_psrai_d: {
5163 SDValue ShAmt = getValue(I.getArgOperand(1));
5164 if (isa<ConstantSDNode>(ShAmt)) {
5165 visitTargetIntrinsic(I, Intrinsic);
5168 unsigned NewIntrinsic = 0;
5169 EVT ShAmtVT = MVT::v2i32;
5170 switch (Intrinsic) {
5171 case Intrinsic::x86_mmx_pslli_w:
5172 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
5174 case Intrinsic::x86_mmx_pslli_d:
5175 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
5177 case Intrinsic::x86_mmx_pslli_q:
5178 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
5180 case Intrinsic::x86_mmx_psrli_w:
5181 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
5183 case Intrinsic::x86_mmx_psrli_d:
5184 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
5186 case Intrinsic::x86_mmx_psrli_q:
5187 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
5189 case Intrinsic::x86_mmx_psrai_w:
5190 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
5192 case Intrinsic::x86_mmx_psrai_d:
5193 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
5195 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5198 // The vector shift intrinsics with scalars uses 32b shift amounts but
5199 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
5201 // We must do this early because v2i32 is not a legal type.
5204 ShOps[1] = DAG.getConstant(0, sdl, MVT::i32);
5205 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
5206 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
5207 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
5208 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
5209 DAG.getConstant(NewIntrinsic, sdl, MVT::i32),
5210 getValue(I.getArgOperand(0)), ShAmt);
5214 case Intrinsic::powi:
5215 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
5216 getValue(I.getArgOperand(1)), DAG));
5218 case Intrinsic::log:
5219 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5221 case Intrinsic::log2:
5222 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5224 case Intrinsic::log10:
5225 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5227 case Intrinsic::exp:
5228 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5230 case Intrinsic::exp2:
5231 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5233 case Intrinsic::pow:
5234 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
5235 getValue(I.getArgOperand(1)), DAG, TLI));
5237 case Intrinsic::sqrt:
5238 case Intrinsic::fabs:
5239 case Intrinsic::sin:
5240 case Intrinsic::cos:
5241 case Intrinsic::floor:
5242 case Intrinsic::ceil:
5243 case Intrinsic::trunc:
5244 case Intrinsic::rint:
5245 case Intrinsic::nearbyint:
5246 case Intrinsic::round:
5247 case Intrinsic::canonicalize: {
5249 switch (Intrinsic) {
5250 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5251 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
5252 case Intrinsic::fabs: Opcode = ISD::FABS; break;
5253 case Intrinsic::sin: Opcode = ISD::FSIN; break;
5254 case Intrinsic::cos: Opcode = ISD::FCOS; break;
5255 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
5256 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
5257 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
5258 case Intrinsic::rint: Opcode = ISD::FRINT; break;
5259 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
5260 case Intrinsic::round: Opcode = ISD::FROUND; break;
5261 case Intrinsic::canonicalize: Opcode = ISD::FCANONICALIZE; break;
5264 setValue(&I, DAG.getNode(Opcode, sdl,
5265 getValue(I.getArgOperand(0)).getValueType(),
5266 getValue(I.getArgOperand(0))));
5269 case Intrinsic::minnum: {
5270 auto VT = getValue(I.getArgOperand(0)).getValueType();
5272 I.hasNoNaNs() && TLI.isOperationLegalOrCustom(ISD::FMINNAN, VT)
5275 setValue(&I, DAG.getNode(Opc, sdl, VT,
5276 getValue(I.getArgOperand(0)),
5277 getValue(I.getArgOperand(1))));
5280 case Intrinsic::maxnum: {
5281 auto VT = getValue(I.getArgOperand(0)).getValueType();
5283 I.hasNoNaNs() && TLI.isOperationLegalOrCustom(ISD::FMAXNAN, VT)
5286 setValue(&I, DAG.getNode(Opc, sdl, VT,
5287 getValue(I.getArgOperand(0)),
5288 getValue(I.getArgOperand(1))));
5291 case Intrinsic::copysign:
5292 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
5293 getValue(I.getArgOperand(0)).getValueType(),
5294 getValue(I.getArgOperand(0)),
5295 getValue(I.getArgOperand(1))));
5297 case Intrinsic::fma:
5298 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5299 getValue(I.getArgOperand(0)).getValueType(),
5300 getValue(I.getArgOperand(0)),
5301 getValue(I.getArgOperand(1)),
5302 getValue(I.getArgOperand(2))));
5304 case Intrinsic::fmuladd: {
5305 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
5306 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
5307 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
5308 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5309 getValue(I.getArgOperand(0)).getValueType(),
5310 getValue(I.getArgOperand(0)),
5311 getValue(I.getArgOperand(1)),
5312 getValue(I.getArgOperand(2))));
5314 // TODO: Intrinsic calls should have fast-math-flags.
5315 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
5316 getValue(I.getArgOperand(0)).getValueType(),
5317 getValue(I.getArgOperand(0)),
5318 getValue(I.getArgOperand(1)));
5319 SDValue Add = DAG.getNode(ISD::FADD, sdl,
5320 getValue(I.getArgOperand(0)).getValueType(),
5322 getValue(I.getArgOperand(2)));
5327 case Intrinsic::convert_to_fp16:
5328 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
5329 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
5330 getValue(I.getArgOperand(0)),
5331 DAG.getTargetConstant(0, sdl,
5334 case Intrinsic::convert_from_fp16:
5335 setValue(&I, DAG.getNode(ISD::FP_EXTEND, sdl,
5336 TLI.getValueType(DAG.getDataLayout(), I.getType()),
5337 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
5338 getValue(I.getArgOperand(0)))));
5340 case Intrinsic::pcmarker: {
5341 SDValue Tmp = getValue(I.getArgOperand(0));
5342 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
5345 case Intrinsic::readcyclecounter: {
5346 SDValue Op = getRoot();
5347 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
5348 DAG.getVTList(MVT::i64, MVT::Other), Op);
5350 DAG.setRoot(Res.getValue(1));
5353 case Intrinsic::bitreverse:
5354 setValue(&I, DAG.getNode(ISD::BITREVERSE, sdl,
5355 getValue(I.getArgOperand(0)).getValueType(),
5356 getValue(I.getArgOperand(0))));
5358 case Intrinsic::bswap:
5359 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
5360 getValue(I.getArgOperand(0)).getValueType(),
5361 getValue(I.getArgOperand(0))));
5363 case Intrinsic::cttz: {
5364 SDValue Arg = getValue(I.getArgOperand(0));
5365 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5366 EVT Ty = Arg.getValueType();
5367 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
5371 case Intrinsic::ctlz: {
5372 SDValue Arg = getValue(I.getArgOperand(0));
5373 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5374 EVT Ty = Arg.getValueType();
5375 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
5379 case Intrinsic::ctpop: {
5380 SDValue Arg = getValue(I.getArgOperand(0));
5381 EVT Ty = Arg.getValueType();
5382 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
5385 case Intrinsic::stacksave: {
5386 SDValue Op = getRoot();
5388 ISD::STACKSAVE, sdl,
5389 DAG.getVTList(TLI.getPointerTy(DAG.getDataLayout()), MVT::Other), Op);
5391 DAG.setRoot(Res.getValue(1));
5394 case Intrinsic::stackrestore: {
5395 Res = getValue(I.getArgOperand(0));
5396 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
5399 case Intrinsic::get_dynamic_area_offset: {
5400 SDValue Op = getRoot();
5401 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
5402 EVT ResTy = TLI.getValueType(DAG.getDataLayout(), I.getType());
5403 // Result type for @llvm.get.dynamic.area.offset should match PtrTy for
5406 report_fatal_error("Wrong result type for @llvm.get.dynamic.area.offset"
5408 Res = DAG.getNode(ISD::GET_DYNAMIC_AREA_OFFSET, sdl, DAG.getVTList(ResTy),
5414 case Intrinsic::stackguard: {
5415 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
5416 MachineFunction &MF = DAG.getMachineFunction();
5417 const Module &M = *MF.getFunction()->getParent();
5418 SDValue Chain = getRoot();
5419 if (TLI.useLoadStackGuardNode()) {
5420 Res = getLoadStackGuard(DAG, sdl, Chain);
5422 const Value *Global = TLI.getSDagStackGuard(M);
5423 unsigned Align = DL->getPrefTypeAlignment(Global->getType());
5424 Res = DAG.getLoad(PtrTy, sdl, Chain, getValue(Global),
5425 MachinePointerInfo(Global, 0), Align,
5426 MachineMemOperand::MOVolatile);
5432 case Intrinsic::stackprotector: {
5433 // Emit code into the DAG to store the stack guard onto the stack.
5434 MachineFunction &MF = DAG.getMachineFunction();
5435 MachineFrameInfo &MFI = MF.getFrameInfo();
5436 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
5437 SDValue Src, Chain = getRoot();
5439 if (TLI.useLoadStackGuardNode())
5440 Src = getLoadStackGuard(DAG, sdl, Chain);
5442 Src = getValue(I.getArgOperand(0)); // The guard's value.
5444 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
5446 int FI = FuncInfo.StaticAllocaMap[Slot];
5447 MFI.setStackProtectorIndex(FI);
5449 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
5451 // Store the stack protector onto the stack.
5452 Res = DAG.getStore(Chain, sdl, Src, FIN, MachinePointerInfo::getFixedStack(
5453 DAG.getMachineFunction(), FI),
5454 /* Alignment = */ 0, MachineMemOperand::MOVolatile);
5459 case Intrinsic::objectsize: {
5460 // If we don't know by now, we're never going to know.
5461 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
5463 assert(CI && "Non-constant type in __builtin_object_size?");
5465 SDValue Arg = getValue(I.getCalledValue());
5466 EVT Ty = Arg.getValueType();
5469 Res = DAG.getConstant(-1ULL, sdl, Ty);
5471 Res = DAG.getConstant(0, sdl, Ty);
5476 case Intrinsic::annotation:
5477 case Intrinsic::ptr_annotation:
5478 case Intrinsic::invariant_group_barrier:
5479 // Drop the intrinsic, but forward the value
5480 setValue(&I, getValue(I.getOperand(0)));
5482 case Intrinsic::assume:
5483 case Intrinsic::var_annotation:
5484 // Discard annotate attributes and assumptions
5487 case Intrinsic::init_trampoline: {
5488 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5492 Ops[1] = getValue(I.getArgOperand(0));
5493 Ops[2] = getValue(I.getArgOperand(1));
5494 Ops[3] = getValue(I.getArgOperand(2));
5495 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5496 Ops[5] = DAG.getSrcValue(F);
5498 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
5503 case Intrinsic::adjust_trampoline: {
5504 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
5505 TLI.getPointerTy(DAG.getDataLayout()),
5506 getValue(I.getArgOperand(0))));
5509 case Intrinsic::gcroot: {
5510 MachineFunction &MF = DAG.getMachineFunction();
5511 const Function *F = MF.getFunction();
5513 assert(F->hasGC() &&
5514 "only valid in functions with gc specified, enforced by Verifier");
5515 assert(GFI && "implied by previous");
5516 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5517 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5519 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5520 GFI->addStackRoot(FI->getIndex(), TypeMap);
5523 case Intrinsic::gcread:
5524 case Intrinsic::gcwrite:
5525 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5526 case Intrinsic::flt_rounds:
5527 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
5530 case Intrinsic::expect: {
5531 // Just replace __builtin_expect(exp, c) with EXP.
5532 setValue(&I, getValue(I.getArgOperand(0)));
5536 case Intrinsic::debugtrap:
5537 case Intrinsic::trap: {
5538 StringRef TrapFuncName =
5540 .getAttribute(AttributeSet::FunctionIndex, "trap-func-name")
5541 .getValueAsString();
5542 if (TrapFuncName.empty()) {
5543 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
5544 ISD::TRAP : ISD::DEBUGTRAP;
5545 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
5548 TargetLowering::ArgListTy Args;
5550 TargetLowering::CallLoweringInfo CLI(DAG);
5551 CLI.setDebugLoc(sdl).setChain(getRoot()).setCallee(
5552 CallingConv::C, I.getType(),
5553 DAG.getExternalSymbol(TrapFuncName.data(),
5554 TLI.getPointerTy(DAG.getDataLayout())),
5557 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5558 DAG.setRoot(Result.second);
5562 case Intrinsic::uadd_with_overflow:
5563 case Intrinsic::sadd_with_overflow:
5564 case Intrinsic::usub_with_overflow:
5565 case Intrinsic::ssub_with_overflow:
5566 case Intrinsic::umul_with_overflow:
5567 case Intrinsic::smul_with_overflow: {
5569 switch (Intrinsic) {
5570 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5571 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5572 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5573 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5574 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5575 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5576 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5578 SDValue Op1 = getValue(I.getArgOperand(0));
5579 SDValue Op2 = getValue(I.getArgOperand(1));
5581 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5582 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
5585 case Intrinsic::prefetch: {
5587 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5589 Ops[1] = getValue(I.getArgOperand(0));
5590 Ops[2] = getValue(I.getArgOperand(1));
5591 Ops[3] = getValue(I.getArgOperand(2));
5592 Ops[4] = getValue(I.getArgOperand(3));
5593 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
5594 DAG.getVTList(MVT::Other), Ops,
5595 EVT::getIntegerVT(*Context, 8),
5596 MachinePointerInfo(I.getArgOperand(0)),
5598 false, /* volatile */
5600 rw==1)); /* write */
5603 case Intrinsic::lifetime_start:
5604 case Intrinsic::lifetime_end: {
5605 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5606 // Stack coloring is not enabled in O0, discard region information.
5607 if (TM.getOptLevel() == CodeGenOpt::None)
5610 SmallVector<Value *, 4> Allocas;
5611 GetUnderlyingObjects(I.getArgOperand(1), Allocas, *DL);
5613 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
5614 E = Allocas.end(); Object != E; ++Object) {
5615 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5617 // Could not find an Alloca.
5618 if (!LifetimeObject)
5621 // First check that the Alloca is static, otherwise it won't have a
5622 // valid frame index.
5623 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
5624 if (SI == FuncInfo.StaticAllocaMap.end())
5627 int FI = SI->second;
5632 DAG.getFrameIndex(FI, TLI.getPointerTy(DAG.getDataLayout()), true);
5633 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5635 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
5640 case Intrinsic::invariant_start:
5641 // Discard region information.
5642 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
5644 case Intrinsic::invariant_end:
5645 // Discard region information.
5647 case Intrinsic::clear_cache:
5648 return TLI.getClearCacheBuiltinName();
5649 case Intrinsic::donothing:
5652 case Intrinsic::experimental_stackmap: {
5656 case Intrinsic::experimental_patchpoint_void:
5657 case Intrinsic::experimental_patchpoint_i64: {
5658 visitPatchpoint(&I);
5661 case Intrinsic::experimental_gc_statepoint: {
5662 LowerStatepoint(ImmutableStatepoint(&I));
5665 case Intrinsic::experimental_gc_result: {
5666 visitGCResult(cast<GCResultInst>(I));
5669 case Intrinsic::experimental_gc_relocate: {
5670 visitGCRelocate(cast<GCRelocateInst>(I));
5673 case Intrinsic::instrprof_increment:
5674 llvm_unreachable("instrprof failed to lower an increment");
5675 case Intrinsic::instrprof_value_profile:
5676 llvm_unreachable("instrprof failed to lower a value profiling call");
5677 case Intrinsic::localescape: {
5678 MachineFunction &MF = DAG.getMachineFunction();
5679 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
5681 // Directly emit some LOCAL_ESCAPE machine instrs. Label assignment emission
5682 // is the same on all targets.
5683 for (unsigned Idx = 0, E = I.getNumArgOperands(); Idx < E; ++Idx) {
5684 Value *Arg = I.getArgOperand(Idx)->stripPointerCasts();
5685 if (isa<ConstantPointerNull>(Arg))
5686 continue; // Skip null pointers. They represent a hole in index space.
5687 AllocaInst *Slot = cast<AllocaInst>(Arg);
5688 assert(FuncInfo.StaticAllocaMap.count(Slot) &&
5689 "can only escape static allocas");
5690 int FI = FuncInfo.StaticAllocaMap[Slot];
5691 MCSymbol *FrameAllocSym =
5692 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5693 GlobalValue::getRealLinkageName(MF.getName()), Idx);
5694 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
5695 TII->get(TargetOpcode::LOCAL_ESCAPE))
5696 .addSym(FrameAllocSym)
5703 case Intrinsic::localrecover: {
5704 // i8* @llvm.localrecover(i8* %fn, i8* %fp, i32 %idx)
5705 MachineFunction &MF = DAG.getMachineFunction();
5706 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout(), 0);
5708 // Get the symbol that defines the frame offset.
5709 auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
5710 auto *Idx = cast<ConstantInt>(I.getArgOperand(2));
5711 unsigned IdxVal = unsigned(Idx->getLimitedValue(INT_MAX));
5712 MCSymbol *FrameAllocSym =
5713 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5714 GlobalValue::getRealLinkageName(Fn->getName()), IdxVal);
5716 // Create a MCSymbol for the label to avoid any target lowering
5717 // that would make this PC relative.
5718 SDValue OffsetSym = DAG.getMCSymbol(FrameAllocSym, PtrVT);
5720 DAG.getNode(ISD::LOCAL_RECOVER, sdl, PtrVT, OffsetSym);
5722 // Add the offset to the FP.
5723 Value *FP = I.getArgOperand(1);
5724 SDValue FPVal = getValue(FP);
5725 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
5731 case Intrinsic::eh_exceptionpointer:
5732 case Intrinsic::eh_exceptioncode: {
5733 // Get the exception pointer vreg, copy from it, and resize it to fit.
5734 const auto *CPI = cast<CatchPadInst>(I.getArgOperand(0));
5735 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
5736 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT);
5737 unsigned VReg = FuncInfo.getCatchPadExceptionPointerVReg(CPI, PtrRC);
5739 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), VReg, PtrVT);
5740 if (Intrinsic == Intrinsic::eh_exceptioncode)
5741 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), MVT::i32);
5746 case Intrinsic::experimental_deoptimize:
5747 LowerDeoptimizeCall(&I);
5752 std::pair<SDValue, SDValue>
5753 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
5754 const BasicBlock *EHPadBB) {
5755 MachineFunction &MF = DAG.getMachineFunction();
5756 MachineModuleInfo &MMI = MF.getMMI();
5757 MCSymbol *BeginLabel = nullptr;
5760 // Insert a label before the invoke call to mark the try range. This can be
5761 // used to detect deletion of the invoke via the MachineModuleInfo.
5762 BeginLabel = MMI.getContext().createTempSymbol();
5764 // For SjLj, keep track of which landing pads go with which invokes
5765 // so as to maintain the ordering of pads in the LSDA.
5766 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5767 if (CallSiteIndex) {
5768 MF.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5769 LPadToCallSiteMap[FuncInfo.MBBMap[EHPadBB]].push_back(CallSiteIndex);
5771 // Now that the call site is handled, stop tracking it.
5772 MMI.setCurrentCallSite(0);
5775 // Both PendingLoads and PendingExports must be flushed here;
5776 // this call might not return.
5778 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5780 CLI.setChain(getRoot());
5782 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5783 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5785 assert((CLI.IsTailCall || Result.second.getNode()) &&
5786 "Non-null chain expected with non-tail call!");
5787 assert((Result.second.getNode() || !Result.first.getNode()) &&
5788 "Null value expected with tail call!");
5790 if (!Result.second.getNode()) {
5791 // As a special case, a null chain means that a tail call has been emitted
5792 // and the DAG root is already updated.
5795 // Since there's no actual continuation from this block, nothing can be
5796 // relying on us setting vregs for them.
5797 PendingExports.clear();
5799 DAG.setRoot(Result.second);
5803 // Insert a label at the end of the invoke call to mark the try range. This
5804 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5805 MCSymbol *EndLabel = MMI.getContext().createTempSymbol();
5806 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5808 // Inform MachineModuleInfo of range.
5809 if (MF.hasEHFunclets()) {
5811 WinEHFuncInfo *EHInfo = DAG.getMachineFunction().getWinEHFuncInfo();
5812 EHInfo->addIPToStateRange(cast<InvokeInst>(CLI.CS->getInstruction()),
5813 BeginLabel, EndLabel);
5815 MF.addInvoke(FuncInfo.MBBMap[EHPadBB], BeginLabel, EndLabel);
5822 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5824 const BasicBlock *EHPadBB) {
5825 auto &DL = DAG.getDataLayout();
5826 FunctionType *FTy = CS.getFunctionType();
5827 Type *RetTy = CS.getType();
5829 TargetLowering::ArgListTy Args;
5830 TargetLowering::ArgListEntry Entry;
5831 Args.reserve(CS.arg_size());
5833 const Value *SwiftErrorVal = nullptr;
5834 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5835 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5837 const Value *V = *i;
5840 if (V->getType()->isEmptyTy())
5843 SDValue ArgNode = getValue(V);
5844 Entry.Node = ArgNode; Entry.Ty = V->getType();
5846 // Skip the first return-type Attribute to get to params.
5847 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5849 // Use swifterror virtual register as input to the call.
5850 if (Entry.isSwiftError && TLI.supportSwiftError()) {
5852 // We find the virtual register for the actual swifterror argument.
5853 // Instead of using the Value, we use the virtual register instead.
5855 DAG.getRegister(FuncInfo.getOrCreateSwiftErrorVReg(FuncInfo.MBB, V),
5856 EVT(TLI.getPointerTy(DL)));
5859 Args.push_back(Entry);
5861 // If we have an explicit sret argument that is an Instruction, (i.e., it
5862 // might point to function-local memory), we can't meaningfully tail-call.
5863 if (Entry.isSRet && isa<Instruction>(V))
5867 // Check if target-independent constraints permit a tail call here.
5868 // Target-dependent constraints are checked within TLI->LowerCallTo.
5869 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5872 // Disable tail calls if there is an swifterror argument. Targets have not
5873 // been updated to support tail calls.
5874 if (TLI.supportSwiftError() && SwiftErrorVal)
5877 TargetLowering::CallLoweringInfo CLI(DAG);
5878 CLI.setDebugLoc(getCurSDLoc())
5879 .setChain(getRoot())
5880 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5881 .setTailCall(isTailCall)
5882 .setConvergent(CS.isConvergent());
5883 std::pair<SDValue, SDValue> Result = lowerInvokable(CLI, EHPadBB);
5885 if (Result.first.getNode()) {
5886 const Instruction *Inst = CS.getInstruction();
5887 Result.first = lowerRangeToAssertZExt(DAG, *Inst, Result.first);
5888 setValue(Inst, Result.first);
5891 // The last element of CLI.InVals has the SDValue for swifterror return.
5892 // Here we copy it to a virtual register and update SwiftErrorMap for
5894 if (SwiftErrorVal && TLI.supportSwiftError()) {
5895 // Get the last element of InVals.
5896 SDValue Src = CLI.InVals.back();
5897 const TargetRegisterClass *RC = TLI.getRegClassFor(TLI.getPointerTy(DL));
5898 unsigned VReg = FuncInfo.MF->getRegInfo().createVirtualRegister(RC);
5899 SDValue CopyNode = CLI.DAG.getCopyToReg(Result.second, CLI.DL, VReg, Src);
5900 // We update the virtual register for the actual swifterror argument.
5901 FuncInfo.setCurrentSwiftErrorVReg(FuncInfo.MBB, SwiftErrorVal, VReg);
5902 DAG.setRoot(CopyNode);
5906 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5907 /// value is equal or not-equal to zero.
5908 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5909 for (const User *U : V->users()) {
5910 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5911 if (IC->isEquality())
5912 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5913 if (C->isNullValue())
5915 // Unknown instruction.
5921 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5923 SelectionDAGBuilder &Builder) {
5925 // Check to see if this load can be trivially constant folded, e.g. if the
5926 // input is from a string literal.
5927 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5928 // Cast pointer to the type we really want to load.
5929 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5930 PointerType::getUnqual(LoadTy));
5932 if (const Constant *LoadCst = ConstantFoldLoadFromConstPtr(
5933 const_cast<Constant *>(LoadInput), LoadTy, *Builder.DL))
5934 return Builder.getValue(LoadCst);
5937 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5938 // still constant memory, the input chain can be the entry node.
5940 bool ConstantMemory = false;
5942 // Do not serialize (non-volatile) loads of constant memory with anything.
5943 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5944 Root = Builder.DAG.getEntryNode();
5945 ConstantMemory = true;
5947 // Do not serialize non-volatile loads against each other.
5948 Root = Builder.DAG.getRoot();
5951 SDValue Ptr = Builder.getValue(PtrVal);
5952 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5953 Ptr, MachinePointerInfo(PtrVal),
5954 /* Alignment = */ 1);
5956 if (!ConstantMemory)
5957 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5961 /// processIntegerCallValue - Record the value for an instruction that
5962 /// produces an integer result, converting the type where necessary.
5963 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5966 EVT VT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5969 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5971 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5972 setValue(&I, Value);
5975 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5976 /// If so, return true and lower it, otherwise return false and it will be
5977 /// lowered like a normal call.
5978 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5979 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5980 if (I.getNumArgOperands() != 3)
5983 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5984 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5985 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5986 !I.getType()->isIntegerTy())
5989 const Value *Size = I.getArgOperand(2);
5990 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5991 if (CSize && CSize->getZExtValue() == 0) {
5992 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5994 setValue(&I, DAG.getConstant(0, getCurSDLoc(), CallVT));
5998 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
5999 std::pair<SDValue, SDValue> Res =
6000 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
6001 getValue(LHS), getValue(RHS), getValue(Size),
6002 MachinePointerInfo(LHS),
6003 MachinePointerInfo(RHS));
6004 if (Res.first.getNode()) {
6005 processIntegerCallValue(I, Res.first, true);
6006 PendingLoads.push_back(Res.second);
6010 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
6011 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
6012 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
6013 bool ActuallyDoIt = true;
6016 switch (CSize->getZExtValue()) {
6018 LoadVT = MVT::Other;
6020 ActuallyDoIt = false;
6024 LoadTy = Type::getInt16Ty(CSize->getContext());
6028 LoadTy = Type::getInt32Ty(CSize->getContext());
6032 LoadTy = Type::getInt64Ty(CSize->getContext());
6036 LoadVT = MVT::v4i32;
6037 LoadTy = Type::getInt32Ty(CSize->getContext());
6038 LoadTy = VectorType::get(LoadTy, 4);
6043 // This turns into unaligned loads. We only do this if the target natively
6044 // supports the MVT we'll be loading or if it is small enough (<= 4) that
6045 // we'll only produce a small number of byte loads.
6047 // Require that we can find a legal MVT, and only do this if the target
6048 // supports unaligned loads of that type. Expanding into byte loads would
6050 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6051 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
6052 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
6053 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
6054 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
6055 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
6056 // TODO: Check alignment of src and dest ptrs.
6057 if (!TLI.isTypeLegal(LoadVT) ||
6058 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
6059 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
6060 ActuallyDoIt = false;
6064 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
6065 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
6067 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
6069 processIntegerCallValue(I, Res, false);
6078 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
6079 /// form. If so, return true and lower it, otherwise return false and it
6080 /// will be lowered like a normal call.
6081 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
6082 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
6083 if (I.getNumArgOperands() != 3)
6086 const Value *Src = I.getArgOperand(0);
6087 const Value *Char = I.getArgOperand(1);
6088 const Value *Length = I.getArgOperand(2);
6089 if (!Src->getType()->isPointerTy() ||
6090 !Char->getType()->isIntegerTy() ||
6091 !Length->getType()->isIntegerTy() ||
6092 !I.getType()->isPointerTy())
6095 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
6096 std::pair<SDValue, SDValue> Res =
6097 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
6098 getValue(Src), getValue(Char), getValue(Length),
6099 MachinePointerInfo(Src));
6100 if (Res.first.getNode()) {
6101 setValue(&I, Res.first);
6102 PendingLoads.push_back(Res.second);
6110 /// visitMemPCpyCall -- lower a mempcpy call as a memcpy followed by code to
6111 /// to adjust the dst pointer by the size of the copied memory.
6112 bool SelectionDAGBuilder::visitMemPCpyCall(const CallInst &I) {
6114 // Verify argument count: void *mempcpy(void *, const void *, size_t)
6115 if (I.getNumArgOperands() != 3)
6118 SDValue Dst = getValue(I.getArgOperand(0));
6119 SDValue Src = getValue(I.getArgOperand(1));
6120 SDValue Size = getValue(I.getArgOperand(2));
6122 unsigned DstAlign = DAG.InferPtrAlignment(Dst);
6123 unsigned SrcAlign = DAG.InferPtrAlignment(Src);
6124 unsigned Align = std::min(DstAlign, SrcAlign);
6125 if (Align == 0) // Alignment of one or both could not be inferred.
6126 Align = 1; // 0 and 1 both specify no alignment, but 0 is reserved.
6129 SDLoc sdl = getCurSDLoc();
6131 // In the mempcpy context we need to pass in a false value for isTailCall
6132 // because the return pointer needs to be adjusted by the size of
6133 // the copied memory.
6134 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Dst, Src, Size, Align, isVol,
6135 false, /*isTailCall=*/false,
6136 MachinePointerInfo(I.getArgOperand(0)),
6137 MachinePointerInfo(I.getArgOperand(1)));
6138 assert(MC.getNode() != nullptr &&
6139 "** memcpy should not be lowered as TailCall in mempcpy context **");
6142 // Check if Size needs to be truncated or extended.
6143 Size = DAG.getSExtOrTrunc(Size, sdl, Dst.getValueType());
6145 // Adjust return pointer to point just past the last dst byte.
6146 SDValue DstPlusSize = DAG.getNode(ISD::ADD, sdl, Dst.getValueType(),
6148 setValue(&I, DstPlusSize);
6152 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
6153 /// optimized form. If so, return true and lower it, otherwise return false
6154 /// and it will be lowered like a normal call.
6155 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
6156 // Verify that the prototype makes sense. char *strcpy(char *, char *)
6157 if (I.getNumArgOperands() != 2)
6160 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
6161 if (!Arg0->getType()->isPointerTy() ||
6162 !Arg1->getType()->isPointerTy() ||
6163 !I.getType()->isPointerTy())
6166 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
6167 std::pair<SDValue, SDValue> Res =
6168 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
6169 getValue(Arg0), getValue(Arg1),
6170 MachinePointerInfo(Arg0),
6171 MachinePointerInfo(Arg1), isStpcpy);
6172 if (Res.first.getNode()) {
6173 setValue(&I, Res.first);
6174 DAG.setRoot(Res.second);
6181 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
6182 /// If so, return true and lower it, otherwise return false and it will be
6183 /// lowered like a normal call.
6184 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
6185 // Verify that the prototype makes sense. int strcmp(void*,void*)
6186 if (I.getNumArgOperands() != 2)
6189 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
6190 if (!Arg0->getType()->isPointerTy() ||
6191 !Arg1->getType()->isPointerTy() ||
6192 !I.getType()->isIntegerTy())
6195 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
6196 std::pair<SDValue, SDValue> Res =
6197 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
6198 getValue(Arg0), getValue(Arg1),
6199 MachinePointerInfo(Arg0),
6200 MachinePointerInfo(Arg1));
6201 if (Res.first.getNode()) {
6202 processIntegerCallValue(I, Res.first, true);
6203 PendingLoads.push_back(Res.second);
6210 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
6211 /// form. If so, return true and lower it, otherwise return false and it
6212 /// will be lowered like a normal call.
6213 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
6214 // Verify that the prototype makes sense. size_t strlen(char *)
6215 if (I.getNumArgOperands() != 1)
6218 const Value *Arg0 = I.getArgOperand(0);
6219 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
6222 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
6223 std::pair<SDValue, SDValue> Res =
6224 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
6225 getValue(Arg0), MachinePointerInfo(Arg0));
6226 if (Res.first.getNode()) {
6227 processIntegerCallValue(I, Res.first, false);
6228 PendingLoads.push_back(Res.second);
6235 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
6236 /// form. If so, return true and lower it, otherwise return false and it
6237 /// will be lowered like a normal call.
6238 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
6239 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
6240 if (I.getNumArgOperands() != 2)
6243 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
6244 if (!Arg0->getType()->isPointerTy() ||
6245 !Arg1->getType()->isIntegerTy() ||
6246 !I.getType()->isIntegerTy())
6249 const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
6250 std::pair<SDValue, SDValue> Res =
6251 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
6252 getValue(Arg0), getValue(Arg1),
6253 MachinePointerInfo(Arg0));
6254 if (Res.first.getNode()) {
6255 processIntegerCallValue(I, Res.first, false);
6256 PendingLoads.push_back(Res.second);
6263 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
6264 /// operation (as expected), translate it to an SDNode with the specified opcode
6265 /// and return true.
6266 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
6268 // Sanity check that it really is a unary floating-point call.
6269 if (I.getNumArgOperands() != 1 ||
6270 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
6271 I.getType() != I.getArgOperand(0)->getType() ||
6272 !I.onlyReadsMemory())
6275 SDValue Tmp = getValue(I.getArgOperand(0));
6276 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
6280 /// visitBinaryFloatCall - If a call instruction is a binary floating-point
6281 /// operation (as expected), translate it to an SDNode with the specified opcode
6282 /// and return true.
6283 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
6285 // Sanity check that it really is a binary floating-point call.
6286 if (I.getNumArgOperands() != 2 ||
6287 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
6288 I.getType() != I.getArgOperand(0)->getType() ||
6289 I.getType() != I.getArgOperand(1)->getType() ||
6290 !I.onlyReadsMemory())
6293 SDValue Tmp0 = getValue(I.getArgOperand(0));
6294 SDValue Tmp1 = getValue(I.getArgOperand(1));
6295 EVT VT = Tmp0.getValueType();
6296 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
6300 void SelectionDAGBuilder::visitCall(const CallInst &I) {
6301 // Handle inline assembly differently.
6302 if (isa<InlineAsm>(I.getCalledValue())) {
6307 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
6308 computeUsesVAFloatArgument(I, MMI);
6310 const char *RenameFn = nullptr;
6311 if (Function *F = I.getCalledFunction()) {
6312 if (F->isDeclaration()) {
6313 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
6314 if (unsigned IID = II->getIntrinsicID(F)) {
6315 RenameFn = visitIntrinsicCall(I, IID);
6320 if (Intrinsic::ID IID = F->getIntrinsicID()) {
6321 RenameFn = visitIntrinsicCall(I, IID);
6327 // Check for well-known libc/libm calls. If the function is internal, it
6328 // can't be a library call. Don't do the check if marked as nobuiltin for
6331 if (!I.isNoBuiltin() && !F->hasLocalLinkage() && F->hasName() &&
6332 LibInfo->getLibFunc(F->getName(), Func) &&
6333 LibInfo->hasOptimizedCodeGen(Func)) {
6336 case LibFunc::copysign:
6337 case LibFunc::copysignf:
6338 case LibFunc::copysignl:
6339 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
6340 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
6341 I.getType() == I.getArgOperand(0)->getType() &&
6342 I.getType() == I.getArgOperand(1)->getType() &&
6343 I.onlyReadsMemory()) {
6344 SDValue LHS = getValue(I.getArgOperand(0));
6345 SDValue RHS = getValue(I.getArgOperand(1));
6346 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
6347 LHS.getValueType(), LHS, RHS));
6352 case LibFunc::fabsf:
6353 case LibFunc::fabsl:
6354 if (visitUnaryFloatCall(I, ISD::FABS))
6358 case LibFunc::fminf:
6359 case LibFunc::fminl:
6360 if (visitBinaryFloatCall(I, ISD::FMINNUM))
6364 case LibFunc::fmaxf:
6365 case LibFunc::fmaxl:
6366 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
6372 if (visitUnaryFloatCall(I, ISD::FSIN))
6378 if (visitUnaryFloatCall(I, ISD::FCOS))
6382 case LibFunc::sqrtf:
6383 case LibFunc::sqrtl:
6384 case LibFunc::sqrt_finite:
6385 case LibFunc::sqrtf_finite:
6386 case LibFunc::sqrtl_finite:
6387 if (visitUnaryFloatCall(I, ISD::FSQRT))
6390 case LibFunc::floor:
6391 case LibFunc::floorf:
6392 case LibFunc::floorl:
6393 if (visitUnaryFloatCall(I, ISD::FFLOOR))
6396 case LibFunc::nearbyint:
6397 case LibFunc::nearbyintf:
6398 case LibFunc::nearbyintl:
6399 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
6403 case LibFunc::ceilf:
6404 case LibFunc::ceill:
6405 if (visitUnaryFloatCall(I, ISD::FCEIL))
6409 case LibFunc::rintf:
6410 case LibFunc::rintl:
6411 if (visitUnaryFloatCall(I, ISD::FRINT))
6414 case LibFunc::round:
6415 case LibFunc::roundf:
6416 case LibFunc::roundl:
6417 if (visitUnaryFloatCall(I, ISD::FROUND))
6420 case LibFunc::trunc:
6421 case LibFunc::truncf:
6422 case LibFunc::truncl:
6423 if (visitUnaryFloatCall(I, ISD::FTRUNC))
6427 case LibFunc::log2f:
6428 case LibFunc::log2l:
6429 if (visitUnaryFloatCall(I, ISD::FLOG2))
6433 case LibFunc::exp2f:
6434 case LibFunc::exp2l:
6435 if (visitUnaryFloatCall(I, ISD::FEXP2))
6438 case LibFunc::memcmp:
6439 if (visitMemCmpCall(I))
6442 case LibFunc::mempcpy:
6443 if (visitMemPCpyCall(I))
6446 case LibFunc::memchr:
6447 if (visitMemChrCall(I))
6450 case LibFunc::strcpy:
6451 if (visitStrCpyCall(I, false))
6454 case LibFunc::stpcpy:
6455 if (visitStrCpyCall(I, true))
6458 case LibFunc::strcmp:
6459 if (visitStrCmpCall(I))
6462 case LibFunc::strlen:
6463 if (visitStrLenCall(I))
6466 case LibFunc::strnlen:
6467 if (visitStrNLenCall(I))
6476 Callee = getValue(I.getCalledValue());
6478 Callee = DAG.getExternalSymbol(
6480 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()));
6482 // Deopt bundles are lowered in LowerCallSiteWithDeoptBundle, and we don't
6483 // have to do anything here to lower funclet bundles.
6484 assert(!I.hasOperandBundlesOtherThan(
6485 {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) &&
6486 "Cannot lower calls with arbitrary operand bundles!");
6488 if (I.countOperandBundlesOfType(LLVMContext::OB_deopt))
6489 LowerCallSiteWithDeoptBundle(&I, Callee, nullptr);
6491 // Check if we can potentially perform a tail call. More detailed checking
6492 // is be done within LowerCallTo, after more information about the call is
6494 LowerCallTo(&I, Callee, I.isTailCall());
6499 /// AsmOperandInfo - This contains information for each constraint that we are
6501 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
6503 /// CallOperand - If this is the result output operand or a clobber
6504 /// this is null, otherwise it is the incoming operand to the CallInst.
6505 /// This gets modified as the asm is processed.
6506 SDValue CallOperand;
6508 /// AssignedRegs - If this is a register or register class operand, this
6509 /// contains the set of register corresponding to the operand.
6510 RegsForValue AssignedRegs;
6512 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
6513 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
6516 /// Whether or not this operand accesses memory
6517 bool hasMemory(const TargetLowering &TLI) const {
6518 // Indirect operand accesses access memory.
6522 for (const auto &Code : Codes)
6523 if (TLI.getConstraintType(Code) == TargetLowering::C_Memory)
6529 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
6530 /// corresponds to. If there is no Value* for this operand, it returns
6532 EVT getCallOperandValEVT(LLVMContext &Context, const TargetLowering &TLI,
6533 const DataLayout &DL) const {
6534 if (!CallOperandVal) return MVT::Other;
6536 if (isa<BasicBlock>(CallOperandVal))
6537 return TLI.getPointerTy(DL);
6539 llvm::Type *OpTy = CallOperandVal->getType();
6541 // FIXME: code duplicated from TargetLowering::ParseConstraints().
6542 // If this is an indirect operand, the operand is a pointer to the
6545 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
6547 report_fatal_error("Indirect operand for inline asm not a pointer!");
6548 OpTy = PtrTy->getElementType();
6551 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
6552 if (StructType *STy = dyn_cast<StructType>(OpTy))
6553 if (STy->getNumElements() == 1)
6554 OpTy = STy->getElementType(0);
6556 // If OpTy is not a single value, it may be a struct/union that we
6557 // can tile with integers.
6558 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
6559 unsigned BitSize = DL.getTypeSizeInBits(OpTy);
6568 OpTy = IntegerType::get(Context, BitSize);
6573 return TLI.getValueType(DL, OpTy, true);
6577 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
6579 } // end anonymous namespace
6581 /// Make sure that the output operand \p OpInfo and its corresponding input
6582 /// operand \p MatchingOpInfo have compatible constraint types (otherwise error
6584 static void patchMatchingInput(const SDISelAsmOperandInfo &OpInfo,
6585 SDISelAsmOperandInfo &MatchingOpInfo,
6586 SelectionDAG &DAG) {
6587 if (OpInfo.ConstraintVT == MatchingOpInfo.ConstraintVT)
6590 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
6591 const auto &TLI = DAG.getTargetLoweringInfo();
6593 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
6594 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
6595 OpInfo.ConstraintVT);
6596 std::pair<unsigned, const TargetRegisterClass *> InputRC =
6597 TLI.getRegForInlineAsmConstraint(TRI, MatchingOpInfo.ConstraintCode,
6598 MatchingOpInfo.ConstraintVT);
6599 if ((OpInfo.ConstraintVT.isInteger() !=
6600 MatchingOpInfo.ConstraintVT.isInteger()) ||
6601 (MatchRC.second != InputRC.second)) {
6602 // FIXME: error out in a more elegant fashion
6603 report_fatal_error("Unsupported asm: input constraint"
6604 " with a matching output constraint of"
6605 " incompatible type!");
6607 MatchingOpInfo.ConstraintVT = OpInfo.ConstraintVT;
6610 /// Get a direct memory input to behave well as an indirect operand.
6611 /// This may introduce stores, hence the need for a \p Chain.
6612 /// \return The (possibly updated) chain.
6613 static SDValue getAddressForMemoryInput(SDValue Chain, const SDLoc &Location,
6614 SDISelAsmOperandInfo &OpInfo,
6615 SelectionDAG &DAG) {
6616 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6618 // If we don't have an indirect input, put it in the constpool if we can,
6619 // otherwise spill it to a stack slot.
6620 // TODO: This isn't quite right. We need to handle these according to
6621 // the addressing mode that the constraint wants. Also, this may take
6622 // an additional register for the computation and we don't want that
6625 // If the operand is a float, integer, or vector constant, spill to a
6626 // constant pool entry to get its address.
6627 const Value *OpVal = OpInfo.CallOperandVal;
6628 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6629 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6630 OpInfo.CallOperand = DAG.getConstantPool(
6631 cast<Constant>(OpVal), TLI.getPointerTy(DAG.getDataLayout()));
6635 // Otherwise, create a stack slot and emit a store to it before the asm.
6636 Type *Ty = OpVal->getType();
6637 auto &DL = DAG.getDataLayout();
6638 uint64_t TySize = DL.getTypeAllocSize(Ty);
6639 unsigned Align = DL.getPrefTypeAlignment(Ty);
6640 MachineFunction &MF = DAG.getMachineFunction();
6641 int SSFI = MF.getFrameInfo().CreateStackObject(TySize, Align, false);
6642 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy(DL));
6643 Chain = DAG.getStore(Chain, Location, OpInfo.CallOperand, StackSlot,
6644 MachinePointerInfo::getFixedStack(MF, SSFI));
6645 OpInfo.CallOperand = StackSlot;
6650 /// GetRegistersForValue - Assign registers (virtual or physical) for the
6651 /// specified operand. We prefer to assign virtual registers, to allow the
6652 /// register allocator to handle the assignment process. However, if the asm
6653 /// uses features that we can't model on machineinstrs, we have SDISel do the
6654 /// allocation. This produces generally horrible, but correct, code.
6656 /// OpInfo describes the operand.
6658 static void GetRegistersForValue(SelectionDAG &DAG, const TargetLowering &TLI,
6660 SDISelAsmOperandInfo &OpInfo) {
6661 LLVMContext &Context = *DAG.getContext();
6663 MachineFunction &MF = DAG.getMachineFunction();
6664 SmallVector<unsigned, 4> Regs;
6666 // If this is a constraint for a single physreg, or a constraint for a
6667 // register class, find it.
6668 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
6669 TLI.getRegForInlineAsmConstraint(MF.getSubtarget().getRegisterInfo(),
6670 OpInfo.ConstraintCode,
6671 OpInfo.ConstraintVT);
6673 unsigned NumRegs = 1;
6674 if (OpInfo.ConstraintVT != MVT::Other) {
6675 // If this is a FP input in an integer register (or visa versa) insert a bit
6676 // cast of the input value. More generally, handle any case where the input
6677 // value disagrees with the register class we plan to stick this in.
6678 if (OpInfo.Type == InlineAsm::isInput &&
6679 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
6680 // Try to convert to the first EVT that the reg class contains. If the
6681 // types are identical size, use a bitcast to convert (e.g. two differing
6683 MVT RegVT = *PhysReg.second->vt_begin();
6684 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
6685 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6686 RegVT, OpInfo.CallOperand);
6687 OpInfo.ConstraintVT = RegVT;
6688 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
6689 // If the input is a FP value and we want it in FP registers, do a
6690 // bitcast to the corresponding integer type. This turns an f64 value
6691 // into i64, which can be passed with two i32 values on a 32-bit
6693 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
6694 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6695 RegVT, OpInfo.CallOperand);
6696 OpInfo.ConstraintVT = RegVT;
6700 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
6704 EVT ValueVT = OpInfo.ConstraintVT;
6706 // If this is a constraint for a specific physical register, like {r17},
6708 if (unsigned AssignedReg = PhysReg.first) {
6709 const TargetRegisterClass *RC = PhysReg.second;
6710 if (OpInfo.ConstraintVT == MVT::Other)
6711 ValueVT = *RC->vt_begin();
6713 // Get the actual register value type. This is important, because the user
6714 // may have asked for (e.g.) the AX register in i32 type. We need to
6715 // remember that AX is actually i16 to get the right extension.
6716 RegVT = *RC->vt_begin();
6718 // This is a explicit reference to a physical register.
6719 Regs.push_back(AssignedReg);
6721 // If this is an expanded reference, add the rest of the regs to Regs.
6723 TargetRegisterClass::iterator I = RC->begin();
6724 for (; *I != AssignedReg; ++I)
6725 assert(I != RC->end() && "Didn't find reg!");
6727 // Already added the first reg.
6729 for (; NumRegs; --NumRegs, ++I) {
6730 assert(I != RC->end() && "Ran out of registers to allocate!");
6735 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6739 // Otherwise, if this was a reference to an LLVM register class, create vregs
6740 // for this reference.
6741 if (const TargetRegisterClass *RC = PhysReg.second) {
6742 RegVT = *RC->vt_begin();
6743 if (OpInfo.ConstraintVT == MVT::Other)
6746 // Create the appropriate number of virtual registers.
6747 MachineRegisterInfo &RegInfo = MF.getRegInfo();
6748 for (; NumRegs; --NumRegs)
6749 Regs.push_back(RegInfo.createVirtualRegister(RC));
6751 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6755 // Otherwise, we couldn't allocate enough registers for this.
6759 findMatchingInlineAsmOperand(unsigned OperandNo,
6760 const std::vector<SDValue> &AsmNodeOperands) {
6761 // Scan until we find the definition we already emitted of this operand.
6762 unsigned CurOp = InlineAsm::Op_FirstOperand;
6763 for (; OperandNo; --OperandNo) {
6764 // Advance to the next operand.
6766 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6767 assert((InlineAsm::isRegDefKind(OpFlag) ||
6768 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6769 InlineAsm::isMemKind(OpFlag)) &&
6770 "Skipped past definitions?");
6771 CurOp += InlineAsm::getNumOperandRegisters(OpFlag) + 1;
6776 /// Fill \p Regs with \p NumRegs new virtual registers of type \p RegVT
6777 /// \return true if it has succeeded, false otherwise
6778 static bool createVirtualRegs(SmallVector<unsigned, 4> &Regs, unsigned NumRegs,
6779 MVT RegVT, SelectionDAG &DAG) {
6780 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6781 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6782 for (unsigned i = 0, e = NumRegs; i != e; ++i) {
6783 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6784 Regs.push_back(RegInfo.createVirtualRegister(RC));
6795 explicit ExtraFlags(ImmutableCallSite CS) {
6796 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
6797 if (IA->hasSideEffects())
6798 Flags |= InlineAsm::Extra_HasSideEffects;
6799 if (IA->isAlignStack())
6800 Flags |= InlineAsm::Extra_IsAlignStack;
6801 if (CS.isConvergent())
6802 Flags |= InlineAsm::Extra_IsConvergent;
6803 Flags |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6806 void update(const llvm::TargetLowering::AsmOperandInfo &OpInfo) {
6807 // Ideally, we would only check against memory constraints. However, the
6808 // meaning of an Other constraint can be target-specific and we can't easily
6809 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6810 // for Other constraints as well.
6811 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6812 OpInfo.ConstraintType == TargetLowering::C_Other) {
6813 if (OpInfo.Type == InlineAsm::isInput)
6814 Flags |= InlineAsm::Extra_MayLoad;
6815 else if (OpInfo.Type == InlineAsm::isOutput)
6816 Flags |= InlineAsm::Extra_MayStore;
6817 else if (OpInfo.Type == InlineAsm::isClobber)
6818 Flags |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6822 unsigned get() const { return Flags; }
6825 /// visitInlineAsm - Handle a call to an InlineAsm object.
6827 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
6828 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
6830 /// ConstraintOperands - Information about all of the constraints.
6831 SDISelAsmOperandInfoVector ConstraintOperands;
6833 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6834 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(
6835 DAG.getDataLayout(), DAG.getSubtarget().getRegisterInfo(), CS);
6837 bool hasMemory = false;
6839 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6840 ExtraFlags ExtraInfo(CS);
6842 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
6843 unsigned ResNo = 0; // ResNo - The result number of the next output.
6844 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6845 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
6846 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
6848 MVT OpVT = MVT::Other;
6850 // Compute the value type for each operand.
6851 if (OpInfo.Type == InlineAsm::isInput ||
6852 (OpInfo.Type == InlineAsm::isOutput && OpInfo.isIndirect)) {
6853 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6855 // Process the call argument. BasicBlocks are labels, currently appearing
6857 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6858 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6860 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6865 .getCallOperandValEVT(*DAG.getContext(), TLI, DAG.getDataLayout())
6869 if (OpInfo.Type == InlineAsm::isOutput && !OpInfo.isIndirect) {
6870 // The return value of the call is this value. As such, there is no
6871 // corresponding argument.
6872 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6873 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
6874 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(),
6875 STy->getElementType(ResNo));
6877 assert(ResNo == 0 && "Asm only has one result!");
6878 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(), CS.getType());
6883 OpInfo.ConstraintVT = OpVT;
6886 hasMemory = OpInfo.hasMemory(TLI);
6888 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6889 // FIXME: Could we compute this on OpInfo rather than TargetConstraints[i]?
6890 auto TargetConstraint = TargetConstraints[i];
6892 // Compute the constraint code and ConstraintType to use.
6893 TLI.ComputeConstraintToUse(TargetConstraint, SDValue());
6895 ExtraInfo.update(TargetConstraint);
6898 SDValue Chain, Flag;
6900 // We won't need to flush pending loads if this asm doesn't touch
6901 // memory and is nonvolatile.
6902 if (hasMemory || IA->hasSideEffects())
6905 Chain = DAG.getRoot();
6907 // Second pass over the constraints: compute which constraint option to use
6908 // and assign registers to constraints that want a specific physreg.
6909 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6910 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6912 // If this is an output operand with a matching input operand, look up the
6913 // matching input. If their types mismatch, e.g. one is an integer, the
6914 // other is floating point, or their sizes are different, flag it as an
6916 if (OpInfo.hasMatchingInput()) {
6917 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6918 patchMatchingInput(OpInfo, Input, DAG);
6921 // Compute the constraint code and ConstraintType to use.
6922 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6924 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6925 OpInfo.Type == InlineAsm::isClobber)
6928 // If this is a memory input, and if the operand is not indirect, do what we
6929 // need to to provide an address for the memory input.
6930 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6931 !OpInfo.isIndirect) {
6932 assert((OpInfo.isMultipleAlternative ||
6933 (OpInfo.Type == InlineAsm::isInput)) &&
6934 "Can only indirectify direct input operands!");
6936 // Memory operands really want the address of the value.
6937 Chain = getAddressForMemoryInput(Chain, getCurSDLoc(), OpInfo, DAG);
6939 // There is no longer a Value* corresponding to this operand.
6940 OpInfo.CallOperandVal = nullptr;
6942 // It is now an indirect operand.
6943 OpInfo.isIndirect = true;
6946 // If this constraint is for a specific register, allocate it before
6948 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6949 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6952 // Third pass - Loop over all of the operands, assigning virtual or physregs
6953 // to register class operands.
6954 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6955 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6957 // C_Register operands have already been allocated, Other/Memory don't need
6959 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6960 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6963 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6964 std::vector<SDValue> AsmNodeOperands;
6965 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6966 AsmNodeOperands.push_back(DAG.getTargetExternalSymbol(
6967 IA->getAsmString().c_str(), TLI.getPointerTy(DAG.getDataLayout())));
6969 // If we have a !srcloc metadata node associated with it, we want to attach
6970 // this to the ultimately generated inline asm machineinstr. To do this, we
6971 // pass in the third operand as this (potentially null) inline asm MDNode.
6972 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6973 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6975 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6976 // bits as operand 3.
6977 AsmNodeOperands.push_back(DAG.getTargetConstant(
6978 ExtraInfo.get(), getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6980 // Loop over all of the inputs, copying the operand values into the
6981 // appropriate registers and processing the output regs.
6982 RegsForValue RetValRegs;
6984 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6985 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6987 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6988 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6990 switch (OpInfo.Type) {
6991 case InlineAsm::isOutput: {
6992 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6993 OpInfo.ConstraintType != TargetLowering::C_Register) {
6994 // Memory output, or 'other' output (e.g. 'X' constraint).
6995 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6997 unsigned ConstraintID =
6998 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6999 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
7000 "Failed to convert memory constraint code to constraint id.");
7002 // Add information to the INLINEASM node to know about this output.
7003 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
7004 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
7005 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(),
7007 AsmNodeOperands.push_back(OpInfo.CallOperand);
7011 // Otherwise, this is a register or register class output.
7013 // Copy the output from the appropriate register. Find a register that
7015 if (OpInfo.AssignedRegs.Regs.empty()) {
7017 CS, "couldn't allocate output register for constraint '" +
7018 Twine(OpInfo.ConstraintCode) + "'");
7022 // If this is an indirect operand, store through the pointer after the
7024 if (OpInfo.isIndirect) {
7025 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
7026 OpInfo.CallOperandVal));
7028 // This is the result value of the call.
7029 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
7030 // Concatenate this output onto the outputs list.
7031 RetValRegs.append(OpInfo.AssignedRegs);
7034 // Add information to the INLINEASM node to know that this register is
7037 .AddInlineAsmOperands(OpInfo.isEarlyClobber
7038 ? InlineAsm::Kind_RegDefEarlyClobber
7039 : InlineAsm::Kind_RegDef,
7040 false, 0, getCurSDLoc(), DAG, AsmNodeOperands);
7043 case InlineAsm::isInput: {
7044 SDValue InOperandVal = OpInfo.CallOperand;
7046 if (OpInfo.isMatchingInputConstraint()) {
7047 // If this is required to match an output register we have already set,
7048 // just use its register.
7049 auto CurOp = findMatchingInlineAsmOperand(OpInfo.getMatchedOperand(),
7052 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
7053 if (InlineAsm::isRegDefKind(OpFlag) ||
7054 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
7055 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
7056 if (OpInfo.isIndirect) {
7057 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
7058 emitInlineAsmError(CS, "inline asm not supported yet:"
7059 " don't know how to handle tied "
7060 "indirect register inputs");
7064 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
7065 SmallVector<unsigned, 4> Regs;
7067 if (!createVirtualRegs(Regs,
7068 InlineAsm::getNumOperandRegisters(OpFlag),
7070 emitInlineAsmError(CS, "inline asm error: This value type register "
7071 "class is not natively supported!");
7075 RegsForValue MatchedRegs(Regs, RegVT, InOperandVal.getValueType());
7077 SDLoc dl = getCurSDLoc();
7078 // Use the produced MatchedRegs object to
7079 MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl,
7080 Chain, &Flag, CS.getInstruction());
7081 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
7082 true, OpInfo.getMatchedOperand(), dl,
7083 DAG, AsmNodeOperands);
7087 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
7088 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
7089 "Unexpected number of operands");
7090 // Add information to the INLINEASM node to know about this input.
7091 // See InlineAsm.h isUseOperandTiedToDef.
7092 OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag);
7093 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
7094 OpInfo.getMatchedOperand());
7095 AsmNodeOperands.push_back(DAG.getTargetConstant(
7096 OpFlag, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
7097 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
7101 // Treat indirect 'X' constraint as memory.
7102 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
7104 OpInfo.ConstraintType = TargetLowering::C_Memory;
7106 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
7107 std::vector<SDValue> Ops;
7108 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
7111 emitInlineAsmError(CS, "invalid operand for inline asm constraint '" +
7112 Twine(OpInfo.ConstraintCode) + "'");
7116 // Add information to the INLINEASM node to know about this input.
7117 unsigned ResOpType =
7118 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
7119 AsmNodeOperands.push_back(DAG.getTargetConstant(
7120 ResOpType, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
7121 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
7125 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
7126 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
7127 assert(InOperandVal.getValueType() ==
7128 TLI.getPointerTy(DAG.getDataLayout()) &&
7129 "Memory operands expect pointer values");
7131 unsigned ConstraintID =
7132 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
7133 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
7134 "Failed to convert memory constraint code to constraint id.");
7136 // Add information to the INLINEASM node to know about this input.
7137 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
7138 ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
7139 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
7142 AsmNodeOperands.push_back(InOperandVal);
7146 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
7147 OpInfo.ConstraintType == TargetLowering::C_Register) &&
7148 "Unknown constraint type!");
7150 // TODO: Support this.
7151 if (OpInfo.isIndirect) {
7153 CS, "Don't know how to handle indirect register inputs yet "
7154 "for constraint '" +
7155 Twine(OpInfo.ConstraintCode) + "'");
7159 // Copy the input into the appropriate registers.
7160 if (OpInfo.AssignedRegs.Regs.empty()) {
7161 emitInlineAsmError(CS, "couldn't allocate input reg for constraint '" +
7162 Twine(OpInfo.ConstraintCode) + "'");
7166 SDLoc dl = getCurSDLoc();
7168 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl,
7169 Chain, &Flag, CS.getInstruction());
7171 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
7172 dl, DAG, AsmNodeOperands);
7175 case InlineAsm::isClobber: {
7176 // Add the clobbered value to the operand list, so that the register
7177 // allocator is aware that the physreg got clobbered.
7178 if (!OpInfo.AssignedRegs.Regs.empty())
7179 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
7180 false, 0, getCurSDLoc(), DAG,
7187 // Finish up input operands. Set the input chain and add the flag last.
7188 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
7189 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
7191 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
7192 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
7193 Flag = Chain.getValue(1);
7195 // If this asm returns a register value, copy the result from that register
7196 // and set it as the value of the call.
7197 if (!RetValRegs.Regs.empty()) {
7198 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
7199 Chain, &Flag, CS.getInstruction());
7201 // FIXME: Why don't we do this for inline asms with MRVs?
7202 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
7203 EVT ResultType = TLI.getValueType(DAG.getDataLayout(), CS.getType());
7205 // If any of the results of the inline asm is a vector, it may have the
7206 // wrong width/num elts. This can happen for register classes that can
7207 // contain multiple different value types. The preg or vreg allocated may
7208 // not have the same VT as was expected. Convert it to the right type
7209 // with bit_convert.
7210 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
7211 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
7214 } else if (ResultType != Val.getValueType() &&
7215 ResultType.isInteger() && Val.getValueType().isInteger()) {
7216 // If a result value was tied to an input value, the computed result may
7217 // have a wider width than the expected result. Extract the relevant
7219 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
7222 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
7225 setValue(CS.getInstruction(), Val);
7226 // Don't need to use this as a chain in this case.
7227 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
7231 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
7233 // Process indirect outputs, first output all of the flagged copies out of
7235 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
7236 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
7237 const Value *Ptr = IndirectStoresToEmit[i].second;
7238 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
7240 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
7243 // Emit the non-flagged stores from the physregs.
7244 SmallVector<SDValue, 8> OutChains;
7245 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
7246 SDValue Val = DAG.getStore(Chain, getCurSDLoc(), StoresToEmit[i].first,
7247 getValue(StoresToEmit[i].second),
7248 MachinePointerInfo(StoresToEmit[i].second));
7249 OutChains.push_back(Val);
7252 if (!OutChains.empty())
7253 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
7258 void SelectionDAGBuilder::emitInlineAsmError(ImmutableCallSite CS,
7259 const Twine &Message) {
7260 LLVMContext &Ctx = *DAG.getContext();
7261 Ctx.emitError(CS.getInstruction(), Message);
7263 // Make sure we leave the DAG in a valid state
7264 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7265 auto VT = TLI.getValueType(DAG.getDataLayout(), CS.getType());
7266 setValue(CS.getInstruction(), DAG.getUNDEF(VT));
7269 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
7270 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
7271 MVT::Other, getRoot(),
7272 getValue(I.getArgOperand(0)),
7273 DAG.getSrcValue(I.getArgOperand(0))));
7276 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
7277 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7278 const DataLayout &DL = DAG.getDataLayout();
7279 SDValue V = DAG.getVAArg(TLI.getValueType(DAG.getDataLayout(), I.getType()),
7280 getCurSDLoc(), getRoot(), getValue(I.getOperand(0)),
7281 DAG.getSrcValue(I.getOperand(0)),
7282 DL.getABITypeAlignment(I.getType()));
7284 DAG.setRoot(V.getValue(1));
7287 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
7288 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
7289 MVT::Other, getRoot(),
7290 getValue(I.getArgOperand(0)),
7291 DAG.getSrcValue(I.getArgOperand(0))));
7294 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
7295 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
7296 MVT::Other, getRoot(),
7297 getValue(I.getArgOperand(0)),
7298 getValue(I.getArgOperand(1)),
7299 DAG.getSrcValue(I.getArgOperand(0)),
7300 DAG.getSrcValue(I.getArgOperand(1))));
7303 SDValue SelectionDAGBuilder::lowerRangeToAssertZExt(SelectionDAG &DAG,
7304 const Instruction &I,
7306 const MDNode *Range = I.getMetadata(LLVMContext::MD_range);
7310 ConstantRange CR = getConstantRangeFromMetadata(*Range);
7311 if (CR.isFullSet() || CR.isEmptySet() || CR.isWrappedSet())
7314 APInt Lo = CR.getUnsignedMin();
7315 if (!Lo.isMinValue())
7318 APInt Hi = CR.getUnsignedMax();
7319 unsigned Bits = Hi.getActiveBits();
7321 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), Bits);
7323 SDLoc SL = getCurSDLoc();
7325 SDValue ZExt = DAG.getNode(ISD::AssertZext, SL, Op.getValueType(), Op,
7326 DAG.getValueType(SmallVT));
7327 unsigned NumVals = Op.getNode()->getNumValues();
7331 SmallVector<SDValue, 4> Ops;
7333 Ops.push_back(ZExt);
7334 for (unsigned I = 1; I != NumVals; ++I)
7335 Ops.push_back(Op.getValue(I));
7337 return DAG.getMergeValues(Ops, SL);
7340 /// \brief Populate a CallLowerinInfo (into \p CLI) based on the properties of
7341 /// the call being lowered.
7343 /// This is a helper for lowering intrinsics that follow a target calling
7344 /// convention or require stack pointer adjustment. Only a subset of the
7345 /// intrinsic's operands need to participate in the calling convention.
7346 void SelectionDAGBuilder::populateCallLoweringInfo(
7347 TargetLowering::CallLoweringInfo &CLI, ImmutableCallSite CS,
7348 unsigned ArgIdx, unsigned NumArgs, SDValue Callee, Type *ReturnTy,
7349 bool IsPatchPoint) {
7350 TargetLowering::ArgListTy Args;
7351 Args.reserve(NumArgs);
7353 // Populate the argument list.
7354 // Attributes for args start at offset 1, after the return attribute.
7355 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
7356 ArgI != ArgE; ++ArgI) {
7357 const Value *V = CS->getOperand(ArgI);
7359 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
7361 TargetLowering::ArgListEntry Entry;
7362 Entry.Node = getValue(V);
7363 Entry.Ty = V->getType();
7364 Entry.setAttributes(&CS, AttrI);
7365 Args.push_back(Entry);
7368 CLI.setDebugLoc(getCurSDLoc())
7369 .setChain(getRoot())
7370 .setCallee(CS.getCallingConv(), ReturnTy, Callee, std::move(Args))
7371 .setDiscardResult(CS->use_empty())
7372 .setIsPatchPoint(IsPatchPoint);
7375 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
7376 /// or patchpoint target node's operand list.
7378 /// Constants are converted to TargetConstants purely as an optimization to
7379 /// avoid constant materialization and register allocation.
7381 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
7382 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
7383 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
7384 /// address materialization and register allocation, but may also be required
7385 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
7386 /// alloca in the entry block, then the runtime may assume that the alloca's
7387 /// StackMap location can be read immediately after compilation and that the
7388 /// location is valid at any point during execution (this is similar to the
7389 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
7390 /// only available in a register, then the runtime would need to trap when
7391 /// execution reaches the StackMap in order to read the alloca's location.
7392 static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
7393 const SDLoc &DL, SmallVectorImpl<SDValue> &Ops,
7394 SelectionDAGBuilder &Builder) {
7395 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
7396 SDValue OpVal = Builder.getValue(CS.getArgument(i));
7397 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
7399 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, DL, MVT::i64));
7401 Builder.DAG.getTargetConstant(C->getSExtValue(), DL, MVT::i64));
7402 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
7403 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
7404 Ops.push_back(Builder.DAG.getTargetFrameIndex(
7405 FI->getIndex(), TLI.getPointerTy(Builder.DAG.getDataLayout())));
7407 Ops.push_back(OpVal);
7411 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
7412 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
7413 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
7414 // [live variables...])
7416 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
7418 SDValue Chain, InFlag, Callee, NullPtr;
7419 SmallVector<SDValue, 32> Ops;
7421 SDLoc DL = getCurSDLoc();
7422 Callee = getValue(CI.getCalledValue());
7423 NullPtr = DAG.getIntPtrConstant(0, DL, true);
7425 // The stackmap intrinsic only records the live variables (the arguemnts
7426 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
7427 // intrinsic, this won't be lowered to a function call. This means we don't
7428 // have to worry about calling conventions and target specific lowering code.
7429 // Instead we perform the call lowering right here.
7431 // chain, flag = CALLSEQ_START(chain, 0)
7432 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
7433 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
7435 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
7436 InFlag = Chain.getValue(1);
7438 // Add the <id> and <numBytes> constants.
7439 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
7440 Ops.push_back(DAG.getTargetConstant(
7441 cast<ConstantSDNode>(IDVal)->getZExtValue(), DL, MVT::i64));
7442 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
7443 Ops.push_back(DAG.getTargetConstant(
7444 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), DL,
7447 // Push live variables for the stack map.
7448 addStackMapLiveVars(&CI, 2, DL, Ops, *this);
7450 // We are not pushing any register mask info here on the operands list,
7451 // because the stackmap doesn't clobber anything.
7453 // Push the chain and the glue flag.
7454 Ops.push_back(Chain);
7455 Ops.push_back(InFlag);
7457 // Create the STACKMAP node.
7458 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7459 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
7460 Chain = SDValue(SM, 0);
7461 InFlag = Chain.getValue(1);
7463 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
7465 // Stackmaps don't generate values, so nothing goes into the NodeMap.
7467 // Set the root to the target-lowered call chain.
7470 // Inform the Frame Information that we have a stackmap in this function.
7471 FuncInfo.MF->getFrameInfo().setHasStackMap();
7474 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
7475 void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
7476 const BasicBlock *EHPadBB) {
7477 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
7482 // [live variables...])
7484 CallingConv::ID CC = CS.getCallingConv();
7485 bool IsAnyRegCC = CC == CallingConv::AnyReg;
7486 bool HasDef = !CS->getType()->isVoidTy();
7487 SDLoc dl = getCurSDLoc();
7488 SDValue Callee = getValue(CS->getOperand(PatchPointOpers::TargetPos));
7490 // Handle immediate and symbolic callees.
7491 if (auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee))
7492 Callee = DAG.getIntPtrConstant(ConstCallee->getZExtValue(), dl,
7494 else if (auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee))
7495 Callee = DAG.getTargetGlobalAddress(SymbolicCallee->getGlobal(),
7496 SDLoc(SymbolicCallee),
7497 SymbolicCallee->getValueType(0));
7499 // Get the real number of arguments participating in the call <numArgs>
7500 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
7501 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
7503 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
7504 // Intrinsics include all meta-operands up to but not including CC.
7505 unsigned NumMetaOpers = PatchPointOpers::CCPos;
7506 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&
7507 "Not enough arguments provided to the patchpoint intrinsic");
7509 // For AnyRegCC the arguments are lowered later on manually.
7510 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
7512 IsAnyRegCC ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
7514 TargetLowering::CallLoweringInfo CLI(DAG);
7515 populateCallLoweringInfo(CLI, CS, NumMetaOpers, NumCallArgs, Callee, ReturnTy,
7517 std::pair<SDValue, SDValue> Result = lowerInvokable(CLI, EHPadBB);
7519 SDNode *CallEnd = Result.second.getNode();
7520 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
7521 CallEnd = CallEnd->getOperand(0).getNode();
7523 /// Get a call instruction from the call sequence chain.
7524 /// Tail calls are not allowed.
7525 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
7526 "Expected a callseq node.");
7527 SDNode *Call = CallEnd->getOperand(0).getNode();
7528 bool HasGlue = Call->getGluedNode();
7530 // Replace the target specific call node with the patchable intrinsic.
7531 SmallVector<SDValue, 8> Ops;
7533 // Add the <id> and <numBytes> constants.
7534 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
7535 Ops.push_back(DAG.getTargetConstant(
7536 cast<ConstantSDNode>(IDVal)->getZExtValue(), dl, MVT::i64));
7537 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
7538 Ops.push_back(DAG.getTargetConstant(
7539 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), dl,
7543 Ops.push_back(Callee);
7545 // Adjust <numArgs> to account for any arguments that have been passed on the
7547 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
7548 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
7549 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
7550 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, dl, MVT::i32));
7552 // Add the calling convention
7553 Ops.push_back(DAG.getTargetConstant((unsigned)CC, dl, MVT::i32));
7555 // Add the arguments we omitted previously. The register allocator should
7556 // place these in any free register.
7558 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
7559 Ops.push_back(getValue(CS.getArgument(i)));
7561 // Push the arguments from the call instruction up to the register mask.
7562 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
7563 Ops.append(Call->op_begin() + 2, e);
7565 // Push live variables for the stack map.
7566 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, dl, Ops, *this);
7568 // Push the register mask info.
7570 Ops.push_back(*(Call->op_end()-2));
7572 Ops.push_back(*(Call->op_end()-1));
7574 // Push the chain (this is originally the first operand of the call, but
7575 // becomes now the last or second to last operand).
7576 Ops.push_back(*(Call->op_begin()));
7578 // Push the glue flag (last operand).
7580 Ops.push_back(*(Call->op_end()-1));
7583 if (IsAnyRegCC && HasDef) {
7584 // Create the return types based on the intrinsic definition
7585 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7586 SmallVector<EVT, 3> ValueVTs;
7587 ComputeValueVTs(TLI, DAG.getDataLayout(), CS->getType(), ValueVTs);
7588 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
7590 // There is always a chain and a glue type at the end
7591 ValueVTs.push_back(MVT::Other);
7592 ValueVTs.push_back(MVT::Glue);
7593 NodeTys = DAG.getVTList(ValueVTs);
7595 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7597 // Replace the target specific call node with a PATCHPOINT node.
7598 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
7601 // Update the NodeMap.
7604 setValue(CS.getInstruction(), SDValue(MN, 0));
7606 setValue(CS.getInstruction(), Result.first);
7609 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
7610 // call sequence. Furthermore the location of the chain and glue can change
7611 // when the AnyReg calling convention is used and the intrinsic returns a
7613 if (IsAnyRegCC && HasDef) {
7614 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
7615 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
7616 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
7618 DAG.ReplaceAllUsesWith(Call, MN);
7619 DAG.DeleteNode(Call);
7621 // Inform the Frame Information that we have a patchpoint in this function.
7622 FuncInfo.MF->getFrameInfo().setHasPatchPoint();
7625 /// Returns an AttributeSet representing the attributes applied to the return
7626 /// value of the given call.
7627 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
7628 SmallVector<Attribute::AttrKind, 2> Attrs;
7630 Attrs.push_back(Attribute::SExt);
7632 Attrs.push_back(Attribute::ZExt);
7634 Attrs.push_back(Attribute::InReg);
7636 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
7640 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
7641 /// implementation, which just calls LowerCall.
7642 /// FIXME: When all targets are
7643 /// migrated to using LowerCall, this hook should be integrated into SDISel.
7644 std::pair<SDValue, SDValue>
7645 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
7646 // Handle the incoming return values from the call.
7648 Type *OrigRetTy = CLI.RetTy;
7649 SmallVector<EVT, 4> RetTys;
7650 SmallVector<uint64_t, 4> Offsets;
7651 auto &DL = CLI.DAG.getDataLayout();
7652 ComputeValueVTs(*this, DL, CLI.RetTy, RetTys, &Offsets);
7654 SmallVector<ISD::OutputArg, 4> Outs;
7655 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this, DL);
7657 bool CanLowerReturn =
7658 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
7659 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
7661 SDValue DemoteStackSlot;
7662 int DemoteStackIdx = -100;
7663 if (!CanLowerReturn) {
7664 // FIXME: equivalent assert?
7665 // assert(!CS.hasInAllocaArgument() &&
7666 // "sret demotion is incompatible with inalloca");
7667 uint64_t TySize = DL.getTypeAllocSize(CLI.RetTy);
7668 unsigned Align = DL.getPrefTypeAlignment(CLI.RetTy);
7669 MachineFunction &MF = CLI.DAG.getMachineFunction();
7670 DemoteStackIdx = MF.getFrameInfo().CreateStackObject(TySize, Align, false);
7671 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
7673 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy(DL));
7675 Entry.Node = DemoteStackSlot;
7676 Entry.Ty = StackSlotPtrType;
7677 Entry.isSExt = false;
7678 Entry.isZExt = false;
7679 Entry.isInReg = false;
7680 Entry.isSRet = true;
7681 Entry.isNest = false;
7682 Entry.isByVal = false;
7683 Entry.isReturned = false;
7684 Entry.isSwiftSelf = false;
7685 Entry.isSwiftError = false;
7686 Entry.Alignment = Align;
7687 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
7688 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
7690 // sret demotion isn't compatible with tail-calls, since the sret argument
7691 // points into the callers stack frame.
7692 CLI.IsTailCall = false;
7694 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7696 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7697 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7698 for (unsigned i = 0; i != NumRegs; ++i) {
7699 ISD::InputArg MyFlags;
7700 MyFlags.VT = RegisterVT;
7702 MyFlags.Used = CLI.IsReturnValueUsed;
7704 MyFlags.Flags.setSExt();
7706 MyFlags.Flags.setZExt();
7708 MyFlags.Flags.setInReg();
7709 CLI.Ins.push_back(MyFlags);
7714 // We push in swifterror return as the last element of CLI.Ins.
7715 ArgListTy &Args = CLI.getArgs();
7716 if (supportSwiftError()) {
7717 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
7718 if (Args[i].isSwiftError) {
7719 ISD::InputArg MyFlags;
7720 MyFlags.VT = getPointerTy(DL);
7721 MyFlags.ArgVT = EVT(getPointerTy(DL));
7722 MyFlags.Flags.setSwiftError();
7723 CLI.Ins.push_back(MyFlags);
7728 // Handle all of the outgoing arguments.
7730 CLI.OutVals.clear();
7731 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
7732 SmallVector<EVT, 4> ValueVTs;
7733 ComputeValueVTs(*this, DL, Args[i].Ty, ValueVTs);
7734 Type *FinalType = Args[i].Ty;
7735 if (Args[i].isByVal)
7736 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
7737 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
7738 FinalType, CLI.CallConv, CLI.IsVarArg);
7739 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
7741 EVT VT = ValueVTs[Value];
7742 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
7743 SDValue Op = SDValue(Args[i].Node.getNode(),
7744 Args[i].Node.getResNo() + Value);
7745 ISD::ArgFlagsTy Flags;
7746 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
7752 if (Args[i].isInReg) {
7753 // If we are using vectorcall calling convention, a structure that is
7754 // passed InReg - is surely an HVA
7755 if (CLI.CallConv == CallingConv::X86_VectorCall &&
7756 isa<StructType>(FinalType)) {
7757 // The first value of a structure is marked
7759 Flags.setHvaStart();
7767 if (Args[i].isSwiftSelf)
7768 Flags.setSwiftSelf();
7769 if (Args[i].isSwiftError)
7770 Flags.setSwiftError();
7771 if (Args[i].isByVal)
7773 if (Args[i].isInAlloca) {
7774 Flags.setInAlloca();
7775 // Set the byval flag for CCAssignFn callbacks that don't know about
7776 // inalloca. This way we can know how many bytes we should've allocated
7777 // and how many bytes a callee cleanup function will pop. If we port
7778 // inalloca to more targets, we'll have to add custom inalloca handling
7779 // in the various CC lowering callbacks.
7782 if (Args[i].isByVal || Args[i].isInAlloca) {
7783 PointerType *Ty = cast<PointerType>(Args[i].Ty);
7784 Type *ElementTy = Ty->getElementType();
7785 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
7786 // For ByVal, alignment should come from FE. BE will guess if this
7787 // info is not there but there are cases it cannot get right.
7788 unsigned FrameAlign;
7789 if (Args[i].Alignment)
7790 FrameAlign = Args[i].Alignment;
7792 FrameAlign = getByValTypeAlignment(ElementTy, DL);
7793 Flags.setByValAlign(FrameAlign);
7798 Flags.setInConsecutiveRegs();
7799 Flags.setOrigAlign(OriginalAlignment);
7801 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
7802 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
7803 SmallVector<SDValue, 4> Parts(NumParts);
7804 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
7807 ExtendKind = ISD::SIGN_EXTEND;
7808 else if (Args[i].isZExt)
7809 ExtendKind = ISD::ZERO_EXTEND;
7811 // Conservatively only handle 'returned' on non-vectors for now
7812 if (Args[i].isReturned && !Op.getValueType().isVector()) {
7813 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
7814 "unexpected use of 'returned'");
7815 // Before passing 'returned' to the target lowering code, ensure that
7816 // either the register MVT and the actual EVT are the same size or that
7817 // the return value and argument are extended in the same way; in these
7818 // cases it's safe to pass the argument register value unchanged as the
7819 // return register value (although it's at the target's option whether
7821 // TODO: allow code generation to take advantage of partially preserved
7822 // registers rather than clobbering the entire register when the
7823 // parameter extension method is not compatible with the return
7825 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7826 (ExtendKind != ISD::ANY_EXTEND &&
7827 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7828 Flags.setReturned();
7831 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
7832 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
7834 for (unsigned j = 0; j != NumParts; ++j) {
7835 // if it isn't first piece, alignment must be 1
7836 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7837 i < CLI.NumFixedArgs,
7838 i, j*Parts[j].getValueType().getStoreSize());
7839 if (NumParts > 1 && j == 0)
7840 MyFlags.Flags.setSplit();
7842 MyFlags.Flags.setOrigAlign(1);
7843 if (j == NumParts - 1)
7844 MyFlags.Flags.setSplitEnd();
7847 CLI.Outs.push_back(MyFlags);
7848 CLI.OutVals.push_back(Parts[j]);
7851 if (NeedsRegBlock && Value == NumValues - 1)
7852 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
7856 SmallVector<SDValue, 4> InVals;
7857 CLI.Chain = LowerCall(CLI, InVals);
7859 // Update CLI.InVals to use outside of this function.
7860 CLI.InVals = InVals;
7862 // Verify that the target's LowerCall behaved as expected.
7863 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7864 "LowerCall didn't return a valid chain!");
7865 assert((!CLI.IsTailCall || InVals.empty()) &&
7866 "LowerCall emitted a return value for a tail call!");
7867 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7868 "LowerCall didn't emit the correct number of values!");
7870 // For a tail call, the return value is merely live-out and there aren't
7871 // any nodes in the DAG representing it. Return a special value to
7872 // indicate that a tail call has been emitted and no more Instructions
7873 // should be processed in the current block.
7874 if (CLI.IsTailCall) {
7875 CLI.DAG.setRoot(CLI.Chain);
7876 return std::make_pair(SDValue(), SDValue());
7880 for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7881 assert(InVals[i].getNode() && "LowerCall emitted a null value!");
7882 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7883 "LowerCall emitted a value with the wrong type!");
7887 SmallVector<SDValue, 4> ReturnValues;
7888 if (!CanLowerReturn) {
7889 // The instruction result is the result of loading from the
7890 // hidden sret parameter.
7891 SmallVector<EVT, 1> PVTs;
7892 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
7894 ComputeValueVTs(*this, DL, PtrRetTy, PVTs);
7895 assert(PVTs.size() == 1 && "Pointers should fit in one register");
7896 EVT PtrVT = PVTs[0];
7898 unsigned NumValues = RetTys.size();
7899 ReturnValues.resize(NumValues);
7900 SmallVector<SDValue, 4> Chains(NumValues);
7902 // An aggregate return value cannot wrap around the address space, so
7903 // offsets to its parts don't wrap either.
7905 Flags.setNoUnsignedWrap(true);
7907 for (unsigned i = 0; i < NumValues; ++i) {
7908 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
7909 CLI.DAG.getConstant(Offsets[i], CLI.DL,
7911 SDValue L = CLI.DAG.getLoad(
7912 RetTys[i], CLI.DL, CLI.Chain, Add,
7913 MachinePointerInfo::getFixedStack(CLI.DAG.getMachineFunction(),
7914 DemoteStackIdx, Offsets[i]),
7915 /* Alignment = */ 1);
7916 ReturnValues[i] = L;
7917 Chains[i] = L.getValue(1);
7920 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7922 // Collect the legal value parts into potentially illegal values
7923 // that correspond to the original function's return values.
7924 Optional<ISD::NodeType> AssertOp;
7926 AssertOp = ISD::AssertSext;
7927 else if (CLI.RetZExt)
7928 AssertOp = ISD::AssertZext;
7929 unsigned CurReg = 0;
7930 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7932 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7933 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7935 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7936 NumRegs, RegisterVT, VT, nullptr,
7941 // For a function returning void, there is no return value. We can't create
7942 // such a node, so we just return a null return value in that case. In
7943 // that case, nothing will actually look at the value.
7944 if (ReturnValues.empty())
7945 return std::make_pair(SDValue(), CLI.Chain);
7948 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7949 CLI.DAG.getVTList(RetTys), ReturnValues);
7950 return std::make_pair(Res, CLI.Chain);
7953 void TargetLowering::LowerOperationWrapper(SDNode *N,
7954 SmallVectorImpl<SDValue> &Results,
7955 SelectionDAG &DAG) const {
7956 if (SDValue Res = LowerOperation(SDValue(N, 0), DAG))
7957 Results.push_back(Res);
7960 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7961 llvm_unreachable("LowerOperation not implemented for this target!");
7965 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7966 SDValue Op = getNonRegisterValue(V);
7967 assert((Op.getOpcode() != ISD::CopyFromReg ||
7968 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7969 "Copy from a reg to the same reg!");
7970 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7972 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7973 RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg,
7975 SDValue Chain = DAG.getEntryNode();
7977 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
7978 FuncInfo.PreferredExtendType.end())
7980 : FuncInfo.PreferredExtendType[V];
7981 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
7982 PendingExports.push_back(Chain);
7985 #include "llvm/CodeGen/SelectionDAGISel.h"
7987 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7988 /// entry block, return true. This includes arguments used by switches, since
7989 /// the switch may expand into multiple basic blocks.
7990 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7991 // With FastISel active, we may be splitting blocks, so force creation
7992 // of virtual registers for all non-dead arguments.
7994 return A->use_empty();
7996 const BasicBlock &Entry = A->getParent()->front();
7997 for (const User *U : A->users())
7998 if (cast<Instruction>(U)->getParent() != &Entry || isa<SwitchInst>(U))
7999 return false; // Use not in entry block.
8004 void SelectionDAGISel::LowerArguments(const Function &F) {
8005 SelectionDAG &DAG = SDB->DAG;
8006 SDLoc dl = SDB->getCurSDLoc();
8007 const DataLayout &DL = DAG.getDataLayout();
8008 SmallVector<ISD::InputArg, 16> Ins;
8010 if (!FuncInfo->CanLowerReturn) {
8011 // Put in an sret pointer parameter before all the other parameters.
8012 SmallVector<EVT, 1> ValueVTs;
8013 ComputeValueVTs(*TLI, DAG.getDataLayout(),
8014 PointerType::getUnqual(F.getReturnType()), ValueVTs);
8016 // NOTE: Assuming that a pointer will never break down to more than one VT
8018 ISD::ArgFlagsTy Flags;
8020 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
8021 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
8022 ISD::InputArg::NoArgIndex, 0);
8023 Ins.push_back(RetArg);
8026 // Set up the incoming argument description vector.
8028 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
8029 I != E; ++I, ++Idx) {
8030 SmallVector<EVT, 4> ValueVTs;
8031 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
8032 bool isArgValueUsed = !I->use_empty();
8033 unsigned PartBase = 0;
8034 Type *FinalType = I->getType();
8035 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
8036 FinalType = cast<PointerType>(FinalType)->getElementType();
8037 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
8038 FinalType, F.getCallingConv(), F.isVarArg());
8039 for (unsigned Value = 0, NumValues = ValueVTs.size();
8040 Value != NumValues; ++Value) {
8041 EVT VT = ValueVTs[Value];
8042 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
8043 ISD::ArgFlagsTy Flags;
8044 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
8046 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
8048 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
8050 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg)) {
8051 // If we are using vectorcall calling convention, a structure that is
8052 // passed InReg - is surely an HVA
8053 if (F.getCallingConv() == CallingConv::X86_VectorCall &&
8054 isa<StructType>(I->getType())) {
8055 // The first value of a structure is marked
8057 Flags.setHvaStart();
8063 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
8065 if (F.getAttributes().hasAttribute(Idx, Attribute::SwiftSelf))
8066 Flags.setSwiftSelf();
8067 if (F.getAttributes().hasAttribute(Idx, Attribute::SwiftError))
8068 Flags.setSwiftError();
8069 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
8071 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
8072 Flags.setInAlloca();
8073 // Set the byval flag for CCAssignFn callbacks that don't know about
8074 // inalloca. This way we can know how many bytes we should've allocated
8075 // and how many bytes a callee cleanup function will pop. If we port
8076 // inalloca to more targets, we'll have to add custom inalloca handling
8077 // in the various CC lowering callbacks.
8080 if (F.getCallingConv() == CallingConv::X86_INTR) {
8081 // IA Interrupt passes frame (1st parameter) by value in the stack.
8085 if (Flags.isByVal() || Flags.isInAlloca()) {
8086 PointerType *Ty = cast<PointerType>(I->getType());
8087 Type *ElementTy = Ty->getElementType();
8088 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
8089 // For ByVal, alignment should be passed from FE. BE will guess if
8090 // this info is not there but there are cases it cannot get right.
8091 unsigned FrameAlign;
8092 if (F.getParamAlignment(Idx))
8093 FrameAlign = F.getParamAlignment(Idx);
8095 FrameAlign = TLI->getByValTypeAlignment(ElementTy, DL);
8096 Flags.setByValAlign(FrameAlign);
8098 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
8101 Flags.setInConsecutiveRegs();
8102 Flags.setOrigAlign(OriginalAlignment);
8104 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
8105 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
8106 for (unsigned i = 0; i != NumRegs; ++i) {
8107 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
8108 Idx-1, PartBase+i*RegisterVT.getStoreSize());
8109 if (NumRegs > 1 && i == 0)
8110 MyFlags.Flags.setSplit();
8111 // if it isn't first piece, alignment must be 1
8113 MyFlags.Flags.setOrigAlign(1);
8114 if (i == NumRegs - 1)
8115 MyFlags.Flags.setSplitEnd();
8117 Ins.push_back(MyFlags);
8119 if (NeedsRegBlock && Value == NumValues - 1)
8120 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
8121 PartBase += VT.getStoreSize();
8125 // Call the target to set up the argument values.
8126 SmallVector<SDValue, 8> InVals;
8127 SDValue NewRoot = TLI->LowerFormalArguments(
8128 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
8130 // Verify that the target's LowerFormalArguments behaved as expected.
8131 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
8132 "LowerFormalArguments didn't return a valid chain!");
8133 assert(InVals.size() == Ins.size() &&
8134 "LowerFormalArguments didn't emit the correct number of values!");
8136 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
8137 assert(InVals[i].getNode() &&
8138 "LowerFormalArguments emitted a null value!");
8139 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
8140 "LowerFormalArguments emitted a value with the wrong type!");
8144 // Update the DAG with the new chain value resulting from argument lowering.
8145 DAG.setRoot(NewRoot);
8147 // Set up the argument values.
8150 if (!FuncInfo->CanLowerReturn) {
8151 // Create a virtual register for the sret pointer, and put in a copy
8152 // from the sret argument into it.
8153 SmallVector<EVT, 1> ValueVTs;
8154 ComputeValueVTs(*TLI, DAG.getDataLayout(),
8155 PointerType::getUnqual(F.getReturnType()), ValueVTs);
8156 MVT VT = ValueVTs[0].getSimpleVT();
8157 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
8158 Optional<ISD::NodeType> AssertOp = None;
8159 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
8160 RegVT, VT, nullptr, AssertOp);
8162 MachineFunction& MF = SDB->DAG.getMachineFunction();
8163 MachineRegisterInfo& RegInfo = MF.getRegInfo();
8164 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
8165 FuncInfo->DemoteRegister = SRetReg;
8167 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
8168 DAG.setRoot(NewRoot);
8170 // i indexes lowered arguments. Bump it past the hidden sret argument.
8171 // Idx indexes LLVM arguments. Don't touch it.
8175 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
8177 SmallVector<SDValue, 4> ArgValues;
8178 SmallVector<EVT, 4> ValueVTs;
8179 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
8180 unsigned NumValues = ValueVTs.size();
8182 // If this argument is unused then remember its value. It is used to generate
8183 // debugging information.
8184 bool isSwiftErrorArg =
8185 TLI->supportSwiftError() &&
8186 F.getAttributes().hasAttribute(Idx, Attribute::SwiftError);
8187 if (I->use_empty() && NumValues && !isSwiftErrorArg) {
8188 SDB->setUnusedArgValue(&*I, InVals[i]);
8190 // Also remember any frame index for use in FastISel.
8191 if (FrameIndexSDNode *FI =
8192 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
8193 FuncInfo->setArgumentFrameIndex(&*I, FI->getIndex());
8196 for (unsigned Val = 0; Val != NumValues; ++Val) {
8197 EVT VT = ValueVTs[Val];
8198 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
8199 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
8201 // Even an apparant 'unused' swifterror argument needs to be returned. So
8202 // we do generate a copy for it that can be used on return from the
8204 if (!I->use_empty() || isSwiftErrorArg) {
8205 Optional<ISD::NodeType> AssertOp;
8206 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
8207 AssertOp = ISD::AssertSext;
8208 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
8209 AssertOp = ISD::AssertZext;
8211 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
8212 NumParts, PartVT, VT,
8213 nullptr, AssertOp));
8219 // We don't need to do anything else for unused arguments.
8220 if (ArgValues.empty())
8223 // Note down frame index.
8224 if (FrameIndexSDNode *FI =
8225 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
8226 FuncInfo->setArgumentFrameIndex(&*I, FI->getIndex());
8228 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
8229 SDB->getCurSDLoc());
8231 SDB->setValue(&*I, Res);
8232 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
8233 if (LoadSDNode *LNode =
8234 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
8235 if (FrameIndexSDNode *FI =
8236 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
8237 FuncInfo->setArgumentFrameIndex(&*I, FI->getIndex());
8240 // Update the SwiftErrorVRegDefMap.
8241 if (Res.getOpcode() == ISD::CopyFromReg && isSwiftErrorArg) {
8242 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
8243 if (TargetRegisterInfo::isVirtualRegister(Reg))
8244 FuncInfo->setCurrentSwiftErrorVReg(FuncInfo->MBB,
8245 FuncInfo->SwiftErrorArg, Reg);
8248 // If this argument is live outside of the entry block, insert a copy from
8249 // wherever we got it to the vreg that other BB's will reference it as.
8250 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
8251 // If we can, though, try to skip creating an unnecessary vreg.
8252 // FIXME: This isn't very clean... it would be nice to make this more
8253 // general. It's also subtly incompatible with the hacks FastISel
8255 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
8256 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
8257 FuncInfo->ValueMap[&*I] = Reg;
8261 if (!isOnlyUsedInEntryBlock(&*I, TM.Options.EnableFastISel)) {
8262 FuncInfo->InitializeRegForValue(&*I);
8263 SDB->CopyToExportRegsIfNeeded(&*I);
8267 assert(i == InVals.size() && "Argument register count mismatch!");
8269 // Finally, if the target has anything special to do, allow it to do so.
8270 EmitFunctionEntryCode();
8273 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
8274 /// ensure constants are generated when needed. Remember the virtual registers
8275 /// that need to be added to the Machine PHI nodes as input. We cannot just
8276 /// directly add them, because expansion might result in multiple MBB's for one
8277 /// BB. As such, the start of the BB might correspond to a different MBB than
8281 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
8282 const TerminatorInst *TI = LLVMBB->getTerminator();
8284 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
8286 // Check PHI nodes in successors that expect a value to be available from this
8288 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
8289 const BasicBlock *SuccBB = TI->getSuccessor(succ);
8290 if (!isa<PHINode>(SuccBB->begin())) continue;
8291 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
8293 // If this terminator has multiple identical successors (common for
8294 // switches), only handle each succ once.
8295 if (!SuccsHandled.insert(SuccMBB).second)
8298 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
8300 // At this point we know that there is a 1-1 correspondence between LLVM PHI
8301 // nodes and Machine PHI nodes, but the incoming operands have not been
8303 for (BasicBlock::const_iterator I = SuccBB->begin();
8304 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
8305 // Ignore dead phi's.
8306 if (PN->use_empty()) continue;
8309 if (PN->getType()->isEmptyTy())
8313 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
8315 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
8316 unsigned &RegOut = ConstantsOut[C];
8318 RegOut = FuncInfo.CreateRegs(C->getType());
8319 CopyValueToVirtualRegister(C, RegOut);
8323 DenseMap<const Value *, unsigned>::iterator I =
8324 FuncInfo.ValueMap.find(PHIOp);
8325 if (I != FuncInfo.ValueMap.end())
8328 assert(isa<AllocaInst>(PHIOp) &&
8329 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
8330 "Didn't codegen value into a register!??");
8331 Reg = FuncInfo.CreateRegs(PHIOp->getType());
8332 CopyValueToVirtualRegister(PHIOp, Reg);
8336 // Remember that this register needs to added to the machine PHI node as
8337 // the input for this MBB.
8338 SmallVector<EVT, 4> ValueVTs;
8339 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8340 ComputeValueVTs(TLI, DAG.getDataLayout(), PN->getType(), ValueVTs);
8341 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
8342 EVT VT = ValueVTs[vti];
8343 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
8344 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
8345 FuncInfo.PHINodesToUpdate.push_back(
8346 std::make_pair(&*MBBI++, Reg + i));
8347 Reg += NumRegisters;
8352 ConstantsOut.clear();
8355 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
8358 SelectionDAGBuilder::StackProtectorDescriptor::
8359 AddSuccessorMBB(const BasicBlock *BB,
8360 MachineBasicBlock *ParentMBB,
8362 MachineBasicBlock *SuccMBB) {
8363 // If SuccBB has not been created yet, create it.
8365 MachineFunction *MF = ParentMBB->getParent();
8366 MachineFunction::iterator BBI(ParentMBB);
8367 SuccMBB = MF->CreateMachineBasicBlock(BB);
8368 MF->insert(++BBI, SuccMBB);
8370 // Add it as a successor of ParentMBB.
8371 ParentMBB->addSuccessor(
8372 SuccMBB, BranchProbabilityInfo::getBranchProbStackProtector(IsLikely));
8376 MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) {
8377 MachineFunction::iterator I(MBB);
8378 if (++I == FuncInfo.MF->end())
8383 /// During lowering new call nodes can be created (such as memset, etc.).
8384 /// Those will become new roots of the current DAG, but complications arise
8385 /// when they are tail calls. In such cases, the call lowering will update
8386 /// the root, but the builder still needs to know that a tail call has been
8387 /// lowered in order to avoid generating an additional return.
8388 void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) {
8389 // If the node is null, we do have a tail call.
8390 if (MaybeTC.getNode() != nullptr)
8391 DAG.setRoot(MaybeTC);
8396 bool SelectionDAGBuilder::isDense(const CaseClusterVector &Clusters,
8397 const SmallVectorImpl<unsigned> &TotalCases,
8398 unsigned First, unsigned Last,
8399 unsigned Density) const {
8400 assert(Last >= First);
8401 assert(TotalCases[Last] >= TotalCases[First]);
8403 const APInt &LowCase = Clusters[First].Low->getValue();
8404 const APInt &HighCase = Clusters[Last].High->getValue();
8405 assert(LowCase.getBitWidth() == HighCase.getBitWidth());
8407 // FIXME: A range of consecutive cases has 100% density, but only requires one
8408 // comparison to lower. We should discriminate against such consecutive ranges
8411 uint64_t Diff = (HighCase - LowCase).getLimitedValue((UINT64_MAX - 1) / 100);
8412 uint64_t Range = Diff + 1;
8415 TotalCases[Last] - (First == 0 ? 0 : TotalCases[First - 1]);
8417 assert(NumCases < UINT64_MAX / 100);
8418 assert(Range >= NumCases);
8420 return NumCases * 100 >= Range * Density;
8423 static inline bool areJTsAllowed(const TargetLowering &TLI,
8424 const SwitchInst *SI) {
8425 const Function *Fn = SI->getParent()->getParent();
8426 if (Fn->getFnAttribute("no-jump-tables").getValueAsString() == "true")
8429 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
8430 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
8433 bool SelectionDAGBuilder::buildJumpTable(const CaseClusterVector &Clusters,
8434 unsigned First, unsigned Last,
8435 const SwitchInst *SI,
8436 MachineBasicBlock *DefaultMBB,
8437 CaseCluster &JTCluster) {
8438 assert(First <= Last);
8440 auto Prob = BranchProbability::getZero();
8441 unsigned NumCmps = 0;
8442 std::vector<MachineBasicBlock*> Table;
8443 DenseMap<MachineBasicBlock*, BranchProbability> JTProbs;
8445 // Initialize probabilities in JTProbs.
8446 for (unsigned I = First; I <= Last; ++I)
8447 JTProbs[Clusters[I].MBB] = BranchProbability::getZero();
8449 for (unsigned I = First; I <= Last; ++I) {
8450 assert(Clusters[I].Kind == CC_Range);
8451 Prob += Clusters[I].Prob;
8452 const APInt &Low = Clusters[I].Low->getValue();
8453 const APInt &High = Clusters[I].High->getValue();
8454 NumCmps += (Low == High) ? 1 : 2;
8456 // Fill the gap between this and the previous cluster.
8457 const APInt &PreviousHigh = Clusters[I - 1].High->getValue();
8458 assert(PreviousHigh.slt(Low));
8459 uint64_t Gap = (Low - PreviousHigh).getLimitedValue() - 1;
8460 for (uint64_t J = 0; J < Gap; J++)
8461 Table.push_back(DefaultMBB);
8463 uint64_t ClusterSize = (High - Low).getLimitedValue() + 1;
8464 for (uint64_t J = 0; J < ClusterSize; ++J)
8465 Table.push_back(Clusters[I].MBB);
8466 JTProbs[Clusters[I].MBB] += Clusters[I].Prob;
8469 unsigned NumDests = JTProbs.size();
8470 if (isSuitableForBitTests(NumDests, NumCmps,
8471 Clusters[First].Low->getValue(),
8472 Clusters[Last].High->getValue())) {
8473 // Clusters[First..Last] should be lowered as bit tests instead.
8477 // Create the MBB that will load from and jump through the table.
8478 // Note: We create it here, but it's not inserted into the function yet.
8479 MachineFunction *CurMF = FuncInfo.MF;
8480 MachineBasicBlock *JumpTableMBB =
8481 CurMF->CreateMachineBasicBlock(SI->getParent());
8483 // Add successors. Note: use table order for determinism.
8484 SmallPtrSet<MachineBasicBlock *, 8> Done;
8485 for (MachineBasicBlock *Succ : Table) {
8486 if (Done.count(Succ))
8488 addSuccessorWithProb(JumpTableMBB, Succ, JTProbs[Succ]);
8491 JumpTableMBB->normalizeSuccProbs();
8493 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8494 unsigned JTI = CurMF->getOrCreateJumpTableInfo(TLI.getJumpTableEncoding())
8495 ->createJumpTableIndex(Table);
8497 // Set up the jump table info.
8498 JumpTable JT(-1U, JTI, JumpTableMBB, nullptr);
8499 JumpTableHeader JTH(Clusters[First].Low->getValue(),
8500 Clusters[Last].High->getValue(), SI->getCondition(),
8502 JTCases.emplace_back(std::move(JTH), std::move(JT));
8504 JTCluster = CaseCluster::jumpTable(Clusters[First].Low, Clusters[Last].High,
8505 JTCases.size() - 1, Prob);
8509 void SelectionDAGBuilder::findJumpTables(CaseClusterVector &Clusters,
8510 const SwitchInst *SI,
8511 MachineBasicBlock *DefaultMBB) {
8513 // Clusters must be non-empty, sorted, and only contain Range clusters.
8514 assert(!Clusters.empty());
8515 for (CaseCluster &C : Clusters)
8516 assert(C.Kind == CC_Range);
8517 for (unsigned i = 1, e = Clusters.size(); i < e; ++i)
8518 assert(Clusters[i - 1].High->getValue().slt(Clusters[i].Low->getValue()));
8521 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8522 if (!areJTsAllowed(TLI, SI))
8525 const bool OptForSize = DefaultMBB->getParent()->getFunction()->optForSize();
8527 const int64_t N = Clusters.size();
8528 const unsigned MinJumpTableEntries = TLI.getMinimumJumpTableEntries();
8529 const unsigned SmallNumberOfEntries = MinJumpTableEntries / 2;
8530 const unsigned MaxJumpTableSize =
8531 OptForSize || TLI.getMaximumJumpTableSize() == 0
8532 ? UINT_MAX : TLI.getMaximumJumpTableSize();
8534 if (N < 2 || N < MinJumpTableEntries)
8537 // TotalCases[i]: Total nbr of cases in Clusters[0..i].
8538 SmallVector<unsigned, 8> TotalCases(N);
8539 for (unsigned i = 0; i < N; ++i) {
8540 const APInt &Hi = Clusters[i].High->getValue();
8541 const APInt &Lo = Clusters[i].Low->getValue();
8542 TotalCases[i] = (Hi - Lo).getLimitedValue() + 1;
8544 TotalCases[i] += TotalCases[i - 1];
8547 const unsigned MinDensity =
8548 OptForSize ? OptsizeJumpTableDensity : JumpTableDensity;
8550 // Cheap case: the whole range may be suitable for jump table.
8551 unsigned JumpTableSize = (Clusters[N - 1].High->getValue() -
8552 Clusters[0].Low->getValue())
8553 .getLimitedValue(UINT_MAX - 1) + 1;
8554 if (JumpTableSize <= MaxJumpTableSize &&
8555 isDense(Clusters, TotalCases, 0, N - 1, MinDensity)) {
8556 CaseCluster JTCluster;
8557 if (buildJumpTable(Clusters, 0, N - 1, SI, DefaultMBB, JTCluster)) {
8558 Clusters[0] = JTCluster;
8564 // The algorithm below is not suitable for -O0.
8565 if (TM.getOptLevel() == CodeGenOpt::None)
8568 // Split Clusters into minimum number of dense partitions. The algorithm uses
8569 // the same idea as Kannan & Proebsting "Correction to 'Producing Good Code
8570 // for the Case Statement'" (1994), but builds the MinPartitions array in
8571 // reverse order to make it easier to reconstruct the partitions in ascending
8572 // order. In the choice between two optimal partitionings, it picks the one
8573 // which yields more jump tables.
8575 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
8576 SmallVector<unsigned, 8> MinPartitions(N);
8577 // LastElement[i] is the last element of the partition starting at i.
8578 SmallVector<unsigned, 8> LastElement(N);
8579 // PartitionsScore[i] is used to break ties when choosing between two
8580 // partitionings resulting in the same number of partitions.
8581 SmallVector<unsigned, 8> PartitionsScore(N);
8582 // For PartitionsScore, a small number of comparisons is considered as good as
8583 // a jump table and a single comparison is considered better than a jump
8585 enum PartitionScores : unsigned {
8592 // Base case: There is only one way to partition Clusters[N-1].
8593 MinPartitions[N - 1] = 1;
8594 LastElement[N - 1] = N - 1;
8595 PartitionsScore[N - 1] = PartitionScores::SingleCase;
8597 // Note: loop indexes are signed to avoid underflow.
8598 for (int64_t i = N - 2; i >= 0; i--) {
8599 // Find optimal partitioning of Clusters[i..N-1].
8600 // Baseline: Put Clusters[i] into a partition on its own.
8601 MinPartitions[i] = MinPartitions[i + 1] + 1;
8603 PartitionsScore[i] = PartitionsScore[i + 1] + PartitionScores::SingleCase;
8605 // Search for a solution that results in fewer partitions.
8606 for (int64_t j = N - 1; j > i; j--) {
8607 // Try building a partition from Clusters[i..j].
8608 JumpTableSize = (Clusters[j].High->getValue() -
8609 Clusters[i].Low->getValue())
8610 .getLimitedValue(UINT_MAX - 1) + 1;
8611 if (JumpTableSize <= MaxJumpTableSize &&
8612 isDense(Clusters, TotalCases, i, j, MinDensity)) {
8613 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
8614 unsigned Score = j == N - 1 ? 0 : PartitionsScore[j + 1];
8615 int64_t NumEntries = j - i + 1;
8617 if (NumEntries == 1)
8618 Score += PartitionScores::SingleCase;
8619 else if (NumEntries <= SmallNumberOfEntries)
8620 Score += PartitionScores::FewCases;
8621 else if (NumEntries >= MinJumpTableEntries)
8622 Score += PartitionScores::Table;
8624 // If this leads to fewer partitions, or to the same number of
8625 // partitions with better score, it is a better partitioning.
8626 if (NumPartitions < MinPartitions[i] ||
8627 (NumPartitions == MinPartitions[i] && Score > PartitionsScore[i])) {
8628 MinPartitions[i] = NumPartitions;
8630 PartitionsScore[i] = Score;
8636 // Iterate over the partitions, replacing some with jump tables in-place.
8637 unsigned DstIndex = 0;
8638 for (unsigned First = 0, Last; First < N; First = Last + 1) {
8639 Last = LastElement[First];
8640 assert(Last >= First);
8641 assert(DstIndex <= First);
8642 unsigned NumClusters = Last - First + 1;
8644 CaseCluster JTCluster;
8645 if (NumClusters >= MinJumpTableEntries &&
8646 buildJumpTable(Clusters, First, Last, SI, DefaultMBB, JTCluster)) {
8647 Clusters[DstIndex++] = JTCluster;
8649 for (unsigned I = First; I <= Last; ++I)
8650 std::memmove(&Clusters[DstIndex++], &Clusters[I], sizeof(Clusters[I]));
8653 Clusters.resize(DstIndex);
8656 bool SelectionDAGBuilder::rangeFitsInWord(const APInt &Low, const APInt &High) {
8657 // FIXME: Using the pointer type doesn't seem ideal.
8658 uint64_t BW = DAG.getDataLayout().getPointerSizeInBits();
8659 uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
8663 bool SelectionDAGBuilder::isSuitableForBitTests(unsigned NumDests,
8666 const APInt &High) {
8667 // FIXME: I don't think NumCmps is the correct metric: a single case and a
8668 // range of cases both require only one branch to lower. Just looking at the
8669 // number of clusters and destinations should be enough to decide whether to
8672 // To lower a range with bit tests, the range must fit the bitwidth of a
8674 if (!rangeFitsInWord(Low, High))
8677 // Decide whether it's profitable to lower this range with bit tests. Each
8678 // destination requires a bit test and branch, and there is an overall range
8679 // check branch. For a small number of clusters, separate comparisons might be
8680 // cheaper, and for many destinations, splitting the range might be better.
8681 return (NumDests == 1 && NumCmps >= 3) ||
8682 (NumDests == 2 && NumCmps >= 5) ||
8683 (NumDests == 3 && NumCmps >= 6);
8686 bool SelectionDAGBuilder::buildBitTests(CaseClusterVector &Clusters,
8687 unsigned First, unsigned Last,
8688 const SwitchInst *SI,
8689 CaseCluster &BTCluster) {
8690 assert(First <= Last);
8694 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
8695 unsigned NumCmps = 0;
8696 for (int64_t I = First; I <= Last; ++I) {
8697 assert(Clusters[I].Kind == CC_Range);
8698 Dests.set(Clusters[I].MBB->getNumber());
8699 NumCmps += (Clusters[I].Low == Clusters[I].High) ? 1 : 2;
8701 unsigned NumDests = Dests.count();
8703 APInt Low = Clusters[First].Low->getValue();
8704 APInt High = Clusters[Last].High->getValue();
8705 assert(Low.slt(High));
8707 if (!isSuitableForBitTests(NumDests, NumCmps, Low, High))
8713 const int BitWidth = DAG.getTargetLoweringInfo()
8714 .getPointerTy(DAG.getDataLayout())
8716 assert(rangeFitsInWord(Low, High) && "Case range must fit in bit mask!");
8718 // Check if the clusters cover a contiguous range such that no value in the
8719 // range will jump to the default statement.
8720 bool ContiguousRange = true;
8721 for (int64_t I = First + 1; I <= Last; ++I) {
8722 if (Clusters[I].Low->getValue() != Clusters[I - 1].High->getValue() + 1) {
8723 ContiguousRange = false;
8728 if (Low.isStrictlyPositive() && High.slt(BitWidth)) {
8729 // Optimize the case where all the case values fit in a word without having
8730 // to subtract minValue. In this case, we can optimize away the subtraction.
8731 LowBound = APInt::getNullValue(Low.getBitWidth());
8733 ContiguousRange = false;
8736 CmpRange = High - Low;
8740 auto TotalProb = BranchProbability::getZero();
8741 for (unsigned i = First; i <= Last; ++i) {
8742 // Find the CaseBits for this destination.
8744 for (j = 0; j < CBV.size(); ++j)
8745 if (CBV[j].BB == Clusters[i].MBB)
8747 if (j == CBV.size())
8749 CaseBits(0, Clusters[i].MBB, 0, BranchProbability::getZero()));
8750 CaseBits *CB = &CBV[j];
8752 // Update Mask, Bits and ExtraProb.
8753 uint64_t Lo = (Clusters[i].Low->getValue() - LowBound).getZExtValue();
8754 uint64_t Hi = (Clusters[i].High->getValue() - LowBound).getZExtValue();
8755 assert(Hi >= Lo && Hi < 64 && "Invalid bit case!");
8756 CB->Mask |= (-1ULL >> (63 - (Hi - Lo))) << Lo;
8757 CB->Bits += Hi - Lo + 1;
8758 CB->ExtraProb += Clusters[i].Prob;
8759 TotalProb += Clusters[i].Prob;
8763 std::sort(CBV.begin(), CBV.end(), [](const CaseBits &a, const CaseBits &b) {
8764 // Sort by probability first, number of bits second.
8765 if (a.ExtraProb != b.ExtraProb)
8766 return a.ExtraProb > b.ExtraProb;
8767 return a.Bits > b.Bits;
8770 for (auto &CB : CBV) {
8771 MachineBasicBlock *BitTestBB =
8772 FuncInfo.MF->CreateMachineBasicBlock(SI->getParent());
8773 BTI.push_back(BitTestCase(CB.Mask, BitTestBB, CB.BB, CB.ExtraProb));
8775 BitTestCases.emplace_back(std::move(LowBound), std::move(CmpRange),
8776 SI->getCondition(), -1U, MVT::Other, false,
8777 ContiguousRange, nullptr, nullptr, std::move(BTI),
8780 BTCluster = CaseCluster::bitTests(Clusters[First].Low, Clusters[Last].High,
8781 BitTestCases.size() - 1, TotalProb);
8785 void SelectionDAGBuilder::findBitTestClusters(CaseClusterVector &Clusters,
8786 const SwitchInst *SI) {
8787 // Partition Clusters into as few subsets as possible, where each subset has a
8788 // range that fits in a machine word and has <= 3 unique destinations.
8791 // Clusters must be sorted and contain Range or JumpTable clusters.
8792 assert(!Clusters.empty());
8793 assert(Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable);
8794 for (const CaseCluster &C : Clusters)
8795 assert(C.Kind == CC_Range || C.Kind == CC_JumpTable);
8796 for (unsigned i = 1; i < Clusters.size(); ++i)
8797 assert(Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue()));
8800 // The algorithm below is not suitable for -O0.
8801 if (TM.getOptLevel() == CodeGenOpt::None)
8804 // If target does not have legal shift left, do not emit bit tests at all.
8805 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8806 EVT PTy = TLI.getPointerTy(DAG.getDataLayout());
8807 if (!TLI.isOperationLegal(ISD::SHL, PTy))
8810 int BitWidth = PTy.getSizeInBits();
8811 const int64_t N = Clusters.size();
8813 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
8814 SmallVector<unsigned, 8> MinPartitions(N);
8815 // LastElement[i] is the last element of the partition starting at i.
8816 SmallVector<unsigned, 8> LastElement(N);
8818 // FIXME: This might not be the best algorithm for finding bit test clusters.
8820 // Base case: There is only one way to partition Clusters[N-1].
8821 MinPartitions[N - 1] = 1;
8822 LastElement[N - 1] = N - 1;
8824 // Note: loop indexes are signed to avoid underflow.
8825 for (int64_t i = N - 2; i >= 0; --i) {
8826 // Find optimal partitioning of Clusters[i..N-1].
8827 // Baseline: Put Clusters[i] into a partition on its own.
8828 MinPartitions[i] = MinPartitions[i + 1] + 1;
8831 // Search for a solution that results in fewer partitions.
8832 // Note: the search is limited by BitWidth, reducing time complexity.
8833 for (int64_t j = std::min(N - 1, i + BitWidth - 1); j > i; --j) {
8834 // Try building a partition from Clusters[i..j].
8837 if (!rangeFitsInWord(Clusters[i].Low->getValue(),
8838 Clusters[j].High->getValue()))
8841 // Check nbr of destinations and cluster types.
8842 // FIXME: This works, but doesn't seem very efficient.
8843 bool RangesOnly = true;
8844 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
8845 for (int64_t k = i; k <= j; k++) {
8846 if (Clusters[k].Kind != CC_Range) {
8850 Dests.set(Clusters[k].MBB->getNumber());
8852 if (!RangesOnly || Dests.count() > 3)
8855 // Check if it's a better partition.
8856 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
8857 if (NumPartitions < MinPartitions[i]) {
8858 // Found a better partition.
8859 MinPartitions[i] = NumPartitions;
8865 // Iterate over the partitions, replacing with bit-test clusters in-place.
8866 unsigned DstIndex = 0;
8867 for (unsigned First = 0, Last; First < N; First = Last + 1) {
8868 Last = LastElement[First];
8869 assert(First <= Last);
8870 assert(DstIndex <= First);
8872 CaseCluster BitTestCluster;
8873 if (buildBitTests(Clusters, First, Last, SI, BitTestCluster)) {
8874 Clusters[DstIndex++] = BitTestCluster;
8876 size_t NumClusters = Last - First + 1;
8877 std::memmove(&Clusters[DstIndex], &Clusters[First],
8878 sizeof(Clusters[0]) * NumClusters);
8879 DstIndex += NumClusters;
8882 Clusters.resize(DstIndex);
8885 void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
8886 MachineBasicBlock *SwitchMBB,
8887 MachineBasicBlock *DefaultMBB) {
8888 MachineFunction *CurMF = FuncInfo.MF;
8889 MachineBasicBlock *NextMBB = nullptr;
8890 MachineFunction::iterator BBI(W.MBB);
8891 if (++BBI != FuncInfo.MF->end())
8894 unsigned Size = W.LastCluster - W.FirstCluster + 1;
8896 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8898 if (Size == 2 && W.MBB == SwitchMBB) {
8899 // If any two of the cases has the same destination, and if one value
8900 // is the same as the other, but has one bit unset that the other has set,
8901 // use bit manipulation to do two compares at once. For example:
8902 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
8903 // TODO: This could be extended to merge any 2 cases in switches with 3
8905 // TODO: Handle cases where W.CaseBB != SwitchBB.
8906 CaseCluster &Small = *W.FirstCluster;
8907 CaseCluster &Big = *W.LastCluster;
8909 if (Small.Low == Small.High && Big.Low == Big.High &&
8910 Small.MBB == Big.MBB) {
8911 const APInt &SmallValue = Small.Low->getValue();
8912 const APInt &BigValue = Big.Low->getValue();
8914 // Check that there is only one bit different.
8915 APInt CommonBit = BigValue ^ SmallValue;
8916 if (CommonBit.isPowerOf2()) {
8917 SDValue CondLHS = getValue(Cond);
8918 EVT VT = CondLHS.getValueType();
8919 SDLoc DL = getCurSDLoc();
8921 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
8922 DAG.getConstant(CommonBit, DL, VT));
8923 SDValue Cond = DAG.getSetCC(
8924 DL, MVT::i1, Or, DAG.getConstant(BigValue | SmallValue, DL, VT),
8927 // Update successor info.
8928 // Both Small and Big will jump to Small.BB, so we sum up the
8930 addSuccessorWithProb(SwitchMBB, Small.MBB, Small.Prob + Big.Prob);
8932 addSuccessorWithProb(
8933 SwitchMBB, DefaultMBB,
8934 // The default destination is the first successor in IR.
8935 BPI->getEdgeProbability(SwitchMBB->getBasicBlock(), (unsigned)0));
8937 addSuccessorWithProb(SwitchMBB, DefaultMBB);
8939 // Insert the true branch.
8941 DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond,
8942 DAG.getBasicBlock(Small.MBB));
8943 // Insert the false branch.
8944 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
8945 DAG.getBasicBlock(DefaultMBB));
8947 DAG.setRoot(BrCond);
8953 if (TM.getOptLevel() != CodeGenOpt::None) {
8954 // Order cases by probability so the most likely case will be checked first.
8955 std::sort(W.FirstCluster, W.LastCluster + 1,
8956 [](const CaseCluster &a, const CaseCluster &b) {
8957 return a.Prob > b.Prob;
8960 // Rearrange the case blocks so that the last one falls through if possible
8961 // without without changing the order of probabilities.
8962 for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) {
8964 if (I->Prob > W.LastCluster->Prob)
8966 if (I->Kind == CC_Range && I->MBB == NextMBB) {
8967 std::swap(*I, *W.LastCluster);
8973 // Compute total probability.
8974 BranchProbability DefaultProb = W.DefaultProb;
8975 BranchProbability UnhandledProbs = DefaultProb;
8976 for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I)
8977 UnhandledProbs += I->Prob;
8979 MachineBasicBlock *CurMBB = W.MBB;
8980 for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
8981 MachineBasicBlock *Fallthrough;
8982 if (I == W.LastCluster) {
8983 // For the last cluster, fall through to the default destination.
8984 Fallthrough = DefaultMBB;
8986 Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock());
8987 CurMF->insert(BBI, Fallthrough);
8988 // Put Cond in a virtual register to make it available from the new blocks.
8989 ExportFromCurrentBlock(Cond);
8991 UnhandledProbs -= I->Prob;
8994 case CC_JumpTable: {
8995 // FIXME: Optimize away range check based on pivot comparisons.
8996 JumpTableHeader *JTH = &JTCases[I->JTCasesIndex].first;
8997 JumpTable *JT = &JTCases[I->JTCasesIndex].second;
8999 // The jump block hasn't been inserted yet; insert it here.
9000 MachineBasicBlock *JumpMBB = JT->MBB;
9001 CurMF->insert(BBI, JumpMBB);
9003 auto JumpProb = I->Prob;
9004 auto FallthroughProb = UnhandledProbs;
9006 // If the default statement is a target of the jump table, we evenly
9007 // distribute the default probability to successors of CurMBB. Also
9008 // update the probability on the edge from JumpMBB to Fallthrough.
9009 for (MachineBasicBlock::succ_iterator SI = JumpMBB->succ_begin(),
9010 SE = JumpMBB->succ_end();
9012 if (*SI == DefaultMBB) {
9013 JumpProb += DefaultProb / 2;
9014 FallthroughProb -= DefaultProb / 2;
9015 JumpMBB->setSuccProbability(SI, DefaultProb / 2);
9016 JumpMBB->normalizeSuccProbs();
9021 addSuccessorWithProb(CurMBB, Fallthrough, FallthroughProb);
9022 addSuccessorWithProb(CurMBB, JumpMBB, JumpProb);
9023 CurMBB->normalizeSuccProbs();
9025 // The jump table header will be inserted in our current block, do the
9026 // range check, and fall through to our fallthrough block.
9027 JTH->HeaderBB = CurMBB;
9028 JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader.
9030 // If we're in the right place, emit the jump table header right now.
9031 if (CurMBB == SwitchMBB) {
9032 visitJumpTableHeader(*JT, *JTH, SwitchMBB);
9033 JTH->Emitted = true;
9038 // FIXME: Optimize away range check based on pivot comparisons.
9039 BitTestBlock *BTB = &BitTestCases[I->BTCasesIndex];
9041 // The bit test blocks haven't been inserted yet; insert them here.
9042 for (BitTestCase &BTC : BTB->Cases)
9043 CurMF->insert(BBI, BTC.ThisBB);
9045 // Fill in fields of the BitTestBlock.
9046 BTB->Parent = CurMBB;
9047 BTB->Default = Fallthrough;
9049 BTB->DefaultProb = UnhandledProbs;
9050 // If the cases in bit test don't form a contiguous range, we evenly
9051 // distribute the probability on the edge to Fallthrough to two
9052 // successors of CurMBB.
9053 if (!BTB->ContiguousRange) {
9054 BTB->Prob += DefaultProb / 2;
9055 BTB->DefaultProb -= DefaultProb / 2;
9058 // If we're in the right place, emit the bit test header right now.
9059 if (CurMBB == SwitchMBB) {
9060 visitBitTestHeader(*BTB, SwitchMBB);
9061 BTB->Emitted = true;
9066 const Value *RHS, *LHS, *MHS;
9068 if (I->Low == I->High) {
9069 // Check Cond == I->Low.
9075 // Check I->Low <= Cond <= I->High.
9082 // The false probability is the sum of all unhandled cases.
9083 CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB, I->Prob,
9086 if (CurMBB == SwitchMBB)
9087 visitSwitchCase(CB, SwitchMBB);
9089 SwitchCases.push_back(CB);
9094 CurMBB = Fallthrough;
9098 unsigned SelectionDAGBuilder::caseClusterRank(const CaseCluster &CC,
9099 CaseClusterIt First,
9100 CaseClusterIt Last) {
9101 return std::count_if(First, Last + 1, [&](const CaseCluster &X) {
9102 if (X.Prob != CC.Prob)
9103 return X.Prob > CC.Prob;
9105 // Ties are broken by comparing the case value.
9106 return X.Low->getValue().slt(CC.Low->getValue());
9110 void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList,
9111 const SwitchWorkListItem &W,
9113 MachineBasicBlock *SwitchMBB) {
9114 assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) &&
9115 "Clusters not sorted?");
9117 assert(W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!");
9119 // Balance the tree based on branch probabilities to create a near-optimal (in
9120 // terms of search time given key frequency) binary search tree. See e.g. Kurt
9121 // Mehlhorn "Nearly Optimal Binary Search Trees" (1975).
9122 CaseClusterIt LastLeft = W.FirstCluster;
9123 CaseClusterIt FirstRight = W.LastCluster;
9124 auto LeftProb = LastLeft->Prob + W.DefaultProb / 2;
9125 auto RightProb = FirstRight->Prob + W.DefaultProb / 2;
9127 // Move LastLeft and FirstRight towards each other from opposite directions to
9128 // find a partitioning of the clusters which balances the probability on both
9129 // sides. If LeftProb and RightProb are equal, alternate which side is
9130 // taken to ensure 0-probability nodes are distributed evenly.
9132 while (LastLeft + 1 < FirstRight) {
9133 if (LeftProb < RightProb || (LeftProb == RightProb && (I & 1)))
9134 LeftProb += (++LastLeft)->Prob;
9136 RightProb += (--FirstRight)->Prob;
9141 // Our binary search tree differs from a typical BST in that ours can have up
9142 // to three values in each leaf. The pivot selection above doesn't take that
9143 // into account, which means the tree might require more nodes and be less
9144 // efficient. We compensate for this here.
9146 unsigned NumLeft = LastLeft - W.FirstCluster + 1;
9147 unsigned NumRight = W.LastCluster - FirstRight + 1;
9149 if (std::min(NumLeft, NumRight) < 3 && std::max(NumLeft, NumRight) > 3) {
9150 // If one side has less than 3 clusters, and the other has more than 3,
9151 // consider taking a cluster from the other side.
9153 if (NumLeft < NumRight) {
9154 // Consider moving the first cluster on the right to the left side.
9155 CaseCluster &CC = *FirstRight;
9156 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
9157 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
9158 if (LeftSideRank <= RightSideRank) {
9159 // Moving the cluster to the left does not demote it.
9165 assert(NumRight < NumLeft);
9166 // Consider moving the last element on the left to the right side.
9167 CaseCluster &CC = *LastLeft;
9168 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
9169 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
9170 if (RightSideRank <= LeftSideRank) {
9171 // Moving the cluster to the right does not demot it.
9181 assert(LastLeft + 1 == FirstRight);
9182 assert(LastLeft >= W.FirstCluster);
9183 assert(FirstRight <= W.LastCluster);
9185 // Use the first element on the right as pivot since we will make less-than
9186 // comparisons against it.
9187 CaseClusterIt PivotCluster = FirstRight;
9188 assert(PivotCluster > W.FirstCluster);
9189 assert(PivotCluster <= W.LastCluster);
9191 CaseClusterIt FirstLeft = W.FirstCluster;
9192 CaseClusterIt LastRight = W.LastCluster;
9194 const ConstantInt *Pivot = PivotCluster->Low;
9196 // New blocks will be inserted immediately after the current one.
9197 MachineFunction::iterator BBI(W.MBB);
9200 // We will branch to the LHS if Value < Pivot. If LHS is a single cluster,
9201 // we can branch to its destination directly if it's squeezed exactly in
9202 // between the known lower bound and Pivot - 1.
9203 MachineBasicBlock *LeftMBB;
9204 if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range &&
9205 FirstLeft->Low == W.GE &&
9206 (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) {
9207 LeftMBB = FirstLeft->MBB;
9209 LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
9210 FuncInfo.MF->insert(BBI, LeftMBB);
9212 {LeftMBB, FirstLeft, LastLeft, W.GE, Pivot, W.DefaultProb / 2});
9213 // Put Cond in a virtual register to make it available from the new blocks.
9214 ExportFromCurrentBlock(Cond);
9217 // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a
9218 // single cluster, RHS.Low == Pivot, and we can branch to its destination
9219 // directly if RHS.High equals the current upper bound.
9220 MachineBasicBlock *RightMBB;
9221 if (FirstRight == LastRight && FirstRight->Kind == CC_Range &&
9222 W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) {
9223 RightMBB = FirstRight->MBB;
9225 RightMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
9226 FuncInfo.MF->insert(BBI, RightMBB);
9228 {RightMBB, FirstRight, LastRight, Pivot, W.LT, W.DefaultProb / 2});
9229 // Put Cond in a virtual register to make it available from the new blocks.
9230 ExportFromCurrentBlock(Cond);
9233 // Create the CaseBlock record that will be used to lower the branch.
9234 CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB,
9235 LeftProb, RightProb);
9237 if (W.MBB == SwitchMBB)
9238 visitSwitchCase(CB, SwitchMBB);
9240 SwitchCases.push_back(CB);
9243 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
9244 // Extract cases from the switch.
9245 BranchProbabilityInfo *BPI = FuncInfo.BPI;
9246 CaseClusterVector Clusters;
9247 Clusters.reserve(SI.getNumCases());
9248 for (auto I : SI.cases()) {
9249 MachineBasicBlock *Succ = FuncInfo.MBBMap[I.getCaseSuccessor()];
9250 const ConstantInt *CaseVal = I.getCaseValue();
9251 BranchProbability Prob =
9252 BPI ? BPI->getEdgeProbability(SI.getParent(), I.getSuccessorIndex())
9253 : BranchProbability(1, SI.getNumCases() + 1);
9254 Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Prob));
9257 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[SI.getDefaultDest()];
9259 // Cluster adjacent cases with the same destination. We do this at all
9260 // optimization levels because it's cheap to do and will make codegen faster
9261 // if there are many clusters.
9262 sortAndRangeify(Clusters);
9264 if (TM.getOptLevel() != CodeGenOpt::None) {
9265 // Replace an unreachable default with the most popular destination.
9266 // FIXME: Exploit unreachable default more aggressively.
9267 bool UnreachableDefault =
9268 isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg());
9269 if (UnreachableDefault && !Clusters.empty()) {
9270 DenseMap<const BasicBlock *, unsigned> Popularity;
9271 unsigned MaxPop = 0;
9272 const BasicBlock *MaxBB = nullptr;
9273 for (auto I : SI.cases()) {
9274 const BasicBlock *BB = I.getCaseSuccessor();
9275 if (++Popularity[BB] > MaxPop) {
9276 MaxPop = Popularity[BB];
9281 assert(MaxPop > 0 && MaxBB);
9282 DefaultMBB = FuncInfo.MBBMap[MaxBB];
9284 // Remove cases that were pointing to the destination that is now the
9286 CaseClusterVector New;
9287 New.reserve(Clusters.size());
9288 for (CaseCluster &CC : Clusters) {
9289 if (CC.MBB != DefaultMBB)
9292 Clusters = std::move(New);
9296 // If there is only the default destination, jump there directly.
9297 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
9298 if (Clusters.empty()) {
9299 SwitchMBB->addSuccessor(DefaultMBB);
9300 if (DefaultMBB != NextBlock(SwitchMBB)) {
9301 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
9302 getControlRoot(), DAG.getBasicBlock(DefaultMBB)));
9307 findJumpTables(Clusters, &SI, DefaultMBB);
9308 findBitTestClusters(Clusters, &SI);
9311 dbgs() << "Case clusters: ";
9312 for (const CaseCluster &C : Clusters) {
9313 if (C.Kind == CC_JumpTable) dbgs() << "JT:";
9314 if (C.Kind == CC_BitTests) dbgs() << "BT:";
9316 C.Low->getValue().print(dbgs(), true);
9317 if (C.Low != C.High) {
9319 C.High->getValue().print(dbgs(), true);
9326 assert(!Clusters.empty());
9327 SwitchWorkList WorkList;
9328 CaseClusterIt First = Clusters.begin();
9329 CaseClusterIt Last = Clusters.end() - 1;
9330 auto DefaultProb = getEdgeProbability(SwitchMBB, DefaultMBB);
9331 WorkList.push_back({SwitchMBB, First, Last, nullptr, nullptr, DefaultProb});
9333 while (!WorkList.empty()) {
9334 SwitchWorkListItem W = WorkList.back();
9335 WorkList.pop_back();
9336 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
9338 if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None &&
9339 !DefaultMBB->getParent()->getFunction()->optForMinSize()) {
9340 // For optimized builds, lower large range as a balanced binary tree.
9341 splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB);
9345 lowerWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB);