1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "ScheduleDAGSDNodes.h"
17 #include "SelectionDAGBuilder.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/TargetTransformInfo.h"
23 #include "llvm/CodeGen/FastISel.h"
24 #include "llvm/CodeGen/FunctionLoweringInfo.h"
25 #include "llvm/CodeGen/GCMetadata.h"
26 #include "llvm/CodeGen/GCStrategy.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
33 #include "llvm/CodeGen/SchedulerRegistry.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/DebugInfo.h"
36 #include "llvm/IR/Constants.h"
37 #include "llvm/IR/Function.h"
38 #include "llvm/IR/InlineAsm.h"
39 #include "llvm/IR/Instructions.h"
40 #include "llvm/IR/IntrinsicInst.h"
41 #include "llvm/IR/Intrinsics.h"
42 #include "llvm/IR/LLVMContext.h"
43 #include "llvm/IR/Module.h"
44 #include "llvm/Support/Compiler.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/ErrorHandling.h"
47 #include "llvm/Support/Timer.h"
48 #include "llvm/Support/raw_ostream.h"
49 #include "llvm/Target/TargetInstrInfo.h"
50 #include "llvm/Target/TargetIntrinsicInfo.h"
51 #include "llvm/Target/TargetLibraryInfo.h"
52 #include "llvm/Target/TargetLowering.h"
53 #include "llvm/Target/TargetMachine.h"
54 #include "llvm/Target/TargetOptions.h"
55 #include "llvm/Target/TargetRegisterInfo.h"
56 #include "llvm/Target/TargetSubtargetInfo.h"
57 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
61 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
62 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
63 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
64 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
65 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
69 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
70 cl::desc("Enable extra verbose messages in the \"fast\" "
71 "instruction selector"));
73 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
74 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
75 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
76 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
77 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
78 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
79 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
81 // Standard binary operators...
82 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
83 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
84 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
85 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
86 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
87 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
88 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
89 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
90 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
91 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
92 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
93 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
95 // Logical operators...
96 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
97 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
98 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
100 // Memory instructions...
101 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
102 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
103 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
104 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
105 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
106 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
107 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
109 // Convert instructions...
110 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
111 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
112 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
113 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
114 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
115 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
116 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
117 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
118 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
119 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
120 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
121 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
123 // Other instructions...
124 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
125 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
126 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
127 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
128 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
129 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
130 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
131 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
132 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
133 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
134 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
135 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
136 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
137 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
138 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
142 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
143 cl::desc("Enable verbose messages in the \"fast\" "
144 "instruction selector"));
146 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
147 cl::desc("Enable abort calls when \"fast\" instruction selection "
148 "fails to lower an instruction"));
150 EnableFastISelAbortArgs("fast-isel-abort-args", cl::Hidden,
151 cl::desc("Enable abort calls when \"fast\" instruction selection "
152 "fails to lower a formal argument"));
156 cl::desc("use Machine Branch Probability Info"),
157 cl::init(true), cl::Hidden);
161 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
162 cl::desc("Pop up a window to show dags before the first "
163 "dag combine pass"));
165 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
166 cl::desc("Pop up a window to show dags before legalize types"));
168 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
169 cl::desc("Pop up a window to show dags before legalize"));
171 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
172 cl::desc("Pop up a window to show dags before the second "
173 "dag combine pass"));
175 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
176 cl::desc("Pop up a window to show dags before the post legalize types"
177 " dag combine pass"));
179 ViewISelDAGs("view-isel-dags", cl::Hidden,
180 cl::desc("Pop up a window to show isel dags as they are selected"));
182 ViewSchedDAGs("view-sched-dags", cl::Hidden,
183 cl::desc("Pop up a window to show sched dags as they are processed"));
185 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
186 cl::desc("Pop up a window to show SUnit dags after they are processed"));
188 static const bool ViewDAGCombine1 = false,
189 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
190 ViewDAGCombine2 = false,
191 ViewDAGCombineLT = false,
192 ViewISelDAGs = false, ViewSchedDAGs = false,
193 ViewSUnitDAGs = false;
196 //===---------------------------------------------------------------------===//
198 /// RegisterScheduler class - Track the registration of instruction schedulers.
200 //===---------------------------------------------------------------------===//
201 MachinePassRegistry RegisterScheduler::Registry;
203 //===---------------------------------------------------------------------===//
205 /// ISHeuristic command line option for instruction schedulers.
207 //===---------------------------------------------------------------------===//
208 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
209 RegisterPassParser<RegisterScheduler> >
210 ISHeuristic("pre-RA-sched",
211 cl::init(&createDefaultScheduler),
212 cl::desc("Instruction schedulers available (before register"
215 static RegisterScheduler
216 defaultListDAGScheduler("default", "Best scheduler for the target",
217 createDefaultScheduler);
220 //===--------------------------------------------------------------------===//
221 /// createDefaultScheduler - This creates an instruction scheduler appropriate
223 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
224 CodeGenOpt::Level OptLevel) {
225 const TargetLowering &TLI = IS->getTargetLowering();
226 const TargetSubtargetInfo &ST = IS->TM.getSubtarget<TargetSubtargetInfo>();
228 if (OptLevel == CodeGenOpt::None || ST.enableMachineScheduler() ||
229 TLI.getSchedulingPreference() == Sched::Source)
230 return createSourceListDAGScheduler(IS, OptLevel);
231 if (TLI.getSchedulingPreference() == Sched::RegPressure)
232 return createBURRListDAGScheduler(IS, OptLevel);
233 if (TLI.getSchedulingPreference() == Sched::Hybrid)
234 return createHybridListDAGScheduler(IS, OptLevel);
235 if (TLI.getSchedulingPreference() == Sched::VLIW)
236 return createVLIWDAGScheduler(IS, OptLevel);
237 assert(TLI.getSchedulingPreference() == Sched::ILP &&
238 "Unknown sched type!");
239 return createILPListDAGScheduler(IS, OptLevel);
243 // EmitInstrWithCustomInserter - This method should be implemented by targets
244 // that mark instructions with the 'usesCustomInserter' flag. These
245 // instructions are special in various ways, which require special support to
246 // insert. The specified MachineInstr is created but not inserted into any
247 // basic blocks, and this method is called to expand it into a sequence of
248 // instructions, potentially also creating new basic blocks and control flow.
249 // When new basic blocks are inserted and the edges from MBB to its successors
250 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
253 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
254 MachineBasicBlock *MBB) const {
256 dbgs() << "If a target marks an instruction with "
257 "'usesCustomInserter', it must implement "
258 "TargetLowering::EmitInstrWithCustomInserter!";
263 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
264 SDNode *Node) const {
265 assert(!MI->hasPostISelHook() &&
266 "If a target marks an instruction with 'hasPostISelHook', "
267 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
270 //===----------------------------------------------------------------------===//
271 // SelectionDAGISel code
272 //===----------------------------------------------------------------------===//
274 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm,
275 CodeGenOpt::Level OL) :
276 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()),
277 FuncInfo(new FunctionLoweringInfo(TLI)),
278 CurDAG(new SelectionDAG(tm, OL)),
279 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
283 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
284 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
285 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
286 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry());
289 SelectionDAGISel::~SelectionDAGISel() {
295 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
296 AU.addRequired<AliasAnalysis>();
297 AU.addPreserved<AliasAnalysis>();
298 AU.addRequired<GCModuleInfo>();
299 AU.addPreserved<GCModuleInfo>();
300 AU.addRequired<TargetLibraryInfo>();
301 if (UseMBPI && OptLevel != CodeGenOpt::None)
302 AU.addRequired<BranchProbabilityInfo>();
303 MachineFunctionPass::getAnalysisUsage(AU);
306 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
307 /// may trap on it. In this case we have to split the edge so that the path
308 /// through the predecessor block that doesn't go to the phi block doesn't
309 /// execute the possibly trapping instruction.
311 /// This is required for correctness, so it must be done at -O0.
313 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
314 // Loop for blocks with phi nodes.
315 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
316 PHINode *PN = dyn_cast<PHINode>(BB->begin());
317 if (PN == 0) continue;
320 // For each block with a PHI node, check to see if any of the input values
321 // are potentially trapping constant expressions. Constant expressions are
322 // the only potentially trapping value that can occur as the argument to a
324 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
325 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
326 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
327 if (CE == 0 || !CE->canTrap()) continue;
329 // The only case we have to worry about is when the edge is critical.
330 // Since this block has a PHI Node, we assume it has multiple input
331 // edges: check to see if the pred has multiple successors.
332 BasicBlock *Pred = PN->getIncomingBlock(i);
333 if (Pred->getTerminator()->getNumSuccessors() == 1)
336 // Okay, we have to split this edge.
337 SplitCriticalEdge(Pred->getTerminator(),
338 GetSuccessorNumber(Pred, BB), SDISel, true);
344 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
345 // Do some sanity-checking on the command-line options.
346 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
347 "-fast-isel-verbose requires -fast-isel");
348 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
349 "-fast-isel-abort requires -fast-isel");
351 const Function &Fn = *mf.getFunction();
352 const TargetInstrInfo &TII = *TM.getInstrInfo();
353 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
356 RegInfo = &MF->getRegInfo();
357 AA = &getAnalysis<AliasAnalysis>();
358 LibInfo = &getAnalysis<TargetLibraryInfo>();
359 TTI = getAnalysisIfAvailable<TargetTransformInfo>();
360 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
362 TargetSubtargetInfo &ST =
363 const_cast<TargetSubtargetInfo&>(TM.getSubtarget<TargetSubtargetInfo>());
364 ST.resetSubtargetFeatures(MF);
365 TM.resetTargetOptions(MF);
367 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
369 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
371 CurDAG->init(*MF, TTI);
372 FuncInfo->set(Fn, *MF);
374 if (UseMBPI && OptLevel != CodeGenOpt::None)
375 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
379 SDB->init(GFI, *AA, LibInfo);
381 MF->setHasMSInlineAsm(false);
382 SelectAllBasicBlocks(Fn);
384 // If the first basic block in the function has live ins that need to be
385 // copied into vregs, emit the copies into the top of the block before
386 // emitting the code for the block.
387 MachineBasicBlock *EntryMBB = MF->begin();
388 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
390 DenseMap<unsigned, unsigned> LiveInMap;
391 if (!FuncInfo->ArgDbgValues.empty())
392 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
393 E = RegInfo->livein_end(); LI != E; ++LI)
395 LiveInMap.insert(std::make_pair(LI->first, LI->second));
397 // Insert DBG_VALUE instructions for function arguments to the entry block.
398 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
399 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
400 unsigned Reg = MI->getOperand(0).getReg();
401 if (TargetRegisterInfo::isPhysicalRegister(Reg))
402 EntryMBB->insert(EntryMBB->begin(), MI);
404 MachineInstr *Def = RegInfo->getVRegDef(Reg);
405 MachineBasicBlock::iterator InsertPos = Def;
406 // FIXME: VR def may not be in entry block.
407 Def->getParent()->insert(llvm::next(InsertPos), MI);
410 // If Reg is live-in then update debug info to track its copy in a vreg.
411 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
412 if (LDI != LiveInMap.end()) {
413 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
414 MachineBasicBlock::iterator InsertPos = Def;
415 const MDNode *Variable =
416 MI->getOperand(MI->getNumOperands()-1).getMetadata();
417 unsigned Offset = MI->getOperand(1).getImm();
418 // Def is never a terminator here, so it is ok to increment InsertPos.
419 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
420 TII.get(TargetOpcode::DBG_VALUE))
421 .addReg(LDI->second, RegState::Debug)
422 .addImm(Offset).addMetadata(Variable);
424 // If this vreg is directly copied into an exported register then
425 // that COPY instructions also need DBG_VALUE, if it is the only
426 // user of LDI->second.
427 MachineInstr *CopyUseMI = NULL;
428 for (MachineRegisterInfo::use_iterator
429 UI = RegInfo->use_begin(LDI->second);
430 MachineInstr *UseMI = UI.skipInstruction();) {
431 if (UseMI->isDebugValue()) continue;
432 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
433 CopyUseMI = UseMI; continue;
435 // Otherwise this is another use or second copy use.
436 CopyUseMI = NULL; break;
439 MachineInstr *NewMI =
440 BuildMI(*MF, CopyUseMI->getDebugLoc(),
441 TII.get(TargetOpcode::DBG_VALUE))
442 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug)
443 .addImm(Offset).addMetadata(Variable);
444 MachineBasicBlock::iterator Pos = CopyUseMI;
445 EntryMBB->insertAfter(Pos, NewMI);
450 // Determine if there are any calls in this machine function.
451 MachineFrameInfo *MFI = MF->getFrameInfo();
452 for (MachineFunction::const_iterator I = MF->begin(), E = MF->end(); I != E;
455 if (MFI->hasCalls() && MF->hasMSInlineAsm())
458 const MachineBasicBlock *MBB = I;
459 for (MachineBasicBlock::const_iterator II = MBB->begin(), IE = MBB->end();
461 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode());
462 if ((MCID.isCall() && !MCID.isReturn()) ||
463 II->isStackAligningInlineAsm()) {
464 MFI->setHasCalls(true);
466 if (II->isMSInlineAsm()) {
467 MF->setHasMSInlineAsm(true);
472 // Determine if there is a call to setjmp in the machine function.
473 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
475 // Replace forward-declared registers with the registers containing
476 // the desired value.
477 MachineRegisterInfo &MRI = MF->getRegInfo();
478 for (DenseMap<unsigned, unsigned>::iterator
479 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
481 unsigned From = I->first;
482 unsigned To = I->second;
483 // If To is also scheduled to be replaced, find what its ultimate
486 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To);
491 MRI.replaceRegWith(From, To);
494 // Freeze the set of reserved registers now that MachineFrameInfo has been
495 // set up. All the information required by getReservedRegs() should be
497 MRI.freezeReservedRegs(*MF);
499 // Release function-specific state. SDB and CurDAG are already cleared
506 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
507 BasicBlock::const_iterator End,
509 // Lower all of the non-terminator instructions. If a call is emitted
510 // as a tail call, cease emitting nodes for this block. Terminators
511 // are handled below.
512 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
515 // Make sure the root of the DAG is up-to-date.
516 CurDAG->setRoot(SDB->getControlRoot());
517 HadTailCall = SDB->HasTailCall;
520 // Final step, emit the lowered DAG as machine code.
524 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
525 SmallPtrSet<SDNode*, 128> VisitedNodes;
526 SmallVector<SDNode*, 128> Worklist;
528 Worklist.push_back(CurDAG->getRoot().getNode());
534 SDNode *N = Worklist.pop_back_val();
536 // If we've already seen this node, ignore it.
537 if (!VisitedNodes.insert(N))
540 // Otherwise, add all chain operands to the worklist.
541 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
542 if (N->getOperand(i).getValueType() == MVT::Other)
543 Worklist.push_back(N->getOperand(i).getNode());
545 // If this is a CopyToReg with a vreg dest, process it.
546 if (N->getOpcode() != ISD::CopyToReg)
549 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
550 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
553 // Ignore non-scalar or non-integer values.
554 SDValue Src = N->getOperand(2);
555 EVT SrcVT = Src.getValueType();
556 if (!SrcVT.isInteger() || SrcVT.isVector())
559 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
560 CurDAG->ComputeMaskedBits(Src, KnownZero, KnownOne);
561 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
562 } while (!Worklist.empty());
565 void SelectionDAGISel::CodeGenAndEmitDAG() {
566 std::string GroupName;
567 if (TimePassesIsEnabled)
568 GroupName = "Instruction Selection and Scheduling";
569 std::string BlockName;
570 int BlockNumber = -1;
573 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
574 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
578 BlockNumber = FuncInfo->MBB->getNumber();
579 BlockName = MF->getName().str() + ":" +
580 FuncInfo->MBB->getBasicBlock()->getName().str();
582 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
583 << " '" << BlockName << "'\n"; CurDAG->dump());
585 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
587 // Run the DAG combiner in pre-legalize mode.
589 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
590 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
593 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
594 << " '" << BlockName << "'\n"; CurDAG->dump());
596 // Second step, hack on the DAG until it only uses operations and types that
597 // the target supports.
598 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
603 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
604 Changed = CurDAG->LegalizeTypes();
607 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
608 << " '" << BlockName << "'\n"; CurDAG->dump());
611 if (ViewDAGCombineLT)
612 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
614 // Run the DAG combiner in post-type-legalize mode.
616 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
617 TimePassesIsEnabled);
618 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
621 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
622 << " '" << BlockName << "'\n"; CurDAG->dump());
626 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
627 Changed = CurDAG->LegalizeVectors();
632 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
633 CurDAG->LegalizeTypes();
636 if (ViewDAGCombineLT)
637 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
639 // Run the DAG combiner in post-type-legalize mode.
641 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
642 TimePassesIsEnabled);
643 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
646 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
647 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
650 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
653 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
657 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
658 << " '" << BlockName << "'\n"; CurDAG->dump());
660 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
662 // Run the DAG combiner in post-legalize mode.
664 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
665 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
668 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
669 << " '" << BlockName << "'\n"; CurDAG->dump());
671 if (OptLevel != CodeGenOpt::None)
672 ComputeLiveOutVRegInfo();
674 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
676 // Third, instruction select all of the operations to machine code, adding the
677 // code to the MachineBasicBlock.
679 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
680 DoInstructionSelection();
683 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
684 << " '" << BlockName << "'\n"; CurDAG->dump());
686 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
688 // Schedule machine code.
689 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
691 NamedRegionTimer T("Instruction Scheduling", GroupName,
692 TimePassesIsEnabled);
693 Scheduler->Run(CurDAG, FuncInfo->MBB);
696 if (ViewSUnitDAGs) Scheduler->viewGraph();
698 // Emit machine code to BB. This can change 'BB' to the last block being
700 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
702 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
704 // FuncInfo->InsertPt is passed by reference and set to the end of the
705 // scheduled instructions.
706 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
709 // If the block was split, make sure we update any references that are used to
710 // update PHI nodes later on.
711 if (FirstMBB != LastMBB)
712 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
714 // Free the scheduler state.
716 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
717 TimePassesIsEnabled);
721 // Free the SelectionDAG state, now that we're finished with it.
726 /// ISelUpdater - helper class to handle updates of the instruction selection
728 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
729 SelectionDAG::allnodes_iterator &ISelPosition;
731 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
732 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
734 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
735 /// deleted is the current ISelPosition node, update ISelPosition.
737 virtual void NodeDeleted(SDNode *N, SDNode *E) {
738 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
742 } // end anonymous namespace
744 void SelectionDAGISel::DoInstructionSelection() {
745 DEBUG(errs() << "===== Instruction selection begins: BB#"
746 << FuncInfo->MBB->getNumber()
747 << " '" << FuncInfo->MBB->getName() << "'\n");
751 // Select target instructions for the DAG.
753 // Number all nodes with a topological order and set DAGSize.
754 DAGSize = CurDAG->AssignTopologicalOrder();
756 // Create a dummy node (which is not added to allnodes), that adds
757 // a reference to the root node, preventing it from being deleted,
758 // and tracking any changes of the root.
759 HandleSDNode Dummy(CurDAG->getRoot());
760 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
763 // Make sure that ISelPosition gets properly updated when nodes are deleted
764 // in calls made from this function.
765 ISelUpdater ISU(*CurDAG, ISelPosition);
767 // The AllNodes list is now topological-sorted. Visit the
768 // nodes by starting at the end of the list (the root of the
769 // graph) and preceding back toward the beginning (the entry
771 while (ISelPosition != CurDAG->allnodes_begin()) {
772 SDNode *Node = --ISelPosition;
773 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
774 // but there are currently some corner cases that it misses. Also, this
775 // makes it theoretically possible to disable the DAGCombiner.
776 if (Node->use_empty())
779 SDNode *ResNode = Select(Node);
781 // FIXME: This is pretty gross. 'Select' should be changed to not return
782 // anything at all and this code should be nuked with a tactical strike.
784 // If node should not be replaced, continue with the next one.
785 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
789 // Propagate ordering
790 CurDAG->AssignOrdering(ResNode, CurDAG->GetOrdering(Node));
792 ReplaceUses(Node, ResNode);
795 // If after the replacement this node is not used any more,
796 // remove this dead node.
797 if (Node->use_empty()) // Don't delete EntryToken, etc.
798 CurDAG->RemoveDeadNode(Node);
801 CurDAG->setRoot(Dummy.getValue());
804 DEBUG(errs() << "===== Instruction selection ends:\n");
806 PostprocessISelDAG();
809 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
810 /// do other setup for EH landing-pad blocks.
811 void SelectionDAGISel::PrepareEHLandingPad() {
812 MachineBasicBlock *MBB = FuncInfo->MBB;
814 // Add a label to mark the beginning of the landing pad. Deletion of the
815 // landing pad can thus be detected via the MachineModuleInfo.
816 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
818 // Assign the call site to the landing pad's begin label.
819 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
821 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
822 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
825 // Mark exception register as live in.
826 unsigned Reg = TLI.getExceptionPointerRegister();
827 if (Reg) MBB->addLiveIn(Reg);
829 // Mark exception selector register as live in.
830 Reg = TLI.getExceptionSelectorRegister();
831 if (Reg) MBB->addLiveIn(Reg);
834 /// TryToFoldFastISelLoad - We're checking to see if we can fold the specified
835 /// load into the specified FoldInst. Note that we could have a sequence where
836 /// multiple LLVM IR instructions are folded into the same machineinstr. For
837 /// example we could have:
838 /// A: x = load i32 *P
839 /// B: y = icmp A, 42
842 /// In this scenario, LI is "A", and FoldInst is "C". We know about "B" (and
843 /// any other folded instructions) because it is between A and C.
845 /// If we succeed in folding the load into the operation, return true.
847 bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI,
848 const Instruction *FoldInst,
850 // We know that the load has a single use, but don't know what it is. If it
851 // isn't one of the folded instructions, then we can't succeed here. Handle
852 // this by scanning the single-use users of the load until we get to FoldInst.
853 unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs.
855 const Instruction *TheUser = LI->use_back();
856 while (TheUser != FoldInst && // Scan up until we find FoldInst.
857 // Stay in the right block.
858 TheUser->getParent() == FoldInst->getParent() &&
859 --MaxUsers) { // Don't scan too far.
860 // If there are multiple or no uses of this instruction, then bail out.
861 if (!TheUser->hasOneUse())
864 TheUser = TheUser->use_back();
867 // If we didn't find the fold instruction, then we failed to collapse the
869 if (TheUser != FoldInst)
872 // Don't try to fold volatile loads. Target has to deal with alignment
874 if (LI->isVolatile()) return false;
876 // Figure out which vreg this is going into. If there is no assigned vreg yet
877 // then there actually was no reference to it. Perhaps the load is referenced
878 // by a dead instruction.
879 unsigned LoadReg = FastIS->getRegForValue(LI);
883 // Check to see what the uses of this vreg are. If it has no uses, or more
884 // than one use (at the machine instr level) then we can't fold it.
885 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg);
886 if (RI == RegInfo->reg_end())
889 // See if there is exactly one use of the vreg. If there are multiple uses,
890 // then the instruction got lowered to multiple machine instructions or the
891 // use of the loaded value ended up being multiple operands of the result, in
892 // either case, we can't fold this.
893 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI;
894 if (PostRI != RegInfo->reg_end())
897 assert(RI.getOperand().isUse() &&
898 "The only use of the vreg must be a use, we haven't emitted the def!");
900 MachineInstr *User = &*RI;
902 // Set the insertion point properly. Folding the load can cause generation of
903 // other random instructions (like sign extends) for addressing modes, make
904 // sure they get inserted in a logical place before the new instruction.
905 FuncInfo->InsertPt = User;
906 FuncInfo->MBB = User->getParent();
908 // Ask the target to try folding the load.
909 return FastIS->TryToFoldLoad(User, RI.getOperandNo(), LI);
912 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
913 /// side-effect free and is either dead or folded into a generated instruction.
914 /// Return false if it needs to be emitted.
915 static bool isFoldedOrDeadInstruction(const Instruction *I,
916 FunctionLoweringInfo *FuncInfo) {
917 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
918 !isa<TerminatorInst>(I) && // Terminators aren't folded.
919 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
920 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
921 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
925 // Collect per Instruction statistics for fast-isel misses. Only those
926 // instructions that cause the bail are accounted for. It does not account for
927 // instructions higher in the block. Thus, summing the per instructions stats
928 // will not add up to what is reported by NumFastIselFailures.
929 static void collectFailStats(const Instruction *I) {
930 switch (I->getOpcode()) {
931 default: assert (0 && "<Invalid operator> ");
934 case Instruction::Ret: NumFastIselFailRet++; return;
935 case Instruction::Br: NumFastIselFailBr++; return;
936 case Instruction::Switch: NumFastIselFailSwitch++; return;
937 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
938 case Instruction::Invoke: NumFastIselFailInvoke++; return;
939 case Instruction::Resume: NumFastIselFailResume++; return;
940 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
942 // Standard binary operators...
943 case Instruction::Add: NumFastIselFailAdd++; return;
944 case Instruction::FAdd: NumFastIselFailFAdd++; return;
945 case Instruction::Sub: NumFastIselFailSub++; return;
946 case Instruction::FSub: NumFastIselFailFSub++; return;
947 case Instruction::Mul: NumFastIselFailMul++; return;
948 case Instruction::FMul: NumFastIselFailFMul++; return;
949 case Instruction::UDiv: NumFastIselFailUDiv++; return;
950 case Instruction::SDiv: NumFastIselFailSDiv++; return;
951 case Instruction::FDiv: NumFastIselFailFDiv++; return;
952 case Instruction::URem: NumFastIselFailURem++; return;
953 case Instruction::SRem: NumFastIselFailSRem++; return;
954 case Instruction::FRem: NumFastIselFailFRem++; return;
956 // Logical operators...
957 case Instruction::And: NumFastIselFailAnd++; return;
958 case Instruction::Or: NumFastIselFailOr++; return;
959 case Instruction::Xor: NumFastIselFailXor++; return;
961 // Memory instructions...
962 case Instruction::Alloca: NumFastIselFailAlloca++; return;
963 case Instruction::Load: NumFastIselFailLoad++; return;
964 case Instruction::Store: NumFastIselFailStore++; return;
965 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
966 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
967 case Instruction::Fence: NumFastIselFailFence++; return;
968 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
970 // Convert instructions...
971 case Instruction::Trunc: NumFastIselFailTrunc++; return;
972 case Instruction::ZExt: NumFastIselFailZExt++; return;
973 case Instruction::SExt: NumFastIselFailSExt++; return;
974 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
975 case Instruction::FPExt: NumFastIselFailFPExt++; return;
976 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
977 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
978 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
979 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
980 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
981 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
982 case Instruction::BitCast: NumFastIselFailBitCast++; return;
984 // Other instructions...
985 case Instruction::ICmp: NumFastIselFailICmp++; return;
986 case Instruction::FCmp: NumFastIselFailFCmp++; return;
987 case Instruction::PHI: NumFastIselFailPHI++; return;
988 case Instruction::Select: NumFastIselFailSelect++; return;
989 case Instruction::Call: NumFastIselFailCall++; return;
990 case Instruction::Shl: NumFastIselFailShl++; return;
991 case Instruction::LShr: NumFastIselFailLShr++; return;
992 case Instruction::AShr: NumFastIselFailAShr++; return;
993 case Instruction::VAArg: NumFastIselFailVAArg++; return;
994 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
995 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
996 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
997 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
998 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
999 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
1004 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
1005 // Initialize the Fast-ISel state, if needed.
1006 FastISel *FastIS = 0;
1007 if (TM.Options.EnableFastISel)
1008 FastIS = TLI.createFastISel(*FuncInfo, LibInfo);
1010 // Iterate over all basic blocks in the function.
1011 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
1012 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
1013 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
1014 const BasicBlock *LLVMBB = *I;
1016 if (OptLevel != CodeGenOpt::None) {
1017 bool AllPredsVisited = true;
1018 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
1020 if (!FuncInfo->VisitedBBs.count(*PI)) {
1021 AllPredsVisited = false;
1026 if (AllPredsVisited) {
1027 for (BasicBlock::const_iterator I = LLVMBB->begin();
1028 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1029 FuncInfo->ComputePHILiveOutRegInfo(PN);
1031 for (BasicBlock::const_iterator I = LLVMBB->begin();
1032 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1033 FuncInfo->InvalidatePHILiveOutRegInfo(PN);
1036 FuncInfo->VisitedBBs.insert(LLVMBB);
1039 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
1040 BasicBlock::const_iterator const End = LLVMBB->end();
1041 BasicBlock::const_iterator BI = End;
1043 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
1044 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1046 // Setup an EH landing-pad block.
1047 if (FuncInfo->MBB->isLandingPad())
1048 PrepareEHLandingPad();
1050 // Before doing SelectionDAG ISel, see if FastISel has been requested.
1052 FastIS->startNewBlock();
1054 // Emit code for any incoming arguments. This must happen before
1055 // beginning FastISel on the entry block.
1056 if (LLVMBB == &Fn.getEntryBlock()) {
1057 // Lower any arguments needed in this block if this is the entry block.
1058 if (!FastIS->LowerArguments()) {
1059 // Fast isel failed to lower these arguments
1060 if (EnableFastISelAbortArgs)
1061 llvm_unreachable("FastISel didn't lower all arguments");
1063 // Use SelectionDAG argument lowering
1065 CurDAG->setRoot(SDB->getControlRoot());
1067 CodeGenAndEmitDAG();
1070 // If we inserted any instructions at the beginning, make a note of
1071 // where they are, so we can be sure to emit subsequent instructions
1073 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1074 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
1076 FastIS->setLastLocalValue(0);
1079 unsigned NumFastIselRemaining = std::distance(Begin, End);
1080 // Do FastISel on as many instructions as possible.
1081 for (; BI != Begin; --BI) {
1082 const Instruction *Inst = llvm::prior(BI);
1084 // If we no longer require this instruction, skip it.
1085 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1086 --NumFastIselRemaining;
1090 // Bottom-up: reset the insert pos at the top, after any local-value
1092 FastIS->recomputeInsertPt();
1094 // Try to select the instruction with FastISel.
1095 if (FastIS->SelectInstruction(Inst)) {
1096 --NumFastIselRemaining;
1097 ++NumFastIselSuccess;
1098 // If fast isel succeeded, skip over all the folded instructions, and
1099 // then see if there is a load right before the selected instructions.
1100 // Try to fold the load if so.
1101 const Instruction *BeforeInst = Inst;
1102 while (BeforeInst != Begin) {
1103 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst));
1104 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1107 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1108 BeforeInst->hasOneUse() &&
1109 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), Inst, FastIS)) {
1110 // If we succeeded, don't re-select the load.
1111 BI = llvm::next(BasicBlock::const_iterator(BeforeInst));
1112 --NumFastIselRemaining;
1113 ++NumFastIselSuccess;
1119 if (EnableFastISelVerbose2)
1120 collectFailStats(Inst);
1123 // Then handle certain instructions as single-LLVM-Instruction blocks.
1124 if (isa<CallInst>(Inst)) {
1126 if (EnableFastISelVerbose || EnableFastISelAbort) {
1127 dbgs() << "FastISel missed call: ";
1131 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
1132 unsigned &R = FuncInfo->ValueMap[Inst];
1134 R = FuncInfo->CreateRegs(Inst->getType());
1137 bool HadTailCall = false;
1138 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt;
1139 SelectBasicBlock(Inst, BI, HadTailCall);
1141 // If the call was emitted as a tail call, we're done with the block.
1142 // We also need to delete any previously emitted instructions.
1144 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end());
1149 // Recompute NumFastIselRemaining as Selection DAG instruction
1150 // selection may have handled the call, input args, etc.
1151 unsigned RemainingNow = std::distance(Begin, BI);
1152 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1153 NumFastIselRemaining = RemainingNow;
1157 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) {
1158 // Don't abort, and use a different message for terminator misses.
1159 NumFastIselFailures += NumFastIselRemaining;
1160 if (EnableFastISelVerbose || EnableFastISelAbort) {
1161 dbgs() << "FastISel missed terminator: ";
1165 NumFastIselFailures += NumFastIselRemaining;
1166 if (EnableFastISelVerbose || EnableFastISelAbort) {
1167 dbgs() << "FastISel miss: ";
1170 if (EnableFastISelAbort)
1171 // The "fast" selector couldn't handle something and bailed.
1172 // For the purpose of debugging, just abort.
1173 llvm_unreachable("FastISel didn't select the entire block");
1178 FastIS->recomputeInsertPt();
1180 // Lower any arguments needed in this block if this is the entry block.
1181 if (LLVMBB == &Fn.getEntryBlock())
1188 ++NumFastIselBlocks;
1191 // Run SelectionDAG instruction selection on the remainder of the block
1192 // not handled by FastISel. If FastISel is not run, this is the entire
1195 SelectBasicBlock(Begin, BI, HadTailCall);
1199 FuncInfo->PHINodesToUpdate.clear();
1203 SDB->clearDanglingDebugInfo();
1207 SelectionDAGISel::FinishBasicBlock() {
1209 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1210 << FuncInfo->PHINodesToUpdate.size() << "\n";
1211 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1212 dbgs() << "Node " << i << " : ("
1213 << FuncInfo->PHINodesToUpdate[i].first
1214 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1216 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1217 // PHI nodes in successors.
1218 if (SDB->SwitchCases.empty() &&
1219 SDB->JTCases.empty() &&
1220 SDB->BitTestCases.empty()) {
1221 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1222 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1223 assert(PHI->isPHI() &&
1224 "This is not a machine PHI node that we are updating!");
1225 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1227 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1232 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1233 // Lower header first, if it wasn't already lowered
1234 if (!SDB->BitTestCases[i].Emitted) {
1235 // Set the current basic block to the mbb we wish to insert the code into
1236 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1237 FuncInfo->InsertPt = FuncInfo->MBB->end();
1239 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1240 CurDAG->setRoot(SDB->getRoot());
1242 CodeGenAndEmitDAG();
1245 uint32_t UnhandledWeight = 0;
1246 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j)
1247 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight;
1249 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1250 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight;
1251 // Set the current basic block to the mbb we wish to insert the code into
1252 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1253 FuncInfo->InsertPt = FuncInfo->MBB->end();
1256 SDB->visitBitTestCase(SDB->BitTestCases[i],
1257 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1259 SDB->BitTestCases[i].Reg,
1260 SDB->BitTestCases[i].Cases[j],
1263 SDB->visitBitTestCase(SDB->BitTestCases[i],
1264 SDB->BitTestCases[i].Default,
1266 SDB->BitTestCases[i].Reg,
1267 SDB->BitTestCases[i].Cases[j],
1271 CurDAG->setRoot(SDB->getRoot());
1273 CodeGenAndEmitDAG();
1277 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1279 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1280 MachineBasicBlock *PHIBB = PHI->getParent();
1281 assert(PHI->isPHI() &&
1282 "This is not a machine PHI node that we are updating!");
1283 // This is "default" BB. We have two jumps to it. From "header" BB and
1284 // from last "case" BB.
1285 if (PHIBB == SDB->BitTestCases[i].Default)
1286 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1287 .addMBB(SDB->BitTestCases[i].Parent)
1288 .addReg(FuncInfo->PHINodesToUpdate[pi].second)
1289 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB);
1290 // One of "cases" BB.
1291 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1293 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1294 if (cBB->isSuccessor(PHIBB))
1295 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1299 SDB->BitTestCases.clear();
1301 // If the JumpTable record is filled in, then we need to emit a jump table.
1302 // Updating the PHI nodes is tricky in this case, since we need to determine
1303 // whether the PHI is a successor of the range check MBB or the jump table MBB
1304 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1305 // Lower header first, if it wasn't already lowered
1306 if (!SDB->JTCases[i].first.Emitted) {
1307 // Set the current basic block to the mbb we wish to insert the code into
1308 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1309 FuncInfo->InsertPt = FuncInfo->MBB->end();
1311 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1313 CurDAG->setRoot(SDB->getRoot());
1315 CodeGenAndEmitDAG();
1318 // Set the current basic block to the mbb we wish to insert the code into
1319 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1320 FuncInfo->InsertPt = FuncInfo->MBB->end();
1322 SDB->visitJumpTable(SDB->JTCases[i].second);
1323 CurDAG->setRoot(SDB->getRoot());
1325 CodeGenAndEmitDAG();
1328 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1330 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1331 MachineBasicBlock *PHIBB = PHI->getParent();
1332 assert(PHI->isPHI() &&
1333 "This is not a machine PHI node that we are updating!");
1334 // "default" BB. We can go there only from header BB.
1335 if (PHIBB == SDB->JTCases[i].second.Default)
1336 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1337 .addMBB(SDB->JTCases[i].first.HeaderBB);
1338 // JT BB. Just iterate over successors here
1339 if (FuncInfo->MBB->isSuccessor(PHIBB))
1340 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1343 SDB->JTCases.clear();
1345 // If the switch block involved a branch to one of the actual successors, we
1346 // need to update PHI nodes in that block.
1347 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1348 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1349 assert(PHI->isPHI() &&
1350 "This is not a machine PHI node that we are updating!");
1351 if (FuncInfo->MBB->isSuccessor(PHI->getParent()))
1352 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1355 // If we generated any switch lowering information, build and codegen any
1356 // additional DAGs necessary.
1357 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1358 // Set the current basic block to the mbb we wish to insert the code into
1359 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1360 FuncInfo->InsertPt = FuncInfo->MBB->end();
1362 // Determine the unique successors.
1363 SmallVector<MachineBasicBlock *, 2> Succs;
1364 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1365 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1366 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1368 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1369 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1370 CurDAG->setRoot(SDB->getRoot());
1372 CodeGenAndEmitDAG();
1374 // Remember the last block, now that any splitting is done, for use in
1375 // populating PHI nodes in successors.
1376 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1378 // Handle any PHI nodes in successors of this chunk, as if we were coming
1379 // from the original BB before switch expansion. Note that PHI nodes can
1380 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1381 // handle them the right number of times.
1382 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1383 FuncInfo->MBB = Succs[i];
1384 FuncInfo->InsertPt = FuncInfo->MBB->end();
1385 // FuncInfo->MBB may have been removed from the CFG if a branch was
1387 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1388 for (MachineBasicBlock::iterator
1389 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
1390 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1391 MachineInstrBuilder PHI(*MF, MBBI);
1392 // This value for this PHI node is recorded in PHINodesToUpdate.
1393 for (unsigned pn = 0; ; ++pn) {
1394 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1395 "Didn't find PHI entry!");
1396 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1397 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1405 SDB->SwitchCases.clear();
1409 /// Create the scheduler. If a specific scheduler was specified
1410 /// via the SchedulerRegistry, use it, otherwise select the
1411 /// one preferred by the target.
1413 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1414 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1418 RegisterScheduler::setDefault(Ctor);
1421 return Ctor(this, OptLevel);
1424 //===----------------------------------------------------------------------===//
1425 // Helper functions used by the generated instruction selector.
1426 //===----------------------------------------------------------------------===//
1427 // Calls to these methods are generated by tblgen.
1429 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1430 /// the dag combiner simplified the 255, we still want to match. RHS is the
1431 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1432 /// specified in the .td file (e.g. 255).
1433 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1434 int64_t DesiredMaskS) const {
1435 const APInt &ActualMask = RHS->getAPIntValue();
1436 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1438 // If the actual mask exactly matches, success!
1439 if (ActualMask == DesiredMask)
1442 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1443 if (ActualMask.intersects(~DesiredMask))
1446 // Otherwise, the DAG Combiner may have proven that the value coming in is
1447 // either already zero or is not demanded. Check for known zero input bits.
1448 APInt NeededMask = DesiredMask & ~ActualMask;
1449 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1452 // TODO: check to see if missing bits are just not demanded.
1454 // Otherwise, this pattern doesn't match.
1458 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1459 /// the dag combiner simplified the 255, we still want to match. RHS is the
1460 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1461 /// specified in the .td file (e.g. 255).
1462 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1463 int64_t DesiredMaskS) const {
1464 const APInt &ActualMask = RHS->getAPIntValue();
1465 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1467 // If the actual mask exactly matches, success!
1468 if (ActualMask == DesiredMask)
1471 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1472 if (ActualMask.intersects(~DesiredMask))
1475 // Otherwise, the DAG Combiner may have proven that the value coming in is
1476 // either already zero or is not demanded. Check for known zero input bits.
1477 APInt NeededMask = DesiredMask & ~ActualMask;
1479 APInt KnownZero, KnownOne;
1480 CurDAG->ComputeMaskedBits(LHS, KnownZero, KnownOne);
1482 // If all the missing bits in the or are already known to be set, match!
1483 if ((NeededMask & KnownOne) == NeededMask)
1486 // TODO: check to see if missing bits are just not demanded.
1488 // Otherwise, this pattern doesn't match.
1493 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1494 /// by tblgen. Others should not call it.
1495 void SelectionDAGISel::
1496 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1497 std::vector<SDValue> InOps;
1498 std::swap(InOps, Ops);
1500 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1501 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1502 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1503 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1505 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1506 if (InOps[e-1].getValueType() == MVT::Glue)
1507 --e; // Don't process a glue operand if it is here.
1510 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1511 if (!InlineAsm::isMemKind(Flags)) {
1512 // Just skip over this operand, copying the operands verbatim.
1513 Ops.insert(Ops.end(), InOps.begin()+i,
1514 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1515 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1517 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1518 "Memory operand with multiple values?");
1519 // Otherwise, this is a memory operand. Ask the target to select it.
1520 std::vector<SDValue> SelOps;
1521 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1522 report_fatal_error("Could not match memory address. Inline asm"
1525 // Add this to the output node.
1527 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1528 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1529 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1534 // Add the glue input back if present.
1535 if (e != InOps.size())
1536 Ops.push_back(InOps.back());
1539 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1542 static SDNode *findGlueUse(SDNode *N) {
1543 unsigned FlagResNo = N->getNumValues()-1;
1544 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1545 SDUse &Use = I.getUse();
1546 if (Use.getResNo() == FlagResNo)
1547 return Use.getUser();
1552 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1553 /// This function recursively traverses up the operand chain, ignoring
1555 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1556 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1557 bool IgnoreChains) {
1558 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1559 // greater than all of its (recursive) operands. If we scan to a point where
1560 // 'use' is smaller than the node we're scanning for, then we know we will
1563 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1564 // happen because we scan down to newly selected nodes in the case of glue
1566 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1569 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1570 // won't fail if we scan it again.
1571 if (!Visited.insert(Use))
1574 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1575 // Ignore chain uses, they are validated by HandleMergeInputChains.
1576 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1579 SDNode *N = Use->getOperand(i).getNode();
1581 if (Use == ImmedUse || Use == Root)
1582 continue; // We are not looking for immediate use.
1587 // Traverse up the operand chain.
1588 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1594 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1595 /// operand node N of U during instruction selection that starts at Root.
1596 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1597 SDNode *Root) const {
1598 if (OptLevel == CodeGenOpt::None) return false;
1599 return N.hasOneUse();
1602 /// IsLegalToFold - Returns true if the specific operand node N of
1603 /// U can be folded during instruction selection that starts at Root.
1604 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1605 CodeGenOpt::Level OptLevel,
1606 bool IgnoreChains) {
1607 if (OptLevel == CodeGenOpt::None) return false;
1609 // If Root use can somehow reach N through a path that that doesn't contain
1610 // U then folding N would create a cycle. e.g. In the following
1611 // diagram, Root can reach N through X. If N is folded into into Root, then
1612 // X is both a predecessor and a successor of U.
1623 // * indicates nodes to be folded together.
1625 // If Root produces glue, then it gets (even more) interesting. Since it
1626 // will be "glued" together with its glue use in the scheduler, we need to
1627 // check if it might reach N.
1646 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1647 // (call it Fold), then X is a predecessor of GU and a successor of
1648 // Fold. But since Fold and GU are glued together, this will create
1649 // a cycle in the scheduling graph.
1651 // If the node has glue, walk down the graph to the "lowest" node in the
1653 EVT VT = Root->getValueType(Root->getNumValues()-1);
1654 while (VT == MVT::Glue) {
1655 SDNode *GU = findGlueUse(Root);
1659 VT = Root->getValueType(Root->getNumValues()-1);
1661 // If our query node has a glue result with a use, we've walked up it. If
1662 // the user (which has already been selected) has a chain or indirectly uses
1663 // the chain, our WalkChainUsers predicate will not consider it. Because of
1664 // this, we cannot ignore chains in this predicate.
1665 IgnoreChains = false;
1669 SmallPtrSet<SDNode*, 16> Visited;
1670 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1673 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1674 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1675 SelectInlineAsmMemoryOperands(Ops);
1677 EVT VTs[] = { MVT::Other, MVT::Glue };
1678 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1679 VTs, &Ops[0], Ops.size());
1681 return New.getNode();
1684 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1685 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1688 /// GetVBR - decode a vbr encoding whose top bit is set.
1689 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1690 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1691 assert(Val >= 128 && "Not a VBR");
1692 Val &= 127; // Remove first vbr bit.
1697 NextBits = MatcherTable[Idx++];
1698 Val |= (NextBits&127) << Shift;
1700 } while (NextBits & 128);
1706 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1707 /// interior glue and chain results to use the new glue and chain results.
1708 void SelectionDAGISel::
1709 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1710 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1712 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1713 bool isMorphNodeTo) {
1714 SmallVector<SDNode*, 4> NowDeadNodes;
1716 // Now that all the normal results are replaced, we replace the chain and
1717 // glue results if present.
1718 if (!ChainNodesMatched.empty()) {
1719 assert(InputChain.getNode() != 0 &&
1720 "Matched input chains but didn't produce a chain");
1721 // Loop over all of the nodes we matched that produced a chain result.
1722 // Replace all the chain results with the final chain we ended up with.
1723 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1724 SDNode *ChainNode = ChainNodesMatched[i];
1726 // If this node was already deleted, don't look at it.
1727 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1730 // Don't replace the results of the root node if we're doing a
1732 if (ChainNode == NodeToMatch && isMorphNodeTo)
1735 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1736 if (ChainVal.getValueType() == MVT::Glue)
1737 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1738 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1739 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
1741 // If the node became dead and we haven't already seen it, delete it.
1742 if (ChainNode->use_empty() &&
1743 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1744 NowDeadNodes.push_back(ChainNode);
1748 // If the result produces glue, update any glue results in the matched
1749 // pattern with the glue result.
1750 if (InputGlue.getNode() != 0) {
1751 // Handle any interior nodes explicitly marked.
1752 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
1753 SDNode *FRN = GlueResultNodesMatched[i];
1755 // If this node was already deleted, don't look at it.
1756 if (FRN->getOpcode() == ISD::DELETED_NODE)
1759 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
1760 "Doesn't have a glue result");
1761 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1764 // If the node became dead and we haven't already seen it, delete it.
1765 if (FRN->use_empty() &&
1766 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1767 NowDeadNodes.push_back(FRN);
1771 if (!NowDeadNodes.empty())
1772 CurDAG->RemoveDeadNodes(NowDeadNodes);
1774 DEBUG(errs() << "ISEL: Match complete!\n");
1780 CR_LeadsToInteriorNode
1783 /// WalkChainUsers - Walk down the users of the specified chained node that is
1784 /// part of the pattern we're matching, looking at all of the users we find.
1785 /// This determines whether something is an interior node, whether we have a
1786 /// non-pattern node in between two pattern nodes (which prevent folding because
1787 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1788 /// between pattern nodes (in which case the TF becomes part of the pattern).
1790 /// The walk we do here is guaranteed to be small because we quickly get down to
1791 /// already selected nodes "below" us.
1793 WalkChainUsers(const SDNode *ChainedNode,
1794 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1795 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1796 ChainResult Result = CR_Simple;
1798 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1799 E = ChainedNode->use_end(); UI != E; ++UI) {
1800 // Make sure the use is of the chain, not some other value we produce.
1801 if (UI.getUse().getValueType() != MVT::Other) continue;
1805 // If we see an already-selected machine node, then we've gone beyond the
1806 // pattern that we're selecting down into the already selected chunk of the
1808 if (User->isMachineOpcode() ||
1809 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1812 unsigned UserOpcode = User->getOpcode();
1813 if (UserOpcode == ISD::CopyToReg ||
1814 UserOpcode == ISD::CopyFromReg ||
1815 UserOpcode == ISD::INLINEASM ||
1816 UserOpcode == ISD::EH_LABEL ||
1817 UserOpcode == ISD::LIFETIME_START ||
1818 UserOpcode == ISD::LIFETIME_END) {
1819 // If their node ID got reset to -1 then they've already been selected.
1820 // Treat them like a MachineOpcode.
1821 if (User->getNodeId() == -1)
1825 // If we have a TokenFactor, we handle it specially.
1826 if (User->getOpcode() != ISD::TokenFactor) {
1827 // If the node isn't a token factor and isn't part of our pattern, then it
1828 // must be a random chained node in between two nodes we're selecting.
1829 // This happens when we have something like:
1834 // Because we structurally match the load/store as a read/modify/write,
1835 // but the call is chained between them. We cannot fold in this case
1836 // because it would induce a cycle in the graph.
1837 if (!std::count(ChainedNodesInPattern.begin(),
1838 ChainedNodesInPattern.end(), User))
1839 return CR_InducesCycle;
1841 // Otherwise we found a node that is part of our pattern. For example in:
1845 // This would happen when we're scanning down from the load and see the
1846 // store as a user. Record that there is a use of ChainedNode that is
1847 // part of the pattern and keep scanning uses.
1848 Result = CR_LeadsToInteriorNode;
1849 InteriorChainedNodes.push_back(User);
1853 // If we found a TokenFactor, there are two cases to consider: first if the
1854 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1855 // uses of the TF are in our pattern) we just want to ignore it. Second,
1856 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1862 // | \ DAG's like cheese
1865 // [TokenFactor] [Op]
1872 // In this case, the TokenFactor becomes part of our match and we rewrite it
1873 // as a new TokenFactor.
1875 // To distinguish these two cases, do a recursive walk down the uses.
1876 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1878 // If the uses of the TokenFactor are just already-selected nodes, ignore
1879 // it, it is "below" our pattern.
1881 case CR_InducesCycle:
1882 // If the uses of the TokenFactor lead to nodes that are not part of our
1883 // pattern that are not selected, folding would turn this into a cycle,
1885 return CR_InducesCycle;
1886 case CR_LeadsToInteriorNode:
1887 break; // Otherwise, keep processing.
1890 // Okay, we know we're in the interesting interior case. The TokenFactor
1891 // is now going to be considered part of the pattern so that we rewrite its
1892 // uses (it may have uses that are not part of the pattern) with the
1893 // ultimate chain result of the generated code. We will also add its chain
1894 // inputs as inputs to the ultimate TokenFactor we create.
1895 Result = CR_LeadsToInteriorNode;
1896 ChainedNodesInPattern.push_back(User);
1897 InteriorChainedNodes.push_back(User);
1904 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1905 /// operation for when the pattern matched at least one node with a chains. The
1906 /// input vector contains a list of all of the chained nodes that we match. We
1907 /// must determine if this is a valid thing to cover (i.e. matching it won't
1908 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1909 /// be used as the input node chain for the generated nodes.
1911 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1912 SelectionDAG *CurDAG) {
1913 // Walk all of the chained nodes we've matched, recursively scanning down the
1914 // users of the chain result. This adds any TokenFactor nodes that are caught
1915 // in between chained nodes to the chained and interior nodes list.
1916 SmallVector<SDNode*, 3> InteriorChainedNodes;
1917 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1918 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1919 InteriorChainedNodes) == CR_InducesCycle)
1920 return SDValue(); // Would induce a cycle.
1923 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1924 // that we are interested in. Form our input TokenFactor node.
1925 SmallVector<SDValue, 3> InputChains;
1926 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1927 // Add the input chain of this node to the InputChains list (which will be
1928 // the operands of the generated TokenFactor) if it's not an interior node.
1929 SDNode *N = ChainNodesMatched[i];
1930 if (N->getOpcode() != ISD::TokenFactor) {
1931 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1934 // Otherwise, add the input chain.
1935 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1936 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1937 InputChains.push_back(InChain);
1941 // If we have a token factor, we want to add all inputs of the token factor
1942 // that are not part of the pattern we're matching.
1943 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1944 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1945 N->getOperand(op).getNode()))
1946 InputChains.push_back(N->getOperand(op));
1951 if (InputChains.size() == 1)
1952 return InputChains[0];
1953 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1954 MVT::Other, &InputChains[0], InputChains.size());
1957 /// MorphNode - Handle morphing a node in place for the selector.
1958 SDNode *SelectionDAGISel::
1959 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1960 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1961 // It is possible we're using MorphNodeTo to replace a node with no
1962 // normal results with one that has a normal result (or we could be
1963 // adding a chain) and the input could have glue and chains as well.
1964 // In this case we need to shift the operands down.
1965 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1966 // than the old isel though.
1967 int OldGlueResultNo = -1, OldChainResultNo = -1;
1969 unsigned NTMNumResults = Node->getNumValues();
1970 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
1971 OldGlueResultNo = NTMNumResults-1;
1972 if (NTMNumResults != 1 &&
1973 Node->getValueType(NTMNumResults-2) == MVT::Other)
1974 OldChainResultNo = NTMNumResults-2;
1975 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1976 OldChainResultNo = NTMNumResults-1;
1978 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1979 // that this deletes operands of the old node that become dead.
1980 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1982 // MorphNodeTo can operate in two ways: if an existing node with the
1983 // specified operands exists, it can just return it. Otherwise, it
1984 // updates the node in place to have the requested operands.
1986 // If we updated the node in place, reset the node ID. To the isel,
1987 // this should be just like a newly allocated machine node.
1991 unsigned ResNumResults = Res->getNumValues();
1992 // Move the glue if needed.
1993 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
1994 (unsigned)OldGlueResultNo != ResNumResults-1)
1995 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
1996 SDValue(Res, ResNumResults-1));
1998 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
2001 // Move the chain reference if needed.
2002 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
2003 (unsigned)OldChainResultNo != ResNumResults-1)
2004 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
2005 SDValue(Res, ResNumResults-1));
2007 // Otherwise, no replacement happened because the node already exists. Replace
2008 // Uses of the old node with the new one.
2010 CurDAG->ReplaceAllUsesWith(Node, Res);
2015 /// CheckSame - Implements OP_CheckSame.
2016 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2017 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2019 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2020 // Accept if it is exactly the same as a previously recorded node.
2021 unsigned RecNo = MatcherTable[MatcherIndex++];
2022 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2023 return N == RecordedNodes[RecNo].first;
2026 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2027 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2028 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2029 const SelectionDAGISel &SDISel) {
2030 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2033 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2034 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2035 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2036 const SelectionDAGISel &SDISel, SDNode *N) {
2037 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2040 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2041 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2043 uint16_t Opc = MatcherTable[MatcherIndex++];
2044 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2045 return N->getOpcode() == Opc;
2048 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2049 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2050 SDValue N, const TargetLowering &TLI) {
2051 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2052 if (N.getValueType() == VT) return true;
2054 // Handle the case when VT is iPTR.
2055 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
2058 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2059 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2060 SDValue N, const TargetLowering &TLI,
2062 if (ChildNo >= N.getNumOperands())
2063 return false; // Match fails if out of range child #.
2064 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
2068 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2069 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2071 return cast<CondCodeSDNode>(N)->get() ==
2072 (ISD::CondCode)MatcherTable[MatcherIndex++];
2075 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2076 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2077 SDValue N, const TargetLowering &TLI) {
2078 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2079 if (cast<VTSDNode>(N)->getVT() == VT)
2082 // Handle the case when VT is iPTR.
2083 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
2086 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2087 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2089 int64_t Val = MatcherTable[MatcherIndex++];
2091 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2093 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2094 return C != 0 && C->getSExtValue() == Val;
2097 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2098 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2099 SDValue N, const SelectionDAGISel &SDISel) {
2100 int64_t Val = MatcherTable[MatcherIndex++];
2102 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2104 if (N->getOpcode() != ISD::AND) return false;
2106 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2107 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2110 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2111 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2112 SDValue N, const SelectionDAGISel &SDISel) {
2113 int64_t Val = MatcherTable[MatcherIndex++];
2115 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2117 if (N->getOpcode() != ISD::OR) return false;
2119 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2120 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2123 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2124 /// scope, evaluate the current node. If the current predicate is known to
2125 /// fail, set Result=true and return anything. If the current predicate is
2126 /// known to pass, set Result=false and return the MatcherIndex to continue
2127 /// with. If the current predicate is unknown, set Result=false and return the
2128 /// MatcherIndex to continue with.
2129 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2130 unsigned Index, SDValue N,
2132 const SelectionDAGISel &SDISel,
2133 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2134 switch (Table[Index++]) {
2137 return Index-1; // Could not evaluate this predicate.
2138 case SelectionDAGISel::OPC_CheckSame:
2139 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2141 case SelectionDAGISel::OPC_CheckPatternPredicate:
2142 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2144 case SelectionDAGISel::OPC_CheckPredicate:
2145 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2147 case SelectionDAGISel::OPC_CheckOpcode:
2148 Result = !::CheckOpcode(Table, Index, N.getNode());
2150 case SelectionDAGISel::OPC_CheckType:
2151 Result = !::CheckType(Table, Index, N, SDISel.TLI);
2153 case SelectionDAGISel::OPC_CheckChild0Type:
2154 case SelectionDAGISel::OPC_CheckChild1Type:
2155 case SelectionDAGISel::OPC_CheckChild2Type:
2156 case SelectionDAGISel::OPC_CheckChild3Type:
2157 case SelectionDAGISel::OPC_CheckChild4Type:
2158 case SelectionDAGISel::OPC_CheckChild5Type:
2159 case SelectionDAGISel::OPC_CheckChild6Type:
2160 case SelectionDAGISel::OPC_CheckChild7Type:
2161 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
2162 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
2164 case SelectionDAGISel::OPC_CheckCondCode:
2165 Result = !::CheckCondCode(Table, Index, N);
2167 case SelectionDAGISel::OPC_CheckValueType:
2168 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
2170 case SelectionDAGISel::OPC_CheckInteger:
2171 Result = !::CheckInteger(Table, Index, N);
2173 case SelectionDAGISel::OPC_CheckAndImm:
2174 Result = !::CheckAndImm(Table, Index, N, SDISel);
2176 case SelectionDAGISel::OPC_CheckOrImm:
2177 Result = !::CheckOrImm(Table, Index, N, SDISel);
2185 /// FailIndex - If this match fails, this is the index to continue with.
2188 /// NodeStack - The node stack when the scope was formed.
2189 SmallVector<SDValue, 4> NodeStack;
2191 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2192 unsigned NumRecordedNodes;
2194 /// NumMatchedMemRefs - The number of matched memref entries.
2195 unsigned NumMatchedMemRefs;
2197 /// InputChain/InputGlue - The current chain/glue
2198 SDValue InputChain, InputGlue;
2200 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2201 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2206 SDNode *SelectionDAGISel::
2207 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2208 unsigned TableSize) {
2209 // FIXME: Should these even be selected? Handle these cases in the caller?
2210 switch (NodeToMatch->getOpcode()) {
2213 case ISD::EntryToken: // These nodes remain the same.
2214 case ISD::BasicBlock:
2216 case ISD::RegisterMask:
2217 //case ISD::VALUETYPE:
2218 //case ISD::CONDCODE:
2219 case ISD::HANDLENODE:
2220 case ISD::MDNODE_SDNODE:
2221 case ISD::TargetConstant:
2222 case ISD::TargetConstantFP:
2223 case ISD::TargetConstantPool:
2224 case ISD::TargetFrameIndex:
2225 case ISD::TargetExternalSymbol:
2226 case ISD::TargetBlockAddress:
2227 case ISD::TargetJumpTable:
2228 case ISD::TargetGlobalTLSAddress:
2229 case ISD::TargetGlobalAddress:
2230 case ISD::TokenFactor:
2231 case ISD::CopyFromReg:
2232 case ISD::CopyToReg:
2234 case ISD::LIFETIME_START:
2235 case ISD::LIFETIME_END:
2236 NodeToMatch->setNodeId(-1); // Mark selected.
2238 case ISD::AssertSext:
2239 case ISD::AssertZext:
2240 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2241 NodeToMatch->getOperand(0));
2243 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2244 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2247 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2249 // Set up the node stack with NodeToMatch as the only node on the stack.
2250 SmallVector<SDValue, 8> NodeStack;
2251 SDValue N = SDValue(NodeToMatch, 0);
2252 NodeStack.push_back(N);
2254 // MatchScopes - Scopes used when matching, if a match failure happens, this
2255 // indicates where to continue checking.
2256 SmallVector<MatchScope, 8> MatchScopes;
2258 // RecordedNodes - This is the set of nodes that have been recorded by the
2259 // state machine. The second value is the parent of the node, or null if the
2260 // root is recorded.
2261 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2263 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2265 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2267 // These are the current input chain and glue for use when generating nodes.
2268 // Various Emit operations change these. For example, emitting a copytoreg
2269 // uses and updates these.
2270 SDValue InputChain, InputGlue;
2272 // ChainNodesMatched - If a pattern matches nodes that have input/output
2273 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2274 // which ones they are. The result is captured into this list so that we can
2275 // update the chain results when the pattern is complete.
2276 SmallVector<SDNode*, 3> ChainNodesMatched;
2277 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2279 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
2280 NodeToMatch->dump(CurDAG);
2283 // Determine where to start the interpreter. Normally we start at opcode #0,
2284 // but if the state machine starts with an OPC_SwitchOpcode, then we
2285 // accelerate the first lookup (which is guaranteed to be hot) with the
2286 // OpcodeOffset table.
2287 unsigned MatcherIndex = 0;
2289 if (!OpcodeOffset.empty()) {
2290 // Already computed the OpcodeOffset table, just index into it.
2291 if (N.getOpcode() < OpcodeOffset.size())
2292 MatcherIndex = OpcodeOffset[N.getOpcode()];
2293 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
2295 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2296 // Otherwise, the table isn't computed, but the state machine does start
2297 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2298 // is the first time we're selecting an instruction.
2301 // Get the size of this case.
2302 unsigned CaseSize = MatcherTable[Idx++];
2304 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2305 if (CaseSize == 0) break;
2307 // Get the opcode, add the index to the table.
2308 uint16_t Opc = MatcherTable[Idx++];
2309 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2310 if (Opc >= OpcodeOffset.size())
2311 OpcodeOffset.resize((Opc+1)*2);
2312 OpcodeOffset[Opc] = Idx;
2316 // Okay, do the lookup for the first opcode.
2317 if (N.getOpcode() < OpcodeOffset.size())
2318 MatcherIndex = OpcodeOffset[N.getOpcode()];
2322 assert(MatcherIndex < TableSize && "Invalid index");
2324 unsigned CurrentOpcodeIndex = MatcherIndex;
2326 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2329 // Okay, the semantics of this operation are that we should push a scope
2330 // then evaluate the first child. However, pushing a scope only to have
2331 // the first check fail (which then pops it) is inefficient. If we can
2332 // determine immediately that the first check (or first several) will
2333 // immediately fail, don't even bother pushing a scope for them.
2337 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2338 if (NumToSkip & 128)
2339 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2340 // Found the end of the scope with no match.
2341 if (NumToSkip == 0) {
2346 FailIndex = MatcherIndex+NumToSkip;
2348 unsigned MatcherIndexOfPredicate = MatcherIndex;
2349 (void)MatcherIndexOfPredicate; // silence warning.
2351 // If we can't evaluate this predicate without pushing a scope (e.g. if
2352 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2353 // push the scope and evaluate the full predicate chain.
2355 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2356 Result, *this, RecordedNodes);
2360 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2361 << "index " << MatcherIndexOfPredicate
2362 << ", continuing at " << FailIndex << "\n");
2363 ++NumDAGIselRetries;
2365 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2366 // move to the next case.
2367 MatcherIndex = FailIndex;
2370 // If the whole scope failed to match, bail.
2371 if (FailIndex == 0) break;
2373 // Push a MatchScope which indicates where to go if the first child fails
2375 MatchScope NewEntry;
2376 NewEntry.FailIndex = FailIndex;
2377 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2378 NewEntry.NumRecordedNodes = RecordedNodes.size();
2379 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2380 NewEntry.InputChain = InputChain;
2381 NewEntry.InputGlue = InputGlue;
2382 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2383 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2384 MatchScopes.push_back(NewEntry);
2387 case OPC_RecordNode: {
2388 // Remember this node, it may end up being an operand in the pattern.
2390 if (NodeStack.size() > 1)
2391 Parent = NodeStack[NodeStack.size()-2].getNode();
2392 RecordedNodes.push_back(std::make_pair(N, Parent));
2396 case OPC_RecordChild0: case OPC_RecordChild1:
2397 case OPC_RecordChild2: case OPC_RecordChild3:
2398 case OPC_RecordChild4: case OPC_RecordChild5:
2399 case OPC_RecordChild6: case OPC_RecordChild7: {
2400 unsigned ChildNo = Opcode-OPC_RecordChild0;
2401 if (ChildNo >= N.getNumOperands())
2402 break; // Match fails if out of range child #.
2404 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2408 case OPC_RecordMemRef:
2409 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2412 case OPC_CaptureGlueInput:
2413 // If the current node has an input glue, capture it in InputGlue.
2414 if (N->getNumOperands() != 0 &&
2415 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2416 InputGlue = N->getOperand(N->getNumOperands()-1);
2419 case OPC_MoveChild: {
2420 unsigned ChildNo = MatcherTable[MatcherIndex++];
2421 if (ChildNo >= N.getNumOperands())
2422 break; // Match fails if out of range child #.
2423 N = N.getOperand(ChildNo);
2424 NodeStack.push_back(N);
2428 case OPC_MoveParent:
2429 // Pop the current node off the NodeStack.
2430 NodeStack.pop_back();
2431 assert(!NodeStack.empty() && "Node stack imbalance!");
2432 N = NodeStack.back();
2436 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2438 case OPC_CheckPatternPredicate:
2439 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2441 case OPC_CheckPredicate:
2442 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2446 case OPC_CheckComplexPat: {
2447 unsigned CPNum = MatcherTable[MatcherIndex++];
2448 unsigned RecNo = MatcherTable[MatcherIndex++];
2449 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2450 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2451 RecordedNodes[RecNo].first, CPNum,
2456 case OPC_CheckOpcode:
2457 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2461 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2464 case OPC_SwitchOpcode: {
2465 unsigned CurNodeOpcode = N.getOpcode();
2466 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2469 // Get the size of this case.
2470 CaseSize = MatcherTable[MatcherIndex++];
2472 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2473 if (CaseSize == 0) break;
2475 uint16_t Opc = MatcherTable[MatcherIndex++];
2476 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2478 // If the opcode matches, then we will execute this case.
2479 if (CurNodeOpcode == Opc)
2482 // Otherwise, skip over this case.
2483 MatcherIndex += CaseSize;
2486 // If no cases matched, bail out.
2487 if (CaseSize == 0) break;
2489 // Otherwise, execute the case we found.
2490 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2491 << " to " << MatcherIndex << "\n");
2495 case OPC_SwitchType: {
2496 MVT CurNodeVT = N.getValueType().getSimpleVT();
2497 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2500 // Get the size of this case.
2501 CaseSize = MatcherTable[MatcherIndex++];
2503 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2504 if (CaseSize == 0) break;
2506 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2507 if (CaseVT == MVT::iPTR)
2508 CaseVT = TLI.getPointerTy();
2510 // If the VT matches, then we will execute this case.
2511 if (CurNodeVT == CaseVT)
2514 // Otherwise, skip over this case.
2515 MatcherIndex += CaseSize;
2518 // If no cases matched, bail out.
2519 if (CaseSize == 0) break;
2521 // Otherwise, execute the case we found.
2522 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2523 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2526 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2527 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2528 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2529 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2530 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2531 Opcode-OPC_CheckChild0Type))
2534 case OPC_CheckCondCode:
2535 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2537 case OPC_CheckValueType:
2538 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2540 case OPC_CheckInteger:
2541 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2543 case OPC_CheckAndImm:
2544 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2546 case OPC_CheckOrImm:
2547 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2550 case OPC_CheckFoldableChainNode: {
2551 assert(NodeStack.size() != 1 && "No parent node");
2552 // Verify that all intermediate nodes between the root and this one have
2554 bool HasMultipleUses = false;
2555 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2556 if (!NodeStack[i].hasOneUse()) {
2557 HasMultipleUses = true;
2560 if (HasMultipleUses) break;
2562 // Check to see that the target thinks this is profitable to fold and that
2563 // we can fold it without inducing cycles in the graph.
2564 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2566 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2567 NodeToMatch, OptLevel,
2568 true/*We validate our own chains*/))
2573 case OPC_EmitInteger: {
2574 MVT::SimpleValueType VT =
2575 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2576 int64_t Val = MatcherTable[MatcherIndex++];
2578 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2579 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2580 CurDAG->getTargetConstant(Val, VT), (SDNode*)0));
2583 case OPC_EmitRegister: {
2584 MVT::SimpleValueType VT =
2585 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2586 unsigned RegNo = MatcherTable[MatcherIndex++];
2587 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2588 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2591 case OPC_EmitRegister2: {
2592 // For targets w/ more than 256 register names, the register enum
2593 // values are stored in two bytes in the matcher table (just like
2595 MVT::SimpleValueType VT =
2596 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2597 unsigned RegNo = MatcherTable[MatcherIndex++];
2598 RegNo |= MatcherTable[MatcherIndex++] << 8;
2599 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2600 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2604 case OPC_EmitConvertToTarget: {
2605 // Convert from IMM/FPIMM to target version.
2606 unsigned RecNo = MatcherTable[MatcherIndex++];
2607 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2608 SDValue Imm = RecordedNodes[RecNo].first;
2610 if (Imm->getOpcode() == ISD::Constant) {
2611 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
2612 Imm = CurDAG->getConstant(*Val, Imm.getValueType(), true);
2613 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2614 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2615 Imm = CurDAG->getConstantFP(*Val, Imm.getValueType(), true);
2618 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2622 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2623 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2624 // These are space-optimized forms of OPC_EmitMergeInputChains.
2625 assert(InputChain.getNode() == 0 &&
2626 "EmitMergeInputChains should be the first chain producing node");
2627 assert(ChainNodesMatched.empty() &&
2628 "Should only have one EmitMergeInputChains per match");
2630 // Read all of the chained nodes.
2631 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2632 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2633 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2635 // FIXME: What if other value results of the node have uses not matched
2637 if (ChainNodesMatched.back() != NodeToMatch &&
2638 !RecordedNodes[RecNo].first.hasOneUse()) {
2639 ChainNodesMatched.clear();
2643 // Merge the input chains if they are not intra-pattern references.
2644 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2646 if (InputChain.getNode() == 0)
2647 break; // Failed to merge.
2651 case OPC_EmitMergeInputChains: {
2652 assert(InputChain.getNode() == 0 &&
2653 "EmitMergeInputChains should be the first chain producing node");
2654 // This node gets a list of nodes we matched in the input that have
2655 // chains. We want to token factor all of the input chains to these nodes
2656 // together. However, if any of the input chains is actually one of the
2657 // nodes matched in this pattern, then we have an intra-match reference.
2658 // Ignore these because the newly token factored chain should not refer to
2660 unsigned NumChains = MatcherTable[MatcherIndex++];
2661 assert(NumChains != 0 && "Can't TF zero chains");
2663 assert(ChainNodesMatched.empty() &&
2664 "Should only have one EmitMergeInputChains per match");
2666 // Read all of the chained nodes.
2667 for (unsigned i = 0; i != NumChains; ++i) {
2668 unsigned RecNo = MatcherTable[MatcherIndex++];
2669 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2670 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2672 // FIXME: What if other value results of the node have uses not matched
2674 if (ChainNodesMatched.back() != NodeToMatch &&
2675 !RecordedNodes[RecNo].first.hasOneUse()) {
2676 ChainNodesMatched.clear();
2681 // If the inner loop broke out, the match fails.
2682 if (ChainNodesMatched.empty())
2685 // Merge the input chains if they are not intra-pattern references.
2686 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2688 if (InputChain.getNode() == 0)
2689 break; // Failed to merge.
2694 case OPC_EmitCopyToReg: {
2695 unsigned RecNo = MatcherTable[MatcherIndex++];
2696 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2697 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2699 if (InputChain.getNode() == 0)
2700 InputChain = CurDAG->getEntryNode();
2702 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2703 DestPhysReg, RecordedNodes[RecNo].first,
2706 InputGlue = InputChain.getValue(1);
2710 case OPC_EmitNodeXForm: {
2711 unsigned XFormNo = MatcherTable[MatcherIndex++];
2712 unsigned RecNo = MatcherTable[MatcherIndex++];
2713 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2714 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2715 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0));
2720 case OPC_MorphNodeTo: {
2721 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2722 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2723 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2724 // Get the result VT list.
2725 unsigned NumVTs = MatcherTable[MatcherIndex++];
2726 SmallVector<EVT, 4> VTs;
2727 for (unsigned i = 0; i != NumVTs; ++i) {
2728 MVT::SimpleValueType VT =
2729 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2730 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2734 if (EmitNodeInfo & OPFL_Chain)
2735 VTs.push_back(MVT::Other);
2736 if (EmitNodeInfo & OPFL_GlueOutput)
2737 VTs.push_back(MVT::Glue);
2739 // This is hot code, so optimize the two most common cases of 1 and 2
2742 if (VTs.size() == 1)
2743 VTList = CurDAG->getVTList(VTs[0]);
2744 else if (VTs.size() == 2)
2745 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2747 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2749 // Get the operand list.
2750 unsigned NumOps = MatcherTable[MatcherIndex++];
2751 SmallVector<SDValue, 8> Ops;
2752 for (unsigned i = 0; i != NumOps; ++i) {
2753 unsigned RecNo = MatcherTable[MatcherIndex++];
2755 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2757 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2758 Ops.push_back(RecordedNodes[RecNo].first);
2761 // If there are variadic operands to add, handle them now.
2762 if (EmitNodeInfo & OPFL_VariadicInfo) {
2763 // Determine the start index to copy from.
2764 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2765 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2766 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2767 "Invalid variadic node");
2768 // Copy all of the variadic operands, not including a potential glue
2770 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2772 SDValue V = NodeToMatch->getOperand(i);
2773 if (V.getValueType() == MVT::Glue) break;
2778 // If this has chain/glue inputs, add them.
2779 if (EmitNodeInfo & OPFL_Chain)
2780 Ops.push_back(InputChain);
2781 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0)
2782 Ops.push_back(InputGlue);
2786 if (Opcode != OPC_MorphNodeTo) {
2787 // If this is a normal EmitNode command, just create the new node and
2788 // add the results to the RecordedNodes list.
2789 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2790 VTList, Ops.data(), Ops.size());
2792 // Add all the non-glue/non-chain results to the RecordedNodes list.
2793 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2794 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
2795 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
2799 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) {
2800 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2803 // NodeToMatch was eliminated by CSE when the target changed the DAG.
2804 // We will visit the equivalent node later.
2805 DEBUG(dbgs() << "Node was eliminated by CSE\n");
2809 // If the node had chain/glue results, update our notion of the current
2811 if (EmitNodeInfo & OPFL_GlueOutput) {
2812 InputGlue = SDValue(Res, VTs.size()-1);
2813 if (EmitNodeInfo & OPFL_Chain)
2814 InputChain = SDValue(Res, VTs.size()-2);
2815 } else if (EmitNodeInfo & OPFL_Chain)
2816 InputChain = SDValue(Res, VTs.size()-1);
2818 // If the OPFL_MemRefs glue is set on this node, slap all of the
2819 // accumulated memrefs onto it.
2821 // FIXME: This is vastly incorrect for patterns with multiple outputs
2822 // instructions that access memory and for ComplexPatterns that match
2824 if (EmitNodeInfo & OPFL_MemRefs) {
2825 // Only attach load or store memory operands if the generated
2826 // instruction may load or store.
2827 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc);
2828 bool mayLoad = MCID.mayLoad();
2829 bool mayStore = MCID.mayStore();
2831 unsigned NumMemRefs = 0;
2832 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2833 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2834 if ((*I)->isLoad()) {
2837 } else if ((*I)->isStore()) {
2845 MachineSDNode::mmo_iterator MemRefs =
2846 MF->allocateMemRefsArray(NumMemRefs);
2848 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
2849 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2850 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2851 if ((*I)->isLoad()) {
2854 } else if ((*I)->isStore()) {
2862 cast<MachineSDNode>(Res)
2863 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
2867 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2868 << " node: "; Res->dump(CurDAG); errs() << "\n");
2870 // If this was a MorphNodeTo then we're completely done!
2871 if (Opcode == OPC_MorphNodeTo) {
2872 // Update chain and glue uses.
2873 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2874 InputGlue, GlueResultNodesMatched, true);
2881 case OPC_MarkGlueResults: {
2882 unsigned NumNodes = MatcherTable[MatcherIndex++];
2884 // Read and remember all the glue-result nodes.
2885 for (unsigned i = 0; i != NumNodes; ++i) {
2886 unsigned RecNo = MatcherTable[MatcherIndex++];
2888 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2890 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2891 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2896 case OPC_CompleteMatch: {
2897 // The match has been completed, and any new nodes (if any) have been
2898 // created. Patch up references to the matched dag to use the newly
2900 unsigned NumResults = MatcherTable[MatcherIndex++];
2902 for (unsigned i = 0; i != NumResults; ++i) {
2903 unsigned ResSlot = MatcherTable[MatcherIndex++];
2905 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2907 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2908 SDValue Res = RecordedNodes[ResSlot].first;
2910 assert(i < NodeToMatch->getNumValues() &&
2911 NodeToMatch->getValueType(i) != MVT::Other &&
2912 NodeToMatch->getValueType(i) != MVT::Glue &&
2913 "Invalid number of results to complete!");
2914 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2915 NodeToMatch->getValueType(i) == MVT::iPTR ||
2916 Res.getValueType() == MVT::iPTR ||
2917 NodeToMatch->getValueType(i).getSizeInBits() ==
2918 Res.getValueType().getSizeInBits()) &&
2919 "invalid replacement");
2920 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2923 // If the root node defines glue, add it to the glue nodes to update list.
2924 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
2925 GlueResultNodesMatched.push_back(NodeToMatch);
2927 // Update chain and glue uses.
2928 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2929 InputGlue, GlueResultNodesMatched, false);
2931 assert(NodeToMatch->use_empty() &&
2932 "Didn't replace all uses of the node?");
2934 // FIXME: We just return here, which interacts correctly with SelectRoot
2935 // above. We should fix this to not return an SDNode* anymore.
2940 // If the code reached this point, then the match failed. See if there is
2941 // another child to try in the current 'Scope', otherwise pop it until we
2942 // find a case to check.
2943 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2944 ++NumDAGIselRetries;
2946 if (MatchScopes.empty()) {
2947 CannotYetSelect(NodeToMatch);
2951 // Restore the interpreter state back to the point where the scope was
2953 MatchScope &LastScope = MatchScopes.back();
2954 RecordedNodes.resize(LastScope.NumRecordedNodes);
2956 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2957 N = NodeStack.back();
2959 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2960 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2961 MatcherIndex = LastScope.FailIndex;
2963 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2965 InputChain = LastScope.InputChain;
2966 InputGlue = LastScope.InputGlue;
2967 if (!LastScope.HasChainNodesMatched)
2968 ChainNodesMatched.clear();
2969 if (!LastScope.HasGlueResultNodesMatched)
2970 GlueResultNodesMatched.clear();
2972 // Check to see what the offset is at the new MatcherIndex. If it is zero
2973 // we have reached the end of this scope, otherwise we have another child
2974 // in the current scope to try.
2975 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2976 if (NumToSkip & 128)
2977 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2979 // If we have another child in this scope to match, update FailIndex and
2981 if (NumToSkip != 0) {
2982 LastScope.FailIndex = MatcherIndex+NumToSkip;
2986 // End of this scope, pop it and try the next child in the containing
2988 MatchScopes.pop_back();
2995 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2997 raw_string_ostream Msg(msg);
2998 Msg << "Cannot select: ";
3000 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
3001 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
3002 N->getOpcode() != ISD::INTRINSIC_VOID) {
3003 N->printrFull(Msg, CurDAG);
3004 Msg << "\nIn function: " << MF->getName();
3006 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
3008 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
3009 if (iid < Intrinsic::num_intrinsics)
3010 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
3011 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
3012 Msg << "target intrinsic %" << TII->getName(iid);
3014 Msg << "unknown intrinsic #" << iid;
3016 report_fatal_error(Msg.str());
3019 char SelectionDAGISel::ID = 0;