1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/TargetLowering.h"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/CallingConvLower.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineJumpTableInfo.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/TargetRegisterInfo.h"
24 #include "llvm/CodeGen/TargetSubtargetInfo.h"
25 #include "llvm/IR/DataLayout.h"
26 #include "llvm/IR/DerivedTypes.h"
27 #include "llvm/IR/GlobalVariable.h"
28 #include "llvm/IR/LLVMContext.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/MC/MCExpr.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/KnownBits.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/Target/TargetLoweringObjectFile.h"
35 #include "llvm/Target/TargetMachine.h"
39 /// NOTE: The TargetMachine owns TLOF.
40 TargetLowering::TargetLowering(const TargetMachine &tm)
41 : TargetLoweringBase(tm) {}
43 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
47 bool TargetLowering::isPositionIndependent() const {
48 return getTargetMachine().isPositionIndependent();
51 /// Check whether a given call node is in tail position within its function. If
52 /// so, it sets Chain to the input chain of the tail call.
53 bool TargetLowering::isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
54 SDValue &Chain) const {
55 const Function &F = DAG.getMachineFunction().getFunction();
57 // Conservatively require the attributes of the call to match those of
58 // the return. Ignore NoAlias and NonNull because they don't affect the
60 AttributeList CallerAttrs = F.getAttributes();
61 if (AttrBuilder(CallerAttrs, AttributeList::ReturnIndex)
62 .removeAttribute(Attribute::NoAlias)
63 .removeAttribute(Attribute::NonNull)
67 // It's not safe to eliminate the sign / zero extension of the return value.
68 if (CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt) ||
69 CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
72 // Check if the only use is a function return node.
73 return isUsedByReturnOnly(Node, Chain);
76 bool TargetLowering::parametersInCSRMatch(const MachineRegisterInfo &MRI,
77 const uint32_t *CallerPreservedMask,
78 const SmallVectorImpl<CCValAssign> &ArgLocs,
79 const SmallVectorImpl<SDValue> &OutVals) const {
80 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
81 const CCValAssign &ArgLoc = ArgLocs[I];
82 if (!ArgLoc.isRegLoc())
84 unsigned Reg = ArgLoc.getLocReg();
85 // Only look at callee saved registers.
86 if (MachineOperand::clobbersPhysReg(CallerPreservedMask, Reg))
88 // Check that we pass the value used for the caller.
89 // (We look for a CopyFromReg reading a virtual register that is used
90 // for the function live-in value of register Reg)
91 SDValue Value = OutVals[I];
92 if (Value->getOpcode() != ISD::CopyFromReg)
94 unsigned ArgReg = cast<RegisterSDNode>(Value->getOperand(1))->getReg();
95 if (MRI.getLiveInPhysReg(ArgReg) != Reg)
101 /// Set CallLoweringInfo attribute flags based on a call instruction
102 /// and called function attributes.
103 void TargetLoweringBase::ArgListEntry::setAttributes(ImmutableCallSite *CS,
105 IsSExt = CS->paramHasAttr(ArgIdx, Attribute::SExt);
106 IsZExt = CS->paramHasAttr(ArgIdx, Attribute::ZExt);
107 IsInReg = CS->paramHasAttr(ArgIdx, Attribute::InReg);
108 IsSRet = CS->paramHasAttr(ArgIdx, Attribute::StructRet);
109 IsNest = CS->paramHasAttr(ArgIdx, Attribute::Nest);
110 IsByVal = CS->paramHasAttr(ArgIdx, Attribute::ByVal);
111 IsInAlloca = CS->paramHasAttr(ArgIdx, Attribute::InAlloca);
112 IsReturned = CS->paramHasAttr(ArgIdx, Attribute::Returned);
113 IsSwiftSelf = CS->paramHasAttr(ArgIdx, Attribute::SwiftSelf);
114 IsSwiftError = CS->paramHasAttr(ArgIdx, Attribute::SwiftError);
115 Alignment = CS->getParamAlignment(ArgIdx);
118 /// Generate a libcall taking the given operands as arguments and returning a
119 /// result of type RetVT.
120 std::pair<SDValue, SDValue>
121 TargetLowering::makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT,
122 ArrayRef<SDValue> Ops, bool isSigned,
123 const SDLoc &dl, bool doesNotReturn,
124 bool isReturnValueUsed) const {
125 TargetLowering::ArgListTy Args;
126 Args.reserve(Ops.size());
128 TargetLowering::ArgListEntry Entry;
129 for (SDValue Op : Ops) {
131 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
132 Entry.IsSExt = shouldSignExtendTypeInLibCall(Op.getValueType(), isSigned);
133 Entry.IsZExt = !shouldSignExtendTypeInLibCall(Op.getValueType(), isSigned);
134 Args.push_back(Entry);
137 if (LC == RTLIB::UNKNOWN_LIBCALL)
138 report_fatal_error("Unsupported library call operation!");
139 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
140 getPointerTy(DAG.getDataLayout()));
142 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
143 TargetLowering::CallLoweringInfo CLI(DAG);
144 bool signExtend = shouldSignExtendTypeInLibCall(RetVT, isSigned);
146 .setChain(DAG.getEntryNode())
147 .setLibCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args))
148 .setNoReturn(doesNotReturn)
149 .setDiscardResult(!isReturnValueUsed)
150 .setSExtResult(signExtend)
151 .setZExtResult(!signExtend);
152 return LowerCallTo(CLI);
155 /// Soften the operands of a comparison. This code is shared among BR_CC,
156 /// SELECT_CC, and SETCC handlers.
157 void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT,
158 SDValue &NewLHS, SDValue &NewRHS,
159 ISD::CondCode &CCCode,
160 const SDLoc &dl) const {
161 assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128 || VT == MVT::ppcf128)
162 && "Unsupported setcc type!");
164 // Expand into one or more soft-fp libcall(s).
165 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
166 bool ShouldInvertCC = false;
170 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
171 (VT == MVT::f64) ? RTLIB::OEQ_F64 :
172 (VT == MVT::f128) ? RTLIB::OEQ_F128 : RTLIB::OEQ_PPCF128;
176 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 :
177 (VT == MVT::f64) ? RTLIB::UNE_F64 :
178 (VT == MVT::f128) ? RTLIB::UNE_F128 : RTLIB::UNE_PPCF128;
182 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
183 (VT == MVT::f64) ? RTLIB::OGE_F64 :
184 (VT == MVT::f128) ? RTLIB::OGE_F128 : RTLIB::OGE_PPCF128;
188 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
189 (VT == MVT::f64) ? RTLIB::OLT_F64 :
190 (VT == MVT::f128) ? RTLIB::OLT_F128 : RTLIB::OLT_PPCF128;
194 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
195 (VT == MVT::f64) ? RTLIB::OLE_F64 :
196 (VT == MVT::f128) ? RTLIB::OLE_F128 : RTLIB::OLE_PPCF128;
200 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
201 (VT == MVT::f64) ? RTLIB::OGT_F64 :
202 (VT == MVT::f128) ? RTLIB::OGT_F128 : RTLIB::OGT_PPCF128;
205 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
206 (VT == MVT::f64) ? RTLIB::UO_F64 :
207 (VT == MVT::f128) ? RTLIB::UO_F128 : RTLIB::UO_PPCF128;
210 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 :
211 (VT == MVT::f64) ? RTLIB::O_F64 :
212 (VT == MVT::f128) ? RTLIB::O_F128 : RTLIB::O_PPCF128;
215 // SETONE = SETOLT | SETOGT
216 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
217 (VT == MVT::f64) ? RTLIB::OLT_F64 :
218 (VT == MVT::f128) ? RTLIB::OLT_F128 : RTLIB::OLT_PPCF128;
219 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
220 (VT == MVT::f64) ? RTLIB::OGT_F64 :
221 (VT == MVT::f128) ? RTLIB::OGT_F128 : RTLIB::OGT_PPCF128;
224 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
225 (VT == MVT::f64) ? RTLIB::UO_F64 :
226 (VT == MVT::f128) ? RTLIB::UO_F128 : RTLIB::UO_PPCF128;
227 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
228 (VT == MVT::f64) ? RTLIB::OEQ_F64 :
229 (VT == MVT::f128) ? RTLIB::OEQ_F128 : RTLIB::OEQ_PPCF128;
232 // Invert CC for unordered comparisons
233 ShouldInvertCC = true;
236 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
237 (VT == MVT::f64) ? RTLIB::OGE_F64 :
238 (VT == MVT::f128) ? RTLIB::OGE_F128 : RTLIB::OGE_PPCF128;
241 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
242 (VT == MVT::f64) ? RTLIB::OGT_F64 :
243 (VT == MVT::f128) ? RTLIB::OGT_F128 : RTLIB::OGT_PPCF128;
246 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
247 (VT == MVT::f64) ? RTLIB::OLE_F64 :
248 (VT == MVT::f128) ? RTLIB::OLE_F128 : RTLIB::OLE_PPCF128;
251 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
252 (VT == MVT::f64) ? RTLIB::OLT_F64 :
253 (VT == MVT::f128) ? RTLIB::OLT_F128 : RTLIB::OLT_PPCF128;
255 default: llvm_unreachable("Do not know how to soften this setcc!");
259 // Use the target specific return value for comparions lib calls.
260 EVT RetVT = getCmpLibcallReturnType();
261 SDValue Ops[2] = {NewLHS, NewRHS};
262 NewLHS = makeLibCall(DAG, LC1, RetVT, Ops, false /*sign irrelevant*/,
264 NewRHS = DAG.getConstant(0, dl, RetVT);
266 CCCode = getCmpLibcallCC(LC1);
268 CCCode = getSetCCInverse(CCCode, /*isInteger=*/true);
270 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
271 SDValue Tmp = DAG.getNode(
273 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), RetVT),
274 NewLHS, NewRHS, DAG.getCondCode(CCCode));
275 NewLHS = makeLibCall(DAG, LC2, RetVT, Ops, false/*sign irrelevant*/,
277 NewLHS = DAG.getNode(
279 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), RetVT),
280 NewLHS, NewRHS, DAG.getCondCode(getCmpLibcallCC(LC2)));
281 NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS);
286 /// Return the entry encoding for a jump table in the current function. The
287 /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
288 unsigned TargetLowering::getJumpTableEncoding() const {
289 // In non-pic modes, just use the address of a block.
290 if (!isPositionIndependent())
291 return MachineJumpTableInfo::EK_BlockAddress;
293 // In PIC mode, if the target supports a GPRel32 directive, use it.
294 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != nullptr)
295 return MachineJumpTableInfo::EK_GPRel32BlockAddress;
297 // Otherwise, use a label difference.
298 return MachineJumpTableInfo::EK_LabelDifference32;
301 SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
302 SelectionDAG &DAG) const {
303 // If our PIC model is GP relative, use the global offset table as the base.
304 unsigned JTEncoding = getJumpTableEncoding();
306 if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) ||
307 (JTEncoding == MachineJumpTableInfo::EK_GPRel32BlockAddress))
308 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy(DAG.getDataLayout()));
313 /// This returns the relocation base for the given PIC jumptable, the same as
314 /// getPICJumpTableRelocBase, but as an MCExpr.
316 TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
317 unsigned JTI,MCContext &Ctx) const{
318 // The normal PIC reloc base is the label at the start of the jump table.
319 return MCSymbolRefExpr::create(MF->getJTISymbol(JTI, Ctx), Ctx);
323 TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
324 const TargetMachine &TM = getTargetMachine();
325 const GlobalValue *GV = GA->getGlobal();
327 // If the address is not even local to this DSO we will have to load it from
328 // a got and then add the offset.
329 if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
332 // If the code is position independent we will have to add a base register.
333 if (isPositionIndependent())
336 // Otherwise we can do it.
340 //===----------------------------------------------------------------------===//
341 // Optimization Methods
342 //===----------------------------------------------------------------------===//
344 /// If the specified instruction has a constant integer operand and there are
345 /// bits set in that constant that are not demanded, then clear those bits and
347 bool TargetLowering::ShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
348 TargetLoweringOpt &TLO) const {
349 SelectionDAG &DAG = TLO.DAG;
351 unsigned Opcode = Op.getOpcode();
353 // Do target-specific constant optimization.
354 if (targetShrinkDemandedConstant(Op, Demanded, TLO))
355 return TLO.New.getNode();
357 // FIXME: ISD::SELECT, ISD::SELECT_CC
364 auto *Op1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
368 // If this is a 'not' op, don't touch it because that's a canonical form.
369 const APInt &C = Op1C->getAPIntValue();
370 if (Opcode == ISD::XOR && Demanded.isSubsetOf(C))
373 if (!C.isSubsetOf(Demanded)) {
374 EVT VT = Op.getValueType();
375 SDValue NewC = DAG.getConstant(Demanded & C, DL, VT);
376 SDValue NewOp = DAG.getNode(Opcode, DL, VT, Op.getOperand(0), NewC);
377 return TLO.CombineTo(Op, NewOp);
387 /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.
388 /// This uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
389 /// generalized for targets with other types of implicit widening casts.
390 bool TargetLowering::ShrinkDemandedOp(SDValue Op, unsigned BitWidth,
391 const APInt &Demanded,
392 TargetLoweringOpt &TLO) const {
393 assert(Op.getNumOperands() == 2 &&
394 "ShrinkDemandedOp only supports binary operators!");
395 assert(Op.getNode()->getNumValues() == 1 &&
396 "ShrinkDemandedOp only supports nodes with one result!");
398 SelectionDAG &DAG = TLO.DAG;
401 // Early return, as this function cannot handle vector types.
402 if (Op.getValueType().isVector())
405 // Don't do this if the node has another user, which may require the
407 if (!Op.getNode()->hasOneUse())
410 // Search for the smallest integer type with free casts to and from
411 // Op's type. For expedience, just check power-of-2 integer types.
412 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
413 unsigned DemandedSize = Demanded.getActiveBits();
414 unsigned SmallVTBits = DemandedSize;
415 if (!isPowerOf2_32(SmallVTBits))
416 SmallVTBits = NextPowerOf2(SmallVTBits);
417 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
418 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
419 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
420 TLI.isZExtFree(SmallVT, Op.getValueType())) {
421 // We found a type with free casts.
422 SDValue X = DAG.getNode(
423 Op.getOpcode(), dl, SmallVT,
424 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, Op.getOperand(0)),
425 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, Op.getOperand(1)));
426 assert(DemandedSize <= SmallVTBits && "Narrowed below demanded bits?");
427 SDValue Z = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), X);
428 return TLO.CombineTo(Op, Z);
434 bool TargetLowering::SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
435 DAGCombinerInfo &DCI) const {
436 SelectionDAG &DAG = DCI.DAG;
437 TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
438 !DCI.isBeforeLegalizeOps());
441 bool Simplified = SimplifyDemandedBits(Op, DemandedBits, Known, TLO);
443 DCI.AddToWorklist(Op.getNode());
444 DCI.CommitTargetLoweringOpt(TLO);
449 bool TargetLowering::SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
451 TargetLoweringOpt &TLO,
453 bool AssumeSingleUse) const {
454 EVT VT = Op.getValueType();
455 APInt DemandedElts = VT.isVector()
456 ? APInt::getAllOnesValue(VT.getVectorNumElements())
458 return SimplifyDemandedBits(Op, DemandedBits, DemandedElts, Known, TLO, Depth,
462 /// Look at Op. At this point, we know that only the OriginalDemandedBits of the
463 /// result of Op are ever used downstream. If we can use this information to
464 /// simplify Op, create a new simplified DAG node and return true, returning the
465 /// original and new nodes in Old and New. Otherwise, analyze the expression and
466 /// return a mask of Known bits for the expression (used to simplify the
467 /// caller). The Known bits may only be accurate for those bits in the
468 /// OriginalDemandedBits and OriginalDemandedElts.
469 bool TargetLowering::SimplifyDemandedBits(
470 SDValue Op, const APInt &OriginalDemandedBits,
471 const APInt &OriginalDemandedElts, KnownBits &Known, TargetLoweringOpt &TLO,
472 unsigned Depth, bool AssumeSingleUse) const {
473 unsigned BitWidth = OriginalDemandedBits.getBitWidth();
474 assert(Op.getScalarValueSizeInBits() == BitWidth &&
475 "Mask size mismatches value type size!");
477 unsigned NumElts = OriginalDemandedElts.getBitWidth();
478 assert((!Op.getValueType().isVector() ||
479 NumElts == Op.getValueType().getVectorNumElements()) &&
480 "Unexpected vector size");
482 APInt DemandedBits = OriginalDemandedBits;
483 APInt DemandedElts = OriginalDemandedElts;
485 auto &DL = TLO.DAG.getDataLayout();
487 // Don't know anything.
488 Known = KnownBits(BitWidth);
490 if (Op.getOpcode() == ISD::Constant) {
491 // We know all of the bits for a constant!
492 Known.One = cast<ConstantSDNode>(Op)->getAPIntValue();
493 Known.Zero = ~Known.One;
497 // Other users may use these bits.
498 EVT VT = Op.getValueType();
499 if (!Op.getNode()->hasOneUse() && !AssumeSingleUse) {
501 // If not at the root, Just compute the Known bits to
502 // simplify things downstream.
503 Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth);
506 // If this is the root being simplified, allow it to have multiple uses,
507 // just set the DemandedBits/Elts to all bits.
508 DemandedBits = APInt::getAllOnesValue(BitWidth);
509 DemandedElts = APInt::getAllOnesValue(NumElts);
510 } else if (OriginalDemandedBits == 0 || OriginalDemandedElts == 0) {
511 // Not demanding any bits/elts from Op.
513 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT));
515 } else if (Depth == 6) { // Limit search depth.
519 KnownBits Known2, KnownOut;
520 switch (Op.getOpcode()) {
521 case ISD::BUILD_VECTOR:
522 // Collect the known bits that are shared by every constant vector element.
523 Known.Zero.setAllBits(); Known.One.setAllBits();
524 for (SDValue SrcOp : Op->ops()) {
525 if (!isa<ConstantSDNode>(SrcOp)) {
526 // We can only handle all constant values - bail out with no known bits.
527 Known = KnownBits(BitWidth);
530 Known2.One = cast<ConstantSDNode>(SrcOp)->getAPIntValue();
531 Known2.Zero = ~Known2.One;
533 // BUILD_VECTOR can implicitly truncate sources, we must handle this.
534 if (Known2.One.getBitWidth() != BitWidth) {
535 assert(Known2.getBitWidth() > BitWidth &&
536 "Expected BUILD_VECTOR implicit truncation");
537 Known2 = Known2.trunc(BitWidth);
540 // Known bits are the values that are shared by every element.
541 // TODO: support per-element known bits.
542 Known.One &= Known2.One;
543 Known.Zero &= Known2.Zero;
545 return false; // Don't fall through, will infinitely loop.
546 case ISD::CONCAT_VECTORS: {
547 Known.Zero.setAllBits();
548 Known.One.setAllBits();
549 EVT SubVT = Op.getOperand(0).getValueType();
550 unsigned NumSubVecs = Op.getNumOperands();
551 unsigned NumSubElts = SubVT.getVectorNumElements();
552 for (unsigned i = 0; i != NumSubVecs; ++i) {
553 APInt DemandedSubElts =
554 DemandedElts.extractBits(NumSubElts, i * NumSubElts);
555 if (SimplifyDemandedBits(Op.getOperand(i), DemandedBits, DemandedSubElts,
556 Known2, TLO, Depth + 1))
558 // Known bits are shared by every demanded subvector element.
559 if (!!DemandedSubElts) {
560 Known.One &= Known2.One;
561 Known.Zero &= Known2.Zero;
566 case ISD::VECTOR_SHUFFLE: {
567 ArrayRef<int> ShuffleMask = cast<ShuffleVectorSDNode>(Op)->getMask();
569 // Collect demanded elements from shuffle operands..
570 APInt DemandedLHS(NumElts, 0);
571 APInt DemandedRHS(NumElts, 0);
572 for (unsigned i = 0; i != NumElts; ++i) {
573 if (!DemandedElts[i])
575 int M = ShuffleMask[i];
577 // For UNDEF elements, we don't know anything about the common state of
578 // the shuffle result.
579 DemandedLHS.clearAllBits();
580 DemandedRHS.clearAllBits();
583 assert(0 <= M && M < (int)(2 * NumElts) && "Shuffle index out of range");
584 if (M < (int)NumElts)
585 DemandedLHS.setBit(M);
587 DemandedRHS.setBit(M - NumElts);
590 if (!!DemandedLHS || !!DemandedRHS) {
591 Known.Zero.setAllBits();
592 Known.One.setAllBits();
594 if (SimplifyDemandedBits(Op.getOperand(0), DemandedBits, DemandedLHS,
595 Known2, TLO, Depth + 1))
597 Known.One &= Known2.One;
598 Known.Zero &= Known2.Zero;
601 if (SimplifyDemandedBits(Op.getOperand(1), DemandedBits, DemandedRHS,
602 Known2, TLO, Depth + 1))
604 Known.One &= Known2.One;
605 Known.Zero &= Known2.Zero;
611 SDValue Op0 = Op.getOperand(0);
612 SDValue Op1 = Op.getOperand(1);
614 // If the RHS is a constant, check to see if the LHS would be zero without
615 // using the bits from the RHS. Below, we use knowledge about the RHS to
616 // simplify the LHS, here we're using information from the LHS to simplify
618 if (ConstantSDNode *RHSC = isConstOrConstSplat(Op1)) {
619 // Do not increment Depth here; that can cause an infinite loop.
620 KnownBits LHSKnown = TLO.DAG.computeKnownBits(Op0, DemandedElts, Depth);
621 // If the LHS already has zeros where RHSC does, this 'and' is dead.
622 if ((LHSKnown.Zero & DemandedBits) ==
623 (~RHSC->getAPIntValue() & DemandedBits))
624 return TLO.CombineTo(Op, Op0);
626 // If any of the set bits in the RHS are known zero on the LHS, shrink
628 if (ShrinkDemandedConstant(Op, ~LHSKnown.Zero & DemandedBits, TLO))
631 // Bitwise-not (xor X, -1) is a special case: we don't usually shrink its
632 // constant, but if this 'and' is only clearing bits that were just set by
633 // the xor, then this 'and' can be eliminated by shrinking the mask of
634 // the xor. For example, for a 32-bit X:
635 // and (xor (srl X, 31), -1), 1 --> xor (srl X, 31), 1
636 if (isBitwiseNot(Op0) && Op0.hasOneUse() &&
637 LHSKnown.One == ~RHSC->getAPIntValue()) {
638 SDValue Xor = TLO.DAG.getNode(ISD::XOR, dl, VT, Op0.getOperand(0), Op1);
639 return TLO.CombineTo(Op, Xor);
643 if (SimplifyDemandedBits(Op1, DemandedBits, DemandedElts, Known, TLO, Depth + 1))
645 assert(!Known.hasConflict() && "Bits known to be one AND zero?");
646 if (SimplifyDemandedBits(Op0, ~Known.Zero & DemandedBits, DemandedElts, Known2, TLO,
649 assert(!Known2.hasConflict() && "Bits known to be one AND zero?");
651 // If all of the demanded bits are known one on one side, return the other.
652 // These bits cannot contribute to the result of the 'and'.
653 if (DemandedBits.isSubsetOf(Known2.Zero | Known.One))
654 return TLO.CombineTo(Op, Op0);
655 if (DemandedBits.isSubsetOf(Known.Zero | Known2.One))
656 return TLO.CombineTo(Op, Op1);
657 // If all of the demanded bits in the inputs are known zeros, return zero.
658 if (DemandedBits.isSubsetOf(Known.Zero | Known2.Zero))
659 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, dl, VT));
660 // If the RHS is a constant, see if we can simplify it.
661 if (ShrinkDemandedConstant(Op, ~Known2.Zero & DemandedBits, TLO))
663 // If the operation can be done in a smaller type, do so.
664 if (ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO))
667 // Output known-1 bits are only known if set in both the LHS & RHS.
668 Known.One &= Known2.One;
669 // Output known-0 are known to be clear if zero in either the LHS | RHS.
670 Known.Zero |= Known2.Zero;
674 SDValue Op0 = Op.getOperand(0);
675 SDValue Op1 = Op.getOperand(1);
677 if (SimplifyDemandedBits(Op1, DemandedBits, DemandedElts, Known, TLO, Depth + 1))
679 assert(!Known.hasConflict() && "Bits known to be one AND zero?");
680 if (SimplifyDemandedBits(Op0, ~Known.One & DemandedBits, DemandedElts, Known2, TLO,
683 assert(!Known2.hasConflict() && "Bits known to be one AND zero?");
685 // If all of the demanded bits are known zero on one side, return the other.
686 // These bits cannot contribute to the result of the 'or'.
687 if (DemandedBits.isSubsetOf(Known2.One | Known.Zero))
688 return TLO.CombineTo(Op, Op0);
689 if (DemandedBits.isSubsetOf(Known.One | Known2.Zero))
690 return TLO.CombineTo(Op, Op1);
691 // If the RHS is a constant, see if we can simplify it.
692 if (ShrinkDemandedConstant(Op, DemandedBits, TLO))
694 // If the operation can be done in a smaller type, do so.
695 if (ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO))
698 // Output known-0 bits are only known if clear in both the LHS & RHS.
699 Known.Zero &= Known2.Zero;
700 // Output known-1 are known to be set if set in either the LHS | RHS.
701 Known.One |= Known2.One;
705 SDValue Op0 = Op.getOperand(0);
706 SDValue Op1 = Op.getOperand(1);
708 if (SimplifyDemandedBits(Op1, DemandedBits, DemandedElts, Known, TLO, Depth + 1))
710 assert(!Known.hasConflict() && "Bits known to be one AND zero?");
711 if (SimplifyDemandedBits(Op0, DemandedBits, DemandedElts, Known2, TLO, Depth + 1))
713 assert(!Known2.hasConflict() && "Bits known to be one AND zero?");
715 // If all of the demanded bits are known zero on one side, return the other.
716 // These bits cannot contribute to the result of the 'xor'.
717 if (DemandedBits.isSubsetOf(Known.Zero))
718 return TLO.CombineTo(Op, Op0);
719 if (DemandedBits.isSubsetOf(Known2.Zero))
720 return TLO.CombineTo(Op, Op1);
721 // If the operation can be done in a smaller type, do so.
722 if (ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO))
725 // If all of the unknown bits are known to be zero on one side or the other
726 // (but not both) turn this into an *inclusive* or.
727 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
728 if (DemandedBits.isSubsetOf(Known.Zero | Known2.Zero))
729 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, VT, Op0, Op1));
731 // Output known-0 bits are known if clear or set in both the LHS & RHS.
732 KnownOut.Zero = (Known.Zero & Known2.Zero) | (Known.One & Known2.One);
733 // Output known-1 are known to be set if set in only one of the LHS, RHS.
734 KnownOut.One = (Known.Zero & Known2.One) | (Known.One & Known2.Zero);
736 if (ConstantSDNode *C = isConstOrConstSplat(Op1)) {
737 // If one side is a constant, and all of the known set bits on the other
738 // side are also set in the constant, turn this into an AND, as we know
739 // the bits will be cleared.
740 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
741 // NB: it is okay if more bits are known than are requested
742 if (C->getAPIntValue() == Known2.One) {
744 TLO.DAG.getConstant(~C->getAPIntValue() & DemandedBits, dl, VT);
745 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, Op0, ANDC));
748 // If the RHS is a constant, see if we can change it. Don't alter a -1
749 // constant because that's a 'not' op, and that is better for combining
751 if (!C->isAllOnesValue()) {
752 if (DemandedBits.isSubsetOf(C->getAPIntValue())) {
753 // We're flipping all demanded bits. Flip the undemanded bits too.
754 SDValue New = TLO.DAG.getNOT(dl, Op0, VT);
755 return TLO.CombineTo(Op, New);
757 // If we can't turn this into a 'not', try to shrink the constant.
758 if (ShrinkDemandedConstant(Op, DemandedBits, TLO))
763 Known = std::move(KnownOut);
767 if (SimplifyDemandedBits(Op.getOperand(2), DemandedBits, Known, TLO,
770 if (SimplifyDemandedBits(Op.getOperand(1), DemandedBits, Known2, TLO,
773 assert(!Known.hasConflict() && "Bits known to be one AND zero?");
774 assert(!Known2.hasConflict() && "Bits known to be one AND zero?");
776 // If the operands are constants, see if we can simplify them.
777 if (ShrinkDemandedConstant(Op, DemandedBits, TLO))
780 // Only known if known in both the LHS and RHS.
781 Known.One &= Known2.One;
782 Known.Zero &= Known2.Zero;
785 if (SimplifyDemandedBits(Op.getOperand(3), DemandedBits, Known, TLO,
788 if (SimplifyDemandedBits(Op.getOperand(2), DemandedBits, Known2, TLO,
791 assert(!Known.hasConflict() && "Bits known to be one AND zero?");
792 assert(!Known2.hasConflict() && "Bits known to be one AND zero?");
794 // If the operands are constants, see if we can simplify them.
795 if (ShrinkDemandedConstant(Op, DemandedBits, TLO))
798 // Only known if known in both the LHS and RHS.
799 Known.One &= Known2.One;
800 Known.Zero &= Known2.Zero;
803 SDValue Op0 = Op.getOperand(0);
804 SDValue Op1 = Op.getOperand(1);
805 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
806 // If (1) we only need the sign-bit, (2) the setcc operands are the same
807 // width as the setcc result, and (3) the result of a setcc conforms to 0 or
808 // -1, we may be able to bypass the setcc.
809 if (DemandedBits.isSignMask() &&
810 Op0.getScalarValueSizeInBits() == BitWidth &&
811 getBooleanContents(VT) ==
812 BooleanContent::ZeroOrNegativeOneBooleanContent) {
813 // If we're testing X < 0, then this compare isn't needed - just use X!
814 // FIXME: We're limiting to integer types here, but this should also work
815 // if we don't care about FP signed-zero. The use of SETLT with FP means
816 // that we don't care about NaNs.
817 if (CC == ISD::SETLT && Op1.getValueType().isInteger() &&
818 (isNullConstant(Op1) || ISD::isBuildVectorAllZeros(Op1.getNode())))
819 return TLO.CombineTo(Op, Op0);
821 // TODO: Should we check for other forms of sign-bit comparisons?
822 // Examples: X <= -1, X >= 0
824 if (getBooleanContents(Op0.getValueType()) ==
825 TargetLowering::ZeroOrOneBooleanContent &&
827 Known.Zero.setBitsFrom(1);
831 SDValue Op0 = Op.getOperand(0);
832 SDValue Op1 = Op.getOperand(1);
834 if (ConstantSDNode *SA = isConstOrConstSplat(Op1)) {
835 // If the shift count is an invalid immediate, don't do anything.
836 if (SA->getAPIntValue().uge(BitWidth))
839 unsigned ShAmt = SA->getZExtValue();
841 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
842 // single shift. We can do this if the bottom bits (which are shifted
843 // out) are never demanded.
844 if (Op0.getOpcode() == ISD::SRL) {
846 (DemandedBits & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
847 if (ConstantSDNode *SA2 = isConstOrConstSplat(Op0.getOperand(1))) {
848 if (SA2->getAPIntValue().ult(BitWidth)) {
849 unsigned C1 = SA2->getZExtValue();
850 unsigned Opc = ISD::SHL;
851 int Diff = ShAmt - C1;
857 SDValue NewSA = TLO.DAG.getConstant(Diff, dl, Op1.getValueType());
858 return TLO.CombineTo(
859 Op, TLO.DAG.getNode(Opc, dl, VT, Op0.getOperand(0), NewSA));
865 if (SimplifyDemandedBits(Op0, DemandedBits.lshr(ShAmt), DemandedElts, Known, TLO,
869 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
870 // are not demanded. This will likely allow the anyext to be folded away.
871 if (Op0.getOpcode() == ISD::ANY_EXTEND) {
872 SDValue InnerOp = Op0.getOperand(0);
873 EVT InnerVT = InnerOp.getValueType();
874 unsigned InnerBits = InnerVT.getScalarSizeInBits();
875 if (ShAmt < InnerBits && DemandedBits.getActiveBits() <= InnerBits &&
876 isTypeDesirableForOp(ISD::SHL, InnerVT)) {
877 EVT ShTy = getShiftAmountTy(InnerVT, DL);
878 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
881 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
882 TLO.DAG.getConstant(ShAmt, dl, ShTy));
883 return TLO.CombineTo(
884 Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT, NarrowShl));
886 // Repeat the SHL optimization above in cases where an extension
887 // intervenes: (shl (anyext (shr x, c1)), c2) to
888 // (shl (anyext x), c2-c1). This requires that the bottom c1 bits
889 // aren't demanded (as above) and that the shifted upper c1 bits of
890 // x aren't demanded.
891 if (Op0.hasOneUse() && InnerOp.getOpcode() == ISD::SRL &&
892 InnerOp.hasOneUse()) {
893 if (ConstantSDNode *SA2 =
894 isConstOrConstSplat(InnerOp.getOperand(1))) {
895 unsigned InnerShAmt = SA2->getLimitedValue(InnerBits);
896 if (InnerShAmt < ShAmt && InnerShAmt < InnerBits &&
897 DemandedBits.getActiveBits() <=
898 (InnerBits - InnerShAmt + ShAmt) &&
899 DemandedBits.countTrailingZeros() >= ShAmt) {
900 SDValue NewSA = TLO.DAG.getConstant(ShAmt - InnerShAmt, dl,
902 SDValue NewExt = TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT,
903 InnerOp.getOperand(0));
904 return TLO.CombineTo(
905 Op, TLO.DAG.getNode(ISD::SHL, dl, VT, NewExt, NewSA));
911 Known.Zero <<= ShAmt;
913 // low bits known zero.
914 Known.Zero.setLowBits(ShAmt);
919 SDValue Op0 = Op.getOperand(0);
920 SDValue Op1 = Op.getOperand(1);
922 if (ConstantSDNode *SA = isConstOrConstSplat(Op1)) {
923 // If the shift count is an invalid immediate, don't do anything.
924 if (SA->getAPIntValue().uge(BitWidth))
927 unsigned ShAmt = SA->getZExtValue();
928 APInt InDemandedMask = (DemandedBits << ShAmt);
930 // If the shift is exact, then it does demand the low bits (and knows that
932 if (Op->getFlags().hasExact())
933 InDemandedMask.setLowBits(ShAmt);
935 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
936 // single shift. We can do this if the top bits (which are shifted out)
937 // are never demanded.
938 if (Op0.getOpcode() == ISD::SHL) {
939 if (ConstantSDNode *SA2 = isConstOrConstSplat(Op0.getOperand(1))) {
941 (DemandedBits & APInt::getHighBitsSet(BitWidth, ShAmt)) == 0) {
942 if (SA2->getAPIntValue().ult(BitWidth)) {
943 unsigned C1 = SA2->getZExtValue();
944 unsigned Opc = ISD::SRL;
945 int Diff = ShAmt - C1;
951 SDValue NewSA = TLO.DAG.getConstant(Diff, dl, Op1.getValueType());
952 return TLO.CombineTo(
953 Op, TLO.DAG.getNode(Opc, dl, VT, Op0.getOperand(0), NewSA));
959 // Compute the new bits that are at the top now.
960 if (SimplifyDemandedBits(Op0, InDemandedMask, DemandedElts, Known, TLO, Depth + 1))
962 assert(!Known.hasConflict() && "Bits known to be one AND zero?");
963 Known.Zero.lshrInPlace(ShAmt);
964 Known.One.lshrInPlace(ShAmt);
966 Known.Zero.setHighBits(ShAmt); // High bits known zero.
971 SDValue Op0 = Op.getOperand(0);
972 SDValue Op1 = Op.getOperand(1);
974 // If this is an arithmetic shift right and only the low-bit is set, we can
975 // always convert this into a logical shr, even if the shift amount is
976 // variable. The low bit of the shift cannot be an input sign bit unless
977 // the shift amount is >= the size of the datatype, which is undefined.
978 if (DemandedBits.isOneValue())
979 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, Op1));
981 if (ConstantSDNode *SA = isConstOrConstSplat(Op1)) {
982 // If the shift count is an invalid immediate, don't do anything.
983 if (SA->getAPIntValue().uge(BitWidth))
986 unsigned ShAmt = SA->getZExtValue();
987 APInt InDemandedMask = (DemandedBits << ShAmt);
989 // If the shift is exact, then it does demand the low bits (and knows that
991 if (Op->getFlags().hasExact())
992 InDemandedMask.setLowBits(ShAmt);
994 // If any of the demanded bits are produced by the sign extension, we also
995 // demand the input sign bit.
996 if (DemandedBits.countLeadingZeros() < ShAmt)
997 InDemandedMask.setSignBit();
999 if (SimplifyDemandedBits(Op0, InDemandedMask, DemandedElts, Known, TLO, Depth + 1))
1001 assert(!Known.hasConflict() && "Bits known to be one AND zero?");
1002 Known.Zero.lshrInPlace(ShAmt);
1003 Known.One.lshrInPlace(ShAmt);
1005 // If the input sign bit is known to be zero, or if none of the top bits
1006 // are demanded, turn this into an unsigned shift right.
1007 if (Known.Zero[BitWidth - ShAmt - 1] ||
1008 DemandedBits.countLeadingZeros() >= ShAmt) {
1010 Flags.setExact(Op->getFlags().hasExact());
1011 return TLO.CombineTo(
1012 Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, Op1, Flags));
1015 int Log2 = DemandedBits.exactLogBase2();
1017 // The bit must come from the sign.
1019 TLO.DAG.getConstant(BitWidth - 1 - Log2, dl, Op1.getValueType());
1020 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, NewSA));
1023 if (Known.One[BitWidth - ShAmt - 1])
1024 // New bits are known one.
1025 Known.One.setHighBits(ShAmt);
1029 case ISD::SIGN_EXTEND_INREG: {
1030 SDValue Op0 = Op.getOperand(0);
1031 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1032 unsigned ExVTBits = ExVT.getScalarSizeInBits();
1034 // If we only care about the highest bit, don't bother shifting right.
1035 if (DemandedBits.isSignMask()) {
1036 bool AlreadySignExtended =
1037 TLO.DAG.ComputeNumSignBits(Op0) >= BitWidth - ExVTBits + 1;
1038 // However if the input is already sign extended we expect the sign
1039 // extension to be dropped altogether later and do not simplify.
1040 if (!AlreadySignExtended) {
1041 // Compute the correct shift amount type, which must be getShiftAmountTy
1042 // for scalar types after legalization.
1043 EVT ShiftAmtTy = VT;
1044 if (TLO.LegalTypes() && !ShiftAmtTy.isVector())
1045 ShiftAmtTy = getShiftAmountTy(ShiftAmtTy, DL);
1048 TLO.DAG.getConstant(BitWidth - ExVTBits, dl, ShiftAmtTy);
1049 return TLO.CombineTo(Op,
1050 TLO.DAG.getNode(ISD::SHL, dl, VT, Op0, ShiftAmt));
1054 // If none of the extended bits are demanded, eliminate the sextinreg.
1055 if (DemandedBits.getActiveBits() <= ExVTBits)
1056 return TLO.CombineTo(Op, Op0);
1058 APInt InputDemandedBits = DemandedBits.getLoBits(ExVTBits);
1060 // Since the sign extended bits are demanded, we know that the sign
1062 InputDemandedBits.setBit(ExVTBits - 1);
1064 if (SimplifyDemandedBits(Op0, InputDemandedBits, Known, TLO, Depth + 1))
1066 assert(!Known.hasConflict() && "Bits known to be one AND zero?");
1068 // If the sign bit of the input is known set or clear, then we know the
1069 // top bits of the result.
1071 // If the input sign bit is known zero, convert this into a zero extension.
1072 if (Known.Zero[ExVTBits - 1])
1073 return TLO.CombineTo(
1074 Op, TLO.DAG.getZeroExtendInReg(Op0, dl, ExVT.getScalarType()));
1076 APInt Mask = APInt::getLowBitsSet(BitWidth, ExVTBits);
1077 if (Known.One[ExVTBits - 1]) { // Input sign bit known set
1078 Known.One.setBitsFrom(ExVTBits);
1080 } else { // Input sign bit unknown
1086 case ISD::BUILD_PAIR: {
1087 EVT HalfVT = Op.getOperand(0).getValueType();
1088 unsigned HalfBitWidth = HalfVT.getScalarSizeInBits();
1090 APInt MaskLo = DemandedBits.getLoBits(HalfBitWidth).trunc(HalfBitWidth);
1091 APInt MaskHi = DemandedBits.getHiBits(HalfBitWidth).trunc(HalfBitWidth);
1093 KnownBits KnownLo, KnownHi;
1095 if (SimplifyDemandedBits(Op.getOperand(0), MaskLo, KnownLo, TLO, Depth + 1))
1098 if (SimplifyDemandedBits(Op.getOperand(1), MaskHi, KnownHi, TLO, Depth + 1))
1101 Known.Zero = KnownLo.Zero.zext(BitWidth) |
1102 KnownHi.Zero.zext(BitWidth).shl(HalfBitWidth);
1104 Known.One = KnownLo.One.zext(BitWidth) |
1105 KnownHi.One.zext(BitWidth).shl(HalfBitWidth);
1108 case ISD::ZERO_EXTEND: {
1109 SDValue Src = Op.getOperand(0);
1110 unsigned InBits = Src.getScalarValueSizeInBits();
1112 // If none of the top bits are demanded, convert this into an any_extend.
1113 if (DemandedBits.getActiveBits() <= InBits)
1114 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT, Src));
1116 APInt InDemandedBits = DemandedBits.trunc(InBits);
1117 if (SimplifyDemandedBits(Src, InDemandedBits, Known, TLO, Depth+1))
1119 assert(!Known.hasConflict() && "Bits known to be one AND zero?");
1120 Known = Known.zext(BitWidth);
1121 Known.Zero.setBitsFrom(InBits);
1124 case ISD::SIGN_EXTEND: {
1125 SDValue Src = Op.getOperand(0);
1126 unsigned InBits = Src.getScalarValueSizeInBits();
1128 // If none of the top bits are demanded, convert this into an any_extend.
1129 if (DemandedBits.getActiveBits() <= InBits)
1130 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT, Src));
1132 // Since some of the sign extended bits are demanded, we know that the sign
1134 APInt InDemandedBits = DemandedBits.trunc(InBits);
1135 InDemandedBits.setBit(InBits - 1);
1137 if (SimplifyDemandedBits(Src, InDemandedBits, Known, TLO, Depth + 1))
1139 assert(!Known.hasConflict() && "Bits known to be one AND zero?");
1140 // If the sign bit is known one, the top bits match.
1141 Known = Known.sext(BitWidth);
1143 // If the sign bit is known zero, convert this to a zero extend.
1144 if (Known.isNonNegative())
1145 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Src));
1148 case ISD::SIGN_EXTEND_VECTOR_INREG: {
1149 // TODO - merge this with SIGN_EXTEND above?
1150 SDValue Src = Op.getOperand(0);
1151 unsigned InBits = Src.getScalarValueSizeInBits();
1153 APInt InDemandedBits = DemandedBits.trunc(InBits);
1155 // If some of the sign extended bits are demanded, we know that the sign
1157 if (InBits < DemandedBits.getActiveBits())
1158 InDemandedBits.setBit(InBits - 1);
1160 if (SimplifyDemandedBits(Src, InDemandedBits, Known, TLO, Depth + 1))
1162 assert(!Known.hasConflict() && "Bits known to be one AND zero?");
1163 // If the sign bit is known one, the top bits match.
1164 Known = Known.sext(BitWidth);
1167 case ISD::ANY_EXTEND: {
1168 SDValue Src = Op.getOperand(0);
1169 unsigned InBits = Src.getScalarValueSizeInBits();
1170 APInt InDemandedBits = DemandedBits.trunc(InBits);
1171 if (SimplifyDemandedBits(Src, InDemandedBits, Known, TLO, Depth+1))
1173 assert(!Known.hasConflict() && "Bits known to be one AND zero?");
1174 Known = Known.zext(BitWidth);
1177 case ISD::TRUNCATE: {
1178 SDValue Src = Op.getOperand(0);
1180 // Simplify the input, using demanded bit information, and compute the known
1181 // zero/one bits live out.
1182 unsigned OperandBitWidth = Src.getScalarValueSizeInBits();
1183 APInt TruncMask = DemandedBits.zext(OperandBitWidth);
1184 if (SimplifyDemandedBits(Src, TruncMask, Known, TLO, Depth + 1))
1186 Known = Known.trunc(BitWidth);
1188 // If the input is only used by this truncate, see if we can shrink it based
1189 // on the known demanded bits.
1190 if (Src.getNode()->hasOneUse()) {
1191 switch (Src.getOpcode()) {
1195 // Shrink SRL by a constant if none of the high bits shifted in are
1197 if (TLO.LegalTypes() && !isTypeDesirableForOp(ISD::SRL, VT))
1198 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
1201 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Src.getOperand(1));
1204 SDValue Shift = Src.getOperand(1);
1205 if (TLO.LegalTypes()) {
1206 uint64_t ShVal = ShAmt->getZExtValue();
1207 Shift = TLO.DAG.getConstant(ShVal, dl, getShiftAmountTy(VT, DL));
1210 if (ShAmt->getZExtValue() < BitWidth) {
1211 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
1212 OperandBitWidth - BitWidth);
1213 HighBits.lshrInPlace(ShAmt->getZExtValue());
1214 HighBits = HighBits.trunc(BitWidth);
1216 if (!(HighBits & DemandedBits)) {
1217 // None of the shifted in bits are needed. Add a truncate of the
1218 // shift input, then shift it.
1220 TLO.DAG.getNode(ISD::TRUNCATE, dl, VT, Src.getOperand(0));
1221 return TLO.CombineTo(
1222 Op, TLO.DAG.getNode(ISD::SRL, dl, VT, NewTrunc, Shift));
1229 assert(!Known.hasConflict() && "Bits known to be one AND zero?");
1232 case ISD::AssertZext: {
1233 // AssertZext demands all of the high bits, plus any of the low bits
1234 // demanded by its users.
1235 EVT ZVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1236 APInt InMask = APInt::getLowBitsSet(BitWidth, ZVT.getSizeInBits());
1237 if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | DemandedBits,
1238 Known, TLO, Depth+1))
1240 assert(!Known.hasConflict() && "Bits known to be one AND zero?");
1242 Known.Zero |= ~InMask;
1245 case ISD::EXTRACT_VECTOR_ELT: {
1246 SDValue Src = Op.getOperand(0);
1247 SDValue Idx = Op.getOperand(1);
1248 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
1249 unsigned EltBitWidth = Src.getScalarValueSizeInBits();
1251 // Demand the bits from every vector element without a constant index.
1252 APInt DemandedSrcElts = APInt::getAllOnesValue(NumSrcElts);
1253 if (auto *CIdx = dyn_cast<ConstantSDNode>(Idx))
1254 if (CIdx->getAPIntValue().ult(NumSrcElts))
1255 DemandedSrcElts = APInt::getOneBitSet(NumSrcElts, CIdx->getZExtValue());
1257 // If BitWidth > EltBitWidth the value is anyext:ed. So we do not know
1258 // anything about the extended bits.
1259 APInt DemandedSrcBits = DemandedBits;
1260 if (BitWidth > EltBitWidth)
1261 DemandedSrcBits = DemandedSrcBits.trunc(EltBitWidth);
1263 if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedSrcElts, Known2, TLO,
1268 if (BitWidth > EltBitWidth)
1269 Known = Known.zext(BitWidth);
1272 case ISD::BITCAST: {
1273 SDValue Src = Op.getOperand(0);
1274 EVT SrcVT = Src.getValueType();
1275 unsigned NumSrcEltBits = SrcVT.getScalarSizeInBits();
1277 // If this is an FP->Int bitcast and if the sign bit is the only
1278 // thing demanded, turn this into a FGETSIGN.
1279 if (!TLO.LegalOperations() && !VT.isVector() && !SrcVT.isVector() &&
1280 DemandedBits == APInt::getSignMask(Op.getValueSizeInBits()) &&
1281 SrcVT.isFloatingPoint()) {
1282 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, VT);
1283 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
1284 if ((OpVTLegal || i32Legal) && VT.isSimple() && SrcVT != MVT::f16 &&
1285 SrcVT != MVT::f128) {
1286 // Cannot eliminate/lower SHL for f128 yet.
1287 EVT Ty = OpVTLegal ? VT : MVT::i32;
1288 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1289 // place. We expect the SHL to be eliminated by other optimizations.
1290 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Src);
1291 unsigned OpVTSizeInBits = Op.getValueSizeInBits();
1292 if (!OpVTLegal && OpVTSizeInBits > 32)
1293 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Sign);
1294 unsigned ShVal = Op.getValueSizeInBits() - 1;
1295 SDValue ShAmt = TLO.DAG.getConstant(ShVal, dl, VT);
1296 return TLO.CombineTo(Op,
1297 TLO.DAG.getNode(ISD::SHL, dl, VT, Sign, ShAmt));
1300 // If bitcast from a vector, see if we can use SimplifyDemandedVectorElts by
1301 // demanding the element if any bits from it are demanded.
1302 // TODO - bigendian once we have test coverage.
1303 // TODO - bool vectors once SimplifyDemandedVectorElts has SETCC support.
1304 if (SrcVT.isVector() && NumSrcEltBits > 1 &&
1305 (BitWidth % NumSrcEltBits) == 0 &&
1306 TLO.DAG.getDataLayout().isLittleEndian()) {
1307 unsigned Scale = BitWidth / NumSrcEltBits;
1308 auto GetDemandedSubMask = [&](APInt &DemandedSubElts) -> bool {
1309 DemandedSubElts = APInt::getNullValue(Scale);
1310 for (unsigned i = 0; i != Scale; ++i) {
1311 unsigned Offset = i * NumSrcEltBits;
1312 APInt Sub = DemandedBits.extractBits(NumSrcEltBits, Offset);
1313 if (!Sub.isNullValue())
1314 DemandedSubElts.setBit(i);
1319 APInt DemandedSubElts;
1320 if (GetDemandedSubMask(DemandedSubElts)) {
1321 unsigned NumSrcElts = SrcVT.getVectorNumElements();
1322 APInt DemandedElts = APInt::getSplat(NumSrcElts, DemandedSubElts);
1324 APInt KnownUndef, KnownZero;
1325 if (SimplifyDemandedVectorElts(Src, DemandedElts, KnownUndef, KnownZero,
1330 // If this is a bitcast, let computeKnownBits handle it. Only do this on a
1331 // recursive call where Known may be useful to the caller.
1333 Known = TLO.DAG.computeKnownBits(Op, Depth);
1341 // Add, Sub, and Mul don't demand any bits in positions beyond that
1342 // of the highest bit demanded of them.
1343 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
1344 unsigned DemandedBitsLZ = DemandedBits.countLeadingZeros();
1345 APInt LoMask = APInt::getLowBitsSet(BitWidth, BitWidth - DemandedBitsLZ);
1346 if (SimplifyDemandedBits(Op0, LoMask, DemandedElts, Known2, TLO, Depth + 1) ||
1347 SimplifyDemandedBits(Op1, LoMask, DemandedElts, Known2, TLO, Depth + 1) ||
1348 // See if the operation should be performed at a smaller bit width.
1349 ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO)) {
1350 SDNodeFlags Flags = Op.getNode()->getFlags();
1351 if (Flags.hasNoSignedWrap() || Flags.hasNoUnsignedWrap()) {
1352 // Disable the nsw and nuw flags. We can no longer guarantee that we
1353 // won't wrap after simplification.
1354 Flags.setNoSignedWrap(false);
1355 Flags.setNoUnsignedWrap(false);
1356 SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1,
1358 return TLO.CombineTo(Op, NewOp);
1363 // If we have a constant operand, we may be able to turn it into -1 if we
1364 // do not demand the high bits. This can make the constant smaller to
1365 // encode, allow more general folding, or match specialized instruction
1366 // patterns (eg, 'blsr' on x86). Don't bother changing 1 to -1 because that
1367 // is probably not useful (and could be detrimental).
1368 ConstantSDNode *C = isConstOrConstSplat(Op1);
1369 APInt HighMask = APInt::getHighBitsSet(BitWidth, DemandedBitsLZ);
1370 if (C && !C->isAllOnesValue() && !C->isOne() &&
1371 (C->getAPIntValue() | HighMask).isAllOnesValue()) {
1372 SDValue Neg1 = TLO.DAG.getAllOnesConstant(dl, VT);
1373 // We can't guarantee that the new math op doesn't wrap, so explicitly
1374 // clear those flags to prevent folding with a potential existing node
1375 // that has those flags set.
1377 Flags.setNoSignedWrap(false);
1378 Flags.setNoUnsignedWrap(false);
1379 SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Neg1, Flags);
1380 return TLO.CombineTo(Op, NewOp);
1386 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) {
1387 if (SimplifyDemandedBitsForTargetNode(Op, DemandedBits, DemandedElts,
1393 // Just use computeKnownBits to compute output bits.
1394 Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth);
1398 // If we know the value of all of the demanded bits, return this as a
1400 if (DemandedBits.isSubsetOf(Known.Zero | Known.One)) {
1401 // Avoid folding to a constant if any OpaqueConstant is involved.
1402 const SDNode *N = Op.getNode();
1403 for (SDNodeIterator I = SDNodeIterator::begin(N),
1404 E = SDNodeIterator::end(N);
1407 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
1411 // TODO: Handle float bits as well.
1413 return TLO.CombineTo(Op, TLO.DAG.getConstant(Known.One, dl, VT));
1419 bool TargetLowering::SimplifyDemandedVectorElts(SDValue Op,
1420 const APInt &DemandedElts,
1423 DAGCombinerInfo &DCI) const {
1424 SelectionDAG &DAG = DCI.DAG;
1425 TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
1426 !DCI.isBeforeLegalizeOps());
1429 SimplifyDemandedVectorElts(Op, DemandedElts, KnownUndef, KnownZero, TLO);
1431 DCI.AddToWorklist(Op.getNode());
1432 DCI.CommitTargetLoweringOpt(TLO);
1437 bool TargetLowering::SimplifyDemandedVectorElts(
1438 SDValue Op, const APInt &DemandedEltMask, APInt &KnownUndef,
1439 APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth,
1440 bool AssumeSingleUse) const {
1441 EVT VT = Op.getValueType();
1442 APInt DemandedElts = DemandedEltMask;
1443 unsigned NumElts = DemandedElts.getBitWidth();
1444 assert(VT.isVector() && "Expected vector op");
1445 assert(VT.getVectorNumElements() == NumElts &&
1446 "Mask size mismatches value type element count!");
1448 KnownUndef = KnownZero = APInt::getNullValue(NumElts);
1452 KnownUndef.setAllBits();
1456 // If Op has other users, assume that all elements are needed.
1457 if (!Op.getNode()->hasOneUse() && !AssumeSingleUse)
1458 DemandedElts.setAllBits();
1460 // Not demanding any elements from Op.
1461 if (DemandedElts == 0) {
1462 KnownUndef.setAllBits();
1463 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT));
1466 // Limit search depth.
1471 unsigned EltSizeInBits = VT.getScalarSizeInBits();
1473 switch (Op.getOpcode()) {
1474 case ISD::SCALAR_TO_VECTOR: {
1475 if (!DemandedElts[0]) {
1476 KnownUndef.setAllBits();
1477 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT));
1479 KnownUndef.setHighBits(NumElts - 1);
1482 case ISD::BITCAST: {
1483 SDValue Src = Op.getOperand(0);
1484 EVT SrcVT = Src.getValueType();
1486 // We only handle vectors here.
1487 // TODO - investigate calling SimplifyDemandedBits/ComputeKnownBits?
1488 if (!SrcVT.isVector())
1491 // Fast handling of 'identity' bitcasts.
1492 unsigned NumSrcElts = SrcVT.getVectorNumElements();
1493 if (NumSrcElts == NumElts)
1494 return SimplifyDemandedVectorElts(Src, DemandedElts, KnownUndef,
1495 KnownZero, TLO, Depth + 1);
1497 APInt SrcZero, SrcUndef;
1498 APInt SrcDemandedElts = APInt::getNullValue(NumSrcElts);
1500 // Bitcast from 'large element' src vector to 'small element' vector, we
1501 // must demand a source element if any DemandedElt maps to it.
1502 if ((NumElts % NumSrcElts) == 0) {
1503 unsigned Scale = NumElts / NumSrcElts;
1504 for (unsigned i = 0; i != NumElts; ++i)
1505 if (DemandedElts[i])
1506 SrcDemandedElts.setBit(i / Scale);
1508 if (SimplifyDemandedVectorElts(Src, SrcDemandedElts, SrcUndef, SrcZero,
1512 // Try calling SimplifyDemandedBits, converting demanded elts to the bits
1513 // of the large element.
1514 // TODO - bigendian once we have test coverage.
1515 if (TLO.DAG.getDataLayout().isLittleEndian()) {
1516 unsigned SrcEltSizeInBits = SrcVT.getScalarSizeInBits();
1517 APInt SrcDemandedBits = APInt::getNullValue(SrcEltSizeInBits);
1518 for (unsigned i = 0; i != NumElts; ++i)
1519 if (DemandedElts[i]) {
1520 unsigned Ofs = (i % Scale) * EltSizeInBits;
1521 SrcDemandedBits.setBits(Ofs, Ofs + EltSizeInBits);
1525 if (SimplifyDemandedBits(Src, SrcDemandedBits, Known, TLO, Depth + 1))
1529 // If the src element is zero/undef then all the output elements will be -
1530 // only demanded elements are guaranteed to be correct.
1531 for (unsigned i = 0; i != NumSrcElts; ++i) {
1532 if (SrcDemandedElts[i]) {
1534 KnownZero.setBits(i * Scale, (i + 1) * Scale);
1536 KnownUndef.setBits(i * Scale, (i + 1) * Scale);
1541 // Bitcast from 'small element' src vector to 'large element' vector, we
1542 // demand all smaller source elements covered by the larger demanded element
1544 if ((NumSrcElts % NumElts) == 0) {
1545 unsigned Scale = NumSrcElts / NumElts;
1546 for (unsigned i = 0; i != NumElts; ++i)
1547 if (DemandedElts[i])
1548 SrcDemandedElts.setBits(i * Scale, (i + 1) * Scale);
1550 if (SimplifyDemandedVectorElts(Src, SrcDemandedElts, SrcUndef, SrcZero,
1554 // If all the src elements covering an output element are zero/undef, then
1555 // the output element will be as well, assuming it was demanded.
1556 for (unsigned i = 0; i != NumElts; ++i) {
1557 if (DemandedElts[i]) {
1558 if (SrcZero.extractBits(Scale, i * Scale).isAllOnesValue())
1559 KnownZero.setBit(i);
1560 if (SrcUndef.extractBits(Scale, i * Scale).isAllOnesValue())
1561 KnownUndef.setBit(i);
1567 case ISD::BUILD_VECTOR: {
1568 // Check all elements and simplify any unused elements with UNDEF.
1569 if (!DemandedElts.isAllOnesValue()) {
1570 // Don't simplify BROADCASTS.
1571 if (llvm::any_of(Op->op_values(),
1572 [&](SDValue Elt) { return Op.getOperand(0) != Elt; })) {
1573 SmallVector<SDValue, 32> Ops(Op->op_begin(), Op->op_end());
1574 bool Updated = false;
1575 for (unsigned i = 0; i != NumElts; ++i) {
1576 if (!DemandedElts[i] && !Ops[i].isUndef()) {
1577 Ops[i] = TLO.DAG.getUNDEF(Ops[0].getValueType());
1578 KnownUndef.setBit(i);
1583 return TLO.CombineTo(Op, TLO.DAG.getBuildVector(VT, DL, Ops));
1586 for (unsigned i = 0; i != NumElts; ++i) {
1587 SDValue SrcOp = Op.getOperand(i);
1588 if (SrcOp.isUndef()) {
1589 KnownUndef.setBit(i);
1590 } else if (EltSizeInBits == SrcOp.getScalarValueSizeInBits() &&
1591 (isNullConstant(SrcOp) || isNullFPConstant(SrcOp))) {
1592 KnownZero.setBit(i);
1597 case ISD::CONCAT_VECTORS: {
1598 EVT SubVT = Op.getOperand(0).getValueType();
1599 unsigned NumSubVecs = Op.getNumOperands();
1600 unsigned NumSubElts = SubVT.getVectorNumElements();
1601 for (unsigned i = 0; i != NumSubVecs; ++i) {
1602 SDValue SubOp = Op.getOperand(i);
1603 APInt SubElts = DemandedElts.extractBits(NumSubElts, i * NumSubElts);
1604 APInt SubUndef, SubZero;
1605 if (SimplifyDemandedVectorElts(SubOp, SubElts, SubUndef, SubZero, TLO,
1608 KnownUndef.insertBits(SubUndef, i * NumSubElts);
1609 KnownZero.insertBits(SubZero, i * NumSubElts);
1613 case ISD::INSERT_SUBVECTOR: {
1614 if (!isa<ConstantSDNode>(Op.getOperand(2)))
1616 SDValue Base = Op.getOperand(0);
1617 SDValue Sub = Op.getOperand(1);
1618 EVT SubVT = Sub.getValueType();
1619 unsigned NumSubElts = SubVT.getVectorNumElements();
1620 const APInt& Idx = cast<ConstantSDNode>(Op.getOperand(2))->getAPIntValue();
1621 if (Idx.ugt(NumElts - NumSubElts))
1623 unsigned SubIdx = Idx.getZExtValue();
1624 APInt SubElts = DemandedElts.extractBits(NumSubElts, SubIdx);
1625 APInt SubUndef, SubZero;
1626 if (SimplifyDemandedVectorElts(Sub, SubElts, SubUndef, SubZero, TLO,
1629 APInt BaseElts = DemandedElts;
1630 BaseElts.insertBits(APInt::getNullValue(NumSubElts), SubIdx);
1631 if (SimplifyDemandedVectorElts(Base, BaseElts, KnownUndef, KnownZero, TLO,
1634 KnownUndef.insertBits(SubUndef, SubIdx);
1635 KnownZero.insertBits(SubZero, SubIdx);
1638 case ISD::EXTRACT_SUBVECTOR: {
1639 SDValue Src = Op.getOperand(0);
1640 ConstantSDNode *SubIdx = dyn_cast<ConstantSDNode>(Op.getOperand(1));
1641 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
1642 if (SubIdx && SubIdx->getAPIntValue().ule(NumSrcElts - NumElts)) {
1643 // Offset the demanded elts by the subvector index.
1644 uint64_t Idx = SubIdx->getZExtValue();
1645 APInt SrcElts = DemandedElts.zextOrSelf(NumSrcElts).shl(Idx);
1646 APInt SrcUndef, SrcZero;
1647 if (SimplifyDemandedVectorElts(Src, SrcElts, SrcUndef, SrcZero, TLO,
1650 KnownUndef = SrcUndef.extractBits(NumElts, Idx);
1651 KnownZero = SrcZero.extractBits(NumElts, Idx);
1655 case ISD::INSERT_VECTOR_ELT: {
1656 SDValue Vec = Op.getOperand(0);
1657 SDValue Scl = Op.getOperand(1);
1658 auto *CIdx = dyn_cast<ConstantSDNode>(Op.getOperand(2));
1660 // For a legal, constant insertion index, if we don't need this insertion
1661 // then strip it, else remove it from the demanded elts.
1662 if (CIdx && CIdx->getAPIntValue().ult(NumElts)) {
1663 unsigned Idx = CIdx->getZExtValue();
1664 if (!DemandedElts[Idx])
1665 return TLO.CombineTo(Op, Vec);
1667 APInt DemandedVecElts(DemandedElts);
1668 DemandedVecElts.clearBit(Idx);
1669 if (SimplifyDemandedVectorElts(Vec, DemandedVecElts, KnownUndef,
1670 KnownZero, TLO, Depth + 1))
1673 KnownUndef.clearBit(Idx);
1675 KnownUndef.setBit(Idx);
1677 KnownZero.clearBit(Idx);
1678 if (isNullConstant(Scl) || isNullFPConstant(Scl))
1679 KnownZero.setBit(Idx);
1683 APInt VecUndef, VecZero;
1684 if (SimplifyDemandedVectorElts(Vec, DemandedElts, VecUndef, VecZero, TLO,
1687 // Without knowing the insertion index we can't set KnownUndef/KnownZero.
1690 case ISD::VSELECT: {
1691 // Try to transform the select condition based on the current demanded
1693 // TODO: If a condition element is undef, we can choose from one arm of the
1694 // select (and if one arm is undef, then we can propagate that to the
1696 // TODO - add support for constant vselect masks (see IR version of this).
1697 APInt UnusedUndef, UnusedZero;
1698 if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedElts, UnusedUndef,
1699 UnusedZero, TLO, Depth + 1))
1702 // See if we can simplify either vselect operand.
1703 APInt DemandedLHS(DemandedElts);
1704 APInt DemandedRHS(DemandedElts);
1705 APInt UndefLHS, ZeroLHS;
1706 APInt UndefRHS, ZeroRHS;
1707 if (SimplifyDemandedVectorElts(Op.getOperand(1), DemandedLHS, UndefLHS,
1708 ZeroLHS, TLO, Depth + 1))
1710 if (SimplifyDemandedVectorElts(Op.getOperand(2), DemandedRHS, UndefRHS,
1711 ZeroRHS, TLO, Depth + 1))
1714 KnownUndef = UndefLHS & UndefRHS;
1715 KnownZero = ZeroLHS & ZeroRHS;
1718 case ISD::VECTOR_SHUFFLE: {
1719 ArrayRef<int> ShuffleMask = cast<ShuffleVectorSDNode>(Op)->getMask();
1721 // Collect demanded elements from shuffle operands..
1722 APInt DemandedLHS(NumElts, 0);
1723 APInt DemandedRHS(NumElts, 0);
1724 for (unsigned i = 0; i != NumElts; ++i) {
1725 int M = ShuffleMask[i];
1726 if (M < 0 || !DemandedElts[i])
1728 assert(0 <= M && M < (int)(2 * NumElts) && "Shuffle index out of range");
1729 if (M < (int)NumElts)
1730 DemandedLHS.setBit(M);
1732 DemandedRHS.setBit(M - NumElts);
1735 // See if we can simplify either shuffle operand.
1736 APInt UndefLHS, ZeroLHS;
1737 APInt UndefRHS, ZeroRHS;
1738 if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedLHS, UndefLHS,
1739 ZeroLHS, TLO, Depth + 1))
1741 if (SimplifyDemandedVectorElts(Op.getOperand(1), DemandedRHS, UndefRHS,
1742 ZeroRHS, TLO, Depth + 1))
1745 // Simplify mask using undef elements from LHS/RHS.
1746 bool Updated = false;
1747 bool IdentityLHS = true, IdentityRHS = true;
1748 SmallVector<int, 32> NewMask(ShuffleMask.begin(), ShuffleMask.end());
1749 for (unsigned i = 0; i != NumElts; ++i) {
1750 int &M = NewMask[i];
1753 if (!DemandedElts[i] || (M < (int)NumElts && UndefLHS[M]) ||
1754 (M >= (int)NumElts && UndefRHS[M - NumElts])) {
1758 IdentityLHS &= (M < 0) || (M == (int)i);
1759 IdentityRHS &= (M < 0) || ((M - NumElts) == i);
1762 // Update legal shuffle masks based on demanded elements if it won't reduce
1763 // to Identity which can cause premature removal of the shuffle mask.
1764 if (Updated && !IdentityLHS && !IdentityRHS && !TLO.LegalOps &&
1765 isShuffleMaskLegal(NewMask, VT))
1766 return TLO.CombineTo(Op,
1767 TLO.DAG.getVectorShuffle(VT, DL, Op.getOperand(0),
1768 Op.getOperand(1), NewMask));
1770 // Propagate undef/zero elements from LHS/RHS.
1771 for (unsigned i = 0; i != NumElts; ++i) {
1772 int M = ShuffleMask[i];
1774 KnownUndef.setBit(i);
1775 } else if (M < (int)NumElts) {
1777 KnownUndef.setBit(i);
1779 KnownZero.setBit(i);
1781 if (UndefRHS[M - NumElts])
1782 KnownUndef.setBit(i);
1783 if (ZeroRHS[M - NumElts])
1784 KnownZero.setBit(i);
1789 case ISD::SIGN_EXTEND_VECTOR_INREG:
1790 case ISD::ZERO_EXTEND_VECTOR_INREG: {
1791 APInt SrcUndef, SrcZero;
1792 SDValue Src = Op.getOperand(0);
1793 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
1794 APInt DemandedSrcElts = DemandedElts.zextOrSelf(NumSrcElts);
1795 if (SimplifyDemandedVectorElts(Src, DemandedSrcElts, SrcUndef,
1796 SrcZero, TLO, Depth + 1))
1798 KnownZero = SrcZero.zextOrTrunc(NumElts);
1799 KnownUndef = SrcUndef.zextOrTrunc(NumElts);
1801 if (Op.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG) {
1802 // zext(undef) upper bits are guaranteed to be zero.
1803 if (DemandedElts.isSubsetOf(KnownUndef))
1804 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, SDLoc(Op), VT));
1805 KnownUndef.clearAllBits();
1818 APInt SrcUndef, SrcZero;
1819 if (SimplifyDemandedVectorElts(Op.getOperand(1), DemandedElts, SrcUndef,
1820 SrcZero, TLO, Depth + 1))
1822 if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedElts, KnownUndef,
1823 KnownZero, TLO, Depth + 1))
1825 KnownZero &= SrcZero;
1826 KnownUndef &= SrcUndef;
1830 APInt SrcUndef, SrcZero;
1831 if (SimplifyDemandedVectorElts(Op.getOperand(1), DemandedElts, SrcUndef,
1832 SrcZero, TLO, Depth + 1))
1834 if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedElts, KnownUndef,
1835 KnownZero, TLO, Depth + 1))
1838 // If either side has a zero element, then the result element is zero, even
1839 // if the other is an UNDEF.
1840 KnownZero |= SrcZero;
1841 KnownUndef &= SrcUndef;
1842 KnownUndef &= ~KnownZero;
1846 case ISD::SIGN_EXTEND:
1847 case ISD::ZERO_EXTEND:
1848 if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedElts, KnownUndef,
1849 KnownZero, TLO, Depth + 1))
1852 if (Op.getOpcode() == ISD::ZERO_EXTEND) {
1853 // zext(undef) upper bits are guaranteed to be zero.
1854 if (DemandedElts.isSubsetOf(KnownUndef))
1855 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, SDLoc(Op), VT));
1856 KnownUndef.clearAllBits();
1860 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) {
1861 if (SimplifyDemandedVectorEltsForTargetNode(Op, DemandedElts, KnownUndef,
1862 KnownZero, TLO, Depth))
1866 APInt DemandedBits = APInt::getAllOnesValue(EltSizeInBits);
1867 if (SimplifyDemandedBits(Op, DemandedBits, DemandedEltMask, Known, TLO,
1868 Depth, AssumeSingleUse))
1874 assert((KnownUndef & KnownZero) == 0 && "Elements flagged as undef AND zero");
1876 // Constant fold all undef cases.
1877 // TODO: Handle zero cases as well.
1878 if (DemandedElts.isSubsetOf(KnownUndef))
1879 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT));
1884 /// Determine which of the bits specified in Mask are known to be either zero or
1885 /// one and return them in the Known.
1886 void TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
1888 const APInt &DemandedElts,
1889 const SelectionDAG &DAG,
1890 unsigned Depth) const {
1891 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1892 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1893 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1894 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1895 "Should use MaskedValueIsZero if you don't know whether Op"
1896 " is a target node!");
1900 void TargetLowering::computeKnownBitsForFrameIndex(const SDValue Op,
1902 const APInt &DemandedElts,
1903 const SelectionDAG &DAG,
1904 unsigned Depth) const {
1905 assert(isa<FrameIndexSDNode>(Op) && "expected FrameIndex");
1907 if (unsigned Align = DAG.InferPtrAlignment(Op)) {
1908 // The low bits are known zero if the pointer is aligned.
1909 Known.Zero.setLowBits(Log2_32(Align));
1913 /// This method can be implemented by targets that want to expose additional
1914 /// information about sign bits to the DAG Combiner.
1915 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
1917 const SelectionDAG &,
1918 unsigned Depth) const {
1919 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1920 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1921 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1922 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1923 "Should use ComputeNumSignBits if you don't know whether Op"
1924 " is a target node!");
1928 bool TargetLowering::SimplifyDemandedVectorEltsForTargetNode(
1929 SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero,
1930 TargetLoweringOpt &TLO, unsigned Depth) const {
1931 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1932 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1933 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1934 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1935 "Should use SimplifyDemandedVectorElts if you don't know whether Op"
1936 " is a target node!");
1940 bool TargetLowering::SimplifyDemandedBitsForTargetNode(
1941 SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts,
1942 KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth) const {
1943 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1944 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1945 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1946 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1947 "Should use SimplifyDemandedBits if you don't know whether Op"
1948 " is a target node!");
1949 computeKnownBitsForTargetNode(Op, Known, DemandedElts, TLO.DAG, Depth);
1953 bool TargetLowering::isKnownNeverNaNForTargetNode(SDValue Op,
1954 const SelectionDAG &DAG,
1956 unsigned Depth) const {
1957 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1958 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1959 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1960 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1961 "Should use isKnownNeverNaN if you don't know whether Op"
1962 " is a target node!");
1966 // FIXME: Ideally, this would use ISD::isConstantSplatVector(), but that must
1967 // work with truncating build vectors and vectors with elements of less than
1969 bool TargetLowering::isConstTrueVal(const SDNode *N) const {
1974 if (auto *CN = dyn_cast<ConstantSDNode>(N)) {
1975 CVal = CN->getAPIntValue();
1976 } else if (auto *BV = dyn_cast<BuildVectorSDNode>(N)) {
1977 auto *CN = BV->getConstantSplatNode();
1981 // If this is a truncating build vector, truncate the splat value.
1982 // Otherwise, we may fail to match the expected values below.
1983 unsigned BVEltWidth = BV->getValueType(0).getScalarSizeInBits();
1984 CVal = CN->getAPIntValue();
1985 if (BVEltWidth < CVal.getBitWidth())
1986 CVal = CVal.trunc(BVEltWidth);
1991 switch (getBooleanContents(N->getValueType(0))) {
1992 case UndefinedBooleanContent:
1994 case ZeroOrOneBooleanContent:
1995 return CVal.isOneValue();
1996 case ZeroOrNegativeOneBooleanContent:
1997 return CVal.isAllOnesValue();
2000 llvm_unreachable("Invalid boolean contents");
2003 bool TargetLowering::isConstFalseVal(const SDNode *N) const {
2007 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
2009 const BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N);
2013 // Only interested in constant splats, we don't care about undef
2014 // elements in identifying boolean constants and getConstantSplatNode
2015 // returns NULL if all ops are undef;
2016 CN = BV->getConstantSplatNode();
2021 if (getBooleanContents(N->getValueType(0)) == UndefinedBooleanContent)
2022 return !CN->getAPIntValue()[0];
2024 return CN->isNullValue();
2027 bool TargetLowering::isExtendedTrueVal(const ConstantSDNode *N, EVT VT,
2032 TargetLowering::BooleanContent Cnt = getBooleanContents(VT);
2034 case TargetLowering::ZeroOrOneBooleanContent:
2035 // An extended value of 1 is always true, unless its original type is i1,
2036 // in which case it will be sign extended to -1.
2037 return (N->isOne() && !SExt) || (SExt && (N->getValueType(0) != MVT::i1));
2038 case TargetLowering::UndefinedBooleanContent:
2039 case TargetLowering::ZeroOrNegativeOneBooleanContent:
2040 return N->isAllOnesValue() && SExt;
2042 llvm_unreachable("Unexpected enumeration.");
2045 /// This helper function of SimplifySetCC tries to optimize the comparison when
2046 /// either operand of the SetCC node is a bitwise-and instruction.
2047 SDValue TargetLowering::simplifySetCCWithAnd(EVT VT, SDValue N0, SDValue N1,
2049 DAGCombinerInfo &DCI,
2050 const SDLoc &DL) const {
2051 // Match these patterns in any of their permutations:
2054 if (N1.getOpcode() == ISD::AND && N0.getOpcode() != ISD::AND)
2057 EVT OpVT = N0.getValueType();
2058 if (N0.getOpcode() != ISD::AND || !OpVT.isInteger() ||
2059 (Cond != ISD::SETEQ && Cond != ISD::SETNE))
2063 if (N0.getOperand(0) == N1) {
2064 X = N0.getOperand(1);
2065 Y = N0.getOperand(0);
2066 } else if (N0.getOperand(1) == N1) {
2067 X = N0.getOperand(0);
2068 Y = N0.getOperand(1);
2073 SelectionDAG &DAG = DCI.DAG;
2074 SDValue Zero = DAG.getConstant(0, DL, OpVT);
2075 if (DAG.isKnownToBeAPowerOfTwo(Y)) {
2076 // Simplify X & Y == Y to X & Y != 0 if Y has exactly one bit set.
2077 // Note that where Y is variable and is known to have at most one bit set
2078 // (for example, if it is Z & 1) we cannot do this; the expressions are not
2079 // equivalent when Y == 0.
2080 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2081 if (DCI.isBeforeLegalizeOps() ||
2082 isCondCodeLegal(Cond, N0.getSimpleValueType()))
2083 return DAG.getSetCC(DL, VT, N0, Zero, Cond);
2084 } else if (N0.hasOneUse() && hasAndNotCompare(Y)) {
2085 // If the target supports an 'and-not' or 'and-complement' logic operation,
2086 // try to use that to make a comparison operation more efficient.
2087 // But don't do this transform if the mask is a single bit because there are
2088 // more efficient ways to deal with that case (for example, 'bt' on x86 or
2089 // 'rlwinm' on PPC).
2091 // Bail out if the compare operand that we want to turn into a zero is
2092 // already a zero (otherwise, infinite loop).
2093 auto *YConst = dyn_cast<ConstantSDNode>(Y);
2094 if (YConst && YConst->isNullValue())
2097 // Transform this into: ~X & Y == 0.
2098 SDValue NotX = DAG.getNOT(SDLoc(X), X, OpVT);
2099 SDValue NewAnd = DAG.getNode(ISD::AND, SDLoc(N0), OpVT, NotX, Y);
2100 return DAG.getSetCC(DL, VT, NewAnd, Zero, Cond);
2106 /// There are multiple IR patterns that could be checking whether certain
2107 /// truncation of a signed number would be lossy or not. The pattern which is
2108 /// best at IR level, may not lower optimally. Thus, we want to unfold it.
2109 /// We are looking for the following pattern: (KeptBits is a constant)
2110 /// (add %x, (1 << (KeptBits-1))) srccond (1 << KeptBits)
2111 /// KeptBits won't be bitwidth(x), that will be constant-folded to true/false.
2112 /// KeptBits also can't be 1, that would have been folded to %x dstcond 0
2113 /// We will unfold it into the natural trunc+sext pattern:
2114 /// ((%x << C) a>> C) dstcond %x
2115 /// Where C = bitwidth(x) - KeptBits and C u< bitwidth(x)
2116 SDValue TargetLowering::optimizeSetCCOfSignedTruncationCheck(
2117 EVT SCCVT, SDValue N0, SDValue N1, ISD::CondCode Cond, DAGCombinerInfo &DCI,
2118 const SDLoc &DL) const {
2119 // We must be comparing with a constant.
2121 if (!(C1 = dyn_cast<ConstantSDNode>(N1)))
2124 // N0 should be: add %x, (1 << (KeptBits-1))
2125 if (N0->getOpcode() != ISD::ADD)
2128 // And we must be 'add'ing a constant.
2129 ConstantSDNode *C01;
2130 if (!(C01 = dyn_cast<ConstantSDNode>(N0->getOperand(1))))
2133 SDValue X = N0->getOperand(0);
2134 EVT XVT = X.getValueType();
2136 // Validate constants ...
2138 APInt I1 = C1->getAPIntValue();
2140 ISD::CondCode NewCond;
2141 if (Cond == ISD::CondCode::SETULT) {
2142 NewCond = ISD::CondCode::SETEQ;
2143 } else if (Cond == ISD::CondCode::SETULE) {
2144 NewCond = ISD::CondCode::SETEQ;
2145 // But need to 'canonicalize' the constant.
2147 } else if (Cond == ISD::CondCode::SETUGT) {
2148 NewCond = ISD::CondCode::SETNE;
2149 // But need to 'canonicalize' the constant.
2151 } else if (Cond == ISD::CondCode::SETUGE) {
2152 NewCond = ISD::CondCode::SETNE;
2156 APInt I01 = C01->getAPIntValue();
2158 auto checkConstants = [&I1, &I01]() -> bool {
2159 // Both of them must be power-of-two, and the constant from setcc is bigger.
2160 return I1.ugt(I01) && I1.isPowerOf2() && I01.isPowerOf2();
2163 if (checkConstants()) {
2164 // Great, e.g. got icmp ult i16 (add i16 %x, 128), 256
2166 // What if we invert constants? (and the target predicate)
2169 NewCond = getSetCCInverse(NewCond, /*isInteger=*/true);
2170 if (!checkConstants())
2172 // Great, e.g. got icmp uge i16 (add i16 %x, -128), -256
2175 // They are power-of-two, so which bit is set?
2176 const unsigned KeptBits = I1.logBase2();
2177 const unsigned KeptBitsMinusOne = I01.logBase2();
2180 if (KeptBits != (KeptBitsMinusOne + 1))
2182 assert(KeptBits > 0 && KeptBits < XVT.getSizeInBits() && "unreachable");
2184 // We don't want to do this in every single case.
2185 SelectionDAG &DAG = DCI.DAG;
2186 if (!DAG.getTargetLoweringInfo().shouldTransformSignedTruncationCheck(
2190 const unsigned MaskedBits = XVT.getSizeInBits() - KeptBits;
2191 assert(MaskedBits > 0 && MaskedBits < XVT.getSizeInBits() && "unreachable");
2193 // Unfold into: ((%x << C) a>> C) cond %x
2194 // Where 'cond' will be either 'eq' or 'ne'.
2195 SDValue ShiftAmt = DAG.getConstant(MaskedBits, DL, XVT);
2196 SDValue T0 = DAG.getNode(ISD::SHL, DL, XVT, X, ShiftAmt);
2197 SDValue T1 = DAG.getNode(ISD::SRA, DL, XVT, T0, ShiftAmt);
2198 SDValue T2 = DAG.getSetCC(DL, SCCVT, T1, X, NewCond);
2203 /// Try to simplify a setcc built with the specified operands and cc. If it is
2204 /// unable to simplify it, return a null SDValue.
2205 SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
2206 ISD::CondCode Cond, bool foldBooleans,
2207 DAGCombinerInfo &DCI,
2208 const SDLoc &dl) const {
2209 SelectionDAG &DAG = DCI.DAG;
2210 EVT OpVT = N0.getValueType();
2212 // These setcc operations always fold.
2216 case ISD::SETFALSE2: return DAG.getBoolConstant(false, dl, VT, OpVT);
2218 case ISD::SETTRUE2: return DAG.getBoolConstant(true, dl, VT, OpVT);
2221 // Ensure that the constant occurs on the RHS and fold constant comparisons.
2222 // TODO: Handle non-splat vector constants. All undef causes trouble.
2223 ISD::CondCode SwappedCC = ISD::getSetCCSwappedOperands(Cond);
2224 if (isConstOrConstSplat(N0) &&
2225 (DCI.isBeforeLegalizeOps() ||
2226 isCondCodeLegal(SwappedCC, N0.getSimpleValueType())))
2227 return DAG.getSetCC(dl, VT, N1, N0, SwappedCC);
2229 if (auto *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
2230 const APInt &C1 = N1C->getAPIntValue();
2232 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
2233 // equality comparison, then we're just comparing whether X itself is
2235 if (N0.getOpcode() == ISD::SRL && (C1.isNullValue() || C1.isOneValue()) &&
2236 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
2237 N0.getOperand(1).getOpcode() == ISD::Constant) {
2239 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
2240 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2241 ShAmt == Log2_32(N0.getValueSizeInBits())) {
2242 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
2243 // (srl (ctlz x), 5) == 0 -> X != 0
2244 // (srl (ctlz x), 5) != 1 -> X != 0
2247 // (srl (ctlz x), 5) != 0 -> X == 0
2248 // (srl (ctlz x), 5) == 1 -> X == 0
2251 SDValue Zero = DAG.getConstant(0, dl, N0.getValueType());
2252 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
2258 // Look through truncs that don't change the value of a ctpop.
2259 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
2260 CTPOP = N0.getOperand(0);
2262 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
2264 N0.getValueSizeInBits() > Log2_32_Ceil(CTPOP.getValueSizeInBits()))) {
2265 EVT CTVT = CTPOP.getValueType();
2266 SDValue CTOp = CTPOP.getOperand(0);
2268 // (ctpop x) u< 2 -> (x & x-1) == 0
2269 // (ctpop x) u> 1 -> (x & x-1) != 0
2270 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
2271 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
2272 DAG.getConstant(1, dl, CTVT));
2273 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
2274 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
2275 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, dl, CTVT), CC);
2278 // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
2281 // (zext x) == C --> x == (trunc C)
2282 // (sext x) == C --> x == (trunc C)
2283 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2284 DCI.isBeforeLegalize() && N0->hasOneUse()) {
2285 unsigned MinBits = N0.getValueSizeInBits();
2287 bool Signed = false;
2288 if (N0->getOpcode() == ISD::ZERO_EXTEND) {
2290 MinBits = N0->getOperand(0).getValueSizeInBits();
2291 PreExt = N0->getOperand(0);
2292 } else if (N0->getOpcode() == ISD::AND) {
2293 // DAGCombine turns costly ZExts into ANDs
2294 if (auto *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
2295 if ((C->getAPIntValue()+1).isPowerOf2()) {
2296 MinBits = C->getAPIntValue().countTrailingOnes();
2297 PreExt = N0->getOperand(0);
2299 } else if (N0->getOpcode() == ISD::SIGN_EXTEND) {
2301 MinBits = N0->getOperand(0).getValueSizeInBits();
2302 PreExt = N0->getOperand(0);
2304 } else if (auto *LN0 = dyn_cast<LoadSDNode>(N0)) {
2305 // ZEXTLOAD / SEXTLOAD
2306 if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
2307 MinBits = LN0->getMemoryVT().getSizeInBits();
2309 } else if (LN0->getExtensionType() == ISD::SEXTLOAD) {
2311 MinBits = LN0->getMemoryVT().getSizeInBits();
2316 // Figure out how many bits we need to preserve this constant.
2317 unsigned ReqdBits = Signed ?
2318 C1.getBitWidth() - C1.getNumSignBits() + 1 :
2321 // Make sure we're not losing bits from the constant.
2323 MinBits < C1.getBitWidth() &&
2324 MinBits >= ReqdBits) {
2325 EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
2326 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
2327 // Will get folded away.
2328 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreExt);
2329 if (MinBits == 1 && C1 == 1)
2330 // Invert the condition.
2331 return DAG.getSetCC(dl, VT, Trunc, DAG.getConstant(0, dl, MVT::i1),
2332 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2333 SDValue C = DAG.getConstant(C1.trunc(MinBits), dl, MinVT);
2334 return DAG.getSetCC(dl, VT, Trunc, C, Cond);
2337 // If truncating the setcc operands is not desirable, we can still
2338 // simplify the expression in some cases:
2339 // setcc ([sz]ext (setcc x, y, cc)), 0, setne) -> setcc (x, y, cc)
2340 // setcc ([sz]ext (setcc x, y, cc)), 0, seteq) -> setcc (x, y, inv(cc))
2341 // setcc (zext (setcc x, y, cc)), 1, setne) -> setcc (x, y, inv(cc))
2342 // setcc (zext (setcc x, y, cc)), 1, seteq) -> setcc (x, y, cc)
2343 // setcc (sext (setcc x, y, cc)), -1, setne) -> setcc (x, y, inv(cc))
2344 // setcc (sext (setcc x, y, cc)), -1, seteq) -> setcc (x, y, cc)
2345 SDValue TopSetCC = N0->getOperand(0);
2346 unsigned N0Opc = N0->getOpcode();
2347 bool SExt = (N0Opc == ISD::SIGN_EXTEND);
2348 if (TopSetCC.getValueType() == MVT::i1 && VT == MVT::i1 &&
2349 TopSetCC.getOpcode() == ISD::SETCC &&
2350 (N0Opc == ISD::ZERO_EXTEND || N0Opc == ISD::SIGN_EXTEND) &&
2351 (isConstFalseVal(N1C) ||
2352 isExtendedTrueVal(N1C, N0->getValueType(0), SExt))) {
2354 bool Inverse = (N1C->isNullValue() && Cond == ISD::SETEQ) ||
2355 (!N1C->isNullValue() && Cond == ISD::SETNE);
2360 ISD::CondCode InvCond = ISD::getSetCCInverse(
2361 cast<CondCodeSDNode>(TopSetCC.getOperand(2))->get(),
2362 TopSetCC.getOperand(0).getValueType().isInteger());
2363 return DAG.getSetCC(dl, VT, TopSetCC.getOperand(0),
2364 TopSetCC.getOperand(1),
2370 // If the LHS is '(and load, const)', the RHS is 0, the test is for
2371 // equality or unsigned, and all 1 bits of the const are in the same
2372 // partial word, see if we can shorten the load.
2373 if (DCI.isBeforeLegalize() &&
2374 !ISD::isSignedIntSetCC(Cond) &&
2375 N0.getOpcode() == ISD::AND && C1 == 0 &&
2376 N0.getNode()->hasOneUse() &&
2377 isa<LoadSDNode>(N0.getOperand(0)) &&
2378 N0.getOperand(0).getNode()->hasOneUse() &&
2379 isa<ConstantSDNode>(N0.getOperand(1))) {
2380 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
2382 unsigned bestWidth = 0, bestOffset = 0;
2383 if (!Lod->isVolatile() && Lod->isUnindexed()) {
2384 unsigned origWidth = N0.getValueSizeInBits();
2385 unsigned maskWidth = origWidth;
2386 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
2387 // 8 bits, but have to be careful...
2388 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
2389 origWidth = Lod->getMemoryVT().getSizeInBits();
2391 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
2392 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
2393 APInt newMask = APInt::getLowBitsSet(maskWidth, width);
2394 for (unsigned offset=0; offset<origWidth/width; offset++) {
2395 if (Mask.isSubsetOf(newMask)) {
2396 if (DAG.getDataLayout().isLittleEndian())
2397 bestOffset = (uint64_t)offset * (width/8);
2399 bestOffset = (origWidth/width - offset - 1) * (width/8);
2400 bestMask = Mask.lshr(offset * (width/8) * 8);
2409 EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
2410 if (newVT.isRound() &&
2411 shouldReduceLoadWidth(Lod, ISD::NON_EXTLOAD, newVT)) {
2412 EVT PtrType = Lod->getOperand(1).getValueType();
2413 SDValue Ptr = Lod->getBasePtr();
2414 if (bestOffset != 0)
2415 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
2416 DAG.getConstant(bestOffset, dl, PtrType));
2417 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
2418 SDValue NewLoad = DAG.getLoad(
2419 newVT, dl, Lod->getChain(), Ptr,
2420 Lod->getPointerInfo().getWithOffset(bestOffset), NewAlign);
2421 return DAG.getSetCC(dl, VT,
2422 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
2423 DAG.getConstant(bestMask.trunc(bestWidth),
2425 DAG.getConstant(0LL, dl, newVT), Cond);
2430 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
2431 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
2432 unsigned InSize = N0.getOperand(0).getValueSizeInBits();
2434 // If the comparison constant has bits in the upper part, the
2435 // zero-extended value could never match.
2436 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
2437 C1.getBitWidth() - InSize))) {
2442 return DAG.getConstant(0, dl, VT);
2446 return DAG.getConstant(1, dl, VT);
2449 // True if the sign bit of C1 is set.
2450 return DAG.getConstant(C1.isNegative(), dl, VT);
2453 // True if the sign bit of C1 isn't set.
2454 return DAG.getConstant(C1.isNonNegative(), dl, VT);
2460 // Otherwise, we can perform the comparison with the low bits.
2468 EVT newVT = N0.getOperand(0).getValueType();
2469 if (DCI.isBeforeLegalizeOps() ||
2470 (isOperationLegal(ISD::SETCC, newVT) &&
2471 isCondCodeLegal(Cond, newVT.getSimpleVT()))) {
2473 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), newVT);
2474 SDValue NewConst = DAG.getConstant(C1.trunc(InSize), dl, newVT);
2476 SDValue NewSetCC = DAG.getSetCC(dl, NewSetCCVT, N0.getOperand(0),
2478 return DAG.getBoolExtOrTrunc(NewSetCC, dl, VT, N0.getValueType());
2483 break; // todo, be more careful with signed comparisons
2485 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2486 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2487 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
2488 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
2489 EVT ExtDstTy = N0.getValueType();
2490 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
2492 // If the constant doesn't fit into the number of bits for the source of
2493 // the sign extension, it is impossible for both sides to be equal.
2494 if (C1.getMinSignedBits() > ExtSrcTyBits)
2495 return DAG.getConstant(Cond == ISD::SETNE, dl, VT);
2498 EVT Op0Ty = N0.getOperand(0).getValueType();
2499 if (Op0Ty == ExtSrcTy) {
2500 ZextOp = N0.getOperand(0);
2502 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
2503 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
2504 DAG.getConstant(Imm, dl, Op0Ty));
2506 if (!DCI.isCalledByLegalizer())
2507 DCI.AddToWorklist(ZextOp.getNode());
2508 // Otherwise, make this a use of a zext.
2509 return DAG.getSetCC(dl, VT, ZextOp,
2510 DAG.getConstant(C1 & APInt::getLowBitsSet(
2515 } else if ((N1C->isNullValue() || N1C->isOne()) &&
2516 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2517 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
2518 if (N0.getOpcode() == ISD::SETCC &&
2519 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
2520 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (!N1C->isOne());
2522 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
2523 // Invert the condition.
2524 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
2525 CC = ISD::getSetCCInverse(CC,
2526 N0.getOperand(0).getValueType().isInteger());
2527 if (DCI.isBeforeLegalizeOps() ||
2528 isCondCodeLegal(CC, N0.getOperand(0).getSimpleValueType()))
2529 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
2532 if ((N0.getOpcode() == ISD::XOR ||
2533 (N0.getOpcode() == ISD::AND &&
2534 N0.getOperand(0).getOpcode() == ISD::XOR &&
2535 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
2536 isa<ConstantSDNode>(N0.getOperand(1)) &&
2537 cast<ConstantSDNode>(N0.getOperand(1))->isOne()) {
2538 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
2539 // can only do this if the top bits are known zero.
2540 unsigned BitWidth = N0.getValueSizeInBits();
2541 if (DAG.MaskedValueIsZero(N0,
2542 APInt::getHighBitsSet(BitWidth,
2544 // Okay, get the un-inverted input value.
2546 if (N0.getOpcode() == ISD::XOR) {
2547 Val = N0.getOperand(0);
2549 assert(N0.getOpcode() == ISD::AND &&
2550 N0.getOperand(0).getOpcode() == ISD::XOR);
2551 // ((X^1)&1)^1 -> X & 1
2552 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
2553 N0.getOperand(0).getOperand(0),
2557 return DAG.getSetCC(dl, VT, Val, N1,
2558 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2560 } else if (N1C->isOne() &&
2562 getBooleanContents(N0->getValueType(0)) ==
2563 ZeroOrOneBooleanContent)) {
2565 if (Op0.getOpcode() == ISD::TRUNCATE)
2566 Op0 = Op0.getOperand(0);
2568 if ((Op0.getOpcode() == ISD::XOR) &&
2569 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
2570 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
2571 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
2572 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
2573 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
2576 if (Op0.getOpcode() == ISD::AND &&
2577 isa<ConstantSDNode>(Op0.getOperand(1)) &&
2578 cast<ConstantSDNode>(Op0.getOperand(1))->isOne()) {
2579 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
2580 if (Op0.getValueType().bitsGT(VT))
2581 Op0 = DAG.getNode(ISD::AND, dl, VT,
2582 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
2583 DAG.getConstant(1, dl, VT));
2584 else if (Op0.getValueType().bitsLT(VT))
2585 Op0 = DAG.getNode(ISD::AND, dl, VT,
2586 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
2587 DAG.getConstant(1, dl, VT));
2589 return DAG.getSetCC(dl, VT, Op0,
2590 DAG.getConstant(0, dl, Op0.getValueType()),
2591 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2593 if (Op0.getOpcode() == ISD::AssertZext &&
2594 cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1)
2595 return DAG.getSetCC(dl, VT, Op0,
2596 DAG.getConstant(0, dl, Op0.getValueType()),
2597 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2602 optimizeSetCCOfSignedTruncationCheck(VT, N0, N1, Cond, DCI, dl))
2606 // These simplifications apply to splat vectors as well.
2607 // TODO: Handle more splat vector cases.
2608 if (auto *N1C = isConstOrConstSplat(N1)) {
2609 const APInt &C1 = N1C->getAPIntValue();
2611 APInt MinVal, MaxVal;
2612 unsigned OperandBitSize = N1C->getValueType(0).getScalarSizeInBits();
2613 if (ISD::isSignedIntSetCC(Cond)) {
2614 MinVal = APInt::getSignedMinValue(OperandBitSize);
2615 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
2617 MinVal = APInt::getMinValue(OperandBitSize);
2618 MaxVal = APInt::getMaxValue(OperandBitSize);
2621 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
2622 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
2623 // X >= MIN --> true
2625 return DAG.getBoolConstant(true, dl, VT, OpVT);
2627 if (!VT.isVector()) { // TODO: Support this for vectors.
2628 // X >= C0 --> X > (C0 - 1)
2630 ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT;
2631 if ((DCI.isBeforeLegalizeOps() ||
2632 isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
2633 (!N1C->isOpaque() || (C.getBitWidth() <= 64 &&
2634 isLegalICmpImmediate(C.getSExtValue())))) {
2635 return DAG.getSetCC(dl, VT, N0,
2636 DAG.getConstant(C, dl, N1.getValueType()),
2642 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
2643 // X <= MAX --> true
2645 return DAG.getBoolConstant(true, dl, VT, OpVT);
2647 // X <= C0 --> X < (C0 + 1)
2648 if (!VT.isVector()) { // TODO: Support this for vectors.
2650 ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT;
2651 if ((DCI.isBeforeLegalizeOps() ||
2652 isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
2653 (!N1C->isOpaque() || (C.getBitWidth() <= 64 &&
2654 isLegalICmpImmediate(C.getSExtValue())))) {
2655 return DAG.getSetCC(dl, VT, N0,
2656 DAG.getConstant(C, dl, N1.getValueType()),
2662 if (Cond == ISD::SETLT || Cond == ISD::SETULT) {
2664 return DAG.getBoolConstant(false, dl, VT, OpVT); // X < MIN --> false
2666 // TODO: Support this for vectors after legalize ops.
2667 if (!VT.isVector() || DCI.isBeforeLegalizeOps()) {
2668 // Canonicalize setlt X, Max --> setne X, Max
2670 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2672 // If we have setult X, 1, turn it into seteq X, 0
2674 return DAG.getSetCC(dl, VT, N0,
2675 DAG.getConstant(MinVal, dl, N0.getValueType()),
2680 if (Cond == ISD::SETGT || Cond == ISD::SETUGT) {
2682 return DAG.getBoolConstant(false, dl, VT, OpVT); // X > MAX --> false
2684 // TODO: Support this for vectors after legalize ops.
2685 if (!VT.isVector() || DCI.isBeforeLegalizeOps()) {
2686 // Canonicalize setgt X, Min --> setne X, Min
2688 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2690 // If we have setugt X, Max-1, turn it into seteq X, Max
2692 return DAG.getSetCC(dl, VT, N0,
2693 DAG.getConstant(MaxVal, dl, N0.getValueType()),
2698 // If we have "setcc X, C0", check to see if we can shrink the immediate
2700 // TODO: Support this for vectors after legalize ops.
2701 if (!VT.isVector() || DCI.isBeforeLegalizeOps()) {
2702 // SETUGT X, SINTMAX -> SETLT X, 0
2703 if (Cond == ISD::SETUGT &&
2704 C1 == APInt::getSignedMaxValue(OperandBitSize))
2705 return DAG.getSetCC(dl, VT, N0,
2706 DAG.getConstant(0, dl, N1.getValueType()),
2709 // SETULT X, SINTMIN -> SETGT X, -1
2710 if (Cond == ISD::SETULT &&
2711 C1 == APInt::getSignedMinValue(OperandBitSize)) {
2712 SDValue ConstMinusOne =
2713 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), dl,
2715 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
2720 // Back to non-vector simplifications.
2721 // TODO: Can we do these for vector splats?
2722 if (auto *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
2723 const APInt &C1 = N1C->getAPIntValue();
2725 // Fold bit comparisons when we can.
2726 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2727 (VT == N0.getValueType() ||
2728 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
2729 N0.getOpcode() == ISD::AND) {
2730 auto &DL = DAG.getDataLayout();
2731 if (auto *AndRHS = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2732 EVT ShiftTy = getShiftAmountTy(N0.getValueType(), DL,
2733 !DCI.isBeforeLegalize());
2734 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
2735 // Perform the xform if the AND RHS is a single bit.
2736 if (AndRHS->getAPIntValue().isPowerOf2()) {
2737 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2738 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2739 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), dl,
2742 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
2743 // (X & 8) == 8 --> (X & 8) >> 3
2744 // Perform the xform if C1 is a single bit.
2745 if (C1.isPowerOf2()) {
2746 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2747 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2748 DAG.getConstant(C1.logBase2(), dl,
2755 if (C1.getMinSignedBits() <= 64 &&
2756 !isLegalICmpImmediate(C1.getSExtValue())) {
2757 // (X & -256) == 256 -> (X >> 8) == 1
2758 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2759 N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
2760 if (auto *AndRHS = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2761 const APInt &AndRHSC = AndRHS->getAPIntValue();
2762 if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) {
2763 unsigned ShiftBits = AndRHSC.countTrailingZeros();
2764 auto &DL = DAG.getDataLayout();
2765 EVT ShiftTy = getShiftAmountTy(N0.getValueType(), DL,
2766 !DCI.isBeforeLegalize());
2767 EVT CmpTy = N0.getValueType();
2768 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0),
2769 DAG.getConstant(ShiftBits, dl,
2771 SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), dl, CmpTy);
2772 return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
2775 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE ||
2776 Cond == ISD::SETULE || Cond == ISD::SETUGT) {
2777 bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT);
2778 // X < 0x100000000 -> (X >> 32) < 1
2779 // X >= 0x100000000 -> (X >> 32) >= 1
2780 // X <= 0x0ffffffff -> (X >> 32) < 1
2781 // X > 0x0ffffffff -> (X >> 32) >= 1
2784 ISD::CondCode NewCond = Cond;
2786 ShiftBits = C1.countTrailingOnes();
2788 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2790 ShiftBits = C1.countTrailingZeros();
2792 NewC.lshrInPlace(ShiftBits);
2793 if (ShiftBits && NewC.getMinSignedBits() <= 64 &&
2794 isLegalICmpImmediate(NewC.getSExtValue())) {
2795 auto &DL = DAG.getDataLayout();
2796 EVT ShiftTy = getShiftAmountTy(N0.getValueType(), DL,
2797 !DCI.isBeforeLegalize());
2798 EVT CmpTy = N0.getValueType();
2799 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0,
2800 DAG.getConstant(ShiftBits, dl, ShiftTy));
2801 SDValue CmpRHS = DAG.getConstant(NewC, dl, CmpTy);
2802 return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond);
2808 if (isa<ConstantFPSDNode>(N0.getNode())) {
2809 // Constant fold or commute setcc.
2810 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
2811 if (O.getNode()) return O;
2812 } else if (auto *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
2813 // If the RHS of an FP comparison is a constant, simplify it away in
2815 if (CFP->getValueAPF().isNaN()) {
2816 // If an operand is known to be a nan, we can fold it.
2817 switch (ISD::getUnorderedFlavor(Cond)) {
2818 default: llvm_unreachable("Unknown flavor!");
2819 case 0: // Known false.
2820 return DAG.getBoolConstant(false, dl, VT, OpVT);
2821 case 1: // Known true.
2822 return DAG.getBoolConstant(true, dl, VT, OpVT);
2823 case 2: // Undefined.
2824 return DAG.getUNDEF(VT);
2828 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
2829 // constant if knowing that the operand is non-nan is enough. We prefer to
2830 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
2832 if (Cond == ISD::SETO || Cond == ISD::SETUO)
2833 return DAG.getSetCC(dl, VT, N0, N0, Cond);
2835 // setcc (fneg x), C -> setcc swap(pred) x, -C
2836 if (N0.getOpcode() == ISD::FNEG) {
2837 ISD::CondCode SwapCond = ISD::getSetCCSwappedOperands(Cond);
2838 if (DCI.isBeforeLegalizeOps() ||
2839 isCondCodeLegal(SwapCond, N0.getSimpleValueType())) {
2840 SDValue NegN1 = DAG.getNode(ISD::FNEG, dl, N0.getValueType(), N1);
2841 return DAG.getSetCC(dl, VT, N0.getOperand(0), NegN1, SwapCond);
2845 // If the condition is not legal, see if we can find an equivalent one
2847 if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) {
2848 // If the comparison was an awkward floating-point == or != and one of
2849 // the comparison operands is infinity or negative infinity, convert the
2850 // condition to a less-awkward <= or >=.
2851 if (CFP->getValueAPF().isInfinity()) {
2852 if (CFP->getValueAPF().isNegative()) {
2853 if (Cond == ISD::SETOEQ &&
2854 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
2855 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
2856 if (Cond == ISD::SETUEQ &&
2857 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
2858 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
2859 if (Cond == ISD::SETUNE &&
2860 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
2861 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
2862 if (Cond == ISD::SETONE &&
2863 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
2864 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
2866 if (Cond == ISD::SETOEQ &&
2867 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
2868 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
2869 if (Cond == ISD::SETUEQ &&
2870 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
2871 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
2872 if (Cond == ISD::SETUNE &&
2873 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
2874 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
2875 if (Cond == ISD::SETONE &&
2876 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
2877 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
2884 // The sext(setcc()) => setcc() optimization relies on the appropriate
2885 // constant being emitted.
2887 bool EqTrue = ISD::isTrueWhenEqual(Cond);
2889 // We can always fold X == X for integer setcc's.
2890 if (N0.getValueType().isInteger())
2891 return DAG.getBoolConstant(EqTrue, dl, VT, OpVT);
2893 unsigned UOF = ISD::getUnorderedFlavor(Cond);
2894 if (UOF == 2) // FP operators that are undefined on NaNs.
2895 return DAG.getBoolConstant(EqTrue, dl, VT, OpVT);
2896 if (UOF == unsigned(EqTrue))
2897 return DAG.getBoolConstant(EqTrue, dl, VT, OpVT);
2898 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
2899 // if it is not already.
2900 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
2901 if (NewCond != Cond &&
2902 (DCI.isBeforeLegalizeOps() ||
2903 isCondCodeLegal(NewCond, N0.getSimpleValueType())))
2904 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
2907 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2908 N0.getValueType().isInteger()) {
2909 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2910 N0.getOpcode() == ISD::XOR) {
2911 // Simplify (X+Y) == (X+Z) --> Y == Z
2912 if (N0.getOpcode() == N1.getOpcode()) {
2913 if (N0.getOperand(0) == N1.getOperand(0))
2914 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
2915 if (N0.getOperand(1) == N1.getOperand(1))
2916 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
2917 if (isCommutativeBinOp(N0.getOpcode())) {
2918 // If X op Y == Y op X, try other combinations.
2919 if (N0.getOperand(0) == N1.getOperand(1))
2920 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
2922 if (N0.getOperand(1) == N1.getOperand(0))
2923 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
2928 // If RHS is a legal immediate value for a compare instruction, we need
2929 // to be careful about increasing register pressure needlessly.
2930 bool LegalRHSImm = false;
2932 if (auto *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2933 if (auto *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2934 // Turn (X+C1) == C2 --> X == C2-C1
2935 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
2936 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2937 DAG.getConstant(RHSC->getAPIntValue()-
2938 LHSR->getAPIntValue(),
2939 dl, N0.getValueType()), Cond);
2942 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
2943 if (N0.getOpcode() == ISD::XOR)
2944 // If we know that all of the inverted bits are zero, don't bother
2945 // performing the inversion.
2946 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
2948 DAG.getSetCC(dl, VT, N0.getOperand(0),
2949 DAG.getConstant(LHSR->getAPIntValue() ^
2950 RHSC->getAPIntValue(),
2951 dl, N0.getValueType()),
2955 // Turn (C1-X) == C2 --> X == C1-C2
2956 if (auto *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
2957 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
2959 DAG.getSetCC(dl, VT, N0.getOperand(1),
2960 DAG.getConstant(SUBC->getAPIntValue() -
2961 RHSC->getAPIntValue(),
2962 dl, N0.getValueType()),
2967 // Could RHSC fold directly into a compare?
2968 if (RHSC->getValueType(0).getSizeInBits() <= 64)
2969 LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue());
2972 // Simplify (X+Z) == X --> Z == 0
2973 // Don't do this if X is an immediate that can fold into a cmp
2974 // instruction and X+Z has other uses. It could be an induction variable
2975 // chain, and the transform would increase register pressure.
2976 if (!LegalRHSImm || N0.getNode()->hasOneUse()) {
2977 if (N0.getOperand(0) == N1)
2978 return DAG.getSetCC(dl, VT, N0.getOperand(1),
2979 DAG.getConstant(0, dl, N0.getValueType()), Cond);
2980 if (N0.getOperand(1) == N1) {
2981 if (isCommutativeBinOp(N0.getOpcode()))
2982 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2983 DAG.getConstant(0, dl, N0.getValueType()),
2985 if (N0.getNode()->hasOneUse()) {
2986 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2987 auto &DL = DAG.getDataLayout();
2988 // (Z-X) == X --> Z == X<<1
2989 SDValue SH = DAG.getNode(
2990 ISD::SHL, dl, N1.getValueType(), N1,
2991 DAG.getConstant(1, dl,
2992 getShiftAmountTy(N1.getValueType(), DL,
2993 !DCI.isBeforeLegalize())));
2994 if (!DCI.isCalledByLegalizer())
2995 DCI.AddToWorklist(SH.getNode());
2996 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
3002 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
3003 N1.getOpcode() == ISD::XOR) {
3004 // Simplify X == (X+Z) --> Z == 0
3005 if (N1.getOperand(0) == N0)
3006 return DAG.getSetCC(dl, VT, N1.getOperand(1),
3007 DAG.getConstant(0, dl, N1.getValueType()), Cond);
3008 if (N1.getOperand(1) == N0) {
3009 if (isCommutativeBinOp(N1.getOpcode()))
3010 return DAG.getSetCC(dl, VT, N1.getOperand(0),
3011 DAG.getConstant(0, dl, N1.getValueType()), Cond);
3012 if (N1.getNode()->hasOneUse()) {
3013 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
3014 auto &DL = DAG.getDataLayout();
3015 // X == (Z-X) --> X<<1 == Z
3016 SDValue SH = DAG.getNode(
3017 ISD::SHL, dl, N1.getValueType(), N0,
3018 DAG.getConstant(1, dl, getShiftAmountTy(N0.getValueType(), DL,
3019 !DCI.isBeforeLegalize())));
3020 if (!DCI.isCalledByLegalizer())
3021 DCI.AddToWorklist(SH.getNode());
3022 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
3027 if (SDValue V = simplifySetCCWithAnd(VT, N0, N1, Cond, DCI, dl))
3031 // Fold away ALL boolean setcc's.
3033 if (N0.getValueType().getScalarType() == MVT::i1 && foldBooleans) {
3034 EVT OpVT = N0.getValueType();
3036 default: llvm_unreachable("Unknown integer setcc!");
3037 case ISD::SETEQ: // X == Y -> ~(X^Y)
3038 Temp = DAG.getNode(ISD::XOR, dl, OpVT, N0, N1);
3039 N0 = DAG.getNOT(dl, Temp, OpVT);
3040 if (!DCI.isCalledByLegalizer())
3041 DCI.AddToWorklist(Temp.getNode());
3043 case ISD::SETNE: // X != Y --> (X^Y)
3044 N0 = DAG.getNode(ISD::XOR, dl, OpVT, N0, N1);
3046 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
3047 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
3048 Temp = DAG.getNOT(dl, N0, OpVT);
3049 N0 = DAG.getNode(ISD::AND, dl, OpVT, N1, Temp);
3050 if (!DCI.isCalledByLegalizer())
3051 DCI.AddToWorklist(Temp.getNode());
3053 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
3054 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
3055 Temp = DAG.getNOT(dl, N1, OpVT);
3056 N0 = DAG.getNode(ISD::AND, dl, OpVT, N0, Temp);
3057 if (!DCI.isCalledByLegalizer())
3058 DCI.AddToWorklist(Temp.getNode());
3060 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
3061 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
3062 Temp = DAG.getNOT(dl, N0, OpVT);
3063 N0 = DAG.getNode(ISD::OR, dl, OpVT, N1, Temp);
3064 if (!DCI.isCalledByLegalizer())
3065 DCI.AddToWorklist(Temp.getNode());
3067 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
3068 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
3069 Temp = DAG.getNOT(dl, N1, OpVT);
3070 N0 = DAG.getNode(ISD::OR, dl, OpVT, N0, Temp);
3073 if (VT.getScalarType() != MVT::i1) {
3074 if (!DCI.isCalledByLegalizer())
3075 DCI.AddToWorklist(N0.getNode());
3076 // FIXME: If running after legalize, we probably can't do this.
3077 ISD::NodeType ExtendCode = getExtendForContent(getBooleanContents(OpVT));
3078 N0 = DAG.getNode(ExtendCode, dl, VT, N0);
3083 // Could not fold it.
3087 /// Returns true (and the GlobalValue and the offset) if the node is a
3088 /// GlobalAddress + offset.
3089 bool TargetLowering::isGAPlusOffset(SDNode *WN, const GlobalValue *&GA,
3090 int64_t &Offset) const {
3092 SDNode *N = unwrapAddress(SDValue(WN, 0)).getNode();
3094 if (auto *GASD = dyn_cast<GlobalAddressSDNode>(N)) {
3095 GA = GASD->getGlobal();
3096 Offset += GASD->getOffset();
3100 if (N->getOpcode() == ISD::ADD) {
3101 SDValue N1 = N->getOperand(0);
3102 SDValue N2 = N->getOperand(1);
3103 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
3104 if (auto *V = dyn_cast<ConstantSDNode>(N2)) {
3105 Offset += V->getSExtValue();
3108 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
3109 if (auto *V = dyn_cast<ConstantSDNode>(N1)) {
3110 Offset += V->getSExtValue();
3119 SDValue TargetLowering::PerformDAGCombine(SDNode *N,
3120 DAGCombinerInfo &DCI) const {
3121 // Default implementation: no optimization.
3125 //===----------------------------------------------------------------------===//
3126 // Inline Assembler Implementation Methods
3127 //===----------------------------------------------------------------------===//
3129 TargetLowering::ConstraintType
3130 TargetLowering::getConstraintType(StringRef Constraint) const {
3131 unsigned S = Constraint.size();
3134 switch (Constraint[0]) {
3136 case 'r': return C_RegisterClass;
3138 case 'o': // offsetable
3139 case 'V': // not offsetable
3141 case 'i': // Simple Integer or Relocatable Constant
3142 case 'n': // Simple Integer
3143 case 'E': // Floating Point Constant
3144 case 'F': // Floating Point Constant
3145 case 's': // Relocatable Constant
3146 case 'p': // Address.
3147 case 'X': // Allow ANY value.
3148 case 'I': // Target registers.
3162 if (S > 1 && Constraint[0] == '{' && Constraint[S-1] == '}') {
3163 if (S == 8 && Constraint.substr(1, 6) == "memory") // "{memory}"
3170 /// Try to replace an X constraint, which matches anything, with another that
3171 /// has more specific requirements based on the type of the corresponding
3173 const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
3174 if (ConstraintVT.isInteger())
3176 if (ConstraintVT.isFloatingPoint())
3177 return "f"; // works for many targets
3181 /// Lower the specified operand into the Ops vector.
3182 /// If it is invalid, don't add anything to Ops.
3183 void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3184 std::string &Constraint,
3185 std::vector<SDValue> &Ops,
3186 SelectionDAG &DAG) const {
3188 if (Constraint.length() > 1) return;
3190 char ConstraintLetter = Constraint[0];
3191 switch (ConstraintLetter) {
3193 case 'X': // Allows any operand; labels (basic block) use this.
3194 if (Op.getOpcode() == ISD::BasicBlock) {
3199 case 'i': // Simple Integer or Relocatable Constant
3200 case 'n': // Simple Integer
3201 case 's': { // Relocatable Constant
3202 // These operands are interested in values of the form (GV+C), where C may
3203 // be folded in as an offset of GV, or it may be explicitly added. Also, it
3204 // is possible and fine if either GV or C are missing.
3205 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3206 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
3208 // If we have "(add GV, C)", pull out GV/C
3209 if (Op.getOpcode() == ISD::ADD) {
3210 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
3211 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
3213 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
3214 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
3222 // If we find a valid operand, map to the TargetXXX version so that the
3223 // value itself doesn't get selected.
3224 if (GA) { // Either &GV or &GV+C
3225 if (ConstraintLetter != 'n') {
3226 int64_t Offs = GA->getOffset();
3227 if (C) Offs += C->getZExtValue();
3228 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
3229 C ? SDLoc(C) : SDLoc(),
3230 Op.getValueType(), Offs));
3234 if (C) { // just C, no GV.
3235 // Simple constants are not allowed for 's'.
3236 if (ConstraintLetter != 's') {
3237 // gcc prints these as sign extended. Sign extend value to 64 bits
3238 // now; without this it would get ZExt'd later in
3239 // ScheduleDAGSDNodes::EmitNode, which is very generic.
3240 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),
3241 SDLoc(C), MVT::i64));
3250 std::pair<unsigned, const TargetRegisterClass *>
3251 TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *RI,
3252 StringRef Constraint,
3254 if (Constraint.empty() || Constraint[0] != '{')
3255 return std::make_pair(0u, static_cast<TargetRegisterClass*>(nullptr));
3256 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
3258 // Remove the braces from around the name.
3259 StringRef RegName(Constraint.data()+1, Constraint.size()-2);
3261 std::pair<unsigned, const TargetRegisterClass*> R =
3262 std::make_pair(0u, static_cast<const TargetRegisterClass*>(nullptr));
3264 // Figure out which register class contains this reg.
3265 for (const TargetRegisterClass *RC : RI->regclasses()) {
3266 // If none of the value types for this register class are valid, we
3267 // can't use it. For example, 64-bit reg classes on 32-bit targets.
3268 if (!isLegalRC(*RI, *RC))
3271 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
3273 if (RegName.equals_lower(RI->getRegAsmName(*I))) {
3274 std::pair<unsigned, const TargetRegisterClass*> S =
3275 std::make_pair(*I, RC);
3277 // If this register class has the requested value type, return it,
3278 // otherwise keep searching and return the first class found
3279 // if no other is found which explicitly has the requested type.
3280 if (RI->isTypeLegalForClass(*RC, VT))
3291 //===----------------------------------------------------------------------===//
3292 // Constraint Selection.
3294 /// Return true of this is an input operand that is a matching constraint like
3296 bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
3297 assert(!ConstraintCode.empty() && "No known constraint!");
3298 return isdigit(static_cast<unsigned char>(ConstraintCode[0]));
3301 /// If this is an input matching constraint, this method returns the output
3302 /// operand it matches.
3303 unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
3304 assert(!ConstraintCode.empty() && "No known constraint!");
3305 return atoi(ConstraintCode.c_str());
3308 /// Split up the constraint string from the inline assembly value into the
3309 /// specific constraints and their prefixes, and also tie in the associated
3311 /// If this returns an empty vector, and if the constraint string itself
3312 /// isn't empty, there was an error parsing.
3313 TargetLowering::AsmOperandInfoVector
3314 TargetLowering::ParseConstraints(const DataLayout &DL,
3315 const TargetRegisterInfo *TRI,
3316 ImmutableCallSite CS) const {
3317 /// Information about all of the constraints.
3318 AsmOperandInfoVector ConstraintOperands;
3319 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
3320 unsigned maCount = 0; // Largest number of multiple alternative constraints.
3322 // Do a prepass over the constraints, canonicalizing them, and building up the
3323 // ConstraintOperands list.
3324 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
3325 unsigned ResNo = 0; // ResNo - The result number of the next output.
3327 for (InlineAsm::ConstraintInfo &CI : IA->ParseConstraints()) {
3328 ConstraintOperands.emplace_back(std::move(CI));
3329 AsmOperandInfo &OpInfo = ConstraintOperands.back();
3331 // Update multiple alternative constraint count.
3332 if (OpInfo.multipleAlternatives.size() > maCount)
3333 maCount = OpInfo.multipleAlternatives.size();
3335 OpInfo.ConstraintVT = MVT::Other;
3337 // Compute the value type for each operand.
3338 switch (OpInfo.Type) {
3339 case InlineAsm::isOutput:
3340 // Indirect outputs just consume an argument.
3341 if (OpInfo.isIndirect) {
3342 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
3346 // The return value of the call is this value. As such, there is no
3347 // corresponding argument.
3348 assert(!CS.getType()->isVoidTy() &&
3350 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
3351 OpInfo.ConstraintVT =
3352 getSimpleValueType(DL, STy->getElementType(ResNo));
3354 assert(ResNo == 0 && "Asm only has one result!");
3355 OpInfo.ConstraintVT = getSimpleValueType(DL, CS.getType());
3359 case InlineAsm::isInput:
3360 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
3362 case InlineAsm::isClobber:
3367 if (OpInfo.CallOperandVal) {
3368 llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
3369 if (OpInfo.isIndirect) {
3370 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
3372 report_fatal_error("Indirect operand for inline asm not a pointer!");
3373 OpTy = PtrTy->getElementType();
3376 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
3377 if (StructType *STy = dyn_cast<StructType>(OpTy))
3378 if (STy->getNumElements() == 1)
3379 OpTy = STy->getElementType(0);
3381 // If OpTy is not a single value, it may be a struct/union that we
3382 // can tile with integers.
3383 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
3384 unsigned BitSize = DL.getTypeSizeInBits(OpTy);
3393 OpInfo.ConstraintVT =
3394 MVT::getVT(IntegerType::get(OpTy->getContext(), BitSize), true);
3397 } else if (PointerType *PT = dyn_cast<PointerType>(OpTy)) {
3398 unsigned PtrSize = DL.getPointerSizeInBits(PT->getAddressSpace());
3399 OpInfo.ConstraintVT = MVT::getIntegerVT(PtrSize);
3401 OpInfo.ConstraintVT = MVT::getVT(OpTy, true);
3406 // If we have multiple alternative constraints, select the best alternative.
3407 if (!ConstraintOperands.empty()) {
3409 unsigned bestMAIndex = 0;
3410 int bestWeight = -1;
3411 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match.
3414 // Compute the sums of the weights for each alternative, keeping track
3415 // of the best (highest weight) one so far.
3416 for (maIndex = 0; maIndex < maCount; ++maIndex) {
3418 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
3419 cIndex != eIndex; ++cIndex) {
3420 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
3421 if (OpInfo.Type == InlineAsm::isClobber)
3424 // If this is an output operand with a matching input operand,
3425 // look up the matching input. If their types mismatch, e.g. one
3426 // is an integer, the other is floating point, or their sizes are
3427 // different, flag it as an maCantMatch.
3428 if (OpInfo.hasMatchingInput()) {
3429 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
3430 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
3431 if ((OpInfo.ConstraintVT.isInteger() !=
3432 Input.ConstraintVT.isInteger()) ||
3433 (OpInfo.ConstraintVT.getSizeInBits() !=
3434 Input.ConstraintVT.getSizeInBits())) {
3435 weightSum = -1; // Can't match.
3440 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
3445 weightSum += weight;
3448 if (weightSum > bestWeight) {
3449 bestWeight = weightSum;
3450 bestMAIndex = maIndex;
3454 // Now select chosen alternative in each constraint.
3455 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
3456 cIndex != eIndex; ++cIndex) {
3457 AsmOperandInfo& cInfo = ConstraintOperands[cIndex];
3458 if (cInfo.Type == InlineAsm::isClobber)
3460 cInfo.selectAlternative(bestMAIndex);
3465 // Check and hook up tied operands, choose constraint code to use.
3466 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
3467 cIndex != eIndex; ++cIndex) {
3468 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
3470 // If this is an output operand with a matching input operand, look up the
3471 // matching input. If their types mismatch, e.g. one is an integer, the
3472 // other is floating point, or their sizes are different, flag it as an
3474 if (OpInfo.hasMatchingInput()) {
3475 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
3477 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
3478 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
3479 getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
3480 OpInfo.ConstraintVT);
3481 std::pair<unsigned, const TargetRegisterClass *> InputRC =
3482 getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
3483 Input.ConstraintVT);
3484 if ((OpInfo.ConstraintVT.isInteger() !=
3485 Input.ConstraintVT.isInteger()) ||
3486 (MatchRC.second != InputRC.second)) {
3487 report_fatal_error("Unsupported asm: input constraint"
3488 " with a matching output constraint of"
3489 " incompatible type!");
3495 return ConstraintOperands;
3498 /// Return an integer indicating how general CT is.
3499 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
3501 case TargetLowering::C_Other:
3502 case TargetLowering::C_Unknown:
3504 case TargetLowering::C_Register:
3506 case TargetLowering::C_RegisterClass:
3508 case TargetLowering::C_Memory:
3511 llvm_unreachable("Invalid constraint type");
3514 /// Examine constraint type and operand type and determine a weight value.
3515 /// This object must already have been set up with the operand type
3516 /// and the current alternative constraint selected.
3517 TargetLowering::ConstraintWeight
3518 TargetLowering::getMultipleConstraintMatchWeight(
3519 AsmOperandInfo &info, int maIndex) const {
3520 InlineAsm::ConstraintCodeVector *rCodes;
3521 if (maIndex >= (int)info.multipleAlternatives.size())
3522 rCodes = &info.Codes;
3524 rCodes = &info.multipleAlternatives[maIndex].Codes;
3525 ConstraintWeight BestWeight = CW_Invalid;
3527 // Loop over the options, keeping track of the most general one.
3528 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
3529 ConstraintWeight weight =
3530 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
3531 if (weight > BestWeight)
3532 BestWeight = weight;
3538 /// Examine constraint type and operand type and determine a weight value.
3539 /// This object must already have been set up with the operand type
3540 /// and the current alternative constraint selected.
3541 TargetLowering::ConstraintWeight
3542 TargetLowering::getSingleConstraintMatchWeight(
3543 AsmOperandInfo &info, const char *constraint) const {
3544 ConstraintWeight weight = CW_Invalid;
3545 Value *CallOperandVal = info.CallOperandVal;
3546 // If we don't have a value, we can't do a match,
3547 // but allow it at the lowest weight.
3548 if (!CallOperandVal)
3550 // Look at the constraint type.
3551 switch (*constraint) {
3552 case 'i': // immediate integer.
3553 case 'n': // immediate integer with a known value.
3554 if (isa<ConstantInt>(CallOperandVal))
3555 weight = CW_Constant;
3557 case 's': // non-explicit intregal immediate.
3558 if (isa<GlobalValue>(CallOperandVal))
3559 weight = CW_Constant;
3561 case 'E': // immediate float if host format.
3562 case 'F': // immediate float.
3563 if (isa<ConstantFP>(CallOperandVal))
3564 weight = CW_Constant;
3566 case '<': // memory operand with autodecrement.
3567 case '>': // memory operand with autoincrement.
3568 case 'm': // memory operand.
3569 case 'o': // offsettable memory operand
3570 case 'V': // non-offsettable memory operand
3573 case 'r': // general register.
3574 case 'g': // general register, memory operand or immediate integer.
3575 // note: Clang converts "g" to "imr".
3576 if (CallOperandVal->getType()->isIntegerTy())
3577 weight = CW_Register;
3579 case 'X': // any operand.
3581 weight = CW_Default;
3587 /// If there are multiple different constraints that we could pick for this
3588 /// operand (e.g. "imr") try to pick the 'best' one.
3589 /// This is somewhat tricky: constraints fall into four classes:
3590 /// Other -> immediates and magic values
3591 /// Register -> one specific register
3592 /// RegisterClass -> a group of regs
3593 /// Memory -> memory
3594 /// Ideally, we would pick the most specific constraint possible: if we have
3595 /// something that fits into a register, we would pick it. The problem here
3596 /// is that if we have something that could either be in a register or in
3597 /// memory that use of the register could cause selection of *other*
3598 /// operands to fail: they might only succeed if we pick memory. Because of
3599 /// this the heuristic we use is:
3601 /// 1) If there is an 'other' constraint, and if the operand is valid for
3602 /// that constraint, use it. This makes us take advantage of 'i'
3603 /// constraints when available.
3604 /// 2) Otherwise, pick the most general constraint present. This prefers
3605 /// 'm' over 'r', for example.
3607 static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
3608 const TargetLowering &TLI,
3609 SDValue Op, SelectionDAG *DAG) {
3610 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
3611 unsigned BestIdx = 0;
3612 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
3613 int BestGenerality = -1;
3615 // Loop over the options, keeping track of the most general one.
3616 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
3617 TargetLowering::ConstraintType CType =
3618 TLI.getConstraintType(OpInfo.Codes[i]);
3620 // If this is an 'other' constraint, see if the operand is valid for it.
3621 // For example, on X86 we might have an 'rI' constraint. If the operand
3622 // is an integer in the range [0..31] we want to use I (saving a load
3623 // of a register), otherwise we must use 'r'.
3624 if (CType == TargetLowering::C_Other && Op.getNode()) {
3625 assert(OpInfo.Codes[i].size() == 1 &&
3626 "Unhandled multi-letter 'other' constraint");
3627 std::vector<SDValue> ResultOps;
3628 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i],
3630 if (!ResultOps.empty()) {
3637 // Things with matching constraints can only be registers, per gcc
3638 // documentation. This mainly affects "g" constraints.
3639 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
3642 // This constraint letter is more general than the previous one, use it.
3643 int Generality = getConstraintGenerality(CType);
3644 if (Generality > BestGenerality) {
3647 BestGenerality = Generality;
3651 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
3652 OpInfo.ConstraintType = BestType;
3655 /// Determines the constraint code and constraint type to use for the specific
3656 /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
3657 void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
3659 SelectionDAG *DAG) const {
3660 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
3662 // Single-letter constraints ('r') are very common.
3663 if (OpInfo.Codes.size() == 1) {
3664 OpInfo.ConstraintCode = OpInfo.Codes[0];
3665 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
3667 ChooseConstraint(OpInfo, *this, Op, DAG);
3670 // 'X' matches anything.
3671 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
3672 // Labels and constants are handled elsewhere ('X' is the only thing
3673 // that matches labels). For Functions, the type here is the type of
3674 // the result, which is not what we want to look at; leave them alone.
3675 Value *v = OpInfo.CallOperandVal;
3676 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
3677 OpInfo.CallOperandVal = v;
3681 // Otherwise, try to resolve it to something we know about by looking at
3682 // the actual operand type.
3683 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
3684 OpInfo.ConstraintCode = Repl;
3685 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
3690 /// Given an exact SDIV by a constant, create a multiplication
3691 /// with the multiplicative inverse of the constant.
3692 static SDValue BuildExactSDIV(const TargetLowering &TLI, SDNode *N,
3693 const SDLoc &dl, SelectionDAG &DAG,
3694 SmallVectorImpl<SDNode *> &Created) {
3695 SDValue Op0 = N->getOperand(0);
3696 SDValue Op1 = N->getOperand(1);
3697 EVT VT = N->getValueType(0);
3698 EVT SVT = VT.getScalarType();
3699 EVT ShVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
3700 EVT ShSVT = ShVT.getScalarType();
3702 bool UseSRA = false;
3703 SmallVector<SDValue, 16> Shifts, Factors;
3705 auto BuildSDIVPattern = [&](ConstantSDNode *C) {
3706 if (C->isNullValue())
3708 APInt Divisor = C->getAPIntValue();
3709 unsigned Shift = Divisor.countTrailingZeros();
3711 Divisor.ashrInPlace(Shift);
3714 // Calculate the multiplicative inverse, using Newton's method.
3716 APInt Factor = Divisor;
3717 while ((t = Divisor * Factor) != 1)
3718 Factor *= APInt(Divisor.getBitWidth(), 2) - t;
3719 Shifts.push_back(DAG.getConstant(Shift, dl, ShSVT));
3720 Factors.push_back(DAG.getConstant(Factor, dl, SVT));
3724 // Collect all magic values from the build vector.
3725 if (!ISD::matchUnaryPredicate(Op1, BuildSDIVPattern))
3728 SDValue Shift, Factor;
3729 if (VT.isVector()) {
3730 Shift = DAG.getBuildVector(ShVT, dl, Shifts);
3731 Factor = DAG.getBuildVector(VT, dl, Factors);
3734 Factor = Factors[0];
3739 // Shift the value upfront if it is even, so the LSB is one.
3741 // TODO: For UDIV use SRL instead of SRA.
3743 Flags.setExact(true);
3744 Res = DAG.getNode(ISD::SRA, dl, VT, Res, Shift, Flags);
3745 Created.push_back(Res.getNode());
3748 return DAG.getNode(ISD::MUL, dl, VT, Res, Factor);
3751 SDValue TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
3753 SmallVectorImpl<SDNode *> &Created) const {
3754 AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
3755 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3756 if (TLI.isIntDivCheap(N->getValueType(0), Attr))
3757 return SDValue(N,0); // Lower SDIV as SDIV
3761 /// Given an ISD::SDIV node expressing a divide by constant,
3762 /// return a DAG expression to select that will generate the same value by
3763 /// multiplying by a magic number.
3764 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
3765 SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
3766 bool IsAfterLegalization,
3767 SmallVectorImpl<SDNode *> &Created) const {
3769 EVT VT = N->getValueType(0);
3770 EVT SVT = VT.getScalarType();
3771 EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout());
3772 EVT ShSVT = ShVT.getScalarType();
3773 unsigned EltBits = VT.getScalarSizeInBits();
3775 // Check to see if we can do this.
3776 // FIXME: We should be more aggressive here.
3777 if (!isTypeLegal(VT))
3780 // If the sdiv has an 'exact' bit we can use a simpler lowering.
3781 if (N->getFlags().hasExact())
3782 return BuildExactSDIV(*this, N, dl, DAG, Created);
3784 SmallVector<SDValue, 16> MagicFactors, Factors, Shifts, ShiftMasks;
3786 auto BuildSDIVPattern = [&](ConstantSDNode *C) {
3787 if (C->isNullValue())
3790 const APInt &Divisor = C->getAPIntValue();
3791 APInt::ms magics = Divisor.magic();
3792 int NumeratorFactor = 0;
3795 if (Divisor.isOneValue() || Divisor.isAllOnesValue()) {
3796 // If d is +1/-1, we just multiply the numerator by +1/-1.
3797 NumeratorFactor = Divisor.getSExtValue();
3801 } else if (Divisor.isStrictlyPositive() && magics.m.isNegative()) {
3802 // If d > 0 and m < 0, add the numerator.
3803 NumeratorFactor = 1;
3804 } else if (Divisor.isNegative() && magics.m.isStrictlyPositive()) {
3805 // If d < 0 and m > 0, subtract the numerator.
3806 NumeratorFactor = -1;
3809 MagicFactors.push_back(DAG.getConstant(magics.m, dl, SVT));
3810 Factors.push_back(DAG.getConstant(NumeratorFactor, dl, SVT));
3811 Shifts.push_back(DAG.getConstant(magics.s, dl, ShSVT));
3812 ShiftMasks.push_back(DAG.getConstant(ShiftMask, dl, SVT));
3816 SDValue N0 = N->getOperand(0);
3817 SDValue N1 = N->getOperand(1);
3819 // Collect the shifts / magic values from each element.
3820 if (!ISD::matchUnaryPredicate(N1, BuildSDIVPattern))
3823 SDValue MagicFactor, Factor, Shift, ShiftMask;
3824 if (VT.isVector()) {
3825 MagicFactor = DAG.getBuildVector(VT, dl, MagicFactors);
3826 Factor = DAG.getBuildVector(VT, dl, Factors);
3827 Shift = DAG.getBuildVector(ShVT, dl, Shifts);
3828 ShiftMask = DAG.getBuildVector(VT, dl, ShiftMasks);
3830 MagicFactor = MagicFactors[0];
3831 Factor = Factors[0];
3833 ShiftMask = ShiftMasks[0];
3836 // Multiply the numerator (operand 0) by the magic value.
3837 // FIXME: We should support doing a MUL in a wider type.
3839 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT)
3840 : isOperationLegalOrCustom(ISD::MULHS, VT))
3841 Q = DAG.getNode(ISD::MULHS, dl, VT, N0, MagicFactor);
3842 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT)
3843 : isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) {
3845 DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), N0, MagicFactor);
3846 Q = SDValue(LoHi.getNode(), 1);
3848 return SDValue(); // No mulhs or equivalent.
3849 Created.push_back(Q.getNode());
3851 // (Optionally) Add/subtract the numerator using Factor.
3852 Factor = DAG.getNode(ISD::MUL, dl, VT, N0, Factor);
3853 Created.push_back(Factor.getNode());
3854 Q = DAG.getNode(ISD::ADD, dl, VT, Q, Factor);
3855 Created.push_back(Q.getNode());
3857 // Shift right algebraic by shift value.
3858 Q = DAG.getNode(ISD::SRA, dl, VT, Q, Shift);
3859 Created.push_back(Q.getNode());
3861 // Extract the sign bit, mask it and add it to the quotient.
3862 SDValue SignShift = DAG.getConstant(EltBits - 1, dl, ShVT);
3863 SDValue T = DAG.getNode(ISD::SRL, dl, VT, Q, SignShift);
3864 Created.push_back(T.getNode());
3865 T = DAG.getNode(ISD::AND, dl, VT, T, ShiftMask);
3866 Created.push_back(T.getNode());
3867 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
3870 /// Given an ISD::UDIV node expressing a divide by constant,
3871 /// return a DAG expression to select that will generate the same value by
3872 /// multiplying by a magic number.
3873 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
3874 SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
3875 bool IsAfterLegalization,
3876 SmallVectorImpl<SDNode *> &Created) const {
3878 EVT VT = N->getValueType(0);
3879 EVT SVT = VT.getScalarType();
3880 EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout());
3881 EVT ShSVT = ShVT.getScalarType();
3882 unsigned EltBits = VT.getScalarSizeInBits();
3884 // Check to see if we can do this.
3885 // FIXME: We should be more aggressive here.
3886 if (!isTypeLegal(VT))
3889 bool UseNPQ = false;
3890 SmallVector<SDValue, 16> PreShifts, PostShifts, MagicFactors, NPQFactors;
3892 auto BuildUDIVPattern = [&](ConstantSDNode *C) {
3893 if (C->isNullValue())
3895 // FIXME: We should use a narrower constant when the upper
3896 // bits are known to be zero.
3897 APInt Divisor = C->getAPIntValue();
3898 APInt::mu magics = Divisor.magicu();
3899 unsigned PreShift = 0, PostShift = 0;
3901 // If the divisor is even, we can avoid using the expensive fixup by
3902 // shifting the divided value upfront.
3903 if (magics.a != 0 && !Divisor[0]) {
3904 PreShift = Divisor.countTrailingZeros();
3905 // Get magic number for the shifted divisor.
3906 magics = Divisor.lshr(PreShift).magicu(PreShift);
3907 assert(magics.a == 0 && "Should use cheap fixup now");
3910 APInt Magic = magics.m;
3913 if (magics.a == 0 || Divisor.isOneValue()) {
3914 assert(magics.s < Divisor.getBitWidth() &&
3915 "We shouldn't generate an undefined shift!");
3916 PostShift = magics.s;
3919 PostShift = magics.s - 1;
3923 PreShifts.push_back(DAG.getConstant(PreShift, dl, ShSVT));
3924 MagicFactors.push_back(DAG.getConstant(Magic, dl, SVT));
3925 NPQFactors.push_back(
3926 DAG.getConstant(SelNPQ ? APInt::getOneBitSet(EltBits, EltBits - 1)
3927 : APInt::getNullValue(EltBits),
3929 PostShifts.push_back(DAG.getConstant(PostShift, dl, ShSVT));
3934 SDValue N0 = N->getOperand(0);
3935 SDValue N1 = N->getOperand(1);
3937 // Collect the shifts/magic values from each element.
3938 if (!ISD::matchUnaryPredicate(N1, BuildUDIVPattern))
3941 SDValue PreShift, PostShift, MagicFactor, NPQFactor;
3942 if (VT.isVector()) {
3943 PreShift = DAG.getBuildVector(ShVT, dl, PreShifts);
3944 MagicFactor = DAG.getBuildVector(VT, dl, MagicFactors);
3945 NPQFactor = DAG.getBuildVector(VT, dl, NPQFactors);
3946 PostShift = DAG.getBuildVector(ShVT, dl, PostShifts);
3948 PreShift = PreShifts[0];
3949 MagicFactor = MagicFactors[0];
3950 PostShift = PostShifts[0];
3954 Q = DAG.getNode(ISD::SRL, dl, VT, Q, PreShift);
3955 Created.push_back(Q.getNode());
3957 // FIXME: We should support doing a MUL in a wider type.
3958 auto GetMULHU = [&](SDValue X, SDValue Y) {
3959 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT)
3960 : isOperationLegalOrCustom(ISD::MULHU, VT))
3961 return DAG.getNode(ISD::MULHU, dl, VT, X, Y);
3962 if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT)
3963 : isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) {
3965 DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), X, Y);
3966 return SDValue(LoHi.getNode(), 1);
3968 return SDValue(); // No mulhu or equivalent
3971 // Multiply the numerator (operand 0) by the magic value.
3972 Q = GetMULHU(Q, MagicFactor);
3976 Created.push_back(Q.getNode());
3979 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N0, Q);
3980 Created.push_back(NPQ.getNode());
3982 // For vectors we might have a mix of non-NPQ/NPQ paths, so use
3983 // MULHU to act as a SRL-by-1 for NPQ, else multiply by zero.
3985 NPQ = GetMULHU(NPQ, NPQFactor);
3987 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, DAG.getConstant(1, dl, ShVT));
3989 Created.push_back(NPQ.getNode());
3991 Q = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
3992 Created.push_back(Q.getNode());
3995 Q = DAG.getNode(ISD::SRL, dl, VT, Q, PostShift);
3996 Created.push_back(Q.getNode());
3998 SDValue One = DAG.getConstant(1, dl, VT);
3999 SDValue IsOne = DAG.getSetCC(dl, VT, N1, One, ISD::SETEQ);
4000 return DAG.getSelect(dl, VT, IsOne, N0, Q);
4003 bool TargetLowering::
4004 verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const {
4005 if (!isa<ConstantSDNode>(Op.getOperand(0))) {
4006 DAG.getContext()->emitError("argument to '__builtin_return_address' must "
4007 "be a constant integer");
4014 //===----------------------------------------------------------------------===//
4015 // Legalization Utilities
4016 //===----------------------------------------------------------------------===//
4018 bool TargetLowering::expandMUL_LOHI(unsigned Opcode, EVT VT, SDLoc dl,
4019 SDValue LHS, SDValue RHS,
4020 SmallVectorImpl<SDValue> &Result,
4021 EVT HiLoVT, SelectionDAG &DAG,
4022 MulExpansionKind Kind, SDValue LL,
4023 SDValue LH, SDValue RL, SDValue RH) const {
4024 assert(Opcode == ISD::MUL || Opcode == ISD::UMUL_LOHI ||
4025 Opcode == ISD::SMUL_LOHI);
4027 bool HasMULHS = (Kind == MulExpansionKind::Always) ||
4028 isOperationLegalOrCustom(ISD::MULHS, HiLoVT);
4029 bool HasMULHU = (Kind == MulExpansionKind::Always) ||
4030 isOperationLegalOrCustom(ISD::MULHU, HiLoVT);
4031 bool HasSMUL_LOHI = (Kind == MulExpansionKind::Always) ||
4032 isOperationLegalOrCustom(ISD::SMUL_LOHI, HiLoVT);
4033 bool HasUMUL_LOHI = (Kind == MulExpansionKind::Always) ||
4034 isOperationLegalOrCustom(ISD::UMUL_LOHI, HiLoVT);
4036 if (!HasMULHU && !HasMULHS && !HasUMUL_LOHI && !HasSMUL_LOHI)
4039 unsigned OuterBitSize = VT.getScalarSizeInBits();
4040 unsigned InnerBitSize = HiLoVT.getScalarSizeInBits();
4041 unsigned LHSSB = DAG.ComputeNumSignBits(LHS);
4042 unsigned RHSSB = DAG.ComputeNumSignBits(RHS);
4044 // LL, LH, RL, and RH must be either all NULL or all set to a value.
4045 assert((LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) ||
4046 (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode()));
4048 SDVTList VTs = DAG.getVTList(HiLoVT, HiLoVT);
4049 auto MakeMUL_LOHI = [&](SDValue L, SDValue R, SDValue &Lo, SDValue &Hi,
4050 bool Signed) -> bool {
4051 if ((Signed && HasSMUL_LOHI) || (!Signed && HasUMUL_LOHI)) {
4052 Lo = DAG.getNode(Signed ? ISD::SMUL_LOHI : ISD::UMUL_LOHI, dl, VTs, L, R);
4053 Hi = SDValue(Lo.getNode(), 1);
4056 if ((Signed && HasMULHS) || (!Signed && HasMULHU)) {
4057 Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, L, R);
4058 Hi = DAG.getNode(Signed ? ISD::MULHS : ISD::MULHU, dl, HiLoVT, L, R);
4066 if (!LL.getNode() && !RL.getNode() &&
4067 isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) {
4068 LL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LHS);
4069 RL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RHS);
4075 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
4076 if (DAG.MaskedValueIsZero(LHS, HighMask) &&
4077 DAG.MaskedValueIsZero(RHS, HighMask)) {
4078 // The inputs are both zero-extended.
4079 if (MakeMUL_LOHI(LL, RL, Lo, Hi, false)) {
4080 Result.push_back(Lo);
4081 Result.push_back(Hi);
4082 if (Opcode != ISD::MUL) {
4083 SDValue Zero = DAG.getConstant(0, dl, HiLoVT);
4084 Result.push_back(Zero);
4085 Result.push_back(Zero);
4091 if (!VT.isVector() && Opcode == ISD::MUL && LHSSB > InnerBitSize &&
4092 RHSSB > InnerBitSize) {
4093 // The input values are both sign-extended.
4094 // TODO non-MUL case?
4095 if (MakeMUL_LOHI(LL, RL, Lo, Hi, true)) {
4096 Result.push_back(Lo);
4097 Result.push_back(Hi);
4102 unsigned ShiftAmount = OuterBitSize - InnerBitSize;
4103 EVT ShiftAmountTy = getShiftAmountTy(VT, DAG.getDataLayout());
4104 if (APInt::getMaxValue(ShiftAmountTy.getSizeInBits()).ult(ShiftAmount)) {
4105 // FIXME getShiftAmountTy does not always return a sensible result when VT
4106 // is an illegal type, and so the type may be too small to fit the shift
4107 // amount. Override it with i32. The shift will have to be legalized.
4108 ShiftAmountTy = MVT::i32;
4110 SDValue Shift = DAG.getConstant(ShiftAmount, dl, ShiftAmountTy);
4112 if (!LH.getNode() && !RH.getNode() &&
4113 isOperationLegalOrCustom(ISD::SRL, VT) &&
4114 isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) {
4115 LH = DAG.getNode(ISD::SRL, dl, VT, LHS, Shift);
4116 LH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LH);
4117 RH = DAG.getNode(ISD::SRL, dl, VT, RHS, Shift);
4118 RH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RH);
4124 if (!MakeMUL_LOHI(LL, RL, Lo, Hi, false))
4127 Result.push_back(Lo);
4129 if (Opcode == ISD::MUL) {
4130 RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
4131 LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
4132 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH);
4133 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);
4134 Result.push_back(Hi);
4138 // Compute the full width result.
4139 auto Merge = [&](SDValue Lo, SDValue Hi) -> SDValue {
4140 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Lo);
4141 Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Hi);
4142 Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
4143 return DAG.getNode(ISD::OR, dl, VT, Lo, Hi);
4146 SDValue Next = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Hi);
4147 if (!MakeMUL_LOHI(LL, RH, Lo, Hi, false))
4150 // This is effectively the add part of a multiply-add of half-sized operands,
4151 // so it cannot overflow.
4152 Next = DAG.getNode(ISD::ADD, dl, VT, Next, Merge(Lo, Hi));
4154 if (!MakeMUL_LOHI(LH, RL, Lo, Hi, false))
4157 SDValue Zero = DAG.getConstant(0, dl, HiLoVT);
4158 EVT BoolType = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
4160 bool UseGlue = (isOperationLegalOrCustom(ISD::ADDC, VT) &&
4161 isOperationLegalOrCustom(ISD::ADDE, VT));
4163 Next = DAG.getNode(ISD::ADDC, dl, DAG.getVTList(VT, MVT::Glue), Next,
4166 Next = DAG.getNode(ISD::ADDCARRY, dl, DAG.getVTList(VT, BoolType), Next,
4167 Merge(Lo, Hi), DAG.getConstant(0, dl, BoolType));
4169 SDValue Carry = Next.getValue(1);
4170 Result.push_back(DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, Next));
4171 Next = DAG.getNode(ISD::SRL, dl, VT, Next, Shift);
4173 if (!MakeMUL_LOHI(LH, RH, Lo, Hi, Opcode == ISD::SMUL_LOHI))
4177 Hi = DAG.getNode(ISD::ADDE, dl, DAG.getVTList(HiLoVT, MVT::Glue), Hi, Zero,
4180 Hi = DAG.getNode(ISD::ADDCARRY, dl, DAG.getVTList(HiLoVT, BoolType), Hi,
4183 Next = DAG.getNode(ISD::ADD, dl, VT, Next, Merge(Lo, Hi));
4185 if (Opcode == ISD::SMUL_LOHI) {
4186 SDValue NextSub = DAG.getNode(ISD::SUB, dl, VT, Next,
4187 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, RL));
4188 Next = DAG.getSelectCC(dl, LH, Zero, NextSub, Next, ISD::SETLT);
4190 NextSub = DAG.getNode(ISD::SUB, dl, VT, Next,
4191 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, LL));
4192 Next = DAG.getSelectCC(dl, RH, Zero, NextSub, Next, ISD::SETLT);
4195 Result.push_back(DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, Next));
4196 Next = DAG.getNode(ISD::SRL, dl, VT, Next, Shift);
4197 Result.push_back(DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, Next));
4201 bool TargetLowering::expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
4202 SelectionDAG &DAG, MulExpansionKind Kind,
4203 SDValue LL, SDValue LH, SDValue RL,
4205 SmallVector<SDValue, 2> Result;
4206 bool Ok = expandMUL_LOHI(N->getOpcode(), N->getValueType(0), N,
4207 N->getOperand(0), N->getOperand(1), Result, HiLoVT,
4208 DAG, Kind, LL, LH, RL, RH);
4210 assert(Result.size() == 2);
4217 bool TargetLowering::expandFunnelShift(SDNode *Node, SDValue &Result,
4218 SelectionDAG &DAG) const {
4219 EVT VT = Node->getValueType(0);
4221 if (VT.isVector() && (!isOperationLegalOrCustom(ISD::SHL, VT) ||
4222 !isOperationLegalOrCustom(ISD::SRL, VT) ||
4223 !isOperationLegalOrCustom(ISD::SUB, VT) ||
4224 !isOperationLegalOrCustomOrPromote(ISD::OR, VT)))
4227 // fshl: (X << (Z % BW)) | (Y >> (BW - (Z % BW)))
4228 // fshr: (X << (BW - (Z % BW))) | (Y >> (Z % BW))
4229 SDValue X = Node->getOperand(0);
4230 SDValue Y = Node->getOperand(1);
4231 SDValue Z = Node->getOperand(2);
4233 unsigned EltSizeInBits = VT.getScalarSizeInBits();
4234 bool IsFSHL = Node->getOpcode() == ISD::FSHL;
4235 SDLoc DL(SDValue(Node, 0));
4237 EVT ShVT = Z.getValueType();
4238 SDValue BitWidthC = DAG.getConstant(EltSizeInBits, DL, ShVT);
4239 SDValue Zero = DAG.getConstant(0, DL, ShVT);
4242 if (isPowerOf2_32(EltSizeInBits)) {
4243 SDValue Mask = DAG.getConstant(EltSizeInBits - 1, DL, ShVT);
4244 ShAmt = DAG.getNode(ISD::AND, DL, ShVT, Z, Mask);
4246 ShAmt = DAG.getNode(ISD::UREM, DL, ShVT, Z, BitWidthC);
4249 SDValue InvShAmt = DAG.getNode(ISD::SUB, DL, ShVT, BitWidthC, ShAmt);
4250 SDValue ShX = DAG.getNode(ISD::SHL, DL, VT, X, IsFSHL ? ShAmt : InvShAmt);
4251 SDValue ShY = DAG.getNode(ISD::SRL, DL, VT, Y, IsFSHL ? InvShAmt : ShAmt);
4252 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShX, ShY);
4254 // If (Z % BW == 0), then the opposite direction shift is shift-by-bitwidth,
4255 // and that is undefined. We must compare and select to avoid UB.
4256 EVT CCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), ShVT);
4258 // For fshl, 0-shift returns the 1st arg (X).
4259 // For fshr, 0-shift returns the 2nd arg (Y).
4260 SDValue IsZeroShift = DAG.getSetCC(DL, CCVT, ShAmt, Zero, ISD::SETEQ);
4261 Result = DAG.getSelect(DL, VT, IsZeroShift, IsFSHL ? X : Y, Or);
4265 // TODO: Merge with expandFunnelShift.
4266 bool TargetLowering::expandROT(SDNode *Node, SDValue &Result,
4267 SelectionDAG &DAG) const {
4268 EVT VT = Node->getValueType(0);
4269 unsigned EltSizeInBits = VT.getScalarSizeInBits();
4270 bool IsLeft = Node->getOpcode() == ISD::ROTL;
4271 SDValue Op0 = Node->getOperand(0);
4272 SDValue Op1 = Node->getOperand(1);
4273 SDLoc DL(SDValue(Node, 0));
4275 EVT ShVT = Op1.getValueType();
4276 SDValue BitWidthC = DAG.getConstant(EltSizeInBits, DL, ShVT);
4278 // If a rotate in the other direction is legal, use it.
4279 unsigned RevRot = IsLeft ? ISD::ROTR : ISD::ROTL;
4280 if (isOperationLegal(RevRot, VT)) {
4281 SDValue Sub = DAG.getNode(ISD::SUB, DL, ShVT, BitWidthC, Op1);
4282 Result = DAG.getNode(RevRot, DL, VT, Op0, Sub);
4286 if (VT.isVector() && (!isOperationLegalOrCustom(ISD::SHL, VT) ||
4287 !isOperationLegalOrCustom(ISD::SRL, VT) ||
4288 !isOperationLegalOrCustom(ISD::SUB, VT) ||
4289 !isOperationLegalOrCustomOrPromote(ISD::OR, VT) ||
4290 !isOperationLegalOrCustomOrPromote(ISD::AND, VT)))
4294 // (rotl x, c) -> (or (shl x, (and c, w-1)), (srl x, (and w-c, w-1)))
4295 // (rotr x, c) -> (or (srl x, (and c, w-1)), (shl x, (and w-c, w-1)))
4297 assert(isPowerOf2_32(EltSizeInBits) && EltSizeInBits > 1 &&
4298 "Expecting the type bitwidth to be a power of 2");
4299 unsigned ShOpc = IsLeft ? ISD::SHL : ISD::SRL;
4300 unsigned HsOpc = IsLeft ? ISD::SRL : ISD::SHL;
4301 SDValue BitWidthMinusOneC = DAG.getConstant(EltSizeInBits - 1, DL, ShVT);
4302 SDValue NegOp1 = DAG.getNode(ISD::SUB, DL, ShVT, BitWidthC, Op1);
4303 SDValue And0 = DAG.getNode(ISD::AND, DL, ShVT, Op1, BitWidthMinusOneC);
4304 SDValue And1 = DAG.getNode(ISD::AND, DL, ShVT, NegOp1, BitWidthMinusOneC);
4305 Result = DAG.getNode(ISD::OR, DL, VT, DAG.getNode(ShOpc, DL, VT, Op0, And0),
4306 DAG.getNode(HsOpc, DL, VT, Op0, And1));
4310 bool TargetLowering::expandFP_TO_SINT(SDNode *Node, SDValue &Result,
4311 SelectionDAG &DAG) const {
4312 SDValue Src = Node->getOperand(0);
4313 EVT SrcVT = Src.getValueType();
4314 EVT DstVT = Node->getValueType(0);
4315 SDLoc dl(SDValue(Node, 0));
4317 // FIXME: Only f32 to i64 conversions are supported.
4318 if (SrcVT != MVT::f32 || DstVT != MVT::i64)
4321 // Expand f32 -> i64 conversion
4322 // This algorithm comes from compiler-rt's implementation of fixsfdi:
4323 // https://github.com/llvm-mirror/compiler-rt/blob/master/lib/builtins/fixsfdi.c
4324 unsigned SrcEltBits = SrcVT.getScalarSizeInBits();
4325 EVT IntVT = SrcVT.changeTypeToInteger();
4326 EVT IntShVT = getShiftAmountTy(IntVT, DAG.getDataLayout());
4328 SDValue ExponentMask = DAG.getConstant(0x7F800000, dl, IntVT);
4329 SDValue ExponentLoBit = DAG.getConstant(23, dl, IntVT);
4330 SDValue Bias = DAG.getConstant(127, dl, IntVT);
4331 SDValue SignMask = DAG.getConstant(APInt::getSignMask(SrcEltBits), dl, IntVT);
4332 SDValue SignLowBit = DAG.getConstant(SrcEltBits - 1, dl, IntVT);
4333 SDValue MantissaMask = DAG.getConstant(0x007FFFFF, dl, IntVT);
4335 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, IntVT, Src);
4337 SDValue ExponentBits = DAG.getNode(
4338 ISD::SRL, dl, IntVT, DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask),
4339 DAG.getZExtOrTrunc(ExponentLoBit, dl, IntShVT));
4340 SDValue Exponent = DAG.getNode(ISD::SUB, dl, IntVT, ExponentBits, Bias);
4342 SDValue Sign = DAG.getNode(ISD::SRA, dl, IntVT,
4343 DAG.getNode(ISD::AND, dl, IntVT, Bits, SignMask),
4344 DAG.getZExtOrTrunc(SignLowBit, dl, IntShVT));
4345 Sign = DAG.getSExtOrTrunc(Sign, dl, DstVT);
4347 SDValue R = DAG.getNode(ISD::OR, dl, IntVT,
4348 DAG.getNode(ISD::AND, dl, IntVT, Bits, MantissaMask),
4349 DAG.getConstant(0x00800000, dl, IntVT));
4351 R = DAG.getZExtOrTrunc(R, dl, DstVT);
4353 R = DAG.getSelectCC(
4354 dl, Exponent, ExponentLoBit,
4355 DAG.getNode(ISD::SHL, dl, DstVT, R,
4357 DAG.getNode(ISD::SUB, dl, IntVT, Exponent, ExponentLoBit),
4359 DAG.getNode(ISD::SRL, dl, DstVT, R,
4361 DAG.getNode(ISD::SUB, dl, IntVT, ExponentLoBit, Exponent),
4365 SDValue Ret = DAG.getNode(ISD::SUB, dl, DstVT,
4366 DAG.getNode(ISD::XOR, dl, DstVT, R, Sign), Sign);
4368 Result = DAG.getSelectCC(dl, Exponent, DAG.getConstant(0, dl, IntVT),
4369 DAG.getConstant(0, dl, DstVT), Ret, ISD::SETLT);
4373 bool TargetLowering::expandFP_TO_UINT(SDNode *Node, SDValue &Result,
4374 SelectionDAG &DAG) const {
4375 SDLoc dl(SDValue(Node, 0));
4376 SDValue Src = Node->getOperand(0);
4378 EVT SrcVT = Src.getValueType();
4379 EVT DstVT = Node->getValueType(0);
4381 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), SrcVT);
4383 // Only expand vector types if we have the appropriate vector bit operations.
4384 if (DstVT.isVector() && (!isOperationLegalOrCustom(ISD::FP_TO_SINT, DstVT) ||
4385 !isOperationLegalOrCustomOrPromote(ISD::XOR, SrcVT)))
4388 // If the maximum float value is smaller then the signed integer range,
4389 // the destination signmask can't be represented by the float, so we can
4390 // just use FP_TO_SINT directly.
4391 const fltSemantics &APFSem = DAG.EVTToAPFloatSemantics(SrcVT);
4392 APFloat APF(APFSem, APInt::getNullValue(SrcVT.getScalarSizeInBits()));
4393 APInt SignMask = APInt::getSignMask(DstVT.getScalarSizeInBits());
4394 if (APFloat::opOverflow &
4395 APF.convertFromAPInt(SignMask, false, APFloat::rmNearestTiesToEven)) {
4396 Result = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, Src);
4400 SDValue Cst = DAG.getConstantFP(APF, dl, SrcVT);
4401 SDValue Sel = DAG.getSetCC(dl, SetCCVT, Src, Cst, ISD::SETLT);
4403 bool Strict = shouldUseStrictFP_TO_INT(SrcVT, DstVT, /*IsSigned*/ false);
4405 // Expand based on maximum range of FP_TO_SINT, if the value exceeds the
4406 // signmask then offset (the result of which should be fully representable).
4407 // Sel = Src < 0x8000000000000000
4408 // Val = select Sel, Src, Src - 0x8000000000000000
4409 // Ofs = select Sel, 0, 0x8000000000000000
4410 // Result = fp_to_sint(Val) ^ Ofs
4412 // TODO: Should any fast-math-flags be set for the FSUB?
4413 SDValue Val = DAG.getSelect(dl, SrcVT, Sel, Src,
4414 DAG.getNode(ISD::FSUB, dl, SrcVT, Src, Cst));
4415 SDValue Ofs = DAG.getSelect(dl, DstVT, Sel, DAG.getConstant(0, dl, DstVT),
4416 DAG.getConstant(SignMask, dl, DstVT));
4417 Result = DAG.getNode(ISD::XOR, dl, DstVT,
4418 DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, Val), Ofs);
4420 // Expand based on maximum range of FP_TO_SINT:
4421 // True = fp_to_sint(Src)
4422 // False = 0x8000000000000000 + fp_to_sint(Src - 0x8000000000000000)
4423 // Result = select (Src < 0x8000000000000000), True, False
4425 SDValue True = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, Src);
4426 // TODO: Should any fast-math-flags be set for the FSUB?
4427 SDValue False = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT,
4428 DAG.getNode(ISD::FSUB, dl, SrcVT, Src, Cst));
4429 False = DAG.getNode(ISD::XOR, dl, DstVT, False,
4430 DAG.getConstant(SignMask, dl, DstVT));
4431 Result = DAG.getSelect(dl, DstVT, Sel, True, False);
4436 bool TargetLowering::expandUINT_TO_FP(SDNode *Node, SDValue &Result,
4437 SelectionDAG &DAG) const {
4438 SDValue Src = Node->getOperand(0);
4439 EVT SrcVT = Src.getValueType();
4440 EVT DstVT = Node->getValueType(0);
4442 if (SrcVT.getScalarType() != MVT::i64)
4445 SDLoc dl(SDValue(Node, 0));
4446 EVT ShiftVT = getShiftAmountTy(SrcVT, DAG.getDataLayout());
4448 if (DstVT.getScalarType() == MVT::f32) {
4449 // Only expand vector types if we have the appropriate vector bit
4451 if (SrcVT.isVector() &&
4452 (!isOperationLegalOrCustom(ISD::SRL, SrcVT) ||
4453 !isOperationLegalOrCustom(ISD::FADD, DstVT) ||
4454 !isOperationLegalOrCustom(ISD::SINT_TO_FP, SrcVT) ||
4455 !isOperationLegalOrCustomOrPromote(ISD::OR, SrcVT) ||
4456 !isOperationLegalOrCustomOrPromote(ISD::AND, SrcVT)))
4459 // For unsigned conversions, convert them to signed conversions using the
4460 // algorithm from the x86_64 __floatundidf in compiler_rt.
4461 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Src);
4463 SDValue ShiftConst = DAG.getConstant(1, dl, ShiftVT);
4464 SDValue Shr = DAG.getNode(ISD::SRL, dl, SrcVT, Src, ShiftConst);
4465 SDValue AndConst = DAG.getConstant(1, dl, SrcVT);
4466 SDValue And = DAG.getNode(ISD::AND, dl, SrcVT, Src, AndConst);
4467 SDValue Or = DAG.getNode(ISD::OR, dl, SrcVT, And, Shr);
4469 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Or);
4470 SDValue Slow = DAG.getNode(ISD::FADD, dl, DstVT, SignCvt, SignCvt);
4472 // TODO: This really should be implemented using a branch rather than a
4473 // select. We happen to get lucky and machinesink does the right
4474 // thing most of the time. This would be a good candidate for a
4475 // pseudo-op, or, even better, for whole-function isel.
4477 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), SrcVT);
4479 SDValue SignBitTest = DAG.getSetCC(
4480 dl, SetCCVT, Src, DAG.getConstant(0, dl, SrcVT), ISD::SETLT);
4481 Result = DAG.getSelect(dl, DstVT, SignBitTest, Slow, Fast);
4485 if (DstVT.getScalarType() == MVT::f64) {
4486 // Only expand vector types if we have the appropriate vector bit
4488 if (SrcVT.isVector() &&
4489 (!isOperationLegalOrCustom(ISD::SRL, SrcVT) ||
4490 !isOperationLegalOrCustom(ISD::FADD, DstVT) ||
4491 !isOperationLegalOrCustom(ISD::FSUB, DstVT) ||
4492 !isOperationLegalOrCustomOrPromote(ISD::OR, SrcVT) ||
4493 !isOperationLegalOrCustomOrPromote(ISD::AND, SrcVT)))
4496 // Implementation of unsigned i64 to f64 following the algorithm in
4497 // __floatundidf in compiler_rt. This implementation has the advantage
4498 // of performing rounding correctly, both in the default rounding mode
4499 // and in all alternate rounding modes.
4500 SDValue TwoP52 = DAG.getConstant(UINT64_C(0x4330000000000000), dl, SrcVT);
4501 SDValue TwoP84PlusTwoP52 = DAG.getConstantFP(
4502 BitsToDouble(UINT64_C(0x4530000000100000)), dl, DstVT);
4503 SDValue TwoP84 = DAG.getConstant(UINT64_C(0x4530000000000000), dl, SrcVT);
4504 SDValue LoMask = DAG.getConstant(UINT64_C(0x00000000FFFFFFFF), dl, SrcVT);
4505 SDValue HiShift = DAG.getConstant(32, dl, ShiftVT);
4507 SDValue Lo = DAG.getNode(ISD::AND, dl, SrcVT, Src, LoMask);
4508 SDValue Hi = DAG.getNode(ISD::SRL, dl, SrcVT, Src, HiShift);
4509 SDValue LoOr = DAG.getNode(ISD::OR, dl, SrcVT, Lo, TwoP52);
4510 SDValue HiOr = DAG.getNode(ISD::OR, dl, SrcVT, Hi, TwoP84);
4511 SDValue LoFlt = DAG.getBitcast(DstVT, LoOr);
4512 SDValue HiFlt = DAG.getBitcast(DstVT, HiOr);
4513 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, DstVT, HiFlt, TwoP84PlusTwoP52);
4514 Result = DAG.getNode(ISD::FADD, dl, DstVT, LoFlt, HiSub);
4521 SDValue TargetLowering::expandFMINNUM_FMAXNUM(SDNode *Node,
4522 SelectionDAG &DAG) const {
4524 unsigned NewOp = Node->getOpcode() == ISD::FMINNUM ?
4525 ISD::FMINNUM_IEEE : ISD::FMAXNUM_IEEE;
4526 EVT VT = Node->getValueType(0);
4527 if (isOperationLegalOrCustom(NewOp, VT)) {
4528 SDValue Quiet0 = Node->getOperand(0);
4529 SDValue Quiet1 = Node->getOperand(1);
4531 if (!Node->getFlags().hasNoNaNs()) {
4532 // Insert canonicalizes if it's possible we need to quiet to get correct
4534 if (!DAG.isKnownNeverSNaN(Quiet0)) {
4535 Quiet0 = DAG.getNode(ISD::FCANONICALIZE, dl, VT, Quiet0,
4538 if (!DAG.isKnownNeverSNaN(Quiet1)) {
4539 Quiet1 = DAG.getNode(ISD::FCANONICALIZE, dl, VT, Quiet1,
4544 return DAG.getNode(NewOp, dl, VT, Quiet0, Quiet1, Node->getFlags());
4550 bool TargetLowering::expandCTPOP(SDNode *Node, SDValue &Result,
4551 SelectionDAG &DAG) const {
4553 EVT VT = Node->getValueType(0);
4554 EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout());
4555 SDValue Op = Node->getOperand(0);
4556 unsigned Len = VT.getScalarSizeInBits();
4557 assert(VT.isInteger() && "CTPOP not implemented for this type.");
4559 // TODO: Add support for irregular type lengths.
4560 if (!(Len <= 128 && Len % 8 == 0))
4563 // Only expand vector types if we have the appropriate vector bit operations.
4564 if (VT.isVector() && (!isOperationLegalOrCustom(ISD::ADD, VT) ||
4565 !isOperationLegalOrCustom(ISD::SUB, VT) ||
4566 !isOperationLegalOrCustom(ISD::SRL, VT) ||
4567 (Len != 8 && !isOperationLegalOrCustom(ISD::MUL, VT)) ||
4568 !isOperationLegalOrCustomOrPromote(ISD::AND, VT)))
4571 // This is the "best" algorithm from
4572 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
4574 DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), dl, VT);
4576 DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), dl, VT);
4578 DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), dl, VT);
4580 DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x01)), dl, VT);
4582 // v = v - ((v >> 1) & 0x55555555...)
4583 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
4584 DAG.getNode(ISD::AND, dl, VT,
4585 DAG.getNode(ISD::SRL, dl, VT, Op,
4586 DAG.getConstant(1, dl, ShVT)),
4588 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
4589 Op = DAG.getNode(ISD::ADD, dl, VT, DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
4590 DAG.getNode(ISD::AND, dl, VT,
4591 DAG.getNode(ISD::SRL, dl, VT, Op,
4592 DAG.getConstant(2, dl, ShVT)),
4594 // v = (v + (v >> 4)) & 0x0F0F0F0F...
4595 Op = DAG.getNode(ISD::AND, dl, VT,
4596 DAG.getNode(ISD::ADD, dl, VT, Op,
4597 DAG.getNode(ISD::SRL, dl, VT, Op,
4598 DAG.getConstant(4, dl, ShVT))),
4600 // v = (v * 0x01010101...) >> (Len - 8)
4603 DAG.getNode(ISD::SRL, dl, VT, DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
4604 DAG.getConstant(Len - 8, dl, ShVT));
4610 bool TargetLowering::expandCTLZ(SDNode *Node, SDValue &Result,
4611 SelectionDAG &DAG) const {
4613 EVT VT = Node->getValueType(0);
4614 EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout());
4615 SDValue Op = Node->getOperand(0);
4616 unsigned NumBitsPerElt = VT.getScalarSizeInBits();
4618 // If the non-ZERO_UNDEF version is supported we can use that instead.
4619 if (Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF &&
4620 isOperationLegalOrCustom(ISD::CTLZ, VT)) {
4621 Result = DAG.getNode(ISD::CTLZ, dl, VT, Op);
4625 // If the ZERO_UNDEF version is supported use that and handle the zero case.
4626 if (isOperationLegalOrCustom(ISD::CTLZ_ZERO_UNDEF, VT)) {
4628 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
4629 SDValue CTLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, VT, Op);
4630 SDValue Zero = DAG.getConstant(0, dl, VT);
4631 SDValue SrcIsZero = DAG.getSetCC(dl, SetCCVT, Op, Zero, ISD::SETEQ);
4632 Result = DAG.getNode(ISD::SELECT, dl, VT, SrcIsZero,
4633 DAG.getConstant(NumBitsPerElt, dl, VT), CTLZ);
4637 // Only expand vector types if we have the appropriate vector bit operations.
4638 if (VT.isVector() && (!isPowerOf2_32(NumBitsPerElt) ||
4639 !isOperationLegalOrCustom(ISD::CTPOP, VT) ||
4640 !isOperationLegalOrCustom(ISD::SRL, VT) ||
4641 !isOperationLegalOrCustomOrPromote(ISD::OR, VT)))
4644 // for now, we do this:
4645 // x = x | (x >> 1);
4646 // x = x | (x >> 2);
4648 // x = x | (x >>16);
4649 // x = x | (x >>32); // for 64-bit input
4650 // return popcount(~x);
4652 // Ref: "Hacker's Delight" by Henry Warren
4653 for (unsigned i = 0; (1U << i) <= (NumBitsPerElt / 2); ++i) {
4654 SDValue Tmp = DAG.getConstant(1ULL << i, dl, ShVT);
4655 Op = DAG.getNode(ISD::OR, dl, VT, Op,
4656 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp));
4658 Op = DAG.getNOT(dl, Op, VT);
4659 Result = DAG.getNode(ISD::CTPOP, dl, VT, Op);
4663 bool TargetLowering::expandCTTZ(SDNode *Node, SDValue &Result,
4664 SelectionDAG &DAG) const {
4666 EVT VT = Node->getValueType(0);
4667 SDValue Op = Node->getOperand(0);
4668 unsigned NumBitsPerElt = VT.getScalarSizeInBits();
4670 // If the non-ZERO_UNDEF version is supported we can use that instead.
4671 if (Node->getOpcode() == ISD::CTTZ_ZERO_UNDEF &&
4672 isOperationLegalOrCustom(ISD::CTTZ, VT)) {
4673 Result = DAG.getNode(ISD::CTTZ, dl, VT, Op);
4677 // If the ZERO_UNDEF version is supported use that and handle the zero case.
4678 if (isOperationLegalOrCustom(ISD::CTTZ_ZERO_UNDEF, VT)) {
4680 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
4681 SDValue CTTZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, VT, Op);
4682 SDValue Zero = DAG.getConstant(0, dl, VT);
4683 SDValue SrcIsZero = DAG.getSetCC(dl, SetCCVT, Op, Zero, ISD::SETEQ);
4684 Result = DAG.getNode(ISD::SELECT, dl, VT, SrcIsZero,
4685 DAG.getConstant(NumBitsPerElt, dl, VT), CTTZ);
4689 // Only expand vector types if we have the appropriate vector bit operations.
4690 if (VT.isVector() && (!isPowerOf2_32(NumBitsPerElt) ||
4691 (!isOperationLegalOrCustom(ISD::CTPOP, VT) &&
4692 !isOperationLegalOrCustom(ISD::CTLZ, VT)) ||
4693 !isOperationLegalOrCustom(ISD::SUB, VT) ||
4694 !isOperationLegalOrCustomOrPromote(ISD::AND, VT) ||
4695 !isOperationLegalOrCustomOrPromote(ISD::XOR, VT)))
4698 // for now, we use: { return popcount(~x & (x - 1)); }
4699 // unless the target has ctlz but not ctpop, in which case we use:
4700 // { return 32 - nlz(~x & (x-1)); }
4701 // Ref: "Hacker's Delight" by Henry Warren
4702 SDValue Tmp = DAG.getNode(
4703 ISD::AND, dl, VT, DAG.getNOT(dl, Op, VT),
4704 DAG.getNode(ISD::SUB, dl, VT, Op, DAG.getConstant(1, dl, VT)));
4706 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
4707 if (isOperationLegal(ISD::CTLZ, VT) && !isOperationLegal(ISD::CTPOP, VT)) {
4709 DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(NumBitsPerElt, dl, VT),
4710 DAG.getNode(ISD::CTLZ, dl, VT, Tmp));
4714 Result = DAG.getNode(ISD::CTPOP, dl, VT, Tmp);
4718 bool TargetLowering::expandABS(SDNode *N, SDValue &Result,
4719 SelectionDAG &DAG) const {
4721 EVT VT = N->getValueType(0);
4722 EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout());
4723 SDValue Op = N->getOperand(0);
4725 // Only expand vector types if we have the appropriate vector operations.
4726 if (VT.isVector() && (!isOperationLegalOrCustom(ISD::SRA, VT) ||
4727 !isOperationLegalOrCustom(ISD::ADD, VT) ||
4728 !isOperationLegalOrCustomOrPromote(ISD::XOR, VT)))
4732 DAG.getNode(ISD::SRA, dl, VT, Op,
4733 DAG.getConstant(VT.getScalarSizeInBits() - 1, dl, ShVT));
4734 SDValue Add = DAG.getNode(ISD::ADD, dl, VT, Op, Shift);
4735 Result = DAG.getNode(ISD::XOR, dl, VT, Add, Shift);
4739 SDValue TargetLowering::scalarizeVectorLoad(LoadSDNode *LD,
4740 SelectionDAG &DAG) const {
4742 SDValue Chain = LD->getChain();
4743 SDValue BasePTR = LD->getBasePtr();
4744 EVT SrcVT = LD->getMemoryVT();
4745 ISD::LoadExtType ExtType = LD->getExtensionType();
4747 unsigned NumElem = SrcVT.getVectorNumElements();
4749 EVT SrcEltVT = SrcVT.getScalarType();
4750 EVT DstEltVT = LD->getValueType(0).getScalarType();
4752 unsigned Stride = SrcEltVT.getSizeInBits() / 8;
4753 assert(SrcEltVT.isByteSized());
4755 SmallVector<SDValue, 8> Vals;
4756 SmallVector<SDValue, 8> LoadChains;
4758 for (unsigned Idx = 0; Idx < NumElem; ++Idx) {
4759 SDValue ScalarLoad =
4760 DAG.getExtLoad(ExtType, SL, DstEltVT, Chain, BasePTR,
4761 LD->getPointerInfo().getWithOffset(Idx * Stride),
4762 SrcEltVT, MinAlign(LD->getAlignment(), Idx * Stride),
4763 LD->getMemOperand()->getFlags(), LD->getAAInfo());
4765 BasePTR = DAG.getObjectPtrOffset(SL, BasePTR, Stride);
4767 Vals.push_back(ScalarLoad.getValue(0));
4768 LoadChains.push_back(ScalarLoad.getValue(1));
4771 SDValue NewChain = DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoadChains);
4772 SDValue Value = DAG.getBuildVector(LD->getValueType(0), SL, Vals);
4774 return DAG.getMergeValues({ Value, NewChain }, SL);
4777 SDValue TargetLowering::scalarizeVectorStore(StoreSDNode *ST,
4778 SelectionDAG &DAG) const {
4781 SDValue Chain = ST->getChain();
4782 SDValue BasePtr = ST->getBasePtr();
4783 SDValue Value = ST->getValue();
4784 EVT StVT = ST->getMemoryVT();
4786 // The type of the data we want to save
4787 EVT RegVT = Value.getValueType();
4788 EVT RegSclVT = RegVT.getScalarType();
4790 // The type of data as saved in memory.
4791 EVT MemSclVT = StVT.getScalarType();
4793 EVT IdxVT = getVectorIdxTy(DAG.getDataLayout());
4794 unsigned NumElem = StVT.getVectorNumElements();
4796 // A vector must always be stored in memory as-is, i.e. without any padding
4797 // between the elements, since various code depend on it, e.g. in the
4798 // handling of a bitcast of a vector type to int, which may be done with a
4799 // vector store followed by an integer load. A vector that does not have
4800 // elements that are byte-sized must therefore be stored as an integer
4801 // built out of the extracted vector elements.
4802 if (!MemSclVT.isByteSized()) {
4803 unsigned NumBits = StVT.getSizeInBits();
4804 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), NumBits);
4806 SDValue CurrVal = DAG.getConstant(0, SL, IntVT);
4808 for (unsigned Idx = 0; Idx < NumElem; ++Idx) {
4809 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, RegSclVT, Value,
4810 DAG.getConstant(Idx, SL, IdxVT));
4811 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, MemSclVT, Elt);
4812 SDValue ExtElt = DAG.getNode(ISD::ZERO_EXTEND, SL, IntVT, Trunc);
4813 unsigned ShiftIntoIdx =
4814 (DAG.getDataLayout().isBigEndian() ? (NumElem - 1) - Idx : Idx);
4815 SDValue ShiftAmount =
4816 DAG.getConstant(ShiftIntoIdx * MemSclVT.getSizeInBits(), SL, IntVT);
4817 SDValue ShiftedElt =
4818 DAG.getNode(ISD::SHL, SL, IntVT, ExtElt, ShiftAmount);
4819 CurrVal = DAG.getNode(ISD::OR, SL, IntVT, CurrVal, ShiftedElt);
4822 return DAG.getStore(Chain, SL, CurrVal, BasePtr, ST->getPointerInfo(),
4823 ST->getAlignment(), ST->getMemOperand()->getFlags(),
4827 // Store Stride in bytes
4828 unsigned Stride = MemSclVT.getSizeInBits() / 8;
4829 assert (Stride && "Zero stride!");
4830 // Extract each of the elements from the original vector and save them into
4831 // memory individually.
4832 SmallVector<SDValue, 8> Stores;
4833 for (unsigned Idx = 0; Idx < NumElem; ++Idx) {
4834 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, RegSclVT, Value,
4835 DAG.getConstant(Idx, SL, IdxVT));
4837 SDValue Ptr = DAG.getObjectPtrOffset(SL, BasePtr, Idx * Stride);
4839 // This scalar TruncStore may be illegal, but we legalize it later.
4840 SDValue Store = DAG.getTruncStore(
4841 Chain, SL, Elt, Ptr, ST->getPointerInfo().getWithOffset(Idx * Stride),
4842 MemSclVT, MinAlign(ST->getAlignment(), Idx * Stride),
4843 ST->getMemOperand()->getFlags(), ST->getAAInfo());
4845 Stores.push_back(Store);
4848 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Stores);
4851 std::pair<SDValue, SDValue>
4852 TargetLowering::expandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG) const {
4853 assert(LD->getAddressingMode() == ISD::UNINDEXED &&
4854 "unaligned indexed loads not implemented!");
4855 SDValue Chain = LD->getChain();
4856 SDValue Ptr = LD->getBasePtr();
4857 EVT VT = LD->getValueType(0);
4858 EVT LoadedVT = LD->getMemoryVT();
4860 auto &MF = DAG.getMachineFunction();
4862 if (VT.isFloatingPoint() || VT.isVector()) {
4863 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
4864 if (isTypeLegal(intVT) && isTypeLegal(LoadedVT)) {
4865 if (!isOperationLegalOrCustom(ISD::LOAD, intVT) &&
4866 LoadedVT.isVector()) {
4867 // Scalarize the load and let the individual components be handled.
4868 SDValue Scalarized = scalarizeVectorLoad(LD, DAG);
4869 if (Scalarized->getOpcode() == ISD::MERGE_VALUES)
4870 return std::make_pair(Scalarized.getOperand(0), Scalarized.getOperand(1));
4871 return std::make_pair(Scalarized.getValue(0), Scalarized.getValue(1));
4874 // Expand to a (misaligned) integer load of the same size,
4875 // then bitconvert to floating point or vector.
4876 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr,
4877 LD->getMemOperand());
4878 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
4880 Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND :
4881 ISD::ANY_EXTEND, dl, VT, Result);
4883 return std::make_pair(Result, newLoad.getValue(1));
4886 // Copy the value to a (aligned) stack slot using (unaligned) integer
4887 // loads and stores, then do a (aligned) load from the stack slot.
4888 MVT RegVT = getRegisterType(*DAG.getContext(), intVT);
4889 unsigned LoadedBytes = LoadedVT.getStoreSize();
4890 unsigned RegBytes = RegVT.getSizeInBits() / 8;
4891 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
4893 // Make sure the stack slot is also aligned for the register type.
4894 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
4895 auto FrameIndex = cast<FrameIndexSDNode>(StackBase.getNode())->getIndex();
4896 SmallVector<SDValue, 8> Stores;
4897 SDValue StackPtr = StackBase;
4898 unsigned Offset = 0;
4900 EVT PtrVT = Ptr.getValueType();
4901 EVT StackPtrVT = StackPtr.getValueType();
4903 SDValue PtrIncrement = DAG.getConstant(RegBytes, dl, PtrVT);
4904 SDValue StackPtrIncrement = DAG.getConstant(RegBytes, dl, StackPtrVT);
4906 // Do all but one copies using the full register width.
4907 for (unsigned i = 1; i < NumRegs; i++) {
4908 // Load one integer register's worth from the original location.
4909 SDValue Load = DAG.getLoad(
4910 RegVT, dl, Chain, Ptr, LD->getPointerInfo().getWithOffset(Offset),
4911 MinAlign(LD->getAlignment(), Offset), LD->getMemOperand()->getFlags(),
4913 // Follow the load with a store to the stack slot. Remember the store.
4914 Stores.push_back(DAG.getStore(
4915 Load.getValue(1), dl, Load, StackPtr,
4916 MachinePointerInfo::getFixedStack(MF, FrameIndex, Offset)));
4917 // Increment the pointers.
4920 Ptr = DAG.getObjectPtrOffset(dl, Ptr, PtrIncrement);
4921 StackPtr = DAG.getObjectPtrOffset(dl, StackPtr, StackPtrIncrement);
4924 // The last copy may be partial. Do an extending load.
4925 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
4926 8 * (LoadedBytes - Offset));
4928 DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
4929 LD->getPointerInfo().getWithOffset(Offset), MemVT,
4930 MinAlign(LD->getAlignment(), Offset),
4931 LD->getMemOperand()->getFlags(), LD->getAAInfo());
4932 // Follow the load with a store to the stack slot. Remember the store.
4933 // On big-endian machines this requires a truncating store to ensure
4934 // that the bits end up in the right place.
4935 Stores.push_back(DAG.getTruncStore(
4936 Load.getValue(1), dl, Load, StackPtr,
4937 MachinePointerInfo::getFixedStack(MF, FrameIndex, Offset), MemVT));
4939 // The order of the stores doesn't matter - say it with a TokenFactor.
4940 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
4942 // Finally, perform the original load only redirected to the stack slot.
4943 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
4944 MachinePointerInfo::getFixedStack(MF, FrameIndex, 0),
4947 // Callers expect a MERGE_VALUES node.
4948 return std::make_pair(Load, TF);
4951 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
4952 "Unaligned load of unsupported type.");
4954 // Compute the new VT that is half the size of the old one. This is an
4956 unsigned NumBits = LoadedVT.getSizeInBits();
4958 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
4961 unsigned Alignment = LD->getAlignment();
4962 unsigned IncrementSize = NumBits / 8;
4963 ISD::LoadExtType HiExtType = LD->getExtensionType();
4965 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
4966 if (HiExtType == ISD::NON_EXTLOAD)
4967 HiExtType = ISD::ZEXTLOAD;
4969 // Load the value in two parts
4971 if (DAG.getDataLayout().isLittleEndian()) {
4972 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
4973 NewLoadedVT, Alignment, LD->getMemOperand()->getFlags(),
4976 Ptr = DAG.getObjectPtrOffset(dl, Ptr, IncrementSize);
4977 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
4978 LD->getPointerInfo().getWithOffset(IncrementSize),
4979 NewLoadedVT, MinAlign(Alignment, IncrementSize),
4980 LD->getMemOperand()->getFlags(), LD->getAAInfo());
4982 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
4983 NewLoadedVT, Alignment, LD->getMemOperand()->getFlags(),
4986 Ptr = DAG.getObjectPtrOffset(dl, Ptr, IncrementSize);
4987 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
4988 LD->getPointerInfo().getWithOffset(IncrementSize),
4989 NewLoadedVT, MinAlign(Alignment, IncrementSize),
4990 LD->getMemOperand()->getFlags(), LD->getAAInfo());
4993 // aggregate the two parts
4994 SDValue ShiftAmount =
4995 DAG.getConstant(NumBits, dl, getShiftAmountTy(Hi.getValueType(),
4996 DAG.getDataLayout()));
4997 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
4998 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
5000 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
5003 return std::make_pair(Result, TF);
5006 SDValue TargetLowering::expandUnalignedStore(StoreSDNode *ST,
5007 SelectionDAG &DAG) const {
5008 assert(ST->getAddressingMode() == ISD::UNINDEXED &&
5009 "unaligned indexed stores not implemented!");
5010 SDValue Chain = ST->getChain();
5011 SDValue Ptr = ST->getBasePtr();
5012 SDValue Val = ST->getValue();
5013 EVT VT = Val.getValueType();
5014 int Alignment = ST->getAlignment();
5015 auto &MF = DAG.getMachineFunction();
5016 EVT MemVT = ST->getMemoryVT();
5019 if (MemVT.isFloatingPoint() || MemVT.isVector()) {
5020 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
5021 if (isTypeLegal(intVT)) {
5022 if (!isOperationLegalOrCustom(ISD::STORE, intVT) &&
5024 // Scalarize the store and let the individual components be handled.
5025 SDValue Result = scalarizeVectorStore(ST, DAG);
5029 // Expand to a bitconvert of the value to the integer type of the
5030 // same size, then a (misaligned) int store.
5031 // FIXME: Does not handle truncating floating point stores!
5032 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
5033 Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
5034 Alignment, ST->getMemOperand()->getFlags());
5037 // Do a (aligned) store to a stack slot, then copy from the stack slot
5038 // to the final destination using (unaligned) integer loads and stores.
5039 EVT StoredVT = ST->getMemoryVT();
5041 getRegisterType(*DAG.getContext(),
5042 EVT::getIntegerVT(*DAG.getContext(),
5043 StoredVT.getSizeInBits()));
5044 EVT PtrVT = Ptr.getValueType();
5045 unsigned StoredBytes = StoredVT.getStoreSize();
5046 unsigned RegBytes = RegVT.getSizeInBits() / 8;
5047 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
5049 // Make sure the stack slot is also aligned for the register type.
5050 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
5051 auto FrameIndex = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
5053 // Perform the original store, only redirected to the stack slot.
5054 SDValue Store = DAG.getTruncStore(
5055 Chain, dl, Val, StackPtr,
5056 MachinePointerInfo::getFixedStack(MF, FrameIndex, 0), StoredVT);
5058 EVT StackPtrVT = StackPtr.getValueType();
5060 SDValue PtrIncrement = DAG.getConstant(RegBytes, dl, PtrVT);
5061 SDValue StackPtrIncrement = DAG.getConstant(RegBytes, dl, StackPtrVT);
5062 SmallVector<SDValue, 8> Stores;
5063 unsigned Offset = 0;
5065 // Do all but one copies using the full register width.
5066 for (unsigned i = 1; i < NumRegs; i++) {
5067 // Load one integer register's worth from the stack slot.
5068 SDValue Load = DAG.getLoad(
5069 RegVT, dl, Store, StackPtr,
5070 MachinePointerInfo::getFixedStack(MF, FrameIndex, Offset));
5071 // Store it to the final location. Remember the store.
5072 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
5073 ST->getPointerInfo().getWithOffset(Offset),
5074 MinAlign(ST->getAlignment(), Offset),
5075 ST->getMemOperand()->getFlags()));
5076 // Increment the pointers.
5078 StackPtr = DAG.getObjectPtrOffset(dl, StackPtr, StackPtrIncrement);
5079 Ptr = DAG.getObjectPtrOffset(dl, Ptr, PtrIncrement);
5082 // The last store may be partial. Do a truncating store. On big-endian
5083 // machines this requires an extending load from the stack slot to ensure
5084 // that the bits are in the right place.
5085 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
5086 8 * (StoredBytes - Offset));
5088 // Load from the stack slot.
5089 SDValue Load = DAG.getExtLoad(
5090 ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
5091 MachinePointerInfo::getFixedStack(MF, FrameIndex, Offset), MemVT);
5094 DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
5095 ST->getPointerInfo().getWithOffset(Offset), MemVT,
5096 MinAlign(ST->getAlignment(), Offset),
5097 ST->getMemOperand()->getFlags(), ST->getAAInfo()));
5098 // The order of the stores doesn't matter - say it with a TokenFactor.
5099 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
5103 assert(ST->getMemoryVT().isInteger() &&
5104 !ST->getMemoryVT().isVector() &&
5105 "Unaligned store of unknown type.");
5106 // Get the half-size VT
5107 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
5108 int NumBits = NewStoredVT.getSizeInBits();
5109 int IncrementSize = NumBits / 8;
5111 // Divide the stored value in two parts.
5112 SDValue ShiftAmount =
5113 DAG.getConstant(NumBits, dl, getShiftAmountTy(Val.getValueType(),
5114 DAG.getDataLayout()));
5116 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
5118 // Store the two parts
5119 SDValue Store1, Store2;
5120 Store1 = DAG.getTruncStore(Chain, dl,
5121 DAG.getDataLayout().isLittleEndian() ? Lo : Hi,
5122 Ptr, ST->getPointerInfo(), NewStoredVT, Alignment,
5123 ST->getMemOperand()->getFlags());
5125 Ptr = DAG.getObjectPtrOffset(dl, Ptr, IncrementSize);
5126 Alignment = MinAlign(Alignment, IncrementSize);
5127 Store2 = DAG.getTruncStore(
5128 Chain, dl, DAG.getDataLayout().isLittleEndian() ? Hi : Lo, Ptr,
5129 ST->getPointerInfo().getWithOffset(IncrementSize), NewStoredVT, Alignment,
5130 ST->getMemOperand()->getFlags(), ST->getAAInfo());
5133 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
5138 TargetLowering::IncrementMemoryAddress(SDValue Addr, SDValue Mask,
5139 const SDLoc &DL, EVT DataVT,
5141 bool IsCompressedMemory) const {
5143 EVT AddrVT = Addr.getValueType();
5144 EVT MaskVT = Mask.getValueType();
5145 assert(DataVT.getVectorNumElements() == MaskVT.getVectorNumElements() &&
5146 "Incompatible types of Data and Mask");
5147 if (IsCompressedMemory) {
5148 // Incrementing the pointer according to number of '1's in the mask.
5149 EVT MaskIntVT = EVT::getIntegerVT(*DAG.getContext(), MaskVT.getSizeInBits());
5150 SDValue MaskInIntReg = DAG.getBitcast(MaskIntVT, Mask);
5151 if (MaskIntVT.getSizeInBits() < 32) {
5152 MaskInIntReg = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, MaskInIntReg);
5153 MaskIntVT = MVT::i32;
5156 // Count '1's with POPCNT.
5157 Increment = DAG.getNode(ISD::CTPOP, DL, MaskIntVT, MaskInIntReg);
5158 Increment = DAG.getZExtOrTrunc(Increment, DL, AddrVT);
5159 // Scale is an element size in bytes.
5160 SDValue Scale = DAG.getConstant(DataVT.getScalarSizeInBits() / 8, DL,
5162 Increment = DAG.getNode(ISD::MUL, DL, AddrVT, Increment, Scale);
5164 Increment = DAG.getConstant(DataVT.getStoreSize(), DL, AddrVT);
5166 return DAG.getNode(ISD::ADD, DL, AddrVT, Addr, Increment);
5169 static SDValue clampDynamicVectorIndex(SelectionDAG &DAG,
5173 if (isa<ConstantSDNode>(Idx))
5176 EVT IdxVT = Idx.getValueType();
5177 unsigned NElts = VecVT.getVectorNumElements();
5178 if (isPowerOf2_32(NElts)) {
5179 APInt Imm = APInt::getLowBitsSet(IdxVT.getSizeInBits(),
5181 return DAG.getNode(ISD::AND, dl, IdxVT, Idx,
5182 DAG.getConstant(Imm, dl, IdxVT));
5185 return DAG.getNode(ISD::UMIN, dl, IdxVT, Idx,
5186 DAG.getConstant(NElts - 1, dl, IdxVT));
5189 SDValue TargetLowering::getVectorElementPointer(SelectionDAG &DAG,
5190 SDValue VecPtr, EVT VecVT,
5191 SDValue Index) const {
5193 // Make sure the index type is big enough to compute in.
5194 Index = DAG.getZExtOrTrunc(Index, dl, VecPtr.getValueType());
5196 EVT EltVT = VecVT.getVectorElementType();
5198 // Calculate the element offset and add it to the pointer.
5199 unsigned EltSize = EltVT.getSizeInBits() / 8; // FIXME: should be ABI size.
5200 assert(EltSize * 8 == EltVT.getSizeInBits() &&
5201 "Converting bits to bytes lost precision");
5203 Index = clampDynamicVectorIndex(DAG, Index, VecVT, dl);
5205 EVT IdxVT = Index.getValueType();
5207 Index = DAG.getNode(ISD::MUL, dl, IdxVT, Index,
5208 DAG.getConstant(EltSize, dl, IdxVT));
5209 return DAG.getNode(ISD::ADD, dl, IdxVT, VecPtr, Index);
5212 //===----------------------------------------------------------------------===//
5213 // Implementation of Emulated TLS Model
5214 //===----------------------------------------------------------------------===//
5216 SDValue TargetLowering::LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA,
5217 SelectionDAG &DAG) const {
5218 // Access to address of TLS varialbe xyz is lowered to a function call:
5219 // __emutls_get_address( address of global variable named "__emutls_v.xyz" )
5220 EVT PtrVT = getPointerTy(DAG.getDataLayout());
5221 PointerType *VoidPtrType = Type::getInt8PtrTy(*DAG.getContext());
5226 std::string NameString = ("__emutls_v." + GA->getGlobal()->getName()).str();
5227 Module *VariableModule = const_cast<Module*>(GA->getGlobal()->getParent());
5228 StringRef EmuTlsVarName(NameString);
5229 GlobalVariable *EmuTlsVar = VariableModule->getNamedGlobal(EmuTlsVarName);
5230 assert(EmuTlsVar && "Cannot find EmuTlsVar ");
5231 Entry.Node = DAG.getGlobalAddress(EmuTlsVar, dl, PtrVT);
5232 Entry.Ty = VoidPtrType;
5233 Args.push_back(Entry);
5235 SDValue EmuTlsGetAddr = DAG.getExternalSymbol("__emutls_get_address", PtrVT);
5237 TargetLowering::CallLoweringInfo CLI(DAG);
5238 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode());
5239 CLI.setLibCallee(CallingConv::C, VoidPtrType, EmuTlsGetAddr, std::move(Args));
5240 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
5242 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
5243 // At last for X86 targets, maybe good for other targets too?
5244 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
5245 MFI.setAdjustsStack(true); // Is this only for X86 target?
5246 MFI.setHasCalls(true);
5248 assert((GA->getOffset() == 0) &&
5249 "Emulated TLS must have zero offset in GlobalAddressSDNode");
5250 return CallResult.first;
5253 SDValue TargetLowering::lowerCmpEqZeroToCtlzSrl(SDValue Op,
5254 SelectionDAG &DAG) const {
5255 assert((Op->getOpcode() == ISD::SETCC) && "Input has to be a SETCC node.");
5258 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
5260 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
5261 if (C->isNullValue() && CC == ISD::SETEQ) {
5262 EVT VT = Op.getOperand(0).getValueType();
5263 SDValue Zext = Op.getOperand(0);
5264 if (VT.bitsLT(MVT::i32)) {
5266 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
5268 unsigned Log2b = Log2_32(VT.getSizeInBits());
5269 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
5270 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
5271 DAG.getConstant(Log2b, dl, MVT::i32));
5272 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
5278 SDValue TargetLowering::expandAddSubSat(SDNode *Node, SelectionDAG &DAG) const {
5279 unsigned Opcode = Node->getOpcode();
5280 SDValue LHS = Node->getOperand(0);
5281 SDValue RHS = Node->getOperand(1);
5282 EVT VT = LHS.getValueType();
5285 // usub.sat(a, b) -> umax(a, b) - b
5286 if (Opcode == ISD::USUBSAT && isOperationLegalOrCustom(ISD::UMAX, VT)) {
5287 SDValue Max = DAG.getNode(ISD::UMAX, dl, VT, LHS, RHS);
5288 return DAG.getNode(ISD::SUB, dl, VT, Max, RHS);
5291 if (VT.isVector()) {
5292 // TODO: Consider not scalarizing here.
5296 unsigned OverflowOp;
5299 OverflowOp = ISD::SADDO;
5302 OverflowOp = ISD::UADDO;
5305 OverflowOp = ISD::SSUBO;
5308 OverflowOp = ISD::USUBO;
5311 llvm_unreachable("Expected method to receive signed or unsigned saturation "
5312 "addition or subtraction node.");
5315 assert(LHS.getValueType().isScalarInteger() &&
5316 "Expected operands to be integers. Vector of int arguments should "
5317 "already be unrolled.");
5318 assert(RHS.getValueType().isScalarInteger() &&
5319 "Expected operands to be integers. Vector of int arguments should "
5320 "already be unrolled.");
5321 assert(LHS.getValueType() == RHS.getValueType() &&
5322 "Expected both operands to be the same type");
5324 unsigned BitWidth = LHS.getValueSizeInBits();
5325 EVT ResultType = LHS.getValueType();
5327 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), ResultType);
5329 DAG.getNode(OverflowOp, dl, DAG.getVTList(ResultType, BoolVT), LHS, RHS);
5330 SDValue SumDiff = Result.getValue(0);
5331 SDValue Overflow = Result.getValue(1);
5332 SDValue Zero = DAG.getConstant(0, dl, ResultType);
5334 if (Opcode == ISD::UADDSAT) {
5335 // Just need to check overflow for SatMax.
5336 APInt MaxVal = APInt::getMaxValue(BitWidth);
5337 SDValue SatMax = DAG.getConstant(MaxVal, dl, ResultType);
5338 return DAG.getSelect(dl, ResultType, Overflow, SatMax, SumDiff);
5339 } else if (Opcode == ISD::USUBSAT) {
5340 // Just need to check overflow for SatMin.
5341 APInt MinVal = APInt::getMinValue(BitWidth);
5342 SDValue SatMin = DAG.getConstant(MinVal, dl, ResultType);
5343 return DAG.getSelect(dl, ResultType, Overflow, SatMin, SumDiff);
5345 // SatMax -> Overflow && SumDiff < 0
5346 // SatMin -> Overflow && SumDiff >= 0
5347 APInt MinVal = APInt::getSignedMinValue(BitWidth);
5348 APInt MaxVal = APInt::getSignedMaxValue(BitWidth);
5349 SDValue SatMin = DAG.getConstant(MinVal, dl, ResultType);
5350 SDValue SatMax = DAG.getConstant(MaxVal, dl, ResultType);
5351 SDValue SumNeg = DAG.getSetCC(dl, BoolVT, SumDiff, Zero, ISD::SETLT);
5352 Result = DAG.getSelect(dl, ResultType, SumNeg, SatMax, SatMin);
5353 return DAG.getSelect(dl, ResultType, Overflow, Result, SumDiff);
5358 TargetLowering::getExpandedFixedPointMultiplication(SDNode *Node,
5359 SelectionDAG &DAG) const {
5360 assert(Node->getOpcode() == ISD::SMULFIX && "Expected opcode to be SMULFIX.");
5361 assert(Node->getNumOperands() == 3 &&
5362 "Expected signed fixed point multiplication to have 3 operands.");
5365 SDValue LHS = Node->getOperand(0);
5366 SDValue RHS = Node->getOperand(1);
5367 assert(LHS.getValueType().isScalarInteger() &&
5368 "Expected operands to be integers. Vector of int arguments should "
5369 "already be unrolled.");
5370 assert(RHS.getValueType().isScalarInteger() &&
5371 "Expected operands to be integers. Vector of int arguments should "
5372 "already be unrolled.");
5373 assert(LHS.getValueType() == RHS.getValueType() &&
5374 "Expected both operands to be the same type");
5376 unsigned Scale = Node->getConstantOperandVal(2);
5377 EVT VT = LHS.getValueType();
5378 assert(Scale < VT.getScalarSizeInBits() &&
5379 "Expected scale to be less than the number of bits.");
5382 return DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
5384 // Get the upper and lower bits of the result.
5386 if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) {
5388 DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), LHS, RHS);
5389 Lo = Result.getValue(0);
5390 Hi = Result.getValue(1);
5391 } else if (isOperationLegalOrCustom(ISD::MULHS, VT)) {
5392 Lo = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
5393 Hi = DAG.getNode(ISD::MULHS, dl, VT, LHS, RHS);
5395 report_fatal_error("Unable to expand signed fixed point multiplication.");
5398 // The result will need to be shifted right by the scale since both operands
5399 // are scaled. The result is given to us in 2 halves, so we only want part of
5400 // both in the result.
5401 EVT ShiftTy = getShiftAmountTy(VT, DAG.getDataLayout());
5402 Lo = DAG.getNode(ISD::SRL, dl, VT, Lo, DAG.getConstant(Scale, dl, ShiftTy));
5404 ISD::SHL, dl, VT, Hi,
5405 DAG.getConstant(VT.getScalarSizeInBits() - Scale, dl, ShiftTy));
5406 return DAG.getNode(ISD::OR, dl, VT, Lo, Hi);