1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/Analysis.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineJumpTableInfo.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/IR/DerivedTypes.h"
24 #include "llvm/IR/GlobalVariable.h"
25 #include "llvm/IR/LLVMContext.h"
26 #include "llvm/MC/MCAsmInfo.h"
27 #include "llvm/MC/MCExpr.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/MathExtras.h"
31 #include "llvm/Target/TargetLoweringObjectFile.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetRegisterInfo.h"
34 #include "llvm/Target/TargetSubtargetInfo.h"
38 /// NOTE: The TargetMachine owns TLOF.
39 TargetLowering::TargetLowering(const TargetMachine &tm)
40 : TargetLoweringBase(tm) {}
42 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
46 /// Check whether a given call node is in tail position within its function. If
47 /// so, it sets Chain to the input chain of the tail call.
48 bool TargetLowering::isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
49 SDValue &Chain) const {
50 const Function *F = DAG.getMachineFunction().getFunction();
52 // Conservatively require the attributes of the call to match those of
53 // the return. Ignore noalias because it doesn't affect the call sequence.
54 AttributeSet CallerAttrs = F->getAttributes();
55 if (AttrBuilder(CallerAttrs, AttributeSet::ReturnIndex)
56 .removeAttribute(Attribute::NoAlias).hasAttributes())
59 // It's not safe to eliminate the sign / zero extension of the return value.
60 if (CallerAttrs.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt) ||
61 CallerAttrs.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
64 // Check if the only use is a function return node.
65 return isUsedByReturnOnly(Node, Chain);
68 /// \brief Set CallLoweringInfo attribute flags based on a call instruction
69 /// and called function attributes.
70 void TargetLowering::ArgListEntry::setAttributes(ImmutableCallSite *CS,
72 isSExt = CS->paramHasAttr(AttrIdx, Attribute::SExt);
73 isZExt = CS->paramHasAttr(AttrIdx, Attribute::ZExt);
74 isInReg = CS->paramHasAttr(AttrIdx, Attribute::InReg);
75 isSRet = CS->paramHasAttr(AttrIdx, Attribute::StructRet);
76 isNest = CS->paramHasAttr(AttrIdx, Attribute::Nest);
77 isByVal = CS->paramHasAttr(AttrIdx, Attribute::ByVal);
78 isInAlloca = CS->paramHasAttr(AttrIdx, Attribute::InAlloca);
79 isReturned = CS->paramHasAttr(AttrIdx, Attribute::Returned);
80 Alignment = CS->getParamAlignment(AttrIdx);
83 /// Generate a libcall taking the given operands as arguments and returning a
84 /// result of type RetVT.
85 std::pair<SDValue, SDValue>
86 TargetLowering::makeLibCall(SelectionDAG &DAG,
87 RTLIB::Libcall LC, EVT RetVT,
88 const SDValue *Ops, unsigned NumOps,
89 bool isSigned, SDLoc dl,
91 bool isReturnValueUsed) const {
92 TargetLowering::ArgListTy Args;
95 TargetLowering::ArgListEntry Entry;
96 for (unsigned i = 0; i != NumOps; ++i) {
98 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
99 Entry.isSExt = shouldSignExtendTypeInLibCall(Ops[i].getValueType(), isSigned);
100 Entry.isZExt = !shouldSignExtendTypeInLibCall(Ops[i].getValueType(), isSigned);
101 Args.push_back(Entry);
103 if (LC == RTLIB::UNKNOWN_LIBCALL)
104 report_fatal_error("Unsupported library call operation!");
105 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC), getPointerTy());
107 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
108 TargetLowering::CallLoweringInfo CLI(DAG);
109 bool signExtend = shouldSignExtendTypeInLibCall(RetVT, isSigned);
110 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
111 .setCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
112 .setNoReturn(doesNotReturn).setDiscardResult(!isReturnValueUsed)
113 .setSExtResult(signExtend).setZExtResult(!signExtend);
114 return LowerCallTo(CLI);
118 /// SoftenSetCCOperands - Soften the operands of a comparison. This code is
119 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
120 void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT,
121 SDValue &NewLHS, SDValue &NewRHS,
122 ISD::CondCode &CCCode,
124 assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128)
125 && "Unsupported setcc type!");
127 // Expand into one or more soft-fp libcall(s).
128 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
132 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
133 (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128;
137 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 :
138 (VT == MVT::f64) ? RTLIB::UNE_F64 : RTLIB::UNE_F128;
142 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
143 (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128;
147 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
148 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
152 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
153 (VT == MVT::f64) ? RTLIB::OLE_F64 : RTLIB::OLE_F128;
157 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
158 (VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128;
161 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
162 (VT == MVT::f64) ? RTLIB::UO_F64 : RTLIB::UO_F128;
165 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 :
166 (VT == MVT::f64) ? RTLIB::O_F64 : RTLIB::O_F128;
169 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
170 (VT == MVT::f64) ? RTLIB::UO_F64 : RTLIB::UO_F128;
173 // SETONE = SETOLT | SETOGT
174 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
175 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
178 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
179 (VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128;
182 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
183 (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128;
186 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
187 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
190 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
191 (VT == MVT::f64) ? RTLIB::OLE_F64 : RTLIB::OLE_F128;
194 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
195 (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128;
197 default: llvm_unreachable("Do not know how to soften this setcc!");
201 // Use the target specific return value for comparions lib calls.
202 EVT RetVT = getCmpLibcallReturnType();
203 SDValue Ops[2] = { NewLHS, NewRHS };
204 NewLHS = makeLibCall(DAG, LC1, RetVT, Ops, 2, false/*sign irrelevant*/,
206 NewRHS = DAG.getConstant(0, dl, RetVT);
207 CCCode = getCmpLibcallCC(LC1);
208 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
209 SDValue Tmp = DAG.getNode(ISD::SETCC, dl,
210 getSetCCResultType(*DAG.getContext(), RetVT),
211 NewLHS, NewRHS, DAG.getCondCode(CCCode));
212 NewLHS = makeLibCall(DAG, LC2, RetVT, Ops, 2, false/*sign irrelevant*/,
214 NewLHS = DAG.getNode(ISD::SETCC, dl,
215 getSetCCResultType(*DAG.getContext(), RetVT), NewLHS,
216 NewRHS, DAG.getCondCode(getCmpLibcallCC(LC2)));
217 NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS);
222 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
223 /// current function. The returned value is a member of the
224 /// MachineJumpTableInfo::JTEntryKind enum.
225 unsigned TargetLowering::getJumpTableEncoding() const {
226 // In non-pic modes, just use the address of a block.
227 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
228 return MachineJumpTableInfo::EK_BlockAddress;
230 // In PIC mode, if the target supports a GPRel32 directive, use it.
231 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != nullptr)
232 return MachineJumpTableInfo::EK_GPRel32BlockAddress;
234 // Otherwise, use a label difference.
235 return MachineJumpTableInfo::EK_LabelDifference32;
238 SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
239 SelectionDAG &DAG) const {
240 // If our PIC model is GP relative, use the global offset table as the base.
241 unsigned JTEncoding = getJumpTableEncoding();
243 if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) ||
244 (JTEncoding == MachineJumpTableInfo::EK_GPRel32BlockAddress))
245 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy(0));
250 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
251 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
254 TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
255 unsigned JTI,MCContext &Ctx) const{
256 // The normal PIC reloc base is the label at the start of the jump table.
257 return MCSymbolRefExpr::create(MF->getJTISymbol(JTI, Ctx), Ctx);
261 TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
262 // Assume that everything is safe in static mode.
263 if (getTargetMachine().getRelocationModel() == Reloc::Static)
266 // In dynamic-no-pic mode, assume that known defined values are safe.
267 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
269 !GA->getGlobal()->isDeclaration() &&
270 !GA->getGlobal()->isWeakForLinker())
273 // Otherwise assume nothing is safe.
277 //===----------------------------------------------------------------------===//
278 // Optimization Methods
279 //===----------------------------------------------------------------------===//
281 /// ShrinkDemandedConstant - Check to see if the specified operand of the
282 /// specified instruction is a constant integer. If so, check to see if there
283 /// are any bits set in the constant that are not demanded. If so, shrink the
284 /// constant and return true.
285 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
286 const APInt &Demanded) {
289 // FIXME: ISD::SELECT, ISD::SELECT_CC
290 switch (Op.getOpcode()) {
295 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
296 if (!C) return false;
298 if (Op.getOpcode() == ISD::XOR &&
299 (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
302 // if we can expand it to have all bits set, do it
303 if (C->getAPIntValue().intersects(~Demanded)) {
304 EVT VT = Op.getValueType();
305 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
306 DAG.getConstant(Demanded &
309 return CombineTo(Op, New);
319 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
320 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
321 /// cast, but it could be generalized for targets with other types of
322 /// implicit widening casts.
324 TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
326 const APInt &Demanded,
328 assert(Op.getNumOperands() == 2 &&
329 "ShrinkDemandedOp only supports binary operators!");
330 assert(Op.getNode()->getNumValues() == 1 &&
331 "ShrinkDemandedOp only supports nodes with one result!");
333 // Early return, as this function cannot handle vector types.
334 if (Op.getValueType().isVector())
337 // Don't do this if the node has another user, which may require the
339 if (!Op.getNode()->hasOneUse())
342 // Search for the smallest integer type with free casts to and from
343 // Op's type. For expedience, just check power-of-2 integer types.
344 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
345 unsigned DemandedSize = BitWidth - Demanded.countLeadingZeros();
346 unsigned SmallVTBits = DemandedSize;
347 if (!isPowerOf2_32(SmallVTBits))
348 SmallVTBits = NextPowerOf2(SmallVTBits);
349 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
350 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
351 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
352 TLI.isZExtFree(SmallVT, Op.getValueType())) {
353 // We found a type with free casts.
354 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
355 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
356 Op.getNode()->getOperand(0)),
357 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
358 Op.getNode()->getOperand(1)));
359 bool NeedZext = DemandedSize > SmallVTBits;
360 SDValue Z = DAG.getNode(NeedZext ? ISD::ZERO_EXTEND : ISD::ANY_EXTEND,
361 dl, Op.getValueType(), X);
362 return CombineTo(Op, Z);
368 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
369 /// DemandedMask bits of the result of Op are ever used downstream. If we can
370 /// use this information to simplify Op, create a new simplified DAG node and
371 /// return true, returning the original and new nodes in Old and New. Otherwise,
372 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
373 /// the expression (used to simplify the caller). The KnownZero/One bits may
374 /// only be accurate for those bits in the DemandedMask.
375 bool TargetLowering::SimplifyDemandedBits(SDValue Op,
376 const APInt &DemandedMask,
379 TargetLoweringOpt &TLO,
380 unsigned Depth) const {
381 unsigned BitWidth = DemandedMask.getBitWidth();
382 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
383 "Mask size mismatches value type size!");
384 APInt NewMask = DemandedMask;
387 // Don't know anything.
388 KnownZero = KnownOne = APInt(BitWidth, 0);
390 // Other users may use these bits.
391 if (!Op.getNode()->hasOneUse()) {
393 // If not at the root, Just compute the KnownZero/KnownOne bits to
394 // simplify things downstream.
395 TLO.DAG.computeKnownBits(Op, KnownZero, KnownOne, Depth);
398 // If this is the root being simplified, allow it to have multiple uses,
399 // just set the NewMask to all bits.
400 NewMask = APInt::getAllOnesValue(BitWidth);
401 } else if (DemandedMask == 0) {
402 // Not demanding any bits from Op.
403 if (Op.getOpcode() != ISD::UNDEF)
404 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
406 } else if (Depth == 6) { // Limit search depth.
410 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
411 switch (Op.getOpcode()) {
413 // We know all of the bits for a constant!
414 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue();
415 KnownZero = ~KnownOne;
416 return false; // Don't fall through, will infinitely loop.
418 // If the RHS is a constant, check to see if the LHS would be zero without
419 // using the bits from the RHS. Below, we use knowledge about the RHS to
420 // simplify the LHS, here we're using information from the LHS to simplify
422 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
423 APInt LHSZero, LHSOne;
424 // Do not increment Depth here; that can cause an infinite loop.
425 TLO.DAG.computeKnownBits(Op.getOperand(0), LHSZero, LHSOne, Depth);
426 // If the LHS already has zeros where RHSC does, this and is dead.
427 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
428 return TLO.CombineTo(Op, Op.getOperand(0));
429 // If any of the set bits in the RHS are known zero on the LHS, shrink
431 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
435 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
436 KnownOne, TLO, Depth+1))
438 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
439 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
440 KnownZero2, KnownOne2, TLO, Depth+1))
442 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
444 // If all of the demanded bits are known one on one side, return the other.
445 // These bits cannot contribute to the result of the 'and'.
446 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
447 return TLO.CombineTo(Op, Op.getOperand(0));
448 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
449 return TLO.CombineTo(Op, Op.getOperand(1));
450 // If all of the demanded bits in the inputs are known zeros, return zero.
451 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
452 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, dl, Op.getValueType()));
453 // If the RHS is a constant, see if we can simplify it.
454 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
456 // If the operation can be done in a smaller type, do so.
457 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
460 // Output known-1 bits are only known if set in both the LHS & RHS.
461 KnownOne &= KnownOne2;
462 // Output known-0 are known to be clear if zero in either the LHS | RHS.
463 KnownZero |= KnownZero2;
466 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
467 KnownOne, TLO, Depth+1))
469 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
470 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
471 KnownZero2, KnownOne2, TLO, Depth+1))
473 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
475 // If all of the demanded bits are known zero on one side, return the other.
476 // These bits cannot contribute to the result of the 'or'.
477 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
478 return TLO.CombineTo(Op, Op.getOperand(0));
479 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
480 return TLO.CombineTo(Op, Op.getOperand(1));
481 // If all of the potentially set bits on one side are known to be set on
482 // the other side, just use the 'other' side.
483 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
484 return TLO.CombineTo(Op, Op.getOperand(0));
485 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
486 return TLO.CombineTo(Op, Op.getOperand(1));
487 // If the RHS is a constant, see if we can simplify it.
488 if (TLO.ShrinkDemandedConstant(Op, NewMask))
490 // If the operation can be done in a smaller type, do so.
491 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
494 // Output known-0 bits are only known if clear in both the LHS & RHS.
495 KnownZero &= KnownZero2;
496 // Output known-1 are known to be set if set in either the LHS | RHS.
497 KnownOne |= KnownOne2;
500 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
501 KnownOne, TLO, Depth+1))
503 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
504 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
505 KnownOne2, TLO, Depth+1))
507 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
509 // If all of the demanded bits are known zero on one side, return the other.
510 // These bits cannot contribute to the result of the 'xor'.
511 if ((KnownZero & NewMask) == NewMask)
512 return TLO.CombineTo(Op, Op.getOperand(0));
513 if ((KnownZero2 & NewMask) == NewMask)
514 return TLO.CombineTo(Op, Op.getOperand(1));
515 // If the operation can be done in a smaller type, do so.
516 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
519 // If all of the unknown bits are known to be zero on one side or the other
520 // (but not both) turn this into an *inclusive* or.
521 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
522 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
523 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
527 // Output known-0 bits are known if clear or set in both the LHS & RHS.
528 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
529 // Output known-1 are known to be set if set in only one of the LHS, RHS.
530 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
532 // If all of the demanded bits on one side are known, and all of the set
533 // bits on that side are also known to be set on the other side, turn this
534 // into an AND, as we know the bits will be cleared.
535 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
536 // NB: it is okay if more bits are known than are requested
537 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known on one side
538 if (KnownOne == KnownOne2) { // set bits are the same on both sides
539 EVT VT = Op.getValueType();
540 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, dl, VT);
541 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
542 Op.getOperand(0), ANDC));
546 // If the RHS is a constant, see if we can simplify it.
547 // for XOR, we prefer to force bits to 1 if they will make a -1.
548 // if we can't force bits, try to shrink constant
549 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
550 APInt Expanded = C->getAPIntValue() | (~NewMask);
551 // if we can expand it to have all bits set, do it
552 if (Expanded.isAllOnesValue()) {
553 if (Expanded != C->getAPIntValue()) {
554 EVT VT = Op.getValueType();
555 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
556 TLO.DAG.getConstant(Expanded, dl, VT));
557 return TLO.CombineTo(Op, New);
559 // if it already has all the bits set, nothing to change
560 // but don't shrink either!
561 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
566 KnownZero = KnownZeroOut;
567 KnownOne = KnownOneOut;
570 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
571 KnownOne, TLO, Depth+1))
573 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
574 KnownOne2, TLO, Depth+1))
576 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
577 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
579 // If the operands are constants, see if we can simplify them.
580 if (TLO.ShrinkDemandedConstant(Op, NewMask))
583 // Only known if known in both the LHS and RHS.
584 KnownOne &= KnownOne2;
585 KnownZero &= KnownZero2;
588 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
589 KnownOne, TLO, Depth+1))
591 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
592 KnownOne2, TLO, Depth+1))
594 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
595 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
597 // If the operands are constants, see if we can simplify them.
598 if (TLO.ShrinkDemandedConstant(Op, NewMask))
601 // Only known if known in both the LHS and RHS.
602 KnownOne &= KnownOne2;
603 KnownZero &= KnownZero2;
606 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
607 unsigned ShAmt = SA->getZExtValue();
608 SDValue InOp = Op.getOperand(0);
610 // If the shift count is an invalid immediate, don't do anything.
611 if (ShAmt >= BitWidth)
614 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
615 // single shift. We can do this if the bottom bits (which are shifted
616 // out) are never demanded.
617 if (InOp.getOpcode() == ISD::SRL &&
618 isa<ConstantSDNode>(InOp.getOperand(1))) {
619 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
620 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
621 unsigned Opc = ISD::SHL;
629 TLO.DAG.getConstant(Diff, dl, Op.getOperand(1).getValueType());
630 EVT VT = Op.getValueType();
631 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
632 InOp.getOperand(0), NewSA));
636 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
637 KnownZero, KnownOne, TLO, Depth+1))
640 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
641 // are not demanded. This will likely allow the anyext to be folded away.
642 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
643 SDValue InnerOp = InOp.getNode()->getOperand(0);
644 EVT InnerVT = InnerOp.getValueType();
645 unsigned InnerBits = InnerVT.getSizeInBits();
646 if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
647 isTypeDesirableForOp(ISD::SHL, InnerVT)) {
648 EVT ShTy = getShiftAmountTy(InnerVT);
649 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
652 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
653 TLO.DAG.getConstant(ShAmt, dl, ShTy));
656 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
659 // Repeat the SHL optimization above in cases where an extension
660 // intervenes: (shl (anyext (shr x, c1)), c2) to
661 // (shl (anyext x), c2-c1). This requires that the bottom c1 bits
662 // aren't demanded (as above) and that the shifted upper c1 bits of
663 // x aren't demanded.
664 if (InOp.hasOneUse() &&
665 InnerOp.getOpcode() == ISD::SRL &&
666 InnerOp.hasOneUse() &&
667 isa<ConstantSDNode>(InnerOp.getOperand(1))) {
668 uint64_t InnerShAmt = cast<ConstantSDNode>(InnerOp.getOperand(1))
670 if (InnerShAmt < ShAmt &&
671 InnerShAmt < InnerBits &&
672 NewMask.lshr(InnerBits - InnerShAmt + ShAmt) == 0 &&
673 NewMask.trunc(ShAmt) == 0) {
675 TLO.DAG.getConstant(ShAmt - InnerShAmt, dl,
676 Op.getOperand(1).getValueType());
677 EVT VT = Op.getValueType();
678 SDValue NewExt = TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT,
679 InnerOp.getOperand(0));
680 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, VT,
686 KnownZero <<= SA->getZExtValue();
687 KnownOne <<= SA->getZExtValue();
688 // low bits known zero.
689 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
693 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
694 EVT VT = Op.getValueType();
695 unsigned ShAmt = SA->getZExtValue();
696 unsigned VTSize = VT.getSizeInBits();
697 SDValue InOp = Op.getOperand(0);
699 // If the shift count is an invalid immediate, don't do anything.
700 if (ShAmt >= BitWidth)
703 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
704 // single shift. We can do this if the top bits (which are shifted out)
705 // are never demanded.
706 if (InOp.getOpcode() == ISD::SHL &&
707 isa<ConstantSDNode>(InOp.getOperand(1))) {
708 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
709 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
710 unsigned Opc = ISD::SRL;
718 TLO.DAG.getConstant(Diff, dl, Op.getOperand(1).getValueType());
719 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
720 InOp.getOperand(0), NewSA));
724 // Compute the new bits that are at the top now.
725 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
726 KnownZero, KnownOne, TLO, Depth+1))
728 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
729 KnownZero = KnownZero.lshr(ShAmt);
730 KnownOne = KnownOne.lshr(ShAmt);
732 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
733 KnownZero |= HighBits; // High bits known zero.
737 // If this is an arithmetic shift right and only the low-bit is set, we can
738 // always convert this into a logical shr, even if the shift amount is
739 // variable. The low bit of the shift cannot be an input sign bit unless
740 // the shift amount is >= the size of the datatype, which is undefined.
742 return TLO.CombineTo(Op,
743 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
744 Op.getOperand(0), Op.getOperand(1)));
746 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
747 EVT VT = Op.getValueType();
748 unsigned ShAmt = SA->getZExtValue();
750 // If the shift count is an invalid immediate, don't do anything.
751 if (ShAmt >= BitWidth)
754 APInt InDemandedMask = (NewMask << ShAmt);
756 // If any of the demanded bits are produced by the sign extension, we also
757 // demand the input sign bit.
758 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
759 if (HighBits.intersects(NewMask))
760 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
762 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
763 KnownZero, KnownOne, TLO, Depth+1))
765 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
766 KnownZero = KnownZero.lshr(ShAmt);
767 KnownOne = KnownOne.lshr(ShAmt);
769 // Handle the sign bit, adjusted to where it is now in the mask.
770 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
772 // If the input sign bit is known to be zero, or if none of the top bits
773 // are demanded, turn this into an unsigned shift right.
774 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits)
775 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
779 int Log2 = NewMask.exactLogBase2();
781 // The bit must come from the sign.
783 TLO.DAG.getConstant(BitWidth - 1 - Log2, dl,
784 Op.getOperand(1).getValueType());
785 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
786 Op.getOperand(0), NewSA));
789 if (KnownOne.intersects(SignBit))
790 // New bits are known one.
791 KnownOne |= HighBits;
794 case ISD::SIGN_EXTEND_INREG: {
795 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
797 APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1);
798 // If we only care about the highest bit, don't bother shifting right.
799 if (MsbMask == NewMask) {
800 unsigned ShAmt = ExVT.getScalarType().getSizeInBits();
801 SDValue InOp = Op.getOperand(0);
802 unsigned VTBits = Op->getValueType(0).getScalarType().getSizeInBits();
803 bool AlreadySignExtended =
804 TLO.DAG.ComputeNumSignBits(InOp) >= VTBits-ShAmt+1;
805 // However if the input is already sign extended we expect the sign
806 // extension to be dropped altogether later and do not simplify.
807 if (!AlreadySignExtended) {
808 // Compute the correct shift amount type, which must be getShiftAmountTy
809 // for scalar types after legalization.
810 EVT ShiftAmtTy = Op.getValueType();
811 if (TLO.LegalTypes() && !ShiftAmtTy.isVector())
812 ShiftAmtTy = getShiftAmountTy(ShiftAmtTy);
814 SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, dl,
816 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
817 Op.getValueType(), InOp,
822 // Sign extension. Compute the demanded bits in the result that are not
823 // present in the input.
825 APInt::getHighBitsSet(BitWidth,
826 BitWidth - ExVT.getScalarType().getSizeInBits());
828 // If none of the extended bits are demanded, eliminate the sextinreg.
829 if ((NewBits & NewMask) == 0)
830 return TLO.CombineTo(Op, Op.getOperand(0));
833 APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth);
834 APInt InputDemandedBits =
835 APInt::getLowBitsSet(BitWidth,
836 ExVT.getScalarType().getSizeInBits()) &
839 // Since the sign extended bits are demanded, we know that the sign
841 InputDemandedBits |= InSignBit;
843 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
844 KnownZero, KnownOne, TLO, Depth+1))
846 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
848 // If the sign bit of the input is known set or clear, then we know the
849 // top bits of the result.
851 // If the input sign bit is known zero, convert this into a zero extension.
852 if (KnownZero.intersects(InSignBit))
853 return TLO.CombineTo(Op,
854 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT));
856 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
858 KnownZero &= ~NewBits;
859 } else { // Input sign bit unknown
860 KnownZero &= ~NewBits;
861 KnownOne &= ~NewBits;
865 case ISD::BUILD_PAIR: {
866 EVT HalfVT = Op.getOperand(0).getValueType();
867 unsigned HalfBitWidth = HalfVT.getScalarSizeInBits();
869 APInt MaskLo = NewMask.getLoBits(HalfBitWidth).trunc(HalfBitWidth);
870 APInt MaskHi = NewMask.getHiBits(HalfBitWidth).trunc(HalfBitWidth);
872 APInt KnownZeroLo, KnownOneLo;
873 APInt KnownZeroHi, KnownOneHi;
875 if (SimplifyDemandedBits(Op.getOperand(0), MaskLo, KnownZeroLo,
876 KnownOneLo, TLO, Depth + 1))
879 if (SimplifyDemandedBits(Op.getOperand(1), MaskHi, KnownZeroHi,
880 KnownOneHi, TLO, Depth + 1))
883 KnownZero = KnownZeroLo.zext(BitWidth) |
884 KnownZeroHi.zext(BitWidth).shl(HalfBitWidth);
886 KnownOne = KnownOneLo.zext(BitWidth) |
887 KnownOneHi.zext(BitWidth).shl(HalfBitWidth);
890 case ISD::ZERO_EXTEND: {
891 unsigned OperandBitWidth =
892 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
893 APInt InMask = NewMask.trunc(OperandBitWidth);
895 // If none of the top bits are demanded, convert this into an any_extend.
897 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
898 if (!NewBits.intersects(NewMask))
899 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
903 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
904 KnownZero, KnownOne, TLO, Depth+1))
906 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
907 KnownZero = KnownZero.zext(BitWidth);
908 KnownOne = KnownOne.zext(BitWidth);
909 KnownZero |= NewBits;
912 case ISD::SIGN_EXTEND: {
913 EVT InVT = Op.getOperand(0).getValueType();
914 unsigned InBits = InVT.getScalarType().getSizeInBits();
915 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
916 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
917 APInt NewBits = ~InMask & NewMask;
919 // If none of the top bits are demanded, convert this into an any_extend.
921 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
925 // Since some of the sign extended bits are demanded, we know that the sign
927 APInt InDemandedBits = InMask & NewMask;
928 InDemandedBits |= InSignBit;
929 InDemandedBits = InDemandedBits.trunc(InBits);
931 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
932 KnownOne, TLO, Depth+1))
934 KnownZero = KnownZero.zext(BitWidth);
935 KnownOne = KnownOne.zext(BitWidth);
937 // If the sign bit is known zero, convert this to a zero extend.
938 if (KnownZero.intersects(InSignBit))
939 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
943 // If the sign bit is known one, the top bits match.
944 if (KnownOne.intersects(InSignBit)) {
946 assert((KnownZero & NewBits) == 0);
947 } else { // Otherwise, top bits aren't known.
948 assert((KnownOne & NewBits) == 0);
949 assert((KnownZero & NewBits) == 0);
953 case ISD::ANY_EXTEND: {
954 unsigned OperandBitWidth =
955 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
956 APInt InMask = NewMask.trunc(OperandBitWidth);
957 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
958 KnownZero, KnownOne, TLO, Depth+1))
960 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
961 KnownZero = KnownZero.zext(BitWidth);
962 KnownOne = KnownOne.zext(BitWidth);
965 case ISD::TRUNCATE: {
966 // Simplify the input, using demanded bit information, and compute the known
967 // zero/one bits live out.
968 unsigned OperandBitWidth =
969 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
970 APInt TruncMask = NewMask.zext(OperandBitWidth);
971 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
972 KnownZero, KnownOne, TLO, Depth+1))
974 KnownZero = KnownZero.trunc(BitWidth);
975 KnownOne = KnownOne.trunc(BitWidth);
977 // If the input is only used by this truncate, see if we can shrink it based
978 // on the known demanded bits.
979 if (Op.getOperand(0).getNode()->hasOneUse()) {
980 SDValue In = Op.getOperand(0);
981 switch (In.getOpcode()) {
984 // Shrink SRL by a constant if none of the high bits shifted in are
986 if (TLO.LegalTypes() &&
987 !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
988 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
991 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
994 SDValue Shift = In.getOperand(1);
995 if (TLO.LegalTypes()) {
996 uint64_t ShVal = ShAmt->getZExtValue();
998 TLO.DAG.getConstant(ShVal, dl, getShiftAmountTy(Op.getValueType()));
1001 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
1002 OperandBitWidth - BitWidth);
1003 HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth);
1005 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1006 // None of the shifted in bits are needed. Add a truncate of the
1007 // shift input, then shift it.
1008 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
1011 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1020 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1023 case ISD::AssertZext: {
1024 // AssertZext demands all of the high bits, plus any of the low bits
1025 // demanded by its users.
1026 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1027 APInt InMask = APInt::getLowBitsSet(BitWidth,
1028 VT.getSizeInBits());
1029 if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask,
1030 KnownZero, KnownOne, TLO, Depth+1))
1032 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1034 KnownZero |= ~InMask & NewMask;
1038 // If this is an FP->Int bitcast and if the sign bit is the only
1039 // thing demanded, turn this into a FGETSIGN.
1040 if (!TLO.LegalOperations() &&
1041 !Op.getValueType().isVector() &&
1042 !Op.getOperand(0).getValueType().isVector() &&
1043 NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
1044 Op.getOperand(0).getValueType().isFloatingPoint()) {
1045 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
1046 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
1047 if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) {
1048 EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32;
1049 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1050 // place. We expect the SHL to be eliminated by other optimizations.
1051 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
1052 unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits();
1053 if (!OpVTLegal && OpVTSizeInBits > 32)
1054 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
1055 unsigned ShVal = Op.getValueType().getSizeInBits()-1;
1056 SDValue ShAmt = TLO.DAG.getConstant(ShVal, dl, Op.getValueType());
1057 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1066 // Add, Sub, and Mul don't demand any bits in positions beyond that
1067 // of the highest bit demanded of them.
1068 APInt LoMask = APInt::getLowBitsSet(BitWidth,
1069 BitWidth - NewMask.countLeadingZeros());
1070 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1071 KnownOne2, TLO, Depth+1))
1073 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1074 KnownOne2, TLO, Depth+1))
1076 // See if the operation should be performed at a smaller bit width.
1077 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1082 // Just use computeKnownBits to compute output bits.
1083 TLO.DAG.computeKnownBits(Op, KnownZero, KnownOne, Depth);
1087 // If we know the value of all of the demanded bits, return this as a
1089 if ((NewMask & (KnownZero|KnownOne)) == NewMask) {
1090 // Avoid folding to a constant if any OpaqueConstant is involved.
1091 const SDNode *N = Op.getNode();
1092 for (SDNodeIterator I = SDNodeIterator::begin(N),
1093 E = SDNodeIterator::end(N); I != E; ++I) {
1095 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
1099 return TLO.CombineTo(Op,
1100 TLO.DAG.getConstant(KnownOne, dl, Op.getValueType()));
1106 /// computeKnownBitsForTargetNode - Determine which of the bits specified
1107 /// in Mask are known to be either zero or one and return them in the
1108 /// KnownZero/KnownOne bitsets.
1109 void TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
1112 const SelectionDAG &DAG,
1113 unsigned Depth) const {
1114 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1115 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1116 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1117 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1118 "Should use MaskedValueIsZero if you don't know whether Op"
1119 " is a target node!");
1120 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0);
1123 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
1124 /// targets that want to expose additional information about sign bits to the
1126 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
1127 const SelectionDAG &,
1128 unsigned Depth) const {
1129 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1130 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1131 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1132 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1133 "Should use ComputeNumSignBits if you don't know whether Op"
1134 " is a target node!");
1138 /// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1139 /// one bit set. This differs from computeKnownBits in that it doesn't need to
1140 /// determine which bit is set.
1142 static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
1143 // A left-shift of a constant one will have exactly one bit set, because
1144 // shifting the bit off the end is undefined.
1145 if (Val.getOpcode() == ISD::SHL)
1146 if (ConstantSDNode *C =
1147 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1148 if (C->getAPIntValue() == 1)
1151 // Similarly, a right-shift of a constant sign-bit will have exactly
1153 if (Val.getOpcode() == ISD::SRL)
1154 if (ConstantSDNode *C =
1155 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1156 if (C->getAPIntValue().isSignBit())
1159 // More could be done here, though the above checks are enough
1160 // to handle some common cases.
1162 // Fall back to computeKnownBits to catch other known cases.
1163 EVT OpVT = Val.getValueType();
1164 unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
1165 APInt KnownZero, KnownOne;
1166 DAG.computeKnownBits(Val, KnownZero, KnownOne);
1167 return (KnownZero.countPopulation() == BitWidth - 1) &&
1168 (KnownOne.countPopulation() == 1);
1171 bool TargetLowering::isConstTrueVal(const SDNode *N) const {
1175 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
1177 const BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N);
1181 BitVector UndefElements;
1182 CN = BV->getConstantSplatNode(&UndefElements);
1183 // Only interested in constant splats, and we don't try to handle undef
1184 // elements in identifying boolean constants.
1185 if (!CN || UndefElements.none())
1189 switch (getBooleanContents(N->getValueType(0))) {
1190 case UndefinedBooleanContent:
1191 return CN->getAPIntValue()[0];
1192 case ZeroOrOneBooleanContent:
1194 case ZeroOrNegativeOneBooleanContent:
1195 return CN->isAllOnesValue();
1198 llvm_unreachable("Invalid boolean contents");
1201 bool TargetLowering::isConstFalseVal(const SDNode *N) const {
1205 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
1207 const BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N);
1211 BitVector UndefElements;
1212 CN = BV->getConstantSplatNode(&UndefElements);
1213 // Only interested in constant splats, and we don't try to handle undef
1214 // elements in identifying boolean constants.
1215 if (!CN || UndefElements.none())
1219 if (getBooleanContents(N->getValueType(0)) == UndefinedBooleanContent)
1220 return !CN->getAPIntValue()[0];
1222 return CN->isNullValue();
1225 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
1226 /// and cc. If it is unable to simplify it, return a null SDValue.
1228 TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1229 ISD::CondCode Cond, bool foldBooleans,
1230 DAGCombinerInfo &DCI, SDLoc dl) const {
1231 SelectionDAG &DAG = DCI.DAG;
1233 // These setcc operations always fold.
1237 case ISD::SETFALSE2: return DAG.getConstant(0, dl, VT);
1239 case ISD::SETTRUE2: {
1240 TargetLowering::BooleanContent Cnt =
1241 getBooleanContents(N0->getValueType(0));
1242 return DAG.getConstant(
1243 Cnt == TargetLowering::ZeroOrNegativeOneBooleanContent ? -1ULL : 1, dl,
1248 // Ensure that the constant occurs on the RHS, and fold constant
1250 ISD::CondCode SwappedCC = ISD::getSetCCSwappedOperands(Cond);
1251 if (isa<ConstantSDNode>(N0.getNode()) &&
1252 (DCI.isBeforeLegalizeOps() ||
1253 isCondCodeLegal(SwappedCC, N0.getSimpleValueType())))
1254 return DAG.getSetCC(dl, VT, N1, N0, SwappedCC);
1256 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1257 const APInt &C1 = N1C->getAPIntValue();
1259 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1260 // equality comparison, then we're just comparing whether X itself is
1262 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1263 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1264 N0.getOperand(1).getOpcode() == ISD::Constant) {
1266 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1267 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1268 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1269 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1270 // (srl (ctlz x), 5) == 0 -> X != 0
1271 // (srl (ctlz x), 5) != 1 -> X != 0
1274 // (srl (ctlz x), 5) != 0 -> X == 0
1275 // (srl (ctlz x), 5) == 1 -> X == 0
1278 SDValue Zero = DAG.getConstant(0, dl, N0.getValueType());
1279 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1285 // Look through truncs that don't change the value of a ctpop.
1286 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
1287 CTPOP = N0.getOperand(0);
1289 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
1290 (N0 == CTPOP || N0.getValueType().getSizeInBits() >
1291 Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) {
1292 EVT CTVT = CTPOP.getValueType();
1293 SDValue CTOp = CTPOP.getOperand(0);
1295 // (ctpop x) u< 2 -> (x & x-1) == 0
1296 // (ctpop x) u> 1 -> (x & x-1) != 0
1297 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
1298 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
1299 DAG.getConstant(1, dl, CTVT));
1300 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
1301 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
1302 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, dl, CTVT), CC);
1305 // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
1308 // (zext x) == C --> x == (trunc C)
1309 // (sext x) == C --> x == (trunc C)
1310 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1311 DCI.isBeforeLegalize() && N0->hasOneUse()) {
1312 unsigned MinBits = N0.getValueSizeInBits();
1314 bool Signed = false;
1315 if (N0->getOpcode() == ISD::ZERO_EXTEND) {
1317 MinBits = N0->getOperand(0).getValueSizeInBits();
1318 PreExt = N0->getOperand(0);
1319 } else if (N0->getOpcode() == ISD::AND) {
1320 // DAGCombine turns costly ZExts into ANDs
1321 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
1322 if ((C->getAPIntValue()+1).isPowerOf2()) {
1323 MinBits = C->getAPIntValue().countTrailingOnes();
1324 PreExt = N0->getOperand(0);
1326 } else if (N0->getOpcode() == ISD::SIGN_EXTEND) {
1328 MinBits = N0->getOperand(0).getValueSizeInBits();
1329 PreExt = N0->getOperand(0);
1331 } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
1332 // ZEXTLOAD / SEXTLOAD
1333 if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
1334 MinBits = LN0->getMemoryVT().getSizeInBits();
1336 } else if (LN0->getExtensionType() == ISD::SEXTLOAD) {
1338 MinBits = LN0->getMemoryVT().getSizeInBits();
1343 // Figure out how many bits we need to preserve this constant.
1344 unsigned ReqdBits = Signed ?
1345 C1.getBitWidth() - C1.getNumSignBits() + 1 :
1348 // Make sure we're not losing bits from the constant.
1350 MinBits < C1.getBitWidth() &&
1351 MinBits >= ReqdBits) {
1352 EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
1353 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
1354 // Will get folded away.
1355 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreExt);
1356 SDValue C = DAG.getConstant(C1.trunc(MinBits), dl, MinVT);
1357 return DAG.getSetCC(dl, VT, Trunc, C, Cond);
1362 // If the LHS is '(and load, const)', the RHS is 0,
1363 // the test is for equality or unsigned, and all 1 bits of the const are
1364 // in the same partial word, see if we can shorten the load.
1365 if (DCI.isBeforeLegalize() &&
1366 !ISD::isSignedIntSetCC(Cond) &&
1367 N0.getOpcode() == ISD::AND && C1 == 0 &&
1368 N0.getNode()->hasOneUse() &&
1369 isa<LoadSDNode>(N0.getOperand(0)) &&
1370 N0.getOperand(0).getNode()->hasOneUse() &&
1371 isa<ConstantSDNode>(N0.getOperand(1))) {
1372 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
1374 unsigned bestWidth = 0, bestOffset = 0;
1375 if (!Lod->isVolatile() && Lod->isUnindexed()) {
1376 unsigned origWidth = N0.getValueType().getSizeInBits();
1377 unsigned maskWidth = origWidth;
1378 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
1379 // 8 bits, but have to be careful...
1380 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
1381 origWidth = Lod->getMemoryVT().getSizeInBits();
1383 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1384 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
1385 APInt newMask = APInt::getLowBitsSet(maskWidth, width);
1386 for (unsigned offset=0; offset<origWidth/width; offset++) {
1387 if ((newMask & Mask) == Mask) {
1388 if (!getDataLayout()->isLittleEndian())
1389 bestOffset = (origWidth/width - offset - 1) * (width/8);
1391 bestOffset = (uint64_t)offset * (width/8);
1392 bestMask = Mask.lshr(offset * (width/8) * 8);
1396 newMask = newMask << width;
1401 EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
1402 if (newVT.isRound()) {
1403 EVT PtrType = Lod->getOperand(1).getValueType();
1404 SDValue Ptr = Lod->getBasePtr();
1405 if (bestOffset != 0)
1406 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
1407 DAG.getConstant(bestOffset, dl, PtrType));
1408 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
1409 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
1410 Lod->getPointerInfo().getWithOffset(bestOffset),
1411 false, false, false, NewAlign);
1412 return DAG.getSetCC(dl, VT,
1413 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
1414 DAG.getConstant(bestMask.trunc(bestWidth),
1416 DAG.getConstant(0LL, dl, newVT), Cond);
1421 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1422 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1423 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
1425 // If the comparison constant has bits in the upper part, the
1426 // zero-extended value could never match.
1427 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
1428 C1.getBitWidth() - InSize))) {
1432 case ISD::SETEQ: return DAG.getConstant(0, dl, VT);
1435 case ISD::SETNE: return DAG.getConstant(1, dl, VT);
1438 // True if the sign bit of C1 is set.
1439 return DAG.getConstant(C1.isNegative(), dl, VT);
1442 // True if the sign bit of C1 isn't set.
1443 return DAG.getConstant(C1.isNonNegative(), dl, VT);
1449 // Otherwise, we can perform the comparison with the low bits.
1457 EVT newVT = N0.getOperand(0).getValueType();
1458 if (DCI.isBeforeLegalizeOps() ||
1459 (isOperationLegal(ISD::SETCC, newVT) &&
1460 getCondCodeAction(Cond, newVT.getSimpleVT()) == Legal)) {
1461 EVT NewSetCCVT = getSetCCResultType(*DAG.getContext(), newVT);
1462 SDValue NewConst = DAG.getConstant(C1.trunc(InSize), dl, newVT);
1464 SDValue NewSetCC = DAG.getSetCC(dl, NewSetCCVT, N0.getOperand(0),
1466 return DAG.getBoolExtOrTrunc(NewSetCC, dl, VT, N0.getValueType());
1471 break; // todo, be more careful with signed comparisons
1473 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1474 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1475 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1476 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
1477 EVT ExtDstTy = N0.getValueType();
1478 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
1480 // If the constant doesn't fit into the number of bits for the source of
1481 // the sign extension, it is impossible for both sides to be equal.
1482 if (C1.getMinSignedBits() > ExtSrcTyBits)
1483 return DAG.getConstant(Cond == ISD::SETNE, dl, VT);
1486 EVT Op0Ty = N0.getOperand(0).getValueType();
1487 if (Op0Ty == ExtSrcTy) {
1488 ZextOp = N0.getOperand(0);
1490 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
1491 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
1492 DAG.getConstant(Imm, dl, Op0Ty));
1494 if (!DCI.isCalledByLegalizer())
1495 DCI.AddToWorklist(ZextOp.getNode());
1496 // Otherwise, make this a use of a zext.
1497 return DAG.getSetCC(dl, VT, ZextOp,
1498 DAG.getConstant(C1 & APInt::getLowBitsSet(
1503 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
1504 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1505 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
1506 if (N0.getOpcode() == ISD::SETCC &&
1507 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
1508 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
1510 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
1511 // Invert the condition.
1512 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1513 CC = ISD::getSetCCInverse(CC,
1514 N0.getOperand(0).getValueType().isInteger());
1515 if (DCI.isBeforeLegalizeOps() ||
1516 isCondCodeLegal(CC, N0.getOperand(0).getSimpleValueType()))
1517 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
1520 if ((N0.getOpcode() == ISD::XOR ||
1521 (N0.getOpcode() == ISD::AND &&
1522 N0.getOperand(0).getOpcode() == ISD::XOR &&
1523 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1524 isa<ConstantSDNode>(N0.getOperand(1)) &&
1525 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
1526 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
1527 // can only do this if the top bits are known zero.
1528 unsigned BitWidth = N0.getValueSizeInBits();
1529 if (DAG.MaskedValueIsZero(N0,
1530 APInt::getHighBitsSet(BitWidth,
1532 // Okay, get the un-inverted input value.
1534 if (N0.getOpcode() == ISD::XOR)
1535 Val = N0.getOperand(0);
1537 assert(N0.getOpcode() == ISD::AND &&
1538 N0.getOperand(0).getOpcode() == ISD::XOR);
1539 // ((X^1)&1)^1 -> X & 1
1540 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
1541 N0.getOperand(0).getOperand(0),
1545 return DAG.getSetCC(dl, VT, Val, N1,
1546 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1548 } else if (N1C->getAPIntValue() == 1 &&
1550 getBooleanContents(N0->getValueType(0)) ==
1551 ZeroOrOneBooleanContent)) {
1553 if (Op0.getOpcode() == ISD::TRUNCATE)
1554 Op0 = Op0.getOperand(0);
1556 if ((Op0.getOpcode() == ISD::XOR) &&
1557 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
1558 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
1559 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
1560 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
1561 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
1564 if (Op0.getOpcode() == ISD::AND &&
1565 isa<ConstantSDNode>(Op0.getOperand(1)) &&
1566 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
1567 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
1568 if (Op0.getValueType().bitsGT(VT))
1569 Op0 = DAG.getNode(ISD::AND, dl, VT,
1570 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
1571 DAG.getConstant(1, dl, VT));
1572 else if (Op0.getValueType().bitsLT(VT))
1573 Op0 = DAG.getNode(ISD::AND, dl, VT,
1574 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
1575 DAG.getConstant(1, dl, VT));
1577 return DAG.getSetCC(dl, VT, Op0,
1578 DAG.getConstant(0, dl, Op0.getValueType()),
1579 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1581 if (Op0.getOpcode() == ISD::AssertZext &&
1582 cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1)
1583 return DAG.getSetCC(dl, VT, Op0,
1584 DAG.getConstant(0, dl, Op0.getValueType()),
1585 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1589 APInt MinVal, MaxVal;
1590 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
1591 if (ISD::isSignedIntSetCC(Cond)) {
1592 MinVal = APInt::getSignedMinValue(OperandBitSize);
1593 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
1595 MinVal = APInt::getMinValue(OperandBitSize);
1596 MaxVal = APInt::getMaxValue(OperandBitSize);
1599 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
1600 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1601 if (C1 == MinVal) return DAG.getConstant(1, dl, VT); // X >= MIN --> true
1602 // X >= C0 --> X > (C0 - 1)
1604 ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT;
1605 if ((DCI.isBeforeLegalizeOps() ||
1606 isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
1607 (!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 &&
1608 isLegalICmpImmediate(C.getSExtValue())))) {
1609 return DAG.getSetCC(dl, VT, N0,
1610 DAG.getConstant(C, dl, N1.getValueType()),
1615 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1616 if (C1 == MaxVal) return DAG.getConstant(1, dl, VT); // X <= MAX --> true
1617 // X <= C0 --> X < (C0 + 1)
1619 ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT;
1620 if ((DCI.isBeforeLegalizeOps() ||
1621 isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
1622 (!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 &&
1623 isLegalICmpImmediate(C.getSExtValue())))) {
1624 return DAG.getSetCC(dl, VT, N0,
1625 DAG.getConstant(C, dl, N1.getValueType()),
1630 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1631 return DAG.getConstant(0, dl, VT); // X < MIN --> false
1632 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1633 return DAG.getConstant(1, dl, VT); // X >= MIN --> true
1634 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1635 return DAG.getConstant(0, dl, VT); // X > MAX --> false
1636 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1637 return DAG.getConstant(1, dl, VT); // X <= MAX --> true
1639 // Canonicalize setgt X, Min --> setne X, Min
1640 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1641 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1642 // Canonicalize setlt X, Max --> setne X, Max
1643 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1644 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1646 // If we have setult X, 1, turn it into seteq X, 0
1647 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1648 return DAG.getSetCC(dl, VT, N0,
1649 DAG.getConstant(MinVal, dl, N0.getValueType()),
1651 // If we have setugt X, Max-1, turn it into seteq X, Max
1652 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1653 return DAG.getSetCC(dl, VT, N0,
1654 DAG.getConstant(MaxVal, dl, N0.getValueType()),
1657 // If we have "setcc X, C0", check to see if we can shrink the immediate
1660 // SETUGT X, SINTMAX -> SETLT X, 0
1661 if (Cond == ISD::SETUGT &&
1662 C1 == APInt::getSignedMaxValue(OperandBitSize))
1663 return DAG.getSetCC(dl, VT, N0,
1664 DAG.getConstant(0, dl, N1.getValueType()),
1667 // SETULT X, SINTMIN -> SETGT X, -1
1668 if (Cond == ISD::SETULT &&
1669 C1 == APInt::getSignedMinValue(OperandBitSize)) {
1670 SDValue ConstMinusOne =
1671 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), dl,
1673 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
1676 // Fold bit comparisons when we can.
1677 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1678 (VT == N0.getValueType() ||
1679 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
1680 N0.getOpcode() == ISD::AND)
1681 if (ConstantSDNode *AndRHS =
1682 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1683 EVT ShiftTy = DCI.isBeforeLegalize() ?
1684 getPointerTy() : getShiftAmountTy(N0.getValueType());
1685 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
1686 // Perform the xform if the AND RHS is a single bit.
1687 if (AndRHS->getAPIntValue().isPowerOf2()) {
1688 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1689 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1690 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), dl,
1693 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
1694 // (X & 8) == 8 --> (X & 8) >> 3
1695 // Perform the xform if C1 is a single bit.
1696 if (C1.isPowerOf2()) {
1697 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1698 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1699 DAG.getConstant(C1.logBase2(), dl,
1705 if (C1.getMinSignedBits() <= 64 &&
1706 !isLegalICmpImmediate(C1.getSExtValue())) {
1707 // (X & -256) == 256 -> (X >> 8) == 1
1708 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1709 N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
1710 if (ConstantSDNode *AndRHS =
1711 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1712 const APInt &AndRHSC = AndRHS->getAPIntValue();
1713 if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) {
1714 unsigned ShiftBits = AndRHSC.countTrailingZeros();
1715 EVT ShiftTy = DCI.isBeforeLegalize() ?
1716 getPointerTy() : getShiftAmountTy(N0.getValueType());
1717 EVT CmpTy = N0.getValueType();
1718 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0),
1719 DAG.getConstant(ShiftBits, dl,
1721 SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), dl, CmpTy);
1722 return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
1725 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE ||
1726 Cond == ISD::SETULE || Cond == ISD::SETUGT) {
1727 bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT);
1728 // X < 0x100000000 -> (X >> 32) < 1
1729 // X >= 0x100000000 -> (X >> 32) >= 1
1730 // X <= 0x0ffffffff -> (X >> 32) < 1
1731 // X > 0x0ffffffff -> (X >> 32) >= 1
1734 ISD::CondCode NewCond = Cond;
1736 ShiftBits = C1.countTrailingOnes();
1738 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1740 ShiftBits = C1.countTrailingZeros();
1742 NewC = NewC.lshr(ShiftBits);
1743 if (ShiftBits && NewC.getMinSignedBits() <= 64 &&
1744 isLegalICmpImmediate(NewC.getSExtValue())) {
1745 EVT ShiftTy = DCI.isBeforeLegalize() ?
1746 getPointerTy() : getShiftAmountTy(N0.getValueType());
1747 EVT CmpTy = N0.getValueType();
1748 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0,
1749 DAG.getConstant(ShiftBits, dl, ShiftTy));
1750 SDValue CmpRHS = DAG.getConstant(NewC, dl, CmpTy);
1751 return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond);
1757 if (isa<ConstantFPSDNode>(N0.getNode())) {
1758 // Constant fold or commute setcc.
1759 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
1760 if (O.getNode()) return O;
1761 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
1762 // If the RHS of an FP comparison is a constant, simplify it away in
1764 if (CFP->getValueAPF().isNaN()) {
1765 // If an operand is known to be a nan, we can fold it.
1766 switch (ISD::getUnorderedFlavor(Cond)) {
1767 default: llvm_unreachable("Unknown flavor!");
1768 case 0: // Known false.
1769 return DAG.getConstant(0, dl, VT);
1770 case 1: // Known true.
1771 return DAG.getConstant(1, dl, VT);
1772 case 2: // Undefined.
1773 return DAG.getUNDEF(VT);
1777 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
1778 // constant if knowing that the operand is non-nan is enough. We prefer to
1779 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
1781 if (Cond == ISD::SETO || Cond == ISD::SETUO)
1782 return DAG.getSetCC(dl, VT, N0, N0, Cond);
1784 // If the condition is not legal, see if we can find an equivalent one
1786 if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) {
1787 // If the comparison was an awkward floating-point == or != and one of
1788 // the comparison operands is infinity or negative infinity, convert the
1789 // condition to a less-awkward <= or >=.
1790 if (CFP->getValueAPF().isInfinity()) {
1791 if (CFP->getValueAPF().isNegative()) {
1792 if (Cond == ISD::SETOEQ &&
1793 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
1794 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
1795 if (Cond == ISD::SETUEQ &&
1796 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
1797 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
1798 if (Cond == ISD::SETUNE &&
1799 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
1800 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
1801 if (Cond == ISD::SETONE &&
1802 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
1803 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
1805 if (Cond == ISD::SETOEQ &&
1806 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
1807 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
1808 if (Cond == ISD::SETUEQ &&
1809 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
1810 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
1811 if (Cond == ISD::SETUNE &&
1812 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
1813 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
1814 if (Cond == ISD::SETONE &&
1815 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
1816 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
1823 // The sext(setcc()) => setcc() optimization relies on the appropriate
1824 // constant being emitted.
1826 switch (getBooleanContents(N0.getValueType())) {
1827 case UndefinedBooleanContent:
1828 case ZeroOrOneBooleanContent:
1829 EqVal = ISD::isTrueWhenEqual(Cond);
1831 case ZeroOrNegativeOneBooleanContent:
1832 EqVal = ISD::isTrueWhenEqual(Cond) ? -1 : 0;
1836 // We can always fold X == X for integer setcc's.
1837 if (N0.getValueType().isInteger()) {
1838 return DAG.getConstant(EqVal, dl, VT);
1840 unsigned UOF = ISD::getUnorderedFlavor(Cond);
1841 if (UOF == 2) // FP operators that are undefined on NaNs.
1842 return DAG.getConstant(EqVal, dl, VT);
1843 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
1844 return DAG.getConstant(EqVal, dl, VT);
1845 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
1846 // if it is not already.
1847 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
1848 if (NewCond != Cond && (DCI.isBeforeLegalizeOps() ||
1849 getCondCodeAction(NewCond, N0.getSimpleValueType()) == Legal))
1850 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
1853 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1854 N0.getValueType().isInteger()) {
1855 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
1856 N0.getOpcode() == ISD::XOR) {
1857 // Simplify (X+Y) == (X+Z) --> Y == Z
1858 if (N0.getOpcode() == N1.getOpcode()) {
1859 if (N0.getOperand(0) == N1.getOperand(0))
1860 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
1861 if (N0.getOperand(1) == N1.getOperand(1))
1862 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
1863 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
1864 // If X op Y == Y op X, try other combinations.
1865 if (N0.getOperand(0) == N1.getOperand(1))
1866 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
1868 if (N0.getOperand(1) == N1.getOperand(0))
1869 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
1874 // If RHS is a legal immediate value for a compare instruction, we need
1875 // to be careful about increasing register pressure needlessly.
1876 bool LegalRHSImm = false;
1878 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
1879 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1880 // Turn (X+C1) == C2 --> X == C2-C1
1881 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
1882 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1883 DAG.getConstant(RHSC->getAPIntValue()-
1884 LHSR->getAPIntValue(),
1885 dl, N0.getValueType()), Cond);
1888 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
1889 if (N0.getOpcode() == ISD::XOR)
1890 // If we know that all of the inverted bits are zero, don't bother
1891 // performing the inversion.
1892 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
1894 DAG.getSetCC(dl, VT, N0.getOperand(0),
1895 DAG.getConstant(LHSR->getAPIntValue() ^
1896 RHSC->getAPIntValue(),
1897 dl, N0.getValueType()),
1901 // Turn (C1-X) == C2 --> X == C1-C2
1902 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
1903 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
1905 DAG.getSetCC(dl, VT, N0.getOperand(1),
1906 DAG.getConstant(SUBC->getAPIntValue() -
1907 RHSC->getAPIntValue(),
1908 dl, N0.getValueType()),
1913 // Could RHSC fold directly into a compare?
1914 if (RHSC->getValueType(0).getSizeInBits() <= 64)
1915 LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue());
1918 // Simplify (X+Z) == X --> Z == 0
1919 // Don't do this if X is an immediate that can fold into a cmp
1920 // instruction and X+Z has other uses. It could be an induction variable
1921 // chain, and the transform would increase register pressure.
1922 if (!LegalRHSImm || N0.getNode()->hasOneUse()) {
1923 if (N0.getOperand(0) == N1)
1924 return DAG.getSetCC(dl, VT, N0.getOperand(1),
1925 DAG.getConstant(0, dl, N0.getValueType()), Cond);
1926 if (N0.getOperand(1) == N1) {
1927 if (DAG.isCommutativeBinOp(N0.getOpcode()))
1928 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1929 DAG.getConstant(0, dl, N0.getValueType()),
1931 if (N0.getNode()->hasOneUse()) {
1932 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
1933 // (Z-X) == X --> Z == X<<1
1934 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1,
1935 DAG.getConstant(1, dl,
1936 getShiftAmountTy(N1.getValueType())));
1937 if (!DCI.isCalledByLegalizer())
1938 DCI.AddToWorklist(SH.getNode());
1939 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
1945 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
1946 N1.getOpcode() == ISD::XOR) {
1947 // Simplify X == (X+Z) --> Z == 0
1948 if (N1.getOperand(0) == N0)
1949 return DAG.getSetCC(dl, VT, N1.getOperand(1),
1950 DAG.getConstant(0, dl, N1.getValueType()), Cond);
1951 if (N1.getOperand(1) == N0) {
1952 if (DAG.isCommutativeBinOp(N1.getOpcode()))
1953 return DAG.getSetCC(dl, VT, N1.getOperand(0),
1954 DAG.getConstant(0, dl, N1.getValueType()), Cond);
1955 if (N1.getNode()->hasOneUse()) {
1956 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
1957 // X == (Z-X) --> X<<1 == Z
1958 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
1959 DAG.getConstant(1, dl,
1960 getShiftAmountTy(N0.getValueType())));
1961 if (!DCI.isCalledByLegalizer())
1962 DCI.AddToWorklist(SH.getNode());
1963 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
1968 // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
1969 // Note that where y is variable and is known to have at most
1970 // one bit set (for example, if it is z&1) we cannot do this;
1971 // the expressions are not equivalent when y==0.
1972 if (N0.getOpcode() == ISD::AND)
1973 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
1974 if (ValueHasExactlyOneBitSet(N1, DAG)) {
1975 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
1976 if (DCI.isBeforeLegalizeOps() ||
1977 isCondCodeLegal(Cond, N0.getSimpleValueType())) {
1978 SDValue Zero = DAG.getConstant(0, dl, N1.getValueType());
1979 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
1983 if (N1.getOpcode() == ISD::AND)
1984 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
1985 if (ValueHasExactlyOneBitSet(N0, DAG)) {
1986 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
1987 if (DCI.isBeforeLegalizeOps() ||
1988 isCondCodeLegal(Cond, N1.getSimpleValueType())) {
1989 SDValue Zero = DAG.getConstant(0, dl, N0.getValueType());
1990 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
1996 // Fold away ALL boolean setcc's.
1998 if (N0.getValueType() == MVT::i1 && foldBooleans) {
2000 default: llvm_unreachable("Unknown integer setcc!");
2001 case ISD::SETEQ: // X == Y -> ~(X^Y)
2002 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2003 N0 = DAG.getNOT(dl, Temp, MVT::i1);
2004 if (!DCI.isCalledByLegalizer())
2005 DCI.AddToWorklist(Temp.getNode());
2007 case ISD::SETNE: // X != Y --> (X^Y)
2008 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2010 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
2011 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
2012 Temp = DAG.getNOT(dl, N0, MVT::i1);
2013 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
2014 if (!DCI.isCalledByLegalizer())
2015 DCI.AddToWorklist(Temp.getNode());
2017 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
2018 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
2019 Temp = DAG.getNOT(dl, N1, MVT::i1);
2020 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
2021 if (!DCI.isCalledByLegalizer())
2022 DCI.AddToWorklist(Temp.getNode());
2024 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
2025 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
2026 Temp = DAG.getNOT(dl, N0, MVT::i1);
2027 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
2028 if (!DCI.isCalledByLegalizer())
2029 DCI.AddToWorklist(Temp.getNode());
2031 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
2032 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
2033 Temp = DAG.getNOT(dl, N1, MVT::i1);
2034 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
2037 if (VT != MVT::i1) {
2038 if (!DCI.isCalledByLegalizer())
2039 DCI.AddToWorklist(N0.getNode());
2040 // FIXME: If running after legalize, we probably can't do this.
2041 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
2046 // Could not fold it.
2050 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2051 /// node is a GlobalAddress + offset.
2052 bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA,
2053 int64_t &Offset) const {
2054 if (isa<GlobalAddressSDNode>(N)) {
2055 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2056 GA = GASD->getGlobal();
2057 Offset += GASD->getOffset();
2061 if (N->getOpcode() == ISD::ADD) {
2062 SDValue N1 = N->getOperand(0);
2063 SDValue N2 = N->getOperand(1);
2064 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
2065 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2067 Offset += V->getSExtValue();
2070 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
2071 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2073 Offset += V->getSExtValue();
2083 SDValue TargetLowering::
2084 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2085 // Default implementation: no optimization.
2089 //===----------------------------------------------------------------------===//
2090 // Inline Assembler Implementation Methods
2091 //===----------------------------------------------------------------------===//
2094 TargetLowering::ConstraintType
2095 TargetLowering::getConstraintType(const std::string &Constraint) const {
2096 unsigned S = Constraint.size();
2099 switch (Constraint[0]) {
2101 case 'r': return C_RegisterClass;
2103 case 'o': // offsetable
2104 case 'V': // not offsetable
2106 case 'i': // Simple Integer or Relocatable Constant
2107 case 'n': // Simple Integer
2108 case 'E': // Floating Point Constant
2109 case 'F': // Floating Point Constant
2110 case 's': // Relocatable Constant
2111 case 'p': // Address.
2112 case 'X': // Allow ANY value.
2113 case 'I': // Target registers.
2127 if (S > 1 && Constraint[0] == '{' && Constraint[S-1] == '}') {
2128 if (S == 8 && !Constraint.compare(1, 6, "memory", 6)) // "{memory}"
2135 /// LowerXConstraint - try to replace an X constraint, which matches anything,
2136 /// with another that has more specific requirements based on the type of the
2137 /// corresponding operand.
2138 const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
2139 if (ConstraintVT.isInteger())
2141 if (ConstraintVT.isFloatingPoint())
2142 return "f"; // works for many targets
2146 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2147 /// vector. If it is invalid, don't add anything to Ops.
2148 void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2149 std::string &Constraint,
2150 std::vector<SDValue> &Ops,
2151 SelectionDAG &DAG) const {
2153 if (Constraint.length() > 1) return;
2155 char ConstraintLetter = Constraint[0];
2156 switch (ConstraintLetter) {
2158 case 'X': // Allows any operand; labels (basic block) use this.
2159 if (Op.getOpcode() == ISD::BasicBlock) {
2164 case 'i': // Simple Integer or Relocatable Constant
2165 case 'n': // Simple Integer
2166 case 's': { // Relocatable Constant
2167 // These operands are interested in values of the form (GV+C), where C may
2168 // be folded in as an offset of GV, or it may be explicitly added. Also, it
2169 // is possible and fine if either GV or C are missing.
2170 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2171 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2173 // If we have "(add GV, C)", pull out GV/C
2174 if (Op.getOpcode() == ISD::ADD) {
2175 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2176 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2178 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2179 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2182 C = nullptr, GA = nullptr;
2185 // If we find a valid operand, map to the TargetXXX version so that the
2186 // value itself doesn't get selected.
2187 if (GA) { // Either &GV or &GV+C
2188 if (ConstraintLetter != 'n') {
2189 int64_t Offs = GA->getOffset();
2190 if (C) Offs += C->getZExtValue();
2191 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
2192 C ? SDLoc(C) : SDLoc(),
2193 Op.getValueType(), Offs));
2197 if (C) { // just C, no GV.
2198 // Simple constants are not allowed for 's'.
2199 if (ConstraintLetter != 's') {
2200 // gcc prints these as sign extended. Sign extend value to 64 bits
2201 // now; without this it would get ZExt'd later in
2202 // ScheduleDAGSDNodes::EmitNode, which is very generic.
2203 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
2204 SDLoc(C), MVT::i64));
2213 std::pair<unsigned, const TargetRegisterClass *>
2214 TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *RI,
2215 const std::string &Constraint,
2217 if (Constraint.empty() || Constraint[0] != '{')
2218 return std::make_pair(0u, static_cast<TargetRegisterClass*>(nullptr));
2219 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2221 // Remove the braces from around the name.
2222 StringRef RegName(Constraint.data()+1, Constraint.size()-2);
2224 std::pair<unsigned, const TargetRegisterClass*> R =
2225 std::make_pair(0u, static_cast<const TargetRegisterClass*>(nullptr));
2227 // Figure out which register class contains this reg.
2228 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
2229 E = RI->regclass_end(); RCI != E; ++RCI) {
2230 const TargetRegisterClass *RC = *RCI;
2232 // If none of the value types for this register class are valid, we
2233 // can't use it. For example, 64-bit reg classes on 32-bit targets.
2237 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2239 if (RegName.equals_lower(RI->getName(*I))) {
2240 std::pair<unsigned, const TargetRegisterClass*> S =
2241 std::make_pair(*I, RC);
2243 // If this register class has the requested value type, return it,
2244 // otherwise keep searching and return the first class found
2245 // if no other is found which explicitly has the requested type.
2246 if (RC->hasType(VT))
2257 //===----------------------------------------------------------------------===//
2258 // Constraint Selection.
2260 /// isMatchingInputConstraint - Return true of this is an input operand that is
2261 /// a matching constraint like "4".
2262 bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
2263 assert(!ConstraintCode.empty() && "No known constraint!");
2264 return isdigit(static_cast<unsigned char>(ConstraintCode[0]));
2267 /// getMatchedOperand - If this is an input matching constraint, this method
2268 /// returns the output operand it matches.
2269 unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2270 assert(!ConstraintCode.empty() && "No known constraint!");
2271 return atoi(ConstraintCode.c_str());
2275 /// ParseConstraints - Split up the constraint string from the inline
2276 /// assembly value into the specific constraints and their prefixes,
2277 /// and also tie in the associated operand values.
2278 /// If this returns an empty vector, and if the constraint string itself
2279 /// isn't empty, there was an error parsing.
2280 TargetLowering::AsmOperandInfoVector
2281 TargetLowering::ParseConstraints(const TargetRegisterInfo *TRI,
2282 ImmutableCallSite CS) const {
2283 /// ConstraintOperands - Information about all of the constraints.
2284 AsmOperandInfoVector ConstraintOperands;
2285 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
2286 unsigned maCount = 0; // Largest number of multiple alternative constraints.
2288 // Do a prepass over the constraints, canonicalizing them, and building up the
2289 // ConstraintOperands list.
2290 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
2291 unsigned ResNo = 0; // ResNo - The result number of the next output.
2293 for (InlineAsm::ConstraintInfo &CI : IA->ParseConstraints()) {
2294 ConstraintOperands.emplace_back(std::move(CI));
2295 AsmOperandInfo &OpInfo = ConstraintOperands.back();
2297 // Update multiple alternative constraint count.
2298 if (OpInfo.multipleAlternatives.size() > maCount)
2299 maCount = OpInfo.multipleAlternatives.size();
2301 OpInfo.ConstraintVT = MVT::Other;
2303 // Compute the value type for each operand.
2304 switch (OpInfo.Type) {
2305 case InlineAsm::isOutput:
2306 // Indirect outputs just consume an argument.
2307 if (OpInfo.isIndirect) {
2308 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2312 // The return value of the call is this value. As such, there is no
2313 // corresponding argument.
2314 assert(!CS.getType()->isVoidTy() &&
2316 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
2317 OpInfo.ConstraintVT = getSimpleValueType(STy->getElementType(ResNo));
2319 assert(ResNo == 0 && "Asm only has one result!");
2320 OpInfo.ConstraintVT = getSimpleValueType(CS.getType());
2324 case InlineAsm::isInput:
2325 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2327 case InlineAsm::isClobber:
2332 if (OpInfo.CallOperandVal) {
2333 llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
2334 if (OpInfo.isIndirect) {
2335 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
2337 report_fatal_error("Indirect operand for inline asm not a pointer!");
2338 OpTy = PtrTy->getElementType();
2341 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
2342 if (StructType *STy = dyn_cast<StructType>(OpTy))
2343 if (STy->getNumElements() == 1)
2344 OpTy = STy->getElementType(0);
2346 // If OpTy is not a single value, it may be a struct/union that we
2347 // can tile with integers.
2348 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
2349 unsigned BitSize = getDataLayout()->getTypeSizeInBits(OpTy);
2358 OpInfo.ConstraintVT =
2359 MVT::getVT(IntegerType::get(OpTy->getContext(), BitSize), true);
2362 } else if (PointerType *PT = dyn_cast<PointerType>(OpTy)) {
2364 = getDataLayout()->getPointerSizeInBits(PT->getAddressSpace());
2365 OpInfo.ConstraintVT = MVT::getIntegerVT(PtrSize);
2367 OpInfo.ConstraintVT = MVT::getVT(OpTy, true);
2372 // If we have multiple alternative constraints, select the best alternative.
2373 if (!ConstraintOperands.empty()) {
2375 unsigned bestMAIndex = 0;
2376 int bestWeight = -1;
2377 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match.
2380 // Compute the sums of the weights for each alternative, keeping track
2381 // of the best (highest weight) one so far.
2382 for (maIndex = 0; maIndex < maCount; ++maIndex) {
2384 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2385 cIndex != eIndex; ++cIndex) {
2386 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2387 if (OpInfo.Type == InlineAsm::isClobber)
2390 // If this is an output operand with a matching input operand,
2391 // look up the matching input. If their types mismatch, e.g. one
2392 // is an integer, the other is floating point, or their sizes are
2393 // different, flag it as an maCantMatch.
2394 if (OpInfo.hasMatchingInput()) {
2395 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2396 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2397 if ((OpInfo.ConstraintVT.isInteger() !=
2398 Input.ConstraintVT.isInteger()) ||
2399 (OpInfo.ConstraintVT.getSizeInBits() !=
2400 Input.ConstraintVT.getSizeInBits())) {
2401 weightSum = -1; // Can't match.
2406 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
2411 weightSum += weight;
2414 if (weightSum > bestWeight) {
2415 bestWeight = weightSum;
2416 bestMAIndex = maIndex;
2420 // Now select chosen alternative in each constraint.
2421 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2422 cIndex != eIndex; ++cIndex) {
2423 AsmOperandInfo& cInfo = ConstraintOperands[cIndex];
2424 if (cInfo.Type == InlineAsm::isClobber)
2426 cInfo.selectAlternative(bestMAIndex);
2431 // Check and hook up tied operands, choose constraint code to use.
2432 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2433 cIndex != eIndex; ++cIndex) {
2434 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2436 // If this is an output operand with a matching input operand, look up the
2437 // matching input. If their types mismatch, e.g. one is an integer, the
2438 // other is floating point, or their sizes are different, flag it as an
2440 if (OpInfo.hasMatchingInput()) {
2441 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2443 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2444 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
2445 getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
2446 OpInfo.ConstraintVT);
2447 std::pair<unsigned, const TargetRegisterClass *> InputRC =
2448 getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
2449 Input.ConstraintVT);
2450 if ((OpInfo.ConstraintVT.isInteger() !=
2451 Input.ConstraintVT.isInteger()) ||
2452 (MatchRC.second != InputRC.second)) {
2453 report_fatal_error("Unsupported asm: input constraint"
2454 " with a matching output constraint of"
2455 " incompatible type!");
2462 return ConstraintOperands;
2466 /// getConstraintGenerality - Return an integer indicating how general CT
2468 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
2470 case TargetLowering::C_Other:
2471 case TargetLowering::C_Unknown:
2473 case TargetLowering::C_Register:
2475 case TargetLowering::C_RegisterClass:
2477 case TargetLowering::C_Memory:
2480 llvm_unreachable("Invalid constraint type");
2483 /// Examine constraint type and operand type and determine a weight value.
2484 /// This object must already have been set up with the operand type
2485 /// and the current alternative constraint selected.
2486 TargetLowering::ConstraintWeight
2487 TargetLowering::getMultipleConstraintMatchWeight(
2488 AsmOperandInfo &info, int maIndex) const {
2489 InlineAsm::ConstraintCodeVector *rCodes;
2490 if (maIndex >= (int)info.multipleAlternatives.size())
2491 rCodes = &info.Codes;
2493 rCodes = &info.multipleAlternatives[maIndex].Codes;
2494 ConstraintWeight BestWeight = CW_Invalid;
2496 // Loop over the options, keeping track of the most general one.
2497 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
2498 ConstraintWeight weight =
2499 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
2500 if (weight > BestWeight)
2501 BestWeight = weight;
2507 /// Examine constraint type and operand type and determine a weight value.
2508 /// This object must already have been set up with the operand type
2509 /// and the current alternative constraint selected.
2510 TargetLowering::ConstraintWeight
2511 TargetLowering::getSingleConstraintMatchWeight(
2512 AsmOperandInfo &info, const char *constraint) const {
2513 ConstraintWeight weight = CW_Invalid;
2514 Value *CallOperandVal = info.CallOperandVal;
2515 // If we don't have a value, we can't do a match,
2516 // but allow it at the lowest weight.
2517 if (!CallOperandVal)
2519 // Look at the constraint type.
2520 switch (*constraint) {
2521 case 'i': // immediate integer.
2522 case 'n': // immediate integer with a known value.
2523 if (isa<ConstantInt>(CallOperandVal))
2524 weight = CW_Constant;
2526 case 's': // non-explicit intregal immediate.
2527 if (isa<GlobalValue>(CallOperandVal))
2528 weight = CW_Constant;
2530 case 'E': // immediate float if host format.
2531 case 'F': // immediate float.
2532 if (isa<ConstantFP>(CallOperandVal))
2533 weight = CW_Constant;
2535 case '<': // memory operand with autodecrement.
2536 case '>': // memory operand with autoincrement.
2537 case 'm': // memory operand.
2538 case 'o': // offsettable memory operand
2539 case 'V': // non-offsettable memory operand
2542 case 'r': // general register.
2543 case 'g': // general register, memory operand or immediate integer.
2544 // note: Clang converts "g" to "imr".
2545 if (CallOperandVal->getType()->isIntegerTy())
2546 weight = CW_Register;
2548 case 'X': // any operand.
2550 weight = CW_Default;
2556 /// ChooseConstraint - If there are multiple different constraints that we
2557 /// could pick for this operand (e.g. "imr") try to pick the 'best' one.
2558 /// This is somewhat tricky: constraints fall into four classes:
2559 /// Other -> immediates and magic values
2560 /// Register -> one specific register
2561 /// RegisterClass -> a group of regs
2562 /// Memory -> memory
2563 /// Ideally, we would pick the most specific constraint possible: if we have
2564 /// something that fits into a register, we would pick it. The problem here
2565 /// is that if we have something that could either be in a register or in
2566 /// memory that use of the register could cause selection of *other*
2567 /// operands to fail: they might only succeed if we pick memory. Because of
2568 /// this the heuristic we use is:
2570 /// 1) If there is an 'other' constraint, and if the operand is valid for
2571 /// that constraint, use it. This makes us take advantage of 'i'
2572 /// constraints when available.
2573 /// 2) Otherwise, pick the most general constraint present. This prefers
2574 /// 'm' over 'r', for example.
2576 static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
2577 const TargetLowering &TLI,
2578 SDValue Op, SelectionDAG *DAG) {
2579 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
2580 unsigned BestIdx = 0;
2581 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
2582 int BestGenerality = -1;
2584 // Loop over the options, keeping track of the most general one.
2585 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
2586 TargetLowering::ConstraintType CType =
2587 TLI.getConstraintType(OpInfo.Codes[i]);
2589 // If this is an 'other' constraint, see if the operand is valid for it.
2590 // For example, on X86 we might have an 'rI' constraint. If the operand
2591 // is an integer in the range [0..31] we want to use I (saving a load
2592 // of a register), otherwise we must use 'r'.
2593 if (CType == TargetLowering::C_Other && Op.getNode()) {
2594 assert(OpInfo.Codes[i].size() == 1 &&
2595 "Unhandled multi-letter 'other' constraint");
2596 std::vector<SDValue> ResultOps;
2597 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i],
2599 if (!ResultOps.empty()) {
2606 // Things with matching constraints can only be registers, per gcc
2607 // documentation. This mainly affects "g" constraints.
2608 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
2611 // This constraint letter is more general than the previous one, use it.
2612 int Generality = getConstraintGenerality(CType);
2613 if (Generality > BestGenerality) {
2616 BestGenerality = Generality;
2620 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
2621 OpInfo.ConstraintType = BestType;
2624 /// ComputeConstraintToUse - Determines the constraint code and constraint
2625 /// type to use for the specific AsmOperandInfo, setting
2626 /// OpInfo.ConstraintCode and OpInfo.ConstraintType.
2627 void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2629 SelectionDAG *DAG) const {
2630 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
2632 // Single-letter constraints ('r') are very common.
2633 if (OpInfo.Codes.size() == 1) {
2634 OpInfo.ConstraintCode = OpInfo.Codes[0];
2635 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2637 ChooseConstraint(OpInfo, *this, Op, DAG);
2640 // 'X' matches anything.
2641 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
2642 // Labels and constants are handled elsewhere ('X' is the only thing
2643 // that matches labels). For Functions, the type here is the type of
2644 // the result, which is not what we want to look at; leave them alone.
2645 Value *v = OpInfo.CallOperandVal;
2646 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
2647 OpInfo.CallOperandVal = v;
2651 // Otherwise, try to resolve it to something we know about by looking at
2652 // the actual operand type.
2653 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
2654 OpInfo.ConstraintCode = Repl;
2655 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2660 /// \brief Given an exact SDIV by a constant, create a multiplication
2661 /// with the multiplicative inverse of the constant.
2662 SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl,
2663 SelectionDAG &DAG) const {
2664 ConstantSDNode *C = cast<ConstantSDNode>(Op2);
2665 APInt d = C->getAPIntValue();
2666 assert(d != 0 && "Division by zero!");
2668 // Shift the value upfront if it is even, so the LSB is one.
2669 unsigned ShAmt = d.countTrailingZeros();
2671 // TODO: For UDIV use SRL instead of SRA.
2673 DAG.getConstant(ShAmt, dl, getShiftAmountTy(Op1.getValueType()));
2674 Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt, false, false,
2679 // Calculate the multiplicative inverse, using Newton's method.
2681 while ((t = d*xn) != 1)
2682 xn *= APInt(d.getBitWidth(), 2) - t;
2684 Op2 = DAG.getConstant(xn, dl, Op1.getValueType());
2685 return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
2688 /// \brief Given an ISD::SDIV node expressing a divide by constant,
2689 /// return a DAG expression to select that will generate the same value by
2690 /// multiplying by a magic number.
2691 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
2692 SDValue TargetLowering::BuildSDIV(SDNode *N, const APInt &Divisor,
2693 SelectionDAG &DAG, bool IsAfterLegalization,
2694 std::vector<SDNode *> *Created) const {
2695 assert(Created && "No vector to hold sdiv ops.");
2697 EVT VT = N->getValueType(0);
2700 // Check to see if we can do this.
2701 // FIXME: We should be more aggressive here.
2702 if (!isTypeLegal(VT))
2705 APInt::ms magics = Divisor.magic();
2707 // Multiply the numerator (operand 0) by the magic value
2708 // FIXME: We should support doing a MUL in a wider type
2710 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) :
2711 isOperationLegalOrCustom(ISD::MULHS, VT))
2712 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
2713 DAG.getConstant(magics.m, dl, VT));
2714 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
2715 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
2716 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
2718 DAG.getConstant(magics.m, dl, VT)).getNode(), 1);
2720 return SDValue(); // No mulhs or equvialent
2721 // If d > 0 and m < 0, add the numerator
2722 if (Divisor.isStrictlyPositive() && magics.m.isNegative()) {
2723 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
2724 Created->push_back(Q.getNode());
2726 // If d < 0 and m > 0, subtract the numerator.
2727 if (Divisor.isNegative() && magics.m.isStrictlyPositive()) {
2728 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
2729 Created->push_back(Q.getNode());
2731 // Shift right algebraic if shift value is nonzero
2733 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
2734 DAG.getConstant(magics.s, dl,
2735 getShiftAmountTy(Q.getValueType())));
2736 Created->push_back(Q.getNode());
2738 // Extract the sign bit and add it to the quotient
2739 SDValue T = DAG.getNode(ISD::SRL, dl, VT, Q,
2740 DAG.getConstant(VT.getScalarSizeInBits() - 1, dl,
2741 getShiftAmountTy(Q.getValueType())));
2742 Created->push_back(T.getNode());
2743 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
2746 /// \brief Given an ISD::UDIV node expressing a divide by constant,
2747 /// return a DAG expression to select that will generate the same value by
2748 /// multiplying by a magic number.
2749 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
2750 SDValue TargetLowering::BuildUDIV(SDNode *N, const APInt &Divisor,
2751 SelectionDAG &DAG, bool IsAfterLegalization,
2752 std::vector<SDNode *> *Created) const {
2753 assert(Created && "No vector to hold udiv ops.");
2755 EVT VT = N->getValueType(0);
2758 // Check to see if we can do this.
2759 // FIXME: We should be more aggressive here.
2760 if (!isTypeLegal(VT))
2763 // FIXME: We should use a narrower constant when the upper
2764 // bits are known to be zero.
2765 APInt::mu magics = Divisor.magicu();
2767 SDValue Q = N->getOperand(0);
2769 // If the divisor is even, we can avoid using the expensive fixup by shifting
2770 // the divided value upfront.
2771 if (magics.a != 0 && !Divisor[0]) {
2772 unsigned Shift = Divisor.countTrailingZeros();
2773 Q = DAG.getNode(ISD::SRL, dl, VT, Q,
2774 DAG.getConstant(Shift, dl,
2775 getShiftAmountTy(Q.getValueType())));
2776 Created->push_back(Q.getNode());
2778 // Get magic number for the shifted divisor.
2779 magics = Divisor.lshr(Shift).magicu(Shift);
2780 assert(magics.a == 0 && "Should use cheap fixup now");
2783 // Multiply the numerator (operand 0) by the magic value
2784 // FIXME: We should support doing a MUL in a wider type
2785 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) :
2786 isOperationLegalOrCustom(ISD::MULHU, VT))
2787 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, dl, VT));
2788 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) :
2789 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
2790 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
2791 DAG.getConstant(magics.m, dl, VT)).getNode(), 1);
2793 return SDValue(); // No mulhu or equvialent
2795 Created->push_back(Q.getNode());
2797 if (magics.a == 0) {
2798 assert(magics.s < Divisor.getBitWidth() &&
2799 "We shouldn't generate an undefined shift!");
2800 return DAG.getNode(ISD::SRL, dl, VT, Q,
2801 DAG.getConstant(magics.s, dl,
2802 getShiftAmountTy(Q.getValueType())));
2804 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
2805 Created->push_back(NPQ.getNode());
2806 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
2807 DAG.getConstant(1, dl,
2808 getShiftAmountTy(NPQ.getValueType())));
2809 Created->push_back(NPQ.getNode());
2810 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
2811 Created->push_back(NPQ.getNode());
2812 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
2813 DAG.getConstant(magics.s - 1, dl,
2814 getShiftAmountTy(NPQ.getValueType())));
2818 bool TargetLowering::
2819 verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const {
2820 if (!isa<ConstantSDNode>(Op.getOperand(0))) {
2821 DAG.getContext()->emitError("argument to '__builtin_return_address' must "
2822 "be a constant integer");
2829 //===----------------------------------------------------------------------===//
2830 // Legalization Utilities
2831 //===----------------------------------------------------------------------===//
2833 bool TargetLowering::expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
2834 SelectionDAG &DAG, SDValue LL, SDValue LH,
2835 SDValue RL, SDValue RH) const {
2836 EVT VT = N->getValueType(0);
2839 bool HasMULHS = isOperationLegalOrCustom(ISD::MULHS, HiLoVT);
2840 bool HasMULHU = isOperationLegalOrCustom(ISD::MULHU, HiLoVT);
2841 bool HasSMUL_LOHI = isOperationLegalOrCustom(ISD::SMUL_LOHI, HiLoVT);
2842 bool HasUMUL_LOHI = isOperationLegalOrCustom(ISD::UMUL_LOHI, HiLoVT);
2843 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
2844 unsigned OuterBitSize = VT.getSizeInBits();
2845 unsigned InnerBitSize = HiLoVT.getSizeInBits();
2846 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
2847 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
2849 // LL, LH, RL, and RH must be either all NULL or all set to a value.
2850 assert((LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) ||
2851 (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode()));
2853 if (!LL.getNode() && !RL.getNode() &&
2854 isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) {
2855 LL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, N->getOperand(0));
2856 RL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, N->getOperand(1));
2862 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
2863 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
2864 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
2865 // The inputs are both zero-extended.
2867 // We can emit a umul_lohi.
2868 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(HiLoVT, HiLoVT), LL,
2870 Hi = SDValue(Lo.getNode(), 1);
2874 // We can emit a mulhu+mul.
2875 Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2876 Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL);
2880 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
2881 // The input values are both sign-extended.
2883 // We can emit a smul_lohi.
2884 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(HiLoVT, HiLoVT), LL,
2886 Hi = SDValue(Lo.getNode(), 1);
2890 // We can emit a mulhs+mul.
2891 Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2892 Hi = DAG.getNode(ISD::MULHS, dl, HiLoVT, LL, RL);
2897 if (!LH.getNode() && !RH.getNode() &&
2898 isOperationLegalOrCustom(ISD::SRL, VT) &&
2899 isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) {
2900 unsigned ShiftAmt = VT.getSizeInBits() - HiLoVT.getSizeInBits();
2901 SDValue Shift = DAG.getConstant(ShiftAmt, dl, getShiftAmountTy(VT));
2902 LH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(0), Shift);
2903 LH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LH);
2904 RH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(1), Shift);
2905 RH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RH);
2912 // Lo,Hi = umul LHS, RHS.
2913 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
2914 DAG.getVTList(HiLoVT, HiLoVT), LL, RL);
2916 Hi = UMulLOHI.getValue(1);
2917 RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
2918 LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
2919 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH);
2920 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);
2924 Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2925 Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL);
2926 RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
2927 LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
2928 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH);
2929 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);
2936 bool TargetLowering::expandFP_TO_SINT(SDNode *Node, SDValue &Result,
2937 SelectionDAG &DAG) const {
2938 EVT VT = Node->getOperand(0).getValueType();
2939 EVT NVT = Node->getValueType(0);
2940 SDLoc dl(SDValue(Node, 0));
2942 // FIXME: Only f32 to i64 conversions are supported.
2943 if (VT != MVT::f32 || NVT != MVT::i64)
2946 // Expand f32 -> i64 conversion
2947 // This algorithm comes from compiler-rt's implementation of fixsfdi:
2948 // https://github.com/llvm-mirror/compiler-rt/blob/master/lib/builtins/fixsfdi.c
2949 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(),
2950 VT.getSizeInBits());
2951 SDValue ExponentMask = DAG.getConstant(0x7F800000, dl, IntVT);
2952 SDValue ExponentLoBit = DAG.getConstant(23, dl, IntVT);
2953 SDValue Bias = DAG.getConstant(127, dl, IntVT);
2954 SDValue SignMask = DAG.getConstant(APInt::getSignBit(VT.getSizeInBits()), dl,
2956 SDValue SignLowBit = DAG.getConstant(VT.getSizeInBits() - 1, dl, IntVT);
2957 SDValue MantissaMask = DAG.getConstant(0x007FFFFF, dl, IntVT);
2959 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, IntVT, Node->getOperand(0));
2961 SDValue ExponentBits = DAG.getNode(ISD::SRL, dl, IntVT,
2962 DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask),
2963 DAG.getZExtOrTrunc(ExponentLoBit, dl, getShiftAmountTy(IntVT)));
2964 SDValue Exponent = DAG.getNode(ISD::SUB, dl, IntVT, ExponentBits, Bias);
2966 SDValue Sign = DAG.getNode(ISD::SRA, dl, IntVT,
2967 DAG.getNode(ISD::AND, dl, IntVT, Bits, SignMask),
2968 DAG.getZExtOrTrunc(SignLowBit, dl, getShiftAmountTy(IntVT)));
2969 Sign = DAG.getSExtOrTrunc(Sign, dl, NVT);
2971 SDValue R = DAG.getNode(ISD::OR, dl, IntVT,
2972 DAG.getNode(ISD::AND, dl, IntVT, Bits, MantissaMask),
2973 DAG.getConstant(0x00800000, dl, IntVT));
2975 R = DAG.getZExtOrTrunc(R, dl, NVT);
2978 R = DAG.getSelectCC(dl, Exponent, ExponentLoBit,
2979 DAG.getNode(ISD::SHL, dl, NVT, R,
2981 DAG.getNode(ISD::SUB, dl, IntVT, Exponent, ExponentLoBit),
2982 dl, getShiftAmountTy(IntVT))),
2983 DAG.getNode(ISD::SRL, dl, NVT, R,
2985 DAG.getNode(ISD::SUB, dl, IntVT, ExponentLoBit, Exponent),
2986 dl, getShiftAmountTy(IntVT))),
2989 SDValue Ret = DAG.getNode(ISD::SUB, dl, NVT,
2990 DAG.getNode(ISD::XOR, dl, NVT, R, Sign),
2993 Result = DAG.getSelectCC(dl, Exponent, DAG.getConstant(0, dl, IntVT),
2994 DAG.getConstant(0, dl, NVT), Ret, ISD::SETLT);