1 //===---------- SplitKit.cpp - Toolkit for splitting live ranges ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SplitAnalysis class as well as mutator functions for
11 // live range splitting.
13 //===----------------------------------------------------------------------===//
16 #include "llvm/ADT/Statistic.h"
17 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
18 #include "llvm/CodeGen/LiveRangeEdit.h"
19 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
20 #include "llvm/CodeGen/MachineDominators.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineLoopInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/VirtRegMap.h"
25 #include "llvm/Support/Debug.h"
26 #include "llvm/Support/MathExtras.h"
27 #include "llvm/Support/raw_ostream.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetMachine.h"
33 #define DEBUG_TYPE "regalloc"
35 STATISTIC(NumFinished, "Number of splits finished");
36 STATISTIC(NumSimple, "Number of splits that were simple");
37 STATISTIC(NumCopies, "Number of copies inserted for splitting");
38 STATISTIC(NumRemats, "Number of rematerialized defs for splitting");
39 STATISTIC(NumRepairs, "Number of invalid live ranges repaired");
41 //===----------------------------------------------------------------------===//
42 // Last Insert Point Analysis
43 //===----------------------------------------------------------------------===//
45 InsertPointAnalysis::InsertPointAnalysis(const LiveIntervals &lis,
47 : LIS(lis), LastInsertPoint(BBNum) {}
50 InsertPointAnalysis::computeLastInsertPoint(const LiveInterval &CurLI,
51 const MachineBasicBlock &MBB) {
52 unsigned Num = MBB.getNumber();
53 std::pair<SlotIndex, SlotIndex> &LIP = LastInsertPoint[Num];
54 SlotIndex MBBEnd = LIS.getMBBEndIdx(&MBB);
56 SmallVector<const MachineBasicBlock *, 1> EHPadSuccessors;
57 for (const MachineBasicBlock *SMBB : MBB.successors())
59 EHPadSuccessors.push_back(SMBB);
61 // Compute insert points on the first call. The pair is independent of the
62 // current live interval.
63 if (!LIP.first.isValid()) {
64 MachineBasicBlock::const_iterator FirstTerm = MBB.getFirstTerminator();
65 if (FirstTerm == MBB.end())
68 LIP.first = LIS.getInstructionIndex(*FirstTerm);
70 // If there is a landing pad successor, also find the call instruction.
71 if (EHPadSuccessors.empty())
73 // There may not be a call instruction (?) in which case we ignore LPad.
74 LIP.second = LIP.first;
75 for (MachineBasicBlock::const_iterator I = MBB.end(), E = MBB.begin();
79 LIP.second = LIS.getInstructionIndex(*I);
85 // If CurLI is live into a landing pad successor, move the last insert point
86 // back to the call that may throw.
90 if (none_of(EHPadSuccessors, [&](const MachineBasicBlock *EHPad) {
91 return LIS.isLiveInToMBB(CurLI, EHPad);
95 // Find the value leaving MBB.
96 const VNInfo *VNI = CurLI.getVNInfoBefore(MBBEnd);
100 // If the value leaving MBB was defined after the call in MBB, it can't
101 // really be live-in to the landing pad. This can happen if the landing pad
102 // has a PHI, and this register is undef on the exceptional edge.
103 // <rdar://problem/10664933>
104 if (!SlotIndex::isEarlierInstr(VNI->def, LIP.second) && VNI->def < MBBEnd)
107 // Value is properly live-in to the landing pad.
108 // Only allow inserts before the call.
112 MachineBasicBlock::iterator
113 InsertPointAnalysis::getLastInsertPointIter(const LiveInterval &CurLI,
114 MachineBasicBlock &MBB) {
115 SlotIndex LIP = getLastInsertPoint(CurLI, MBB);
116 if (LIP == LIS.getMBBEndIdx(&MBB))
118 return LIS.getInstructionFromIndex(LIP);
121 //===----------------------------------------------------------------------===//
123 //===----------------------------------------------------------------------===//
125 SplitAnalysis::SplitAnalysis(const VirtRegMap &vrm, const LiveIntervals &lis,
126 const MachineLoopInfo &mli)
127 : MF(vrm.getMachineFunction()), VRM(vrm), LIS(lis), Loops(mli),
128 TII(*MF.getSubtarget().getInstrInfo()), CurLI(nullptr),
129 IPA(lis, MF.getNumBlockIDs()) {}
131 void SplitAnalysis::clear() {
134 ThroughBlocks.clear();
136 DidRepairRange = false;
139 /// analyzeUses - Count instructions, basic blocks, and loops using CurLI.
140 void SplitAnalysis::analyzeUses() {
141 assert(UseSlots.empty() && "Call clear first");
143 // First get all the defs from the interval values. This provides the correct
144 // slots for early clobbers.
145 for (const VNInfo *VNI : CurLI->valnos)
146 if (!VNI->isPHIDef() && !VNI->isUnused())
147 UseSlots.push_back(VNI->def);
149 // Get use slots form the use-def chain.
150 const MachineRegisterInfo &MRI = MF.getRegInfo();
151 for (MachineOperand &MO : MRI.use_nodbg_operands(CurLI->reg))
153 UseSlots.push_back(LIS.getInstructionIndex(*MO.getParent()).getRegSlot());
155 array_pod_sort(UseSlots.begin(), UseSlots.end());
157 // Remove duplicates, keeping the smaller slot for each instruction.
158 // That is what we want for early clobbers.
159 UseSlots.erase(std::unique(UseSlots.begin(), UseSlots.end(),
160 SlotIndex::isSameInstr),
163 // Compute per-live block info.
164 if (!calcLiveBlockInfo()) {
165 // FIXME: calcLiveBlockInfo found inconsistencies in the live range.
166 // I am looking at you, RegisterCoalescer!
167 DidRepairRange = true;
169 DEBUG(dbgs() << "*** Fixing inconsistent live interval! ***\n");
170 const_cast<LiveIntervals&>(LIS)
171 .shrinkToUses(const_cast<LiveInterval*>(CurLI));
173 ThroughBlocks.clear();
174 bool fixed = calcLiveBlockInfo();
176 assert(fixed && "Couldn't fix broken live interval");
179 DEBUG(dbgs() << "Analyze counted "
180 << UseSlots.size() << " instrs in "
181 << UseBlocks.size() << " blocks, through "
182 << NumThroughBlocks << " blocks.\n");
185 /// calcLiveBlockInfo - Fill the LiveBlocks array with information about blocks
186 /// where CurLI is live.
187 bool SplitAnalysis::calcLiveBlockInfo() {
188 ThroughBlocks.resize(MF.getNumBlockIDs());
189 NumThroughBlocks = NumGapBlocks = 0;
193 LiveInterval::const_iterator LVI = CurLI->begin();
194 LiveInterval::const_iterator LVE = CurLI->end();
196 SmallVectorImpl<SlotIndex>::const_iterator UseI, UseE;
197 UseI = UseSlots.begin();
198 UseE = UseSlots.end();
200 // Loop over basic blocks where CurLI is live.
201 MachineFunction::iterator MFI =
202 LIS.getMBBFromIndex(LVI->start)->getIterator();
206 SlotIndex Start, Stop;
207 std::tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
209 // If the block contains no uses, the range must be live through. At one
210 // point, RegisterCoalescer could create dangling ranges that ended
212 if (UseI == UseE || *UseI >= Stop) {
214 ThroughBlocks.set(BI.MBB->getNumber());
215 // The range shouldn't end mid-block if there are no uses. This shouldn't
220 // This block has uses. Find the first and last uses in the block.
221 BI.FirstInstr = *UseI;
222 assert(BI.FirstInstr >= Start);
224 while (UseI != UseE && *UseI < Stop);
225 BI.LastInstr = UseI[-1];
226 assert(BI.LastInstr < Stop);
228 // LVI is the first live segment overlapping MBB.
229 BI.LiveIn = LVI->start <= Start;
231 // When not live in, the first use should be a def.
233 assert(LVI->start == LVI->valno->def && "Dangling Segment start");
234 assert(LVI->start == BI.FirstInstr && "First instr should be a def");
235 BI.FirstDef = BI.FirstInstr;
238 // Look for gaps in the live range.
240 while (LVI->end < Stop) {
241 SlotIndex LastStop = LVI->end;
242 if (++LVI == LVE || LVI->start >= Stop) {
244 BI.LastInstr = LastStop;
248 if (LastStop < LVI->start) {
249 // There is a gap in the live range. Create duplicate entries for the
250 // live-in snippet and the live-out snippet.
253 // Push the Live-in part.
255 UseBlocks.push_back(BI);
256 UseBlocks.back().LastInstr = LastStop;
258 // Set up BI for the live-out part.
261 BI.FirstInstr = BI.FirstDef = LVI->start;
264 // A Segment that starts in the middle of the block must be a def.
265 assert(LVI->start == LVI->valno->def && "Dangling Segment start");
267 BI.FirstDef = LVI->start;
270 UseBlocks.push_back(BI);
272 // LVI is now at LVE or LVI->end >= Stop.
277 // Live segment ends exactly at Stop. Move to the next segment.
278 if (LVI->end == Stop && ++LVI == LVE)
281 // Pick the next basic block.
282 if (LVI->start < Stop)
285 MFI = LIS.getMBBFromIndex(LVI->start)->getIterator();
288 assert(getNumLiveBlocks() == countLiveBlocks(CurLI) && "Bad block count");
292 unsigned SplitAnalysis::countLiveBlocks(const LiveInterval *cli) const {
295 LiveInterval *li = const_cast<LiveInterval*>(cli);
296 LiveInterval::iterator LVI = li->begin();
297 LiveInterval::iterator LVE = li->end();
300 // Loop over basic blocks where li is live.
301 MachineFunction::const_iterator MFI =
302 LIS.getMBBFromIndex(LVI->start)->getIterator();
303 SlotIndex Stop = LIS.getMBBEndIdx(&*MFI);
306 LVI = li->advanceTo(LVI, Stop);
311 Stop = LIS.getMBBEndIdx(&*MFI);
312 } while (Stop <= LVI->start);
316 bool SplitAnalysis::isOriginalEndpoint(SlotIndex Idx) const {
317 unsigned OrigReg = VRM.getOriginal(CurLI->reg);
318 const LiveInterval &Orig = LIS.getInterval(OrigReg);
319 assert(!Orig.empty() && "Splitting empty interval?");
320 LiveInterval::const_iterator I = Orig.find(Idx);
322 // Range containing Idx should begin at Idx.
323 if (I != Orig.end() && I->start <= Idx)
324 return I->start == Idx;
326 // Range does not contain Idx, previous must end at Idx.
327 return I != Orig.begin() && (--I)->end == Idx;
330 void SplitAnalysis::analyze(const LiveInterval *li) {
337 //===----------------------------------------------------------------------===//
339 //===----------------------------------------------------------------------===//
341 /// Create a new SplitEditor for editing the LiveInterval analyzed by SA.
342 SplitEditor::SplitEditor(SplitAnalysis &sa, AliasAnalysis &aa,
343 LiveIntervals &lis, VirtRegMap &vrm,
344 MachineDominatorTree &mdt,
345 MachineBlockFrequencyInfo &mbfi)
346 : SA(sa), AA(aa), LIS(lis), VRM(vrm),
347 MRI(vrm.getMachineFunction().getRegInfo()), MDT(mdt),
348 TII(*vrm.getMachineFunction().getSubtarget().getInstrInfo()),
349 TRI(*vrm.getMachineFunction().getSubtarget().getRegisterInfo()),
350 MBFI(mbfi), Edit(nullptr), OpenIdx(0), SpillMode(SM_Partition),
351 RegAssign(Allocator) {}
353 void SplitEditor::reset(LiveRangeEdit &LRE, ComplementSpillMode SM) {
360 // Reset the LiveRangeCalc instances needed for this spill mode.
361 LRCalc[0].reset(&VRM.getMachineFunction(), LIS.getSlotIndexes(), &MDT,
362 &LIS.getVNInfoAllocator());
364 LRCalc[1].reset(&VRM.getMachineFunction(), LIS.getSlotIndexes(), &MDT,
365 &LIS.getVNInfoAllocator());
367 // We don't need an AliasAnalysis since we will only be performing
368 // cheap-as-a-copy remats anyway.
369 Edit->anyRematerializable(nullptr);
372 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
373 LLVM_DUMP_METHOD void SplitEditor::dump() const {
374 if (RegAssign.empty()) {
375 dbgs() << " empty\n";
379 for (RegAssignMap::const_iterator I = RegAssign.begin(); I.valid(); ++I)
380 dbgs() << " [" << I.start() << ';' << I.stop() << "):" << I.value();
385 LiveInterval::SubRange &SplitEditor::getSubRangeForMask(LaneBitmask LM,
387 for (LiveInterval::SubRange &S : LI.subranges())
388 if (S.LaneMask == LM)
390 llvm_unreachable("SubRange for this mask not found");
393 void SplitEditor::addDeadDef(LiveInterval &LI, VNInfo *VNI, bool Original) {
394 if (!LI.hasSubRanges()) {
395 LI.createDeadDef(VNI);
399 SlotIndex Def = VNI->def;
401 // If we are transferring a def from the original interval, make sure
402 // to only update the subranges for which the original subranges had
403 // a def at this location.
404 for (LiveInterval::SubRange &S : LI.subranges()) {
405 auto &PS = getSubRangeForMask(S.LaneMask, Edit->getParent());
406 VNInfo *PV = PS.getVNInfoAt(Def);
407 if (PV != nullptr && PV->def == Def)
408 S.createDeadDef(Def, LIS.getVNInfoAllocator());
411 // This is a new def: either from rematerialization, or from an inserted
412 // copy. Since rematerialization can regenerate a definition of a sub-
413 // register, we need to check which subranges need to be updated.
414 const MachineInstr *DefMI = LIS.getInstructionFromIndex(Def);
415 assert(DefMI != nullptr);
417 for (const MachineOperand &DefOp : DefMI->defs()) {
418 unsigned R = DefOp.getReg();
421 if (unsigned SR = DefOp.getSubReg())
422 LM |= TRI.getSubRegIndexLaneMask(SR);
424 LM = MRI.getMaxLaneMaskForVReg(R);
428 for (LiveInterval::SubRange &S : LI.subranges())
429 if ((S.LaneMask & LM).any())
430 S.createDeadDef(Def, LIS.getVNInfoAllocator());
434 VNInfo *SplitEditor::defValue(unsigned RegIdx,
435 const VNInfo *ParentVNI,
438 assert(ParentVNI && "Mapping NULL value");
439 assert(Idx.isValid() && "Invalid SlotIndex");
440 assert(Edit->getParent().getVNInfoAt(Idx) == ParentVNI && "Bad Parent VNI");
441 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx));
443 // Create a new value.
444 VNInfo *VNI = LI->getNextValue(Idx, LIS.getVNInfoAllocator());
446 bool Force = LI->hasSubRanges();
447 ValueForcePair FP(Force ? nullptr : VNI, Force);
448 // Use insert for lookup, so we can add missing values with a second lookup.
449 std::pair<ValueMap::iterator, bool> InsP =
450 Values.insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->id), FP));
452 // This was the first time (RegIdx, ParentVNI) was mapped, and it is not
453 // forced. Keep it as a simple def without any liveness.
454 if (!Force && InsP.second)
457 // If the previous value was a simple mapping, add liveness for it now.
458 if (VNInfo *OldVNI = InsP.first->second.getPointer()) {
459 addDeadDef(*LI, OldVNI, Original);
461 // No longer a simple mapping. Switch to a complex mapping. If the
462 // interval has subranges, make it a forced mapping.
463 InsP.first->second = ValueForcePair(nullptr, Force);
466 // This is a complex mapping, add liveness for VNI
467 addDeadDef(*LI, VNI, Original);
471 void SplitEditor::forceRecompute(unsigned RegIdx, const VNInfo *ParentVNI) {
472 assert(ParentVNI && "Mapping NULL value");
473 ValueForcePair &VFP = Values[std::make_pair(RegIdx, ParentVNI->id)];
474 VNInfo *VNI = VFP.getPointer();
476 // ParentVNI was either unmapped or already complex mapped. Either way, just
477 // set the force bit.
483 // This was previously a single mapping. Make sure the old def is represented
484 // by a trivial live range.
485 addDeadDef(LIS.getInterval(Edit->get(RegIdx)), VNI, false);
487 // Mark as complex mapped, forced.
488 VFP = ValueForcePair(nullptr, true);
491 SlotIndex SplitEditor::buildSingleSubRegCopy(unsigned FromReg, unsigned ToReg,
492 MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore,
493 unsigned SubIdx, LiveInterval &DestLI, bool Late, SlotIndex Def) {
494 const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY);
495 bool FirstCopy = !Def.isValid();
496 MachineInstr *CopyMI = BuildMI(MBB, InsertBefore, DebugLoc(), Desc)
497 .addReg(ToReg, RegState::Define | getUndefRegState(FirstCopy)
498 | getInternalReadRegState(!FirstCopy), SubIdx)
499 .addReg(FromReg, 0, SubIdx);
501 BumpPtrAllocator &Allocator = LIS.getVNInfoAllocator();
503 SlotIndexes &Indexes = *LIS.getSlotIndexes();
504 Def = Indexes.insertMachineInstrInMaps(*CopyMI, Late).getRegSlot();
506 CopyMI->bundleWithPred();
508 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubIdx);
509 DestLI.refineSubRanges(Allocator, LaneMask,
510 [Def, &Allocator](LiveInterval::SubRange& SR) {
511 SR.createDeadDef(Def, Allocator);
516 SlotIndex SplitEditor::buildCopy(unsigned FromReg, unsigned ToReg,
517 LaneBitmask LaneMask, MachineBasicBlock &MBB,
518 MachineBasicBlock::iterator InsertBefore, bool Late, unsigned RegIdx) {
519 const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY);
520 if (LaneMask.all() || LaneMask == MRI.getMaxLaneMaskForVReg(FromReg)) {
521 // The full vreg is copied.
522 MachineInstr *CopyMI =
523 BuildMI(MBB, InsertBefore, DebugLoc(), Desc, ToReg).addReg(FromReg);
524 SlotIndexes &Indexes = *LIS.getSlotIndexes();
525 return Indexes.insertMachineInstrInMaps(*CopyMI, Late).getRegSlot();
528 // Only a subset of lanes needs to be copied. The following is a simple
529 // heuristic to construct a sequence of COPYs. We could add a target
530 // specific callback if this turns out to be suboptimal.
531 LiveInterval &DestLI = LIS.getInterval(Edit->get(RegIdx));
533 // First pass: Try to find a perfectly matching subregister index. If none
534 // exists find the one covering the most lanemask bits.
535 SmallVector<unsigned, 8> PossibleIndexes;
536 unsigned BestIdx = 0;
537 unsigned BestCover = 0;
538 const TargetRegisterClass *RC = MRI.getRegClass(FromReg);
539 assert(RC == MRI.getRegClass(ToReg) && "Should have same reg class");
540 for (unsigned Idx = 1, E = TRI.getNumSubRegIndices(); Idx < E; ++Idx) {
541 // Is this index even compatible with the given class?
542 if (TRI.getSubClassWithSubReg(RC, Idx) != RC)
544 LaneBitmask SubRegMask = TRI.getSubRegIndexLaneMask(Idx);
545 // Early exit if we found a perfect match.
546 if (SubRegMask == LaneMask) {
551 // The index must not cover any lanes outside \p LaneMask.
552 if ((SubRegMask & ~LaneMask).any())
555 unsigned PopCount = countPopulation(SubRegMask.getAsInteger());
556 PossibleIndexes.push_back(Idx);
557 if (PopCount > BestCover) {
558 BestCover = PopCount;
563 // Abort if we cannot possibly implement the COPY with the given indexes.
565 report_fatal_error("Impossible to implement partial COPY");
567 SlotIndex Def = buildSingleSubRegCopy(FromReg, ToReg, MBB, InsertBefore,
568 BestIdx, DestLI, Late, SlotIndex());
570 // Greedy heuristic: Keep iterating keeping the best covering subreg index
572 LaneBitmask LanesLeft = LaneMask & ~(TRI.getSubRegIndexLaneMask(BestIdx));
573 while (LanesLeft.any()) {
574 unsigned BestIdx = 0;
575 int BestCover = INT_MIN;
576 for (unsigned Idx : PossibleIndexes) {
577 LaneBitmask SubRegMask = TRI.getSubRegIndexLaneMask(Idx);
578 // Early exit if we found a perfect match.
579 if (SubRegMask == LanesLeft) {
584 // Try to cover as much of the remaining lanes as possible but
585 // as few of the already covered lanes as possible.
586 int Cover = countPopulation((SubRegMask & LanesLeft).getAsInteger())
587 - countPopulation((SubRegMask & ~LanesLeft).getAsInteger());
588 if (Cover > BestCover) {
595 report_fatal_error("Impossible to implement partial COPY");
597 buildSingleSubRegCopy(FromReg, ToReg, MBB, InsertBefore, BestIdx,
599 LanesLeft &= ~TRI.getSubRegIndexLaneMask(BestIdx);
605 VNInfo *SplitEditor::defFromParent(unsigned RegIdx,
608 MachineBasicBlock &MBB,
609 MachineBasicBlock::iterator I) {
611 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx));
613 // We may be trying to avoid interference that ends at a deleted instruction,
614 // so always begin RegIdx 0 early and all others late.
615 bool Late = RegIdx != 0;
617 // Attempt cheap-as-a-copy rematerialization.
618 unsigned Original = VRM.getOriginal(Edit->get(RegIdx));
619 LiveInterval &OrigLI = LIS.getInterval(Original);
620 VNInfo *OrigVNI = OrigLI.getVNInfoAt(UseIdx);
622 unsigned Reg = LI->reg;
623 bool DidRemat = false;
625 LiveRangeEdit::Remat RM(ParentVNI);
626 RM.OrigMI = LIS.getInstructionFromIndex(OrigVNI->def);
627 if (Edit->canRematerializeAt(RM, OrigVNI, UseIdx, true)) {
628 Def = Edit->rematerializeAt(MBB, I, Reg, RM, TRI, Late);
634 LaneBitmask LaneMask;
635 if (LI->hasSubRanges()) {
636 LaneMask = LaneBitmask::getNone();
637 for (LiveInterval::SubRange &S : LI->subranges())
638 LaneMask |= S.LaneMask;
640 LaneMask = LaneBitmask::getAll();
644 Def = buildCopy(Edit->getReg(), Reg, LaneMask, MBB, I, Late, RegIdx);
647 // Define the value in Reg.
648 return defValue(RegIdx, ParentVNI, Def, false);
651 /// Create a new virtual register and live interval.
652 unsigned SplitEditor::openIntv() {
653 // Create the complement as index 0.
655 Edit->createEmptyInterval();
657 // Create the open interval.
658 OpenIdx = Edit->size();
659 Edit->createEmptyInterval();
663 void SplitEditor::selectIntv(unsigned Idx) {
664 assert(Idx != 0 && "Cannot select the complement interval");
665 assert(Idx < Edit->size() && "Can only select previously opened interval");
666 DEBUG(dbgs() << " selectIntv " << OpenIdx << " -> " << Idx << '\n');
670 SlotIndex SplitEditor::enterIntvBefore(SlotIndex Idx) {
671 assert(OpenIdx && "openIntv not called before enterIntvBefore");
672 DEBUG(dbgs() << " enterIntvBefore " << Idx);
673 Idx = Idx.getBaseIndex();
674 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
676 DEBUG(dbgs() << ": not live\n");
679 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
680 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
681 assert(MI && "enterIntvBefore called with invalid index");
683 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(), MI);
687 SlotIndex SplitEditor::enterIntvAfter(SlotIndex Idx) {
688 assert(OpenIdx && "openIntv not called before enterIntvAfter");
689 DEBUG(dbgs() << " enterIntvAfter " << Idx);
690 Idx = Idx.getBoundaryIndex();
691 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
693 DEBUG(dbgs() << ": not live\n");
696 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
697 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
698 assert(MI && "enterIntvAfter called with invalid index");
700 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(),
701 std::next(MachineBasicBlock::iterator(MI)));
705 SlotIndex SplitEditor::enterIntvAtEnd(MachineBasicBlock &MBB) {
706 assert(OpenIdx && "openIntv not called before enterIntvAtEnd");
707 SlotIndex End = LIS.getMBBEndIdx(&MBB);
708 SlotIndex Last = End.getPrevSlot();
709 DEBUG(dbgs() << " enterIntvAtEnd BB#" << MBB.getNumber() << ", " << Last);
710 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Last);
712 DEBUG(dbgs() << ": not live\n");
715 DEBUG(dbgs() << ": valno " << ParentVNI->id);
716 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Last, MBB,
717 SA.getLastSplitPointIter(&MBB));
718 RegAssign.insert(VNI->def, End, OpenIdx);
723 /// useIntv - indicate that all instructions in MBB should use OpenLI.
724 void SplitEditor::useIntv(const MachineBasicBlock &MBB) {
725 useIntv(LIS.getMBBStartIdx(&MBB), LIS.getMBBEndIdx(&MBB));
728 void SplitEditor::useIntv(SlotIndex Start, SlotIndex End) {
729 assert(OpenIdx && "openIntv not called before useIntv");
730 DEBUG(dbgs() << " useIntv [" << Start << ';' << End << "):");
731 RegAssign.insert(Start, End, OpenIdx);
735 SlotIndex SplitEditor::leaveIntvAfter(SlotIndex Idx) {
736 assert(OpenIdx && "openIntv not called before leaveIntvAfter");
737 DEBUG(dbgs() << " leaveIntvAfter " << Idx);
739 // The interval must be live beyond the instruction at Idx.
740 SlotIndex Boundary = Idx.getBoundaryIndex();
741 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Boundary);
743 DEBUG(dbgs() << ": not live\n");
744 return Boundary.getNextSlot();
746 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
747 MachineInstr *MI = LIS.getInstructionFromIndex(Boundary);
748 assert(MI && "No instruction at index");
750 // In spill mode, make live ranges as short as possible by inserting the copy
751 // before MI. This is only possible if that instruction doesn't redefine the
752 // value. The inserted COPY is not a kill, and we don't need to recompute
753 // the source live range. The spiller also won't try to hoist this copy.
754 if (SpillMode && !SlotIndex::isSameInstr(ParentVNI->def, Idx) &&
755 MI->readsVirtualRegister(Edit->getReg())) {
756 forceRecompute(0, ParentVNI);
757 defFromParent(0, ParentVNI, Idx, *MI->getParent(), MI);
761 VNInfo *VNI = defFromParent(0, ParentVNI, Boundary, *MI->getParent(),
762 std::next(MachineBasicBlock::iterator(MI)));
766 SlotIndex SplitEditor::leaveIntvBefore(SlotIndex Idx) {
767 assert(OpenIdx && "openIntv not called before leaveIntvBefore");
768 DEBUG(dbgs() << " leaveIntvBefore " << Idx);
770 // The interval must be live into the instruction at Idx.
771 Idx = Idx.getBaseIndex();
772 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
774 DEBUG(dbgs() << ": not live\n");
775 return Idx.getNextSlot();
777 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
779 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
780 assert(MI && "No instruction at index");
781 VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(), MI);
785 SlotIndex SplitEditor::leaveIntvAtTop(MachineBasicBlock &MBB) {
786 assert(OpenIdx && "openIntv not called before leaveIntvAtTop");
787 SlotIndex Start = LIS.getMBBStartIdx(&MBB);
788 DEBUG(dbgs() << " leaveIntvAtTop BB#" << MBB.getNumber() << ", " << Start);
790 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
792 DEBUG(dbgs() << ": not live\n");
796 VNInfo *VNI = defFromParent(0, ParentVNI, Start, MBB,
797 MBB.SkipPHIsLabelsAndDebug(MBB.begin()));
798 RegAssign.insert(Start, VNI->def, OpenIdx);
803 void SplitEditor::overlapIntv(SlotIndex Start, SlotIndex End) {
804 assert(OpenIdx && "openIntv not called before overlapIntv");
805 const VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
806 assert(ParentVNI == Edit->getParent().getVNInfoBefore(End) &&
807 "Parent changes value in extended range");
808 assert(LIS.getMBBFromIndex(Start) == LIS.getMBBFromIndex(End) &&
809 "Range cannot span basic blocks");
811 // The complement interval will be extended as needed by LRCalc.extend().
813 forceRecompute(0, ParentVNI);
814 DEBUG(dbgs() << " overlapIntv [" << Start << ';' << End << "):");
815 RegAssign.insert(Start, End, OpenIdx);
819 //===----------------------------------------------------------------------===//
821 //===----------------------------------------------------------------------===//
823 void SplitEditor::removeBackCopies(SmallVectorImpl<VNInfo*> &Copies) {
824 LiveInterval *LI = &LIS.getInterval(Edit->get(0));
825 DEBUG(dbgs() << "Removing " << Copies.size() << " back-copies.\n");
826 RegAssignMap::iterator AssignI;
827 AssignI.setMap(RegAssign);
829 for (unsigned i = 0, e = Copies.size(); i != e; ++i) {
830 SlotIndex Def = Copies[i]->def;
831 MachineInstr *MI = LIS.getInstructionFromIndex(Def);
832 assert(MI && "No instruction for back-copy");
834 MachineBasicBlock *MBB = MI->getParent();
835 MachineBasicBlock::iterator MBBI(MI);
837 do AtBegin = MBBI == MBB->begin();
838 while (!AtBegin && (--MBBI)->isDebugValue());
840 DEBUG(dbgs() << "Removing " << Def << '\t' << *MI);
841 LIS.removeVRegDefAt(*LI, Def);
842 LIS.RemoveMachineInstrFromMaps(*MI);
843 MI->eraseFromParent();
845 // Adjust RegAssign if a register assignment is killed at Def. We want to
846 // avoid calculating the live range of the source register if possible.
847 AssignI.find(Def.getPrevSlot());
848 if (!AssignI.valid() || AssignI.start() >= Def)
850 // If MI doesn't kill the assigned register, just leave it.
851 if (AssignI.stop() != Def)
853 unsigned RegIdx = AssignI.value();
854 if (AtBegin || !MBBI->readsVirtualRegister(Edit->getReg())) {
855 DEBUG(dbgs() << " cannot find simple kill of RegIdx " << RegIdx << '\n');
856 forceRecompute(RegIdx, Edit->getParent().getVNInfoAt(Def));
858 SlotIndex Kill = LIS.getInstructionIndex(*MBBI).getRegSlot();
859 DEBUG(dbgs() << " move kill to " << Kill << '\t' << *MBBI);
860 AssignI.setStop(Kill);
866 SplitEditor::findShallowDominator(MachineBasicBlock *MBB,
867 MachineBasicBlock *DefMBB) {
870 assert(MDT.dominates(DefMBB, MBB) && "MBB must be dominated by the def.");
872 const MachineLoopInfo &Loops = SA.Loops;
873 const MachineLoop *DefLoop = Loops.getLoopFor(DefMBB);
874 MachineDomTreeNode *DefDomNode = MDT[DefMBB];
876 // Best candidate so far.
877 MachineBasicBlock *BestMBB = MBB;
878 unsigned BestDepth = UINT_MAX;
881 const MachineLoop *Loop = Loops.getLoopFor(MBB);
883 // MBB isn't in a loop, it doesn't get any better. All dominators have a
884 // higher frequency by definition.
886 DEBUG(dbgs() << "Def in BB#" << DefMBB->getNumber() << " dominates BB#"
887 << MBB->getNumber() << " at depth 0\n");
891 // We'll never be able to exit the DefLoop.
892 if (Loop == DefLoop) {
893 DEBUG(dbgs() << "Def in BB#" << DefMBB->getNumber() << " dominates BB#"
894 << MBB->getNumber() << " in the same loop\n");
898 // Least busy dominator seen so far.
899 unsigned Depth = Loop->getLoopDepth();
900 if (Depth < BestDepth) {
903 DEBUG(dbgs() << "Def in BB#" << DefMBB->getNumber() << " dominates BB#"
904 << MBB->getNumber() << " at depth " << Depth << '\n');
907 // Leave loop by going to the immediate dominator of the loop header.
908 // This is a bigger stride than simply walking up the dominator tree.
909 MachineDomTreeNode *IDom = MDT[Loop->getHeader()]->getIDom();
911 // Too far up the dominator tree?
912 if (!IDom || !MDT.dominates(DefDomNode, IDom))
915 MBB = IDom->getBlock();
919 void SplitEditor::computeRedundantBackCopies(
920 DenseSet<unsigned> &NotToHoistSet, SmallVectorImpl<VNInfo *> &BackCopies) {
921 LiveInterval *LI = &LIS.getInterval(Edit->get(0));
922 LiveInterval *Parent = &Edit->getParent();
923 SmallVector<SmallPtrSet<VNInfo *, 8>, 8> EqualVNs(Parent->getNumValNums());
924 SmallPtrSet<VNInfo *, 8> DominatedVNIs;
926 // Aggregate VNIs having the same value as ParentVNI.
927 for (VNInfo *VNI : LI->valnos) {
930 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(VNI->def);
931 EqualVNs[ParentVNI->id].insert(VNI);
934 // For VNI aggregation of each ParentVNI, collect dominated, i.e.,
935 // redundant VNIs to BackCopies.
936 for (unsigned i = 0, e = Parent->getNumValNums(); i != e; ++i) {
937 VNInfo *ParentVNI = Parent->getValNumInfo(i);
938 if (!NotToHoistSet.count(ParentVNI->id))
940 SmallPtrSetIterator<VNInfo *> It1 = EqualVNs[ParentVNI->id].begin();
941 SmallPtrSetIterator<VNInfo *> It2 = It1;
942 for (; It1 != EqualVNs[ParentVNI->id].end(); ++It1) {
944 for (++It2; It2 != EqualVNs[ParentVNI->id].end(); ++It2) {
945 if (DominatedVNIs.count(*It1) || DominatedVNIs.count(*It2))
948 MachineBasicBlock *MBB1 = LIS.getMBBFromIndex((*It1)->def);
949 MachineBasicBlock *MBB2 = LIS.getMBBFromIndex((*It2)->def);
951 DominatedVNIs.insert((*It1)->def < (*It2)->def ? (*It2) : (*It1));
952 } else if (MDT.dominates(MBB1, MBB2)) {
953 DominatedVNIs.insert(*It2);
954 } else if (MDT.dominates(MBB2, MBB1)) {
955 DominatedVNIs.insert(*It1);
959 if (!DominatedVNIs.empty()) {
960 forceRecompute(0, ParentVNI);
961 for (auto VNI : DominatedVNIs) {
962 BackCopies.push_back(VNI);
964 DominatedVNIs.clear();
969 /// For SM_Size mode, find a common dominator for all the back-copies for
970 /// the same ParentVNI and hoist the backcopies to the dominator BB.
971 /// For SM_Speed mode, if the common dominator is hot and it is not beneficial
972 /// to do the hoisting, simply remove the dominated backcopies for the same
974 void SplitEditor::hoistCopies() {
975 // Get the complement interval, always RegIdx 0.
976 LiveInterval *LI = &LIS.getInterval(Edit->get(0));
977 LiveInterval *Parent = &Edit->getParent();
979 // Track the nearest common dominator for all back-copies for each ParentVNI,
980 // indexed by ParentVNI->id.
981 typedef std::pair<MachineBasicBlock*, SlotIndex> DomPair;
982 SmallVector<DomPair, 8> NearestDom(Parent->getNumValNums());
983 // The total cost of all the back-copies for each ParentVNI.
984 SmallVector<BlockFrequency, 8> Costs(Parent->getNumValNums());
985 // The ParentVNI->id set for which hoisting back-copies are not beneficial
987 DenseSet<unsigned> NotToHoistSet;
989 // Find the nearest common dominator for parent values with multiple
990 // back-copies. If a single back-copy dominates, put it in DomPair.second.
991 for (VNInfo *VNI : LI->valnos) {
994 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(VNI->def);
995 assert(ParentVNI && "Parent not live at complement def");
997 // Don't hoist remats. The complement is probably going to disappear
998 // completely anyway.
999 if (Edit->didRematerialize(ParentVNI))
1002 MachineBasicBlock *ValMBB = LIS.getMBBFromIndex(VNI->def);
1004 DomPair &Dom = NearestDom[ParentVNI->id];
1006 // Keep directly defined parent values. This is either a PHI or an
1007 // instruction in the complement range. All other copies of ParentVNI
1008 // should be eliminated.
1009 if (VNI->def == ParentVNI->def) {
1010 DEBUG(dbgs() << "Direct complement def at " << VNI->def << '\n');
1011 Dom = DomPair(ValMBB, VNI->def);
1014 // Skip the singly mapped values. There is nothing to gain from hoisting a
1015 // single back-copy.
1016 if (Values.lookup(std::make_pair(0, ParentVNI->id)).getPointer()) {
1017 DEBUG(dbgs() << "Single complement def at " << VNI->def << '\n');
1022 // First time we see ParentVNI. VNI dominates itself.
1023 Dom = DomPair(ValMBB, VNI->def);
1024 } else if (Dom.first == ValMBB) {
1025 // Two defs in the same block. Pick the earlier def.
1026 if (!Dom.second.isValid() || VNI->def < Dom.second)
1027 Dom.second = VNI->def;
1029 // Different basic blocks. Check if one dominates.
1030 MachineBasicBlock *Near =
1031 MDT.findNearestCommonDominator(Dom.first, ValMBB);
1033 // Def ValMBB dominates.
1034 Dom = DomPair(ValMBB, VNI->def);
1035 else if (Near != Dom.first)
1036 // None dominate. Hoist to common dominator, need new def.
1037 Dom = DomPair(Near, SlotIndex());
1038 Costs[ParentVNI->id] += MBFI.getBlockFreq(ValMBB);
1041 DEBUG(dbgs() << "Multi-mapped complement " << VNI->id << '@' << VNI->def
1042 << " for parent " << ParentVNI->id << '@' << ParentVNI->def
1043 << " hoist to BB#" << Dom.first->getNumber() << ' '
1044 << Dom.second << '\n');
1047 // Insert the hoisted copies.
1048 for (unsigned i = 0, e = Parent->getNumValNums(); i != e; ++i) {
1049 DomPair &Dom = NearestDom[i];
1050 if (!Dom.first || Dom.second.isValid())
1052 // This value needs a hoisted copy inserted at the end of Dom.first.
1053 VNInfo *ParentVNI = Parent->getValNumInfo(i);
1054 MachineBasicBlock *DefMBB = LIS.getMBBFromIndex(ParentVNI->def);
1055 // Get a less loopy dominator than Dom.first.
1056 Dom.first = findShallowDominator(Dom.first, DefMBB);
1057 if (SpillMode == SM_Speed &&
1058 MBFI.getBlockFreq(Dom.first) > Costs[ParentVNI->id]) {
1059 NotToHoistSet.insert(ParentVNI->id);
1062 SlotIndex Last = LIS.getMBBEndIdx(Dom.first).getPrevSlot();
1064 defFromParent(0, ParentVNI, Last, *Dom.first,
1065 SA.getLastSplitPointIter(Dom.first))->def;
1068 // Remove redundant back-copies that are now known to be dominated by another
1069 // def with the same value.
1070 SmallVector<VNInfo*, 8> BackCopies;
1071 for (VNInfo *VNI : LI->valnos) {
1072 if (VNI->isUnused())
1074 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(VNI->def);
1075 const DomPair &Dom = NearestDom[ParentVNI->id];
1076 if (!Dom.first || Dom.second == VNI->def ||
1077 NotToHoistSet.count(ParentVNI->id))
1079 BackCopies.push_back(VNI);
1080 forceRecompute(0, ParentVNI);
1083 // If it is not beneficial to hoist all the BackCopies, simply remove
1084 // redundant BackCopies in speed mode.
1085 if (SpillMode == SM_Speed && !NotToHoistSet.empty())
1086 computeRedundantBackCopies(NotToHoistSet, BackCopies);
1088 removeBackCopies(BackCopies);
1092 /// transferValues - Transfer all possible values to the new live ranges.
1093 /// Values that were rematerialized are left alone, they need LRCalc.extend().
1094 bool SplitEditor::transferValues() {
1095 bool Skipped = false;
1096 RegAssignMap::const_iterator AssignI = RegAssign.begin();
1097 for (const LiveRange::Segment &S : Edit->getParent()) {
1098 DEBUG(dbgs() << " blit " << S << ':');
1099 VNInfo *ParentVNI = S.valno;
1100 // RegAssign has holes where RegIdx 0 should be used.
1101 SlotIndex Start = S.start;
1102 AssignI.advanceTo(Start);
1105 SlotIndex End = S.end;
1106 if (!AssignI.valid()) {
1108 } else if (AssignI.start() <= Start) {
1109 RegIdx = AssignI.value();
1110 if (AssignI.stop() < End) {
1111 End = AssignI.stop();
1116 End = std::min(End, AssignI.start());
1119 // The interval [Start;End) is continuously mapped to RegIdx, ParentVNI.
1120 DEBUG(dbgs() << " [" << Start << ';' << End << ")=" << RegIdx
1121 << '(' << PrintReg(Edit->get(RegIdx)) << ')');
1122 LiveInterval &LI = LIS.getInterval(Edit->get(RegIdx));
1124 // Check for a simply defined value that can be blitted directly.
1125 ValueForcePair VFP = Values.lookup(std::make_pair(RegIdx, ParentVNI->id));
1126 if (VNInfo *VNI = VFP.getPointer()) {
1127 DEBUG(dbgs() << ':' << VNI->id);
1128 LI.addSegment(LiveInterval::Segment(Start, End, VNI));
1133 // Skip values with forced recomputation.
1135 DEBUG(dbgs() << "(recalc)");
1141 LiveRangeCalc &LRC = getLRCalc(RegIdx);
1143 // This value has multiple defs in RegIdx, but it wasn't rematerialized,
1144 // so the live range is accurate. Add live-in blocks in [Start;End) to the
1146 MachineFunction::iterator MBB = LIS.getMBBFromIndex(Start)->getIterator();
1147 SlotIndex BlockStart, BlockEnd;
1148 std::tie(BlockStart, BlockEnd) = LIS.getSlotIndexes()->getMBBRange(&*MBB);
1150 // The first block may be live-in, or it may have its own def.
1151 if (Start != BlockStart) {
1152 VNInfo *VNI = LI.extendInBlock(BlockStart, std::min(BlockEnd, End));
1153 assert(VNI && "Missing def for complex mapped value");
1154 DEBUG(dbgs() << ':' << VNI->id << "*BB#" << MBB->getNumber());
1155 // MBB has its own def. Is it also live-out?
1156 if (BlockEnd <= End)
1157 LRC.setLiveOutValue(&*MBB, VNI);
1159 // Skip to the next block for live-in.
1161 BlockStart = BlockEnd;
1164 // Handle the live-in blocks covered by [Start;End).
1165 assert(Start <= BlockStart && "Expected live-in block");
1166 while (BlockStart < End) {
1167 DEBUG(dbgs() << ">BB#" << MBB->getNumber());
1168 BlockEnd = LIS.getMBBEndIdx(&*MBB);
1169 if (BlockStart == ParentVNI->def) {
1170 // This block has the def of a parent PHI, so it isn't live-in.
1171 assert(ParentVNI->isPHIDef() && "Non-phi defined at block start?");
1172 VNInfo *VNI = LI.extendInBlock(BlockStart, std::min(BlockEnd, End));
1173 assert(VNI && "Missing def for complex mapped parent PHI");
1174 if (End >= BlockEnd)
1175 LRC.setLiveOutValue(&*MBB, VNI); // Live-out as well.
1177 // This block needs a live-in value. The last block covered may not
1180 LRC.addLiveInBlock(LI, MDT[&*MBB], End);
1182 // Live-through, and we don't know the value.
1183 LRC.addLiveInBlock(LI, MDT[&*MBB]);
1184 LRC.setLiveOutValue(&*MBB, nullptr);
1187 BlockStart = BlockEnd;
1191 } while (Start != S.end);
1192 DEBUG(dbgs() << '\n');
1195 LRCalc[0].calculateValues();
1197 LRCalc[1].calculateValues();
1202 static bool removeDeadSegment(SlotIndex Def, LiveRange &LR) {
1203 const LiveRange::Segment *Seg = LR.getSegmentContaining(Def);
1206 if (Seg->end != Def.getDeadSlot())
1208 // This is a dead PHI. Remove it.
1209 LR.removeSegment(*Seg, true);
1213 void SplitEditor::extendPHIRange(MachineBasicBlock &B, LiveRangeCalc &LRC,
1214 LiveRange &LR, LaneBitmask LM,
1215 ArrayRef<SlotIndex> Undefs) {
1216 for (MachineBasicBlock *P : B.predecessors()) {
1217 SlotIndex End = LIS.getMBBEndIdx(P);
1218 SlotIndex LastUse = End.getPrevSlot();
1219 // The predecessor may not have a live-out value. That is OK, like an
1220 // undef PHI operand.
1221 LiveInterval &PLI = Edit->getParent();
1222 // Need the cast because the inputs to ?: would otherwise be deemed
1223 // "incompatible": SubRange vs LiveInterval.
1224 LiveRange &PSR = !LM.all() ? getSubRangeForMask(LM, PLI)
1225 : static_cast<LiveRange&>(PLI);
1226 if (PSR.liveAt(LastUse))
1227 LRC.extend(LR, End, /*PhysReg=*/0, Undefs);
1231 void SplitEditor::extendPHIKillRanges() {
1232 // Extend live ranges to be live-out for successor PHI values.
1234 // Visit each PHI def slot in the parent live interval. If the def is dead,
1235 // remove it. Otherwise, extend the live interval to reach the end indexes
1236 // of all predecessor blocks.
1238 LiveInterval &ParentLI = Edit->getParent();
1239 for (const VNInfo *V : ParentLI.valnos) {
1240 if (V->isUnused() || !V->isPHIDef())
1243 unsigned RegIdx = RegAssign.lookup(V->def);
1244 LiveInterval &LI = LIS.getInterval(Edit->get(RegIdx));
1245 LiveRangeCalc &LRC = getLRCalc(RegIdx);
1246 MachineBasicBlock &B = *LIS.getMBBFromIndex(V->def);
1247 if (!removeDeadSegment(V->def, LI))
1248 extendPHIRange(B, LRC, LI, LaneBitmask::getAll(), /*Undefs=*/{});
1251 SmallVector<SlotIndex, 4> Undefs;
1252 LiveRangeCalc SubLRC;
1254 for (LiveInterval::SubRange &PS : ParentLI.subranges()) {
1255 for (const VNInfo *V : PS.valnos) {
1256 if (V->isUnused() || !V->isPHIDef())
1258 unsigned RegIdx = RegAssign.lookup(V->def);
1259 LiveInterval &LI = LIS.getInterval(Edit->get(RegIdx));
1260 LiveInterval::SubRange &S = getSubRangeForMask(PS.LaneMask, LI);
1261 if (removeDeadSegment(V->def, S))
1264 MachineBasicBlock &B = *LIS.getMBBFromIndex(V->def);
1265 SubLRC.reset(&VRM.getMachineFunction(), LIS.getSlotIndexes(), &MDT,
1266 &LIS.getVNInfoAllocator());
1268 LI.computeSubRangeUndefs(Undefs, PS.LaneMask, MRI, *LIS.getSlotIndexes());
1269 extendPHIRange(B, SubLRC, S, PS.LaneMask, Undefs);
1274 /// rewriteAssigned - Rewrite all uses of Edit->getReg().
1275 void SplitEditor::rewriteAssigned(bool ExtendRanges) {
1277 ExtPoint(const MachineOperand &O, unsigned R, SlotIndex N)
1278 : MO(O), RegIdx(R), Next(N) {}
1284 SmallVector<ExtPoint,4> ExtPoints;
1286 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Edit->getReg()),
1287 RE = MRI.reg_end(); RI != RE;) {
1288 MachineOperand &MO = *RI;
1289 MachineInstr *MI = MO.getParent();
1291 // LiveDebugVariables should have handled all DBG_VALUE instructions.
1292 if (MI->isDebugValue()) {
1293 DEBUG(dbgs() << "Zapping " << *MI);
1298 // <undef> operands don't really read the register, so it doesn't matter
1299 // which register we choose. When the use operand is tied to a def, we must
1300 // use the same register as the def, so just do that always.
1301 SlotIndex Idx = LIS.getInstructionIndex(*MI);
1302 if (MO.isDef() || MO.isUndef())
1303 Idx = Idx.getRegSlot(MO.isEarlyClobber());
1305 // Rewrite to the mapped register at Idx.
1306 unsigned RegIdx = RegAssign.lookup(Idx);
1307 LiveInterval &LI = LIS.getInterval(Edit->get(RegIdx));
1309 DEBUG(dbgs() << " rewr BB#" << MI->getParent()->getNumber() << '\t'
1310 << Idx << ':' << RegIdx << '\t' << *MI);
1312 // Extend liveness to Idx if the instruction reads reg.
1313 if (!ExtendRanges || MO.isUndef())
1316 // Skip instructions that don't read Reg.
1318 if (!MO.getSubReg() && !MO.isEarlyClobber())
1320 // We may want to extend a live range for a partial redef, or for a use
1321 // tied to an early clobber.
1322 Idx = Idx.getPrevSlot();
1323 if (!Edit->getParent().liveAt(Idx))
1326 Idx = Idx.getRegSlot(true);
1328 SlotIndex Next = Idx.getNextSlot();
1329 if (LI.hasSubRanges()) {
1330 // We have to delay extending subranges until we have seen all operands
1331 // defining the register. This is because a <def,read-undef> operand
1332 // will create an "undef" point, and we cannot extend any subranges
1333 // until all of them have been accounted for.
1335 ExtPoints.push_back(ExtPoint(MO, RegIdx, Next));
1337 LiveRangeCalc &LRC = getLRCalc(RegIdx);
1338 LRC.extend(LI, Next, 0, ArrayRef<SlotIndex>());
1342 for (ExtPoint &EP : ExtPoints) {
1343 LiveInterval &LI = LIS.getInterval(Edit->get(EP.RegIdx));
1344 assert(LI.hasSubRanges());
1346 LiveRangeCalc SubLRC;
1347 unsigned Reg = EP.MO.getReg(), Sub = EP.MO.getSubReg();
1348 LaneBitmask LM = Sub != 0 ? TRI.getSubRegIndexLaneMask(Sub)
1349 : MRI.getMaxLaneMaskForVReg(Reg);
1350 for (LiveInterval::SubRange &S : LI.subranges()) {
1351 if ((S.LaneMask & LM).none())
1353 // The problem here can be that the new register may have been created
1354 // for a partially defined original register. For example:
1355 // %vreg827:subreg_hireg<def,read-undef> = ...
1357 // %vreg828<def> = COPY %vreg827
1360 SubLRC.reset(&VRM.getMachineFunction(), LIS.getSlotIndexes(), &MDT,
1361 &LIS.getVNInfoAllocator());
1362 SmallVector<SlotIndex, 4> Undefs;
1363 LI.computeSubRangeUndefs(Undefs, S.LaneMask, MRI, *LIS.getSlotIndexes());
1364 SubLRC.extend(S, EP.Next, 0, Undefs);
1368 for (unsigned R : *Edit) {
1369 LiveInterval &LI = LIS.getInterval(R);
1370 if (!LI.hasSubRanges())
1373 LI.removeEmptySubRanges();
1374 LIS.constructMainRangeFromSubranges(LI);
1378 void SplitEditor::deleteRematVictims() {
1379 SmallVector<MachineInstr*, 8> Dead;
1380 for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I){
1381 LiveInterval *LI = &LIS.getInterval(*I);
1382 for (const LiveRange::Segment &S : LI->segments) {
1383 // Dead defs end at the dead slot.
1384 if (S.end != S.valno->def.getDeadSlot())
1386 if (S.valno->isPHIDef())
1388 MachineInstr *MI = LIS.getInstructionFromIndex(S.valno->def);
1389 assert(MI && "Missing instruction for dead def");
1390 MI->addRegisterDead(LI->reg, &TRI);
1392 if (!MI->allDefsAreDead())
1395 DEBUG(dbgs() << "All defs dead: " << *MI);
1403 Edit->eliminateDeadDefs(Dead, None, &AA);
1406 void SplitEditor::finish(SmallVectorImpl<unsigned> *LRMap) {
1409 // At this point, the live intervals in Edit contain VNInfos corresponding to
1410 // the inserted copies.
1412 // Add the original defs from the parent interval.
1413 for (const VNInfo *ParentVNI : Edit->getParent().valnos) {
1414 if (ParentVNI->isUnused())
1416 unsigned RegIdx = RegAssign.lookup(ParentVNI->def);
1417 defValue(RegIdx, ParentVNI, ParentVNI->def, true);
1419 // Force rematted values to be recomputed everywhere.
1420 // The new live ranges may be truncated.
1421 if (Edit->didRematerialize(ParentVNI))
1422 for (unsigned i = 0, e = Edit->size(); i != e; ++i)
1423 forceRecompute(i, ParentVNI);
1426 // Hoist back-copies to the complement interval when in spill mode.
1427 switch (SpillMode) {
1429 // Leave all back-copies as is.
1433 // hoistCopies will behave differently between size and speed.
1437 // Transfer the simply mapped values, check if any are skipped.
1438 bool Skipped = transferValues();
1440 // Rewrite virtual registers, possibly extending ranges.
1441 rewriteAssigned(Skipped);
1444 extendPHIKillRanges();
1448 // Delete defs that were rematted everywhere.
1450 deleteRematVictims();
1452 // Get rid of unused values and set phi-kill flags.
1453 for (unsigned Reg : *Edit) {
1454 LiveInterval &LI = LIS.getInterval(Reg);
1455 LI.removeEmptySubRanges();
1456 LI.RenumberValues();
1459 // Provide a reverse mapping from original indices to Edit ranges.
1462 for (unsigned i = 0, e = Edit->size(); i != e; ++i)
1463 LRMap->push_back(i);
1466 // Now check if any registers were separated into multiple components.
1467 ConnectedVNInfoEqClasses ConEQ(LIS);
1468 for (unsigned i = 0, e = Edit->size(); i != e; ++i) {
1469 // Don't use iterators, they are invalidated by create() below.
1470 unsigned VReg = Edit->get(i);
1471 LiveInterval &LI = LIS.getInterval(VReg);
1472 SmallVector<LiveInterval*, 8> SplitLIs;
1473 LIS.splitSeparateComponents(LI, SplitLIs);
1474 unsigned Original = VRM.getOriginal(VReg);
1475 for (LiveInterval *SplitLI : SplitLIs)
1476 VRM.setIsSplitFromReg(SplitLI->reg, Original);
1478 // The new intervals all map back to i.
1480 LRMap->resize(Edit->size(), i);
1483 // Calculate spill weight and allocation hints for new intervals.
1484 Edit->calculateRegClassAndHint(VRM.getMachineFunction(), SA.Loops, MBFI);
1486 assert(!LRMap || LRMap->size() == Edit->size());
1490 //===----------------------------------------------------------------------===//
1491 // Single Block Splitting
1492 //===----------------------------------------------------------------------===//
1494 bool SplitAnalysis::shouldSplitSingleBlock(const BlockInfo &BI,
1495 bool SingleInstrs) const {
1496 // Always split for multiple instructions.
1497 if (!BI.isOneInstr())
1499 // Don't split for single instructions unless explicitly requested.
1502 // Splitting a live-through range always makes progress.
1503 if (BI.LiveIn && BI.LiveOut)
1505 // No point in isolating a copy. It has no register class constraints.
1506 if (LIS.getInstructionFromIndex(BI.FirstInstr)->isCopyLike())
1508 // Finally, don't isolate an end point that was created by earlier splits.
1509 return isOriginalEndpoint(BI.FirstInstr);
1512 void SplitEditor::splitSingleBlock(const SplitAnalysis::BlockInfo &BI) {
1514 SlotIndex LastSplitPoint = SA.getLastSplitPoint(BI.MBB->getNumber());
1515 SlotIndex SegStart = enterIntvBefore(std::min(BI.FirstInstr,
1517 if (!BI.LiveOut || BI.LastInstr < LastSplitPoint) {
1518 useIntv(SegStart, leaveIntvAfter(BI.LastInstr));
1520 // The last use is after the last valid split point.
1521 SlotIndex SegStop = leaveIntvBefore(LastSplitPoint);
1522 useIntv(SegStart, SegStop);
1523 overlapIntv(SegStop, BI.LastInstr);
1528 //===----------------------------------------------------------------------===//
1529 // Global Live Range Splitting Support
1530 //===----------------------------------------------------------------------===//
1532 // These methods support a method of global live range splitting that uses a
1533 // global algorithm to decide intervals for CFG edges. They will insert split
1534 // points and color intervals in basic blocks while avoiding interference.
1536 // Note that splitSingleBlock is also useful for blocks where both CFG edges
1537 // are on the stack.
1539 void SplitEditor::splitLiveThroughBlock(unsigned MBBNum,
1540 unsigned IntvIn, SlotIndex LeaveBefore,
1541 unsigned IntvOut, SlotIndex EnterAfter){
1542 SlotIndex Start, Stop;
1543 std::tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(MBBNum);
1545 DEBUG(dbgs() << "BB#" << MBBNum << " [" << Start << ';' << Stop
1546 << ") intf " << LeaveBefore << '-' << EnterAfter
1547 << ", live-through " << IntvIn << " -> " << IntvOut);
1549 assert((IntvIn || IntvOut) && "Use splitSingleBlock for isolated blocks");
1551 assert((!LeaveBefore || LeaveBefore < Stop) && "Interference after block");
1552 assert((!IntvIn || !LeaveBefore || LeaveBefore > Start) && "Impossible intf");
1553 assert((!EnterAfter || EnterAfter >= Start) && "Interference before block");
1555 MachineBasicBlock *MBB = VRM.getMachineFunction().getBlockNumbered(MBBNum);
1558 DEBUG(dbgs() << ", spill on entry.\n");
1560 // <<<<<<<<< Possible LeaveBefore interference.
1561 // |-----------| Live through.
1562 // -____________ Spill on entry.
1565 SlotIndex Idx = leaveIntvAtTop(*MBB);
1566 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1572 DEBUG(dbgs() << ", reload on exit.\n");
1574 // >>>>>>> Possible EnterAfter interference.
1575 // |-----------| Live through.
1576 // ___________-- Reload on exit.
1578 selectIntv(IntvOut);
1579 SlotIndex Idx = enterIntvAtEnd(*MBB);
1580 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1585 if (IntvIn == IntvOut && !LeaveBefore && !EnterAfter) {
1586 DEBUG(dbgs() << ", straight through.\n");
1588 // |-----------| Live through.
1589 // ------------- Straight through, same intv, no interference.
1591 selectIntv(IntvOut);
1592 useIntv(Start, Stop);
1596 // We cannot legally insert splits after LSP.
1597 SlotIndex LSP = SA.getLastSplitPoint(MBBNum);
1598 assert((!IntvOut || !EnterAfter || EnterAfter < LSP) && "Impossible intf");
1600 if (IntvIn != IntvOut && (!LeaveBefore || !EnterAfter ||
1601 LeaveBefore.getBaseIndex() > EnterAfter.getBoundaryIndex())) {
1602 DEBUG(dbgs() << ", switch avoiding interference.\n");
1604 // >>>> <<<< Non-overlapping EnterAfter/LeaveBefore interference.
1605 // |-----------| Live through.
1606 // ------======= Switch intervals between interference.
1608 selectIntv(IntvOut);
1610 if (LeaveBefore && LeaveBefore < LSP) {
1611 Idx = enterIntvBefore(LeaveBefore);
1614 Idx = enterIntvAtEnd(*MBB);
1617 useIntv(Start, Idx);
1618 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1619 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1623 DEBUG(dbgs() << ", create local intv for interference.\n");
1625 // >>><><><><<<< Overlapping EnterAfter/LeaveBefore interference.
1626 // |-----------| Live through.
1627 // ==---------== Switch intervals before/after interference.
1629 assert(LeaveBefore <= EnterAfter && "Missed case");
1631 selectIntv(IntvOut);
1632 SlotIndex Idx = enterIntvAfter(EnterAfter);
1634 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1637 Idx = leaveIntvBefore(LeaveBefore);
1638 useIntv(Start, Idx);
1639 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1643 void SplitEditor::splitRegInBlock(const SplitAnalysis::BlockInfo &BI,
1644 unsigned IntvIn, SlotIndex LeaveBefore) {
1645 SlotIndex Start, Stop;
1646 std::tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
1648 DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " [" << Start << ';' << Stop
1649 << "), uses " << BI.FirstInstr << '-' << BI.LastInstr
1650 << ", reg-in " << IntvIn << ", leave before " << LeaveBefore
1651 << (BI.LiveOut ? ", stack-out" : ", killed in block"));
1653 assert(IntvIn && "Must have register in");
1654 assert(BI.LiveIn && "Must be live-in");
1655 assert((!LeaveBefore || LeaveBefore > Start) && "Bad interference");
1657 if (!BI.LiveOut && (!LeaveBefore || LeaveBefore >= BI.LastInstr)) {
1658 DEBUG(dbgs() << " before interference.\n");
1660 // <<< Interference after kill.
1661 // |---o---x | Killed in block.
1662 // ========= Use IntvIn everywhere.
1665 useIntv(Start, BI.LastInstr);
1669 SlotIndex LSP = SA.getLastSplitPoint(BI.MBB->getNumber());
1671 if (!LeaveBefore || LeaveBefore > BI.LastInstr.getBoundaryIndex()) {
1673 // <<< Possible interference after last use.
1674 // |---o---o---| Live-out on stack.
1675 // =========____ Leave IntvIn after last use.
1677 // < Interference after last use.
1678 // |---o---o--o| Live-out on stack, late last use.
1679 // ============ Copy to stack after LSP, overlap IntvIn.
1680 // \_____ Stack interval is live-out.
1682 if (BI.LastInstr < LSP) {
1683 DEBUG(dbgs() << ", spill after last use before interference.\n");
1685 SlotIndex Idx = leaveIntvAfter(BI.LastInstr);
1686 useIntv(Start, Idx);
1687 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1689 DEBUG(dbgs() << ", spill before last split point.\n");
1691 SlotIndex Idx = leaveIntvBefore(LSP);
1692 overlapIntv(Idx, BI.LastInstr);
1693 useIntv(Start, Idx);
1694 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1699 // The interference is overlapping somewhere we wanted to use IntvIn. That
1700 // means we need to create a local interval that can be allocated a
1701 // different register.
1702 unsigned LocalIntv = openIntv();
1704 DEBUG(dbgs() << ", creating local interval " << LocalIntv << ".\n");
1706 if (!BI.LiveOut || BI.LastInstr < LSP) {
1708 // <<<<<<< Interference overlapping uses.
1709 // |---o---o---| Live-out on stack.
1710 // =====----____ Leave IntvIn before interference, then spill.
1712 SlotIndex To = leaveIntvAfter(BI.LastInstr);
1713 SlotIndex From = enterIntvBefore(LeaveBefore);
1716 useIntv(Start, From);
1717 assert((!LeaveBefore || From <= LeaveBefore) && "Interference");
1721 // <<<<<<< Interference overlapping uses.
1722 // |---o---o--o| Live-out on stack, late last use.
1723 // =====------- Copy to stack before LSP, overlap LocalIntv.
1724 // \_____ Stack interval is live-out.
1726 SlotIndex To = leaveIntvBefore(LSP);
1727 overlapIntv(To, BI.LastInstr);
1728 SlotIndex From = enterIntvBefore(std::min(To, LeaveBefore));
1731 useIntv(Start, From);
1732 assert((!LeaveBefore || From <= LeaveBefore) && "Interference");
1735 void SplitEditor::splitRegOutBlock(const SplitAnalysis::BlockInfo &BI,
1736 unsigned IntvOut, SlotIndex EnterAfter) {
1737 SlotIndex Start, Stop;
1738 std::tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
1740 DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " [" << Start << ';' << Stop
1741 << "), uses " << BI.FirstInstr << '-' << BI.LastInstr
1742 << ", reg-out " << IntvOut << ", enter after " << EnterAfter
1743 << (BI.LiveIn ? ", stack-in" : ", defined in block"));
1745 SlotIndex LSP = SA.getLastSplitPoint(BI.MBB->getNumber());
1747 assert(IntvOut && "Must have register out");
1748 assert(BI.LiveOut && "Must be live-out");
1749 assert((!EnterAfter || EnterAfter < LSP) && "Bad interference");
1751 if (!BI.LiveIn && (!EnterAfter || EnterAfter <= BI.FirstInstr)) {
1752 DEBUG(dbgs() << " after interference.\n");
1754 // >>>> Interference before def.
1755 // | o---o---| Defined in block.
1756 // ========= Use IntvOut everywhere.
1758 selectIntv(IntvOut);
1759 useIntv(BI.FirstInstr, Stop);
1763 if (!EnterAfter || EnterAfter < BI.FirstInstr.getBaseIndex()) {
1764 DEBUG(dbgs() << ", reload after interference.\n");
1766 // >>>> Interference before def.
1767 // |---o---o---| Live-through, stack-in.
1768 // ____========= Enter IntvOut before first use.
1770 selectIntv(IntvOut);
1771 SlotIndex Idx = enterIntvBefore(std::min(LSP, BI.FirstInstr));
1773 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1777 // The interference is overlapping somewhere we wanted to use IntvOut. That
1778 // means we need to create a local interval that can be allocated a
1779 // different register.
1780 DEBUG(dbgs() << ", interference overlaps uses.\n");
1782 // >>>>>>> Interference overlapping uses.
1783 // |---o---o---| Live-through, stack-in.
1784 // ____---====== Create local interval for interference range.
1786 selectIntv(IntvOut);
1787 SlotIndex Idx = enterIntvAfter(EnterAfter);
1789 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1792 SlotIndex From = enterIntvBefore(std::min(Idx, BI.FirstInstr));