1 //===---------- SplitKit.cpp - Toolkit for splitting live ranges ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SplitAnalysis class as well as mutator functions for
11 // live range splitting.
13 //===----------------------------------------------------------------------===//
16 #include "llvm/ADT/Statistic.h"
17 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
18 #include "llvm/CodeGen/LiveRangeEdit.h"
19 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
20 #include "llvm/CodeGen/MachineDominators.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineLoopInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/VirtRegMap.h"
25 #include "llvm/Support/Debug.h"
26 #include "llvm/Support/MathExtras.h"
27 #include "llvm/Support/raw_ostream.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetMachine.h"
33 #define DEBUG_TYPE "regalloc"
35 STATISTIC(NumFinished, "Number of splits finished");
36 STATISTIC(NumSimple, "Number of splits that were simple");
37 STATISTIC(NumCopies, "Number of copies inserted for splitting");
38 STATISTIC(NumRemats, "Number of rematerialized defs for splitting");
39 STATISTIC(NumRepairs, "Number of invalid live ranges repaired");
41 //===----------------------------------------------------------------------===//
42 // Last Insert Point Analysis
43 //===----------------------------------------------------------------------===//
45 InsertPointAnalysis::InsertPointAnalysis(const LiveIntervals &lis,
47 : LIS(lis), LastInsertPoint(BBNum) {}
50 InsertPointAnalysis::computeLastInsertPoint(const LiveInterval &CurLI,
51 const MachineBasicBlock &MBB) {
52 unsigned Num = MBB.getNumber();
53 std::pair<SlotIndex, SlotIndex> &LIP = LastInsertPoint[Num];
54 SlotIndex MBBEnd = LIS.getMBBEndIdx(&MBB);
56 SmallVector<const MachineBasicBlock *, 1> EHPadSucessors;
57 for (const MachineBasicBlock *SMBB : MBB.successors())
59 EHPadSucessors.push_back(SMBB);
61 // Compute insert points on the first call. The pair is independent of the
62 // current live interval.
63 if (!LIP.first.isValid()) {
64 MachineBasicBlock::const_iterator FirstTerm = MBB.getFirstTerminator();
65 if (FirstTerm == MBB.end())
68 LIP.first = LIS.getInstructionIndex(*FirstTerm);
70 // If there is a landing pad successor, also find the call instruction.
71 if (EHPadSucessors.empty())
73 // There may not be a call instruction (?) in which case we ignore LPad.
74 LIP.second = LIP.first;
75 for (MachineBasicBlock::const_iterator I = MBB.end(), E = MBB.begin();
79 LIP.second = LIS.getInstructionIndex(*I);
85 // If CurLI is live into a landing pad successor, move the last insert point
86 // back to the call that may throw.
90 if (none_of(EHPadSucessors, [&](const MachineBasicBlock *EHPad) {
91 return LIS.isLiveInToMBB(CurLI, EHPad);
95 // Find the value leaving MBB.
96 const VNInfo *VNI = CurLI.getVNInfoBefore(MBBEnd);
100 // If the value leaving MBB was defined after the call in MBB, it can't
101 // really be live-in to the landing pad. This can happen if the landing pad
102 // has a PHI, and this register is undef on the exceptional edge.
103 // <rdar://problem/10664933>
104 if (!SlotIndex::isEarlierInstr(VNI->def, LIP.second) && VNI->def < MBBEnd)
107 // Value is properly live-in to the landing pad.
108 // Only allow inserts before the call.
112 MachineBasicBlock::iterator
113 InsertPointAnalysis::getLastInsertPointIter(const LiveInterval &CurLI,
114 MachineBasicBlock &MBB) {
115 SlotIndex LIP = getLastInsertPoint(CurLI, MBB);
116 if (LIP == LIS.getMBBEndIdx(&MBB))
118 return LIS.getInstructionFromIndex(LIP);
121 //===----------------------------------------------------------------------===//
123 //===----------------------------------------------------------------------===//
125 SplitAnalysis::SplitAnalysis(const VirtRegMap &vrm, const LiveIntervals &lis,
126 const MachineLoopInfo &mli)
127 : MF(vrm.getMachineFunction()), VRM(vrm), LIS(lis), Loops(mli),
128 TII(*MF.getSubtarget().getInstrInfo()), CurLI(nullptr),
129 IPA(lis, MF.getNumBlockIDs()) {}
131 void SplitAnalysis::clear() {
134 ThroughBlocks.clear();
136 DidRepairRange = false;
139 /// analyzeUses - Count instructions, basic blocks, and loops using CurLI.
140 void SplitAnalysis::analyzeUses() {
141 assert(UseSlots.empty() && "Call clear first");
143 // First get all the defs from the interval values. This provides the correct
144 // slots for early clobbers.
145 for (const VNInfo *VNI : CurLI->valnos)
146 if (!VNI->isPHIDef() && !VNI->isUnused())
147 UseSlots.push_back(VNI->def);
149 // Get use slots form the use-def chain.
150 const MachineRegisterInfo &MRI = MF.getRegInfo();
151 for (MachineOperand &MO : MRI.use_nodbg_operands(CurLI->reg))
153 UseSlots.push_back(LIS.getInstructionIndex(*MO.getParent()).getRegSlot());
155 array_pod_sort(UseSlots.begin(), UseSlots.end());
157 // Remove duplicates, keeping the smaller slot for each instruction.
158 // That is what we want for early clobbers.
159 UseSlots.erase(std::unique(UseSlots.begin(), UseSlots.end(),
160 SlotIndex::isSameInstr),
163 // Compute per-live block info.
164 if (!calcLiveBlockInfo()) {
165 // FIXME: calcLiveBlockInfo found inconsistencies in the live range.
166 // I am looking at you, RegisterCoalescer!
167 DidRepairRange = true;
169 DEBUG(dbgs() << "*** Fixing inconsistent live interval! ***\n");
170 const_cast<LiveIntervals&>(LIS)
171 .shrinkToUses(const_cast<LiveInterval*>(CurLI));
173 ThroughBlocks.clear();
174 bool fixed = calcLiveBlockInfo();
176 assert(fixed && "Couldn't fix broken live interval");
179 DEBUG(dbgs() << "Analyze counted "
180 << UseSlots.size() << " instrs in "
181 << UseBlocks.size() << " blocks, through "
182 << NumThroughBlocks << " blocks.\n");
185 /// calcLiveBlockInfo - Fill the LiveBlocks array with information about blocks
186 /// where CurLI is live.
187 bool SplitAnalysis::calcLiveBlockInfo() {
188 ThroughBlocks.resize(MF.getNumBlockIDs());
189 NumThroughBlocks = NumGapBlocks = 0;
193 LiveInterval::const_iterator LVI = CurLI->begin();
194 LiveInterval::const_iterator LVE = CurLI->end();
196 SmallVectorImpl<SlotIndex>::const_iterator UseI, UseE;
197 UseI = UseSlots.begin();
198 UseE = UseSlots.end();
200 // Loop over basic blocks where CurLI is live.
201 MachineFunction::iterator MFI =
202 LIS.getMBBFromIndex(LVI->start)->getIterator();
206 SlotIndex Start, Stop;
207 std::tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
209 // If the block contains no uses, the range must be live through. At one
210 // point, RegisterCoalescer could create dangling ranges that ended
212 if (UseI == UseE || *UseI >= Stop) {
214 ThroughBlocks.set(BI.MBB->getNumber());
215 // The range shouldn't end mid-block if there are no uses. This shouldn't
220 // This block has uses. Find the first and last uses in the block.
221 BI.FirstInstr = *UseI;
222 assert(BI.FirstInstr >= Start);
224 while (UseI != UseE && *UseI < Stop);
225 BI.LastInstr = UseI[-1];
226 assert(BI.LastInstr < Stop);
228 // LVI is the first live segment overlapping MBB.
229 BI.LiveIn = LVI->start <= Start;
231 // When not live in, the first use should be a def.
233 assert(LVI->start == LVI->valno->def && "Dangling Segment start");
234 assert(LVI->start == BI.FirstInstr && "First instr should be a def");
235 BI.FirstDef = BI.FirstInstr;
238 // Look for gaps in the live range.
240 while (LVI->end < Stop) {
241 SlotIndex LastStop = LVI->end;
242 if (++LVI == LVE || LVI->start >= Stop) {
244 BI.LastInstr = LastStop;
248 if (LastStop < LVI->start) {
249 // There is a gap in the live range. Create duplicate entries for the
250 // live-in snippet and the live-out snippet.
253 // Push the Live-in part.
255 UseBlocks.push_back(BI);
256 UseBlocks.back().LastInstr = LastStop;
258 // Set up BI for the live-out part.
261 BI.FirstInstr = BI.FirstDef = LVI->start;
264 // A Segment that starts in the middle of the block must be a def.
265 assert(LVI->start == LVI->valno->def && "Dangling Segment start");
267 BI.FirstDef = LVI->start;
270 UseBlocks.push_back(BI);
272 // LVI is now at LVE or LVI->end >= Stop.
277 // Live segment ends exactly at Stop. Move to the next segment.
278 if (LVI->end == Stop && ++LVI == LVE)
281 // Pick the next basic block.
282 if (LVI->start < Stop)
285 MFI = LIS.getMBBFromIndex(LVI->start)->getIterator();
288 assert(getNumLiveBlocks() == countLiveBlocks(CurLI) && "Bad block count");
292 unsigned SplitAnalysis::countLiveBlocks(const LiveInterval *cli) const {
295 LiveInterval *li = const_cast<LiveInterval*>(cli);
296 LiveInterval::iterator LVI = li->begin();
297 LiveInterval::iterator LVE = li->end();
300 // Loop over basic blocks where li is live.
301 MachineFunction::const_iterator MFI =
302 LIS.getMBBFromIndex(LVI->start)->getIterator();
303 SlotIndex Stop = LIS.getMBBEndIdx(&*MFI);
306 LVI = li->advanceTo(LVI, Stop);
311 Stop = LIS.getMBBEndIdx(&*MFI);
312 } while (Stop <= LVI->start);
316 bool SplitAnalysis::isOriginalEndpoint(SlotIndex Idx) const {
317 unsigned OrigReg = VRM.getOriginal(CurLI->reg);
318 const LiveInterval &Orig = LIS.getInterval(OrigReg);
319 assert(!Orig.empty() && "Splitting empty interval?");
320 LiveInterval::const_iterator I = Orig.find(Idx);
322 // Range containing Idx should begin at Idx.
323 if (I != Orig.end() && I->start <= Idx)
324 return I->start == Idx;
326 // Range does not contain Idx, previous must end at Idx.
327 return I != Orig.begin() && (--I)->end == Idx;
330 void SplitAnalysis::analyze(const LiveInterval *li) {
337 //===----------------------------------------------------------------------===//
339 //===----------------------------------------------------------------------===//
341 /// Create a new SplitEditor for editing the LiveInterval analyzed by SA.
342 SplitEditor::SplitEditor(SplitAnalysis &sa, AliasAnalysis &aa,
343 LiveIntervals &lis, VirtRegMap &vrm,
344 MachineDominatorTree &mdt,
345 MachineBlockFrequencyInfo &mbfi)
346 : SA(sa), AA(aa), LIS(lis), VRM(vrm),
347 MRI(vrm.getMachineFunction().getRegInfo()), MDT(mdt),
348 TII(*vrm.getMachineFunction().getSubtarget().getInstrInfo()),
349 TRI(*vrm.getMachineFunction().getSubtarget().getRegisterInfo()),
350 MBFI(mbfi), Edit(nullptr), OpenIdx(0), SpillMode(SM_Partition),
351 RegAssign(Allocator) {}
353 void SplitEditor::reset(LiveRangeEdit &LRE, ComplementSpillMode SM) {
360 // Reset the LiveRangeCalc instances needed for this spill mode.
361 LRCalc[0].reset(&VRM.getMachineFunction(), LIS.getSlotIndexes(), &MDT,
362 &LIS.getVNInfoAllocator());
364 LRCalc[1].reset(&VRM.getMachineFunction(), LIS.getSlotIndexes(), &MDT,
365 &LIS.getVNInfoAllocator());
367 // We don't need an AliasAnalysis since we will only be performing
368 // cheap-as-a-copy remats anyway.
369 Edit->anyRematerializable(nullptr);
372 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
373 LLVM_DUMP_METHOD void SplitEditor::dump() const {
374 if (RegAssign.empty()) {
375 dbgs() << " empty\n";
379 for (RegAssignMap::const_iterator I = RegAssign.begin(); I.valid(); ++I)
380 dbgs() << " [" << I.start() << ';' << I.stop() << "):" << I.value();
385 LiveInterval::SubRange &SplitEditor::getSubRangeForMask(LaneBitmask LM,
387 for (LiveInterval::SubRange &S : LI.subranges())
388 if (S.LaneMask == LM)
390 llvm_unreachable("SubRange for this mask not found");
393 void SplitEditor::addDeadDef(LiveInterval &LI, VNInfo *VNI, bool Original) {
394 if (!LI.hasSubRanges()) {
395 LI.createDeadDef(VNI);
399 SlotIndex Def = VNI->def;
401 // If we are transferring a def from the original interval, make sure
402 // to only update the subranges for which the original subranges had
403 // a def at this location.
404 for (LiveInterval::SubRange &S : LI.subranges()) {
405 auto &PS = getSubRangeForMask(S.LaneMask, Edit->getParent());
406 VNInfo *PV = PS.getVNInfoAt(Def);
407 if (PV != nullptr && PV->def == Def)
408 S.createDeadDef(Def, LIS.getVNInfoAllocator());
411 // This is a new def: either from rematerialization, or from an inserted
412 // copy. Since rematerialization can regenerate a definition of a sub-
413 // register, we need to check which subranges need to be updated.
414 const MachineInstr *DefMI = LIS.getInstructionFromIndex(Def);
415 assert(DefMI != nullptr);
417 for (const MachineOperand &DefOp : DefMI->defs()) {
418 unsigned R = DefOp.getReg();
421 if (unsigned SR = DefOp.getSubReg())
422 LM |= TRI.getSubRegIndexLaneMask(SR);
424 LM = MRI.getMaxLaneMaskForVReg(R);
428 for (LiveInterval::SubRange &S : LI.subranges())
429 if ((S.LaneMask & LM).any())
430 S.createDeadDef(Def, LIS.getVNInfoAllocator());
434 VNInfo *SplitEditor::defValue(unsigned RegIdx,
435 const VNInfo *ParentVNI,
438 assert(ParentVNI && "Mapping NULL value");
439 assert(Idx.isValid() && "Invalid SlotIndex");
440 assert(Edit->getParent().getVNInfoAt(Idx) == ParentVNI && "Bad Parent VNI");
441 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx));
443 // Create a new value.
444 VNInfo *VNI = LI->getNextValue(Idx, LIS.getVNInfoAllocator());
446 bool Force = LI->hasSubRanges();
447 ValueForcePair FP(Force ? nullptr : VNI, Force);
448 // Use insert for lookup, so we can add missing values with a second lookup.
449 std::pair<ValueMap::iterator, bool> InsP =
450 Values.insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->id), FP));
452 // This was the first time (RegIdx, ParentVNI) was mapped, and it is not
453 // forced. Keep it as a simple def without any liveness.
454 if (!Force && InsP.second)
457 // If the previous value was a simple mapping, add liveness for it now.
458 if (VNInfo *OldVNI = InsP.first->second.getPointer()) {
459 addDeadDef(*LI, OldVNI, Original);
461 // No longer a simple mapping. Switch to a complex mapping. If the
462 // interval has subranges, make it a forced mapping.
463 InsP.first->second = ValueForcePair(nullptr, Force);
466 // This is a complex mapping, add liveness for VNI
467 addDeadDef(*LI, VNI, Original);
471 void SplitEditor::forceRecompute(unsigned RegIdx, const VNInfo *ParentVNI) {
472 assert(ParentVNI && "Mapping NULL value");
473 ValueForcePair &VFP = Values[std::make_pair(RegIdx, ParentVNI->id)];
474 VNInfo *VNI = VFP.getPointer();
476 // ParentVNI was either unmapped or already complex mapped. Either way, just
477 // set the force bit.
483 // This was previously a single mapping. Make sure the old def is represented
484 // by a trivial live range.
485 addDeadDef(LIS.getInterval(Edit->get(RegIdx)), VNI, false);
487 // Mark as complex mapped, forced.
488 VFP = ValueForcePair(nullptr, true);
491 SlotIndex SplitEditor::buildSingleSubRegCopy(unsigned FromReg, unsigned ToReg,
492 MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore,
493 unsigned SubIdx, LiveInterval &DestLI, bool Late, SlotIndex Def) {
494 const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY);
495 bool FirstCopy = !Def.isValid();
496 MachineInstr *CopyMI = BuildMI(MBB, InsertBefore, DebugLoc(), Desc)
497 .addReg(ToReg, RegState::Define | getUndefRegState(FirstCopy)
498 | getInternalReadRegState(!FirstCopy), SubIdx)
499 .addReg(FromReg, 0, SubIdx);
501 BumpPtrAllocator &Allocator = LIS.getVNInfoAllocator();
503 SlotIndexes &Indexes = *LIS.getSlotIndexes();
504 Def = Indexes.insertMachineInstrInMaps(*CopyMI, Late).getRegSlot();
506 CopyMI->bundleWithPred();
508 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubIdx);
509 DestLI.refineSubRanges(Allocator, LaneMask,
510 [Def, &Allocator](LiveInterval::SubRange& SR) {
511 SR.createDeadDef(Def, Allocator);
516 SlotIndex SplitEditor::buildCopy(unsigned FromReg, unsigned ToReg,
517 LaneBitmask LaneMask, MachineBasicBlock &MBB,
518 MachineBasicBlock::iterator InsertBefore, bool Late, unsigned RegIdx) {
519 const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY);
520 if (LaneMask.all() || LaneMask == MRI.getMaxLaneMaskForVReg(FromReg)) {
521 // The full vreg is copied.
522 MachineInstr *CopyMI =
523 BuildMI(MBB, InsertBefore, DebugLoc(), Desc, ToReg).addReg(FromReg);
524 SlotIndexes &Indexes = *LIS.getSlotIndexes();
525 return Indexes.insertMachineInstrInMaps(*CopyMI, Late).getRegSlot();
528 // Only a subset of lanes needs to be copied. The following is a simple
529 // heuristic to construct a sequence of COPYs. We could add a target
530 // specific callback if this turns out to be suboptimal.
531 LiveInterval &DestLI = LIS.getInterval(Edit->get(RegIdx));
533 // First pass: Try to find a perfectly matching subregister index. If none
534 // exists find the one covering the most lanemask bits.
535 SmallVector<unsigned, 8> PossibleIndexes;
536 unsigned BestIdx = 0;
537 unsigned BestCover = 0;
538 const TargetRegisterClass *RC = MRI.getRegClass(FromReg);
539 assert(RC == MRI.getRegClass(ToReg) && "Should have same reg class");
540 for (unsigned Idx = 1, E = TRI.getNumSubRegIndices(); Idx < E; ++Idx) {
541 // Is this index even compatible with the given class?
542 if (TRI.getSubClassWithSubReg(RC, Idx) != RC)
544 LaneBitmask SubRegMask = TRI.getSubRegIndexLaneMask(Idx);
545 // Early exit if we found a perfect match.
546 if (SubRegMask == LaneMask) {
551 // The index must not cover any lanes outside \p LaneMask.
552 if ((SubRegMask & ~LaneMask).any())
555 unsigned PopCount = countPopulation(SubRegMask.getAsInteger());
556 PossibleIndexes.push_back(Idx);
557 if (PopCount > BestCover) {
558 BestCover = PopCount;
563 // Abort if we cannot possibly implement the COPY with the given indexes.
565 report_fatal_error("Impossible to implement partial COPY");
567 SlotIndex Def = buildSingleSubRegCopy(FromReg, ToReg, MBB, InsertBefore,
568 BestIdx, DestLI, Late, SlotIndex());
570 // Greedy heuristic: Keep iterating keeping the best covering subreg index
572 LaneBitmask LanesLeft =
573 LaneMask & ~(TRI.getSubRegIndexLaneMask(BestCover));
574 while (LanesLeft.any()) {
575 unsigned BestIdx = 0;
576 int BestCover = INT_MIN;
577 for (unsigned Idx : PossibleIndexes) {
578 LaneBitmask SubRegMask = TRI.getSubRegIndexLaneMask(Idx);
579 // Early exit if we found a perfect match.
580 if (SubRegMask == LanesLeft) {
585 // Try to cover as much of the remaining lanes as possible but
586 // as few of the already covered lanes as possible.
587 int Cover = countPopulation((SubRegMask & LanesLeft).getAsInteger())
588 - countPopulation((SubRegMask & ~LanesLeft).getAsInteger());
589 if (Cover > BestCover) {
596 report_fatal_error("Impossible to implement partial COPY");
598 buildSingleSubRegCopy(FromReg, ToReg, MBB, InsertBefore, BestIdx,
600 LanesLeft &= ~TRI.getSubRegIndexLaneMask(BestIdx);
606 VNInfo *SplitEditor::defFromParent(unsigned RegIdx,
609 MachineBasicBlock &MBB,
610 MachineBasicBlock::iterator I) {
612 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx));
614 // We may be trying to avoid interference that ends at a deleted instruction,
615 // so always begin RegIdx 0 early and all others late.
616 bool Late = RegIdx != 0;
618 // Attempt cheap-as-a-copy rematerialization.
619 unsigned Original = VRM.getOriginal(Edit->get(RegIdx));
620 LiveInterval &OrigLI = LIS.getInterval(Original);
621 VNInfo *OrigVNI = OrigLI.getVNInfoAt(UseIdx);
623 unsigned Reg = LI->reg;
624 bool DidRemat = false;
626 LiveRangeEdit::Remat RM(ParentVNI);
627 RM.OrigMI = LIS.getInstructionFromIndex(OrigVNI->def);
628 if (Edit->canRematerializeAt(RM, OrigVNI, UseIdx, true)) {
629 Def = Edit->rematerializeAt(MBB, I, Reg, RM, TRI, Late);
635 LaneBitmask LaneMask;
636 if (LI->hasSubRanges()) {
637 LaneMask = LaneBitmask::getNone();
638 for (LiveInterval::SubRange &S : LI->subranges())
639 LaneMask |= S.LaneMask;
641 LaneMask = LaneBitmask::getAll();
645 Def = buildCopy(Edit->getReg(), Reg, LaneMask, MBB, I, Late, RegIdx);
648 // Define the value in Reg.
649 return defValue(RegIdx, ParentVNI, Def, false);
652 /// Create a new virtual register and live interval.
653 unsigned SplitEditor::openIntv() {
654 // Create the complement as index 0.
656 Edit->createEmptyInterval();
658 // Create the open interval.
659 OpenIdx = Edit->size();
660 Edit->createEmptyInterval();
664 void SplitEditor::selectIntv(unsigned Idx) {
665 assert(Idx != 0 && "Cannot select the complement interval");
666 assert(Idx < Edit->size() && "Can only select previously opened interval");
667 DEBUG(dbgs() << " selectIntv " << OpenIdx << " -> " << Idx << '\n');
671 SlotIndex SplitEditor::enterIntvBefore(SlotIndex Idx) {
672 assert(OpenIdx && "openIntv not called before enterIntvBefore");
673 DEBUG(dbgs() << " enterIntvBefore " << Idx);
674 Idx = Idx.getBaseIndex();
675 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
677 DEBUG(dbgs() << ": not live\n");
680 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
681 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
682 assert(MI && "enterIntvBefore called with invalid index");
684 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(), MI);
688 SlotIndex SplitEditor::enterIntvAfter(SlotIndex Idx) {
689 assert(OpenIdx && "openIntv not called before enterIntvAfter");
690 DEBUG(dbgs() << " enterIntvAfter " << Idx);
691 Idx = Idx.getBoundaryIndex();
692 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
694 DEBUG(dbgs() << ": not live\n");
697 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
698 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
699 assert(MI && "enterIntvAfter called with invalid index");
701 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(),
702 std::next(MachineBasicBlock::iterator(MI)));
706 SlotIndex SplitEditor::enterIntvAtEnd(MachineBasicBlock &MBB) {
707 assert(OpenIdx && "openIntv not called before enterIntvAtEnd");
708 SlotIndex End = LIS.getMBBEndIdx(&MBB);
709 SlotIndex Last = End.getPrevSlot();
710 DEBUG(dbgs() << " enterIntvAtEnd BB#" << MBB.getNumber() << ", " << Last);
711 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Last);
713 DEBUG(dbgs() << ": not live\n");
716 DEBUG(dbgs() << ": valno " << ParentVNI->id);
717 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Last, MBB,
718 SA.getLastSplitPointIter(&MBB));
719 RegAssign.insert(VNI->def, End, OpenIdx);
724 /// useIntv - indicate that all instructions in MBB should use OpenLI.
725 void SplitEditor::useIntv(const MachineBasicBlock &MBB) {
726 useIntv(LIS.getMBBStartIdx(&MBB), LIS.getMBBEndIdx(&MBB));
729 void SplitEditor::useIntv(SlotIndex Start, SlotIndex End) {
730 assert(OpenIdx && "openIntv not called before useIntv");
731 DEBUG(dbgs() << " useIntv [" << Start << ';' << End << "):");
732 RegAssign.insert(Start, End, OpenIdx);
736 SlotIndex SplitEditor::leaveIntvAfter(SlotIndex Idx) {
737 assert(OpenIdx && "openIntv not called before leaveIntvAfter");
738 DEBUG(dbgs() << " leaveIntvAfter " << Idx);
740 // The interval must be live beyond the instruction at Idx.
741 SlotIndex Boundary = Idx.getBoundaryIndex();
742 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Boundary);
744 DEBUG(dbgs() << ": not live\n");
745 return Boundary.getNextSlot();
747 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
748 MachineInstr *MI = LIS.getInstructionFromIndex(Boundary);
749 assert(MI && "No instruction at index");
751 // In spill mode, make live ranges as short as possible by inserting the copy
752 // before MI. This is only possible if that instruction doesn't redefine the
753 // value. The inserted COPY is not a kill, and we don't need to recompute
754 // the source live range. The spiller also won't try to hoist this copy.
755 if (SpillMode && !SlotIndex::isSameInstr(ParentVNI->def, Idx) &&
756 MI->readsVirtualRegister(Edit->getReg())) {
757 forceRecompute(0, ParentVNI);
758 defFromParent(0, ParentVNI, Idx, *MI->getParent(), MI);
762 VNInfo *VNI = defFromParent(0, ParentVNI, Boundary, *MI->getParent(),
763 std::next(MachineBasicBlock::iterator(MI)));
767 SlotIndex SplitEditor::leaveIntvBefore(SlotIndex Idx) {
768 assert(OpenIdx && "openIntv not called before leaveIntvBefore");
769 DEBUG(dbgs() << " leaveIntvBefore " << Idx);
771 // The interval must be live into the instruction at Idx.
772 Idx = Idx.getBaseIndex();
773 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
775 DEBUG(dbgs() << ": not live\n");
776 return Idx.getNextSlot();
778 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
780 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
781 assert(MI && "No instruction at index");
782 VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(), MI);
786 SlotIndex SplitEditor::leaveIntvAtTop(MachineBasicBlock &MBB) {
787 assert(OpenIdx && "openIntv not called before leaveIntvAtTop");
788 SlotIndex Start = LIS.getMBBStartIdx(&MBB);
789 DEBUG(dbgs() << " leaveIntvAtTop BB#" << MBB.getNumber() << ", " << Start);
791 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
793 DEBUG(dbgs() << ": not live\n");
797 VNInfo *VNI = defFromParent(0, ParentVNI, Start, MBB,
798 MBB.SkipPHIsLabelsAndDebug(MBB.begin()));
799 RegAssign.insert(Start, VNI->def, OpenIdx);
804 void SplitEditor::overlapIntv(SlotIndex Start, SlotIndex End) {
805 assert(OpenIdx && "openIntv not called before overlapIntv");
806 const VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
807 assert(ParentVNI == Edit->getParent().getVNInfoBefore(End) &&
808 "Parent changes value in extended range");
809 assert(LIS.getMBBFromIndex(Start) == LIS.getMBBFromIndex(End) &&
810 "Range cannot span basic blocks");
812 // The complement interval will be extended as needed by LRCalc.extend().
814 forceRecompute(0, ParentVNI);
815 DEBUG(dbgs() << " overlapIntv [" << Start << ';' << End << "):");
816 RegAssign.insert(Start, End, OpenIdx);
820 //===----------------------------------------------------------------------===//
822 //===----------------------------------------------------------------------===//
824 void SplitEditor::removeBackCopies(SmallVectorImpl<VNInfo*> &Copies) {
825 LiveInterval *LI = &LIS.getInterval(Edit->get(0));
826 DEBUG(dbgs() << "Removing " << Copies.size() << " back-copies.\n");
827 RegAssignMap::iterator AssignI;
828 AssignI.setMap(RegAssign);
830 for (unsigned i = 0, e = Copies.size(); i != e; ++i) {
831 SlotIndex Def = Copies[i]->def;
832 MachineInstr *MI = LIS.getInstructionFromIndex(Def);
833 assert(MI && "No instruction for back-copy");
835 MachineBasicBlock *MBB = MI->getParent();
836 MachineBasicBlock::iterator MBBI(MI);
838 do AtBegin = MBBI == MBB->begin();
839 while (!AtBegin && (--MBBI)->isDebugValue());
841 DEBUG(dbgs() << "Removing " << Def << '\t' << *MI);
842 LIS.removeVRegDefAt(*LI, Def);
843 LIS.RemoveMachineInstrFromMaps(*MI);
844 MI->eraseFromParent();
846 // Adjust RegAssign if a register assignment is killed at Def. We want to
847 // avoid calculating the live range of the source register if possible.
848 AssignI.find(Def.getPrevSlot());
849 if (!AssignI.valid() || AssignI.start() >= Def)
851 // If MI doesn't kill the assigned register, just leave it.
852 if (AssignI.stop() != Def)
854 unsigned RegIdx = AssignI.value();
855 if (AtBegin || !MBBI->readsVirtualRegister(Edit->getReg())) {
856 DEBUG(dbgs() << " cannot find simple kill of RegIdx " << RegIdx << '\n');
857 forceRecompute(RegIdx, Edit->getParent().getVNInfoAt(Def));
859 SlotIndex Kill = LIS.getInstructionIndex(*MBBI).getRegSlot();
860 DEBUG(dbgs() << " move kill to " << Kill << '\t' << *MBBI);
861 AssignI.setStop(Kill);
867 SplitEditor::findShallowDominator(MachineBasicBlock *MBB,
868 MachineBasicBlock *DefMBB) {
871 assert(MDT.dominates(DefMBB, MBB) && "MBB must be dominated by the def.");
873 const MachineLoopInfo &Loops = SA.Loops;
874 const MachineLoop *DefLoop = Loops.getLoopFor(DefMBB);
875 MachineDomTreeNode *DefDomNode = MDT[DefMBB];
877 // Best candidate so far.
878 MachineBasicBlock *BestMBB = MBB;
879 unsigned BestDepth = UINT_MAX;
882 const MachineLoop *Loop = Loops.getLoopFor(MBB);
884 // MBB isn't in a loop, it doesn't get any better. All dominators have a
885 // higher frequency by definition.
887 DEBUG(dbgs() << "Def in BB#" << DefMBB->getNumber() << " dominates BB#"
888 << MBB->getNumber() << " at depth 0\n");
892 // We'll never be able to exit the DefLoop.
893 if (Loop == DefLoop) {
894 DEBUG(dbgs() << "Def in BB#" << DefMBB->getNumber() << " dominates BB#"
895 << MBB->getNumber() << " in the same loop\n");
899 // Least busy dominator seen so far.
900 unsigned Depth = Loop->getLoopDepth();
901 if (Depth < BestDepth) {
904 DEBUG(dbgs() << "Def in BB#" << DefMBB->getNumber() << " dominates BB#"
905 << MBB->getNumber() << " at depth " << Depth << '\n');
908 // Leave loop by going to the immediate dominator of the loop header.
909 // This is a bigger stride than simply walking up the dominator tree.
910 MachineDomTreeNode *IDom = MDT[Loop->getHeader()]->getIDom();
912 // Too far up the dominator tree?
913 if (!IDom || !MDT.dominates(DefDomNode, IDom))
916 MBB = IDom->getBlock();
920 void SplitEditor::computeRedundantBackCopies(
921 DenseSet<unsigned> &NotToHoistSet, SmallVectorImpl<VNInfo *> &BackCopies) {
922 LiveInterval *LI = &LIS.getInterval(Edit->get(0));
923 LiveInterval *Parent = &Edit->getParent();
924 SmallVector<SmallPtrSet<VNInfo *, 8>, 8> EqualVNs(Parent->getNumValNums());
925 SmallPtrSet<VNInfo *, 8> DominatedVNIs;
927 // Aggregate VNIs having the same value as ParentVNI.
928 for (VNInfo *VNI : LI->valnos) {
931 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(VNI->def);
932 EqualVNs[ParentVNI->id].insert(VNI);
935 // For VNI aggregation of each ParentVNI, collect dominated, i.e.,
936 // redundant VNIs to BackCopies.
937 for (unsigned i = 0, e = Parent->getNumValNums(); i != e; ++i) {
938 VNInfo *ParentVNI = Parent->getValNumInfo(i);
939 if (!NotToHoistSet.count(ParentVNI->id))
941 SmallPtrSetIterator<VNInfo *> It1 = EqualVNs[ParentVNI->id].begin();
942 SmallPtrSetIterator<VNInfo *> It2 = It1;
943 for (; It1 != EqualVNs[ParentVNI->id].end(); ++It1) {
945 for (++It2; It2 != EqualVNs[ParentVNI->id].end(); ++It2) {
946 if (DominatedVNIs.count(*It1) || DominatedVNIs.count(*It2))
949 MachineBasicBlock *MBB1 = LIS.getMBBFromIndex((*It1)->def);
950 MachineBasicBlock *MBB2 = LIS.getMBBFromIndex((*It2)->def);
952 DominatedVNIs.insert((*It1)->def < (*It2)->def ? (*It2) : (*It1));
953 } else if (MDT.dominates(MBB1, MBB2)) {
954 DominatedVNIs.insert(*It2);
955 } else if (MDT.dominates(MBB2, MBB1)) {
956 DominatedVNIs.insert(*It1);
960 if (!DominatedVNIs.empty()) {
961 forceRecompute(0, ParentVNI);
962 for (auto VNI : DominatedVNIs) {
963 BackCopies.push_back(VNI);
965 DominatedVNIs.clear();
970 /// For SM_Size mode, find a common dominator for all the back-copies for
971 /// the same ParentVNI and hoist the backcopies to the dominator BB.
972 /// For SM_Speed mode, if the common dominator is hot and it is not beneficial
973 /// to do the hoisting, simply remove the dominated backcopies for the same
975 void SplitEditor::hoistCopies() {
976 // Get the complement interval, always RegIdx 0.
977 LiveInterval *LI = &LIS.getInterval(Edit->get(0));
978 LiveInterval *Parent = &Edit->getParent();
980 // Track the nearest common dominator for all back-copies for each ParentVNI,
981 // indexed by ParentVNI->id.
982 typedef std::pair<MachineBasicBlock*, SlotIndex> DomPair;
983 SmallVector<DomPair, 8> NearestDom(Parent->getNumValNums());
984 // The total cost of all the back-copies for each ParentVNI.
985 SmallVector<BlockFrequency, 8> Costs(Parent->getNumValNums());
986 // The ParentVNI->id set for which hoisting back-copies are not beneficial
988 DenseSet<unsigned> NotToHoistSet;
990 // Find the nearest common dominator for parent values with multiple
991 // back-copies. If a single back-copy dominates, put it in DomPair.second.
992 for (VNInfo *VNI : LI->valnos) {
995 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(VNI->def);
996 assert(ParentVNI && "Parent not live at complement def");
998 // Don't hoist remats. The complement is probably going to disappear
999 // completely anyway.
1000 if (Edit->didRematerialize(ParentVNI))
1003 MachineBasicBlock *ValMBB = LIS.getMBBFromIndex(VNI->def);
1005 DomPair &Dom = NearestDom[ParentVNI->id];
1007 // Keep directly defined parent values. This is either a PHI or an
1008 // instruction in the complement range. All other copies of ParentVNI
1009 // should be eliminated.
1010 if (VNI->def == ParentVNI->def) {
1011 DEBUG(dbgs() << "Direct complement def at " << VNI->def << '\n');
1012 Dom = DomPair(ValMBB, VNI->def);
1015 // Skip the singly mapped values. There is nothing to gain from hoisting a
1016 // single back-copy.
1017 if (Values.lookup(std::make_pair(0, ParentVNI->id)).getPointer()) {
1018 DEBUG(dbgs() << "Single complement def at " << VNI->def << '\n');
1023 // First time we see ParentVNI. VNI dominates itself.
1024 Dom = DomPair(ValMBB, VNI->def);
1025 } else if (Dom.first == ValMBB) {
1026 // Two defs in the same block. Pick the earlier def.
1027 if (!Dom.second.isValid() || VNI->def < Dom.second)
1028 Dom.second = VNI->def;
1030 // Different basic blocks. Check if one dominates.
1031 MachineBasicBlock *Near =
1032 MDT.findNearestCommonDominator(Dom.first, ValMBB);
1034 // Def ValMBB dominates.
1035 Dom = DomPair(ValMBB, VNI->def);
1036 else if (Near != Dom.first)
1037 // None dominate. Hoist to common dominator, need new def.
1038 Dom = DomPair(Near, SlotIndex());
1039 Costs[ParentVNI->id] += MBFI.getBlockFreq(ValMBB);
1042 DEBUG(dbgs() << "Multi-mapped complement " << VNI->id << '@' << VNI->def
1043 << " for parent " << ParentVNI->id << '@' << ParentVNI->def
1044 << " hoist to BB#" << Dom.first->getNumber() << ' '
1045 << Dom.second << '\n');
1048 // Insert the hoisted copies.
1049 for (unsigned i = 0, e = Parent->getNumValNums(); i != e; ++i) {
1050 DomPair &Dom = NearestDom[i];
1051 if (!Dom.first || Dom.second.isValid())
1053 // This value needs a hoisted copy inserted at the end of Dom.first.
1054 VNInfo *ParentVNI = Parent->getValNumInfo(i);
1055 MachineBasicBlock *DefMBB = LIS.getMBBFromIndex(ParentVNI->def);
1056 // Get a less loopy dominator than Dom.first.
1057 Dom.first = findShallowDominator(Dom.first, DefMBB);
1058 if (SpillMode == SM_Speed &&
1059 MBFI.getBlockFreq(Dom.first) > Costs[ParentVNI->id]) {
1060 NotToHoistSet.insert(ParentVNI->id);
1063 SlotIndex Last = LIS.getMBBEndIdx(Dom.first).getPrevSlot();
1065 defFromParent(0, ParentVNI, Last, *Dom.first,
1066 SA.getLastSplitPointIter(Dom.first))->def;
1069 // Remove redundant back-copies that are now known to be dominated by another
1070 // def with the same value.
1071 SmallVector<VNInfo*, 8> BackCopies;
1072 for (VNInfo *VNI : LI->valnos) {
1073 if (VNI->isUnused())
1075 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(VNI->def);
1076 const DomPair &Dom = NearestDom[ParentVNI->id];
1077 if (!Dom.first || Dom.second == VNI->def ||
1078 NotToHoistSet.count(ParentVNI->id))
1080 BackCopies.push_back(VNI);
1081 forceRecompute(0, ParentVNI);
1084 // If it is not beneficial to hoist all the BackCopies, simply remove
1085 // redundant BackCopies in speed mode.
1086 if (SpillMode == SM_Speed && !NotToHoistSet.empty())
1087 computeRedundantBackCopies(NotToHoistSet, BackCopies);
1089 removeBackCopies(BackCopies);
1093 /// transferValues - Transfer all possible values to the new live ranges.
1094 /// Values that were rematerialized are left alone, they need LRCalc.extend().
1095 bool SplitEditor::transferValues() {
1096 bool Skipped = false;
1097 RegAssignMap::const_iterator AssignI = RegAssign.begin();
1098 for (const LiveRange::Segment &S : Edit->getParent()) {
1099 DEBUG(dbgs() << " blit " << S << ':');
1100 VNInfo *ParentVNI = S.valno;
1101 // RegAssign has holes where RegIdx 0 should be used.
1102 SlotIndex Start = S.start;
1103 AssignI.advanceTo(Start);
1106 SlotIndex End = S.end;
1107 if (!AssignI.valid()) {
1109 } else if (AssignI.start() <= Start) {
1110 RegIdx = AssignI.value();
1111 if (AssignI.stop() < End) {
1112 End = AssignI.stop();
1117 End = std::min(End, AssignI.start());
1120 // The interval [Start;End) is continuously mapped to RegIdx, ParentVNI.
1121 DEBUG(dbgs() << " [" << Start << ';' << End << ")=" << RegIdx
1122 << '(' << PrintReg(Edit->get(RegIdx)) << ')');
1123 LiveInterval &LI = LIS.getInterval(Edit->get(RegIdx));
1125 // Check for a simply defined value that can be blitted directly.
1126 ValueForcePair VFP = Values.lookup(std::make_pair(RegIdx, ParentVNI->id));
1127 if (VNInfo *VNI = VFP.getPointer()) {
1128 DEBUG(dbgs() << ':' << VNI->id);
1129 LI.addSegment(LiveInterval::Segment(Start, End, VNI));
1134 // Skip values with forced recomputation.
1136 DEBUG(dbgs() << "(recalc)");
1142 LiveRangeCalc &LRC = getLRCalc(RegIdx);
1144 // This value has multiple defs in RegIdx, but it wasn't rematerialized,
1145 // so the live range is accurate. Add live-in blocks in [Start;End) to the
1147 MachineFunction::iterator MBB = LIS.getMBBFromIndex(Start)->getIterator();
1148 SlotIndex BlockStart, BlockEnd;
1149 std::tie(BlockStart, BlockEnd) = LIS.getSlotIndexes()->getMBBRange(&*MBB);
1151 // The first block may be live-in, or it may have its own def.
1152 if (Start != BlockStart) {
1153 VNInfo *VNI = LI.extendInBlock(BlockStart, std::min(BlockEnd, End));
1154 assert(VNI && "Missing def for complex mapped value");
1155 DEBUG(dbgs() << ':' << VNI->id << "*BB#" << MBB->getNumber());
1156 // MBB has its own def. Is it also live-out?
1157 if (BlockEnd <= End)
1158 LRC.setLiveOutValue(&*MBB, VNI);
1160 // Skip to the next block for live-in.
1162 BlockStart = BlockEnd;
1165 // Handle the live-in blocks covered by [Start;End).
1166 assert(Start <= BlockStart && "Expected live-in block");
1167 while (BlockStart < End) {
1168 DEBUG(dbgs() << ">BB#" << MBB->getNumber());
1169 BlockEnd = LIS.getMBBEndIdx(&*MBB);
1170 if (BlockStart == ParentVNI->def) {
1171 // This block has the def of a parent PHI, so it isn't live-in.
1172 assert(ParentVNI->isPHIDef() && "Non-phi defined at block start?");
1173 VNInfo *VNI = LI.extendInBlock(BlockStart, std::min(BlockEnd, End));
1174 assert(VNI && "Missing def for complex mapped parent PHI");
1175 if (End >= BlockEnd)
1176 LRC.setLiveOutValue(&*MBB, VNI); // Live-out as well.
1178 // This block needs a live-in value. The last block covered may not
1181 LRC.addLiveInBlock(LI, MDT[&*MBB], End);
1183 // Live-through, and we don't know the value.
1184 LRC.addLiveInBlock(LI, MDT[&*MBB]);
1185 LRC.setLiveOutValue(&*MBB, nullptr);
1188 BlockStart = BlockEnd;
1192 } while (Start != S.end);
1193 DEBUG(dbgs() << '\n');
1196 LRCalc[0].calculateValues();
1198 LRCalc[1].calculateValues();
1203 static bool removeDeadSegment(SlotIndex Def, LiveRange &LR) {
1204 const LiveRange::Segment *Seg = LR.getSegmentContaining(Def);
1207 if (Seg->end != Def.getDeadSlot())
1209 // This is a dead PHI. Remove it.
1210 LR.removeSegment(*Seg, true);
1214 void SplitEditor::extendPHIRange(MachineBasicBlock &B, LiveRangeCalc &LRC,
1215 LiveRange &LR, LaneBitmask LM,
1216 ArrayRef<SlotIndex> Undefs) {
1217 for (MachineBasicBlock *P : B.predecessors()) {
1218 SlotIndex End = LIS.getMBBEndIdx(P);
1219 SlotIndex LastUse = End.getPrevSlot();
1220 // The predecessor may not have a live-out value. That is OK, like an
1221 // undef PHI operand.
1222 LiveInterval &PLI = Edit->getParent();
1223 // Need the cast because the inputs to ?: would otherwise be deemed
1224 // "incompatible": SubRange vs LiveInterval.
1225 LiveRange &PSR = !LM.all() ? getSubRangeForMask(LM, PLI)
1226 : static_cast<LiveRange&>(PLI);
1227 if (PSR.liveAt(LastUse))
1228 LRC.extend(LR, End, /*PhysReg=*/0, Undefs);
1232 void SplitEditor::extendPHIKillRanges() {
1233 // Extend live ranges to be live-out for successor PHI values.
1235 // Visit each PHI def slot in the parent live interval. If the def is dead,
1236 // remove it. Otherwise, extend the live interval to reach the end indexes
1237 // of all predecessor blocks.
1239 LiveInterval &ParentLI = Edit->getParent();
1240 for (const VNInfo *V : ParentLI.valnos) {
1241 if (V->isUnused() || !V->isPHIDef())
1244 unsigned RegIdx = RegAssign.lookup(V->def);
1245 LiveInterval &LI = LIS.getInterval(Edit->get(RegIdx));
1246 LiveRangeCalc &LRC = getLRCalc(RegIdx);
1247 MachineBasicBlock &B = *LIS.getMBBFromIndex(V->def);
1248 if (!removeDeadSegment(V->def, LI))
1249 extendPHIRange(B, LRC, LI, LaneBitmask::getAll(), /*Undefs=*/{});
1252 SmallVector<SlotIndex, 4> Undefs;
1253 LiveRangeCalc SubLRC;
1255 for (LiveInterval::SubRange &PS : ParentLI.subranges()) {
1256 for (const VNInfo *V : PS.valnos) {
1257 if (V->isUnused() || !V->isPHIDef())
1259 unsigned RegIdx = RegAssign.lookup(V->def);
1260 LiveInterval &LI = LIS.getInterval(Edit->get(RegIdx));
1261 LiveInterval::SubRange &S = getSubRangeForMask(PS.LaneMask, LI);
1262 if (removeDeadSegment(V->def, S))
1265 MachineBasicBlock &B = *LIS.getMBBFromIndex(V->def);
1266 SubLRC.reset(&VRM.getMachineFunction(), LIS.getSlotIndexes(), &MDT,
1267 &LIS.getVNInfoAllocator());
1269 LI.computeSubRangeUndefs(Undefs, PS.LaneMask, MRI, *LIS.getSlotIndexes());
1270 extendPHIRange(B, SubLRC, S, PS.LaneMask, Undefs);
1275 /// rewriteAssigned - Rewrite all uses of Edit->getReg().
1276 void SplitEditor::rewriteAssigned(bool ExtendRanges) {
1278 ExtPoint(const MachineOperand &O, unsigned R, SlotIndex N)
1279 : MO(O), RegIdx(R), Next(N) {}
1285 SmallVector<ExtPoint,4> ExtPoints;
1287 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Edit->getReg()),
1288 RE = MRI.reg_end(); RI != RE;) {
1289 MachineOperand &MO = *RI;
1290 MachineInstr *MI = MO.getParent();
1292 // LiveDebugVariables should have handled all DBG_VALUE instructions.
1293 if (MI->isDebugValue()) {
1294 DEBUG(dbgs() << "Zapping " << *MI);
1299 // <undef> operands don't really read the register, so it doesn't matter
1300 // which register we choose. When the use operand is tied to a def, we must
1301 // use the same register as the def, so just do that always.
1302 SlotIndex Idx = LIS.getInstructionIndex(*MI);
1303 if (MO.isDef() || MO.isUndef())
1304 Idx = Idx.getRegSlot(MO.isEarlyClobber());
1306 // Rewrite to the mapped register at Idx.
1307 unsigned RegIdx = RegAssign.lookup(Idx);
1308 LiveInterval &LI = LIS.getInterval(Edit->get(RegIdx));
1310 DEBUG(dbgs() << " rewr BB#" << MI->getParent()->getNumber() << '\t'
1311 << Idx << ':' << RegIdx << '\t' << *MI);
1313 // Extend liveness to Idx if the instruction reads reg.
1314 if (!ExtendRanges || MO.isUndef())
1317 // Skip instructions that don't read Reg.
1319 if (!MO.getSubReg() && !MO.isEarlyClobber())
1321 // We may want to extend a live range for a partial redef, or for a use
1322 // tied to an early clobber.
1323 Idx = Idx.getPrevSlot();
1324 if (!Edit->getParent().liveAt(Idx))
1327 Idx = Idx.getRegSlot(true);
1329 SlotIndex Next = Idx.getNextSlot();
1330 if (LI.hasSubRanges()) {
1331 // We have to delay extending subranges until we have seen all operands
1332 // defining the register. This is because a <def,read-undef> operand
1333 // will create an "undef" point, and we cannot extend any subranges
1334 // until all of them have been accounted for.
1336 ExtPoints.push_back(ExtPoint(MO, RegIdx, Next));
1338 LiveRangeCalc &LRC = getLRCalc(RegIdx);
1339 LRC.extend(LI, Next, 0, ArrayRef<SlotIndex>());
1343 for (ExtPoint &EP : ExtPoints) {
1344 LiveInterval &LI = LIS.getInterval(Edit->get(EP.RegIdx));
1345 assert(LI.hasSubRanges());
1347 LiveRangeCalc SubLRC;
1348 unsigned Reg = EP.MO.getReg(), Sub = EP.MO.getSubReg();
1349 LaneBitmask LM = Sub != 0 ? TRI.getSubRegIndexLaneMask(Sub)
1350 : MRI.getMaxLaneMaskForVReg(Reg);
1351 for (LiveInterval::SubRange &S : LI.subranges()) {
1352 if ((S.LaneMask & LM).none())
1354 // The problem here can be that the new register may have been created
1355 // for a partially defined original register. For example:
1356 // %vreg827:subreg_hireg<def,read-undef> = ...
1358 // %vreg828<def> = COPY %vreg827
1361 SubLRC.reset(&VRM.getMachineFunction(), LIS.getSlotIndexes(), &MDT,
1362 &LIS.getVNInfoAllocator());
1363 SmallVector<SlotIndex, 4> Undefs;
1364 LI.computeSubRangeUndefs(Undefs, S.LaneMask, MRI, *LIS.getSlotIndexes());
1365 SubLRC.extend(S, EP.Next, 0, Undefs);
1369 for (unsigned R : *Edit) {
1370 LiveInterval &LI = LIS.getInterval(R);
1371 if (!LI.hasSubRanges())
1374 LI.removeEmptySubRanges();
1375 LIS.constructMainRangeFromSubranges(LI);
1379 void SplitEditor::deleteRematVictims() {
1380 SmallVector<MachineInstr*, 8> Dead;
1381 for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I){
1382 LiveInterval *LI = &LIS.getInterval(*I);
1383 for (const LiveRange::Segment &S : LI->segments) {
1384 // Dead defs end at the dead slot.
1385 if (S.end != S.valno->def.getDeadSlot())
1387 if (S.valno->isPHIDef())
1389 MachineInstr *MI = LIS.getInstructionFromIndex(S.valno->def);
1390 assert(MI && "Missing instruction for dead def");
1391 MI->addRegisterDead(LI->reg, &TRI);
1393 if (!MI->allDefsAreDead())
1396 DEBUG(dbgs() << "All defs dead: " << *MI);
1404 Edit->eliminateDeadDefs(Dead, None, &AA);
1407 void SplitEditor::finish(SmallVectorImpl<unsigned> *LRMap) {
1410 // At this point, the live intervals in Edit contain VNInfos corresponding to
1411 // the inserted copies.
1413 // Add the original defs from the parent interval.
1414 for (const VNInfo *ParentVNI : Edit->getParent().valnos) {
1415 if (ParentVNI->isUnused())
1417 unsigned RegIdx = RegAssign.lookup(ParentVNI->def);
1418 defValue(RegIdx, ParentVNI, ParentVNI->def, true);
1420 // Force rematted values to be recomputed everywhere.
1421 // The new live ranges may be truncated.
1422 if (Edit->didRematerialize(ParentVNI))
1423 for (unsigned i = 0, e = Edit->size(); i != e; ++i)
1424 forceRecompute(i, ParentVNI);
1427 // Hoist back-copies to the complement interval when in spill mode.
1428 switch (SpillMode) {
1430 // Leave all back-copies as is.
1434 // hoistCopies will behave differently between size and speed.
1438 // Transfer the simply mapped values, check if any are skipped.
1439 bool Skipped = transferValues();
1441 // Rewrite virtual registers, possibly extending ranges.
1442 rewriteAssigned(Skipped);
1445 extendPHIKillRanges();
1449 // Delete defs that were rematted everywhere.
1451 deleteRematVictims();
1453 // Get rid of unused values and set phi-kill flags.
1454 for (unsigned Reg : *Edit) {
1455 LiveInterval &LI = LIS.getInterval(Reg);
1456 LI.removeEmptySubRanges();
1457 LI.RenumberValues();
1460 // Provide a reverse mapping from original indices to Edit ranges.
1463 for (unsigned i = 0, e = Edit->size(); i != e; ++i)
1464 LRMap->push_back(i);
1467 // Now check if any registers were separated into multiple components.
1468 ConnectedVNInfoEqClasses ConEQ(LIS);
1469 for (unsigned i = 0, e = Edit->size(); i != e; ++i) {
1470 // Don't use iterators, they are invalidated by create() below.
1471 unsigned VReg = Edit->get(i);
1472 LiveInterval &LI = LIS.getInterval(VReg);
1473 SmallVector<LiveInterval*, 8> SplitLIs;
1474 LIS.splitSeparateComponents(LI, SplitLIs);
1475 unsigned Original = VRM.getOriginal(VReg);
1476 for (LiveInterval *SplitLI : SplitLIs)
1477 VRM.setIsSplitFromReg(SplitLI->reg, Original);
1479 // The new intervals all map back to i.
1481 LRMap->resize(Edit->size(), i);
1484 // Calculate spill weight and allocation hints for new intervals.
1485 Edit->calculateRegClassAndHint(VRM.getMachineFunction(), SA.Loops, MBFI);
1487 assert(!LRMap || LRMap->size() == Edit->size());
1491 //===----------------------------------------------------------------------===//
1492 // Single Block Splitting
1493 //===----------------------------------------------------------------------===//
1495 bool SplitAnalysis::shouldSplitSingleBlock(const BlockInfo &BI,
1496 bool SingleInstrs) const {
1497 // Always split for multiple instructions.
1498 if (!BI.isOneInstr())
1500 // Don't split for single instructions unless explicitly requested.
1503 // Splitting a live-through range always makes progress.
1504 if (BI.LiveIn && BI.LiveOut)
1506 // No point in isolating a copy. It has no register class constraints.
1507 if (LIS.getInstructionFromIndex(BI.FirstInstr)->isCopyLike())
1509 // Finally, don't isolate an end point that was created by earlier splits.
1510 return isOriginalEndpoint(BI.FirstInstr);
1513 void SplitEditor::splitSingleBlock(const SplitAnalysis::BlockInfo &BI) {
1515 SlotIndex LastSplitPoint = SA.getLastSplitPoint(BI.MBB->getNumber());
1516 SlotIndex SegStart = enterIntvBefore(std::min(BI.FirstInstr,
1518 if (!BI.LiveOut || BI.LastInstr < LastSplitPoint) {
1519 useIntv(SegStart, leaveIntvAfter(BI.LastInstr));
1521 // The last use is after the last valid split point.
1522 SlotIndex SegStop = leaveIntvBefore(LastSplitPoint);
1523 useIntv(SegStart, SegStop);
1524 overlapIntv(SegStop, BI.LastInstr);
1529 //===----------------------------------------------------------------------===//
1530 // Global Live Range Splitting Support
1531 //===----------------------------------------------------------------------===//
1533 // These methods support a method of global live range splitting that uses a
1534 // global algorithm to decide intervals for CFG edges. They will insert split
1535 // points and color intervals in basic blocks while avoiding interference.
1537 // Note that splitSingleBlock is also useful for blocks where both CFG edges
1538 // are on the stack.
1540 void SplitEditor::splitLiveThroughBlock(unsigned MBBNum,
1541 unsigned IntvIn, SlotIndex LeaveBefore,
1542 unsigned IntvOut, SlotIndex EnterAfter){
1543 SlotIndex Start, Stop;
1544 std::tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(MBBNum);
1546 DEBUG(dbgs() << "BB#" << MBBNum << " [" << Start << ';' << Stop
1547 << ") intf " << LeaveBefore << '-' << EnterAfter
1548 << ", live-through " << IntvIn << " -> " << IntvOut);
1550 assert((IntvIn || IntvOut) && "Use splitSingleBlock for isolated blocks");
1552 assert((!LeaveBefore || LeaveBefore < Stop) && "Interference after block");
1553 assert((!IntvIn || !LeaveBefore || LeaveBefore > Start) && "Impossible intf");
1554 assert((!EnterAfter || EnterAfter >= Start) && "Interference before block");
1556 MachineBasicBlock *MBB = VRM.getMachineFunction().getBlockNumbered(MBBNum);
1559 DEBUG(dbgs() << ", spill on entry.\n");
1561 // <<<<<<<<< Possible LeaveBefore interference.
1562 // |-----------| Live through.
1563 // -____________ Spill on entry.
1566 SlotIndex Idx = leaveIntvAtTop(*MBB);
1567 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1573 DEBUG(dbgs() << ", reload on exit.\n");
1575 // >>>>>>> Possible EnterAfter interference.
1576 // |-----------| Live through.
1577 // ___________-- Reload on exit.
1579 selectIntv(IntvOut);
1580 SlotIndex Idx = enterIntvAtEnd(*MBB);
1581 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1586 if (IntvIn == IntvOut && !LeaveBefore && !EnterAfter) {
1587 DEBUG(dbgs() << ", straight through.\n");
1589 // |-----------| Live through.
1590 // ------------- Straight through, same intv, no interference.
1592 selectIntv(IntvOut);
1593 useIntv(Start, Stop);
1597 // We cannot legally insert splits after LSP.
1598 SlotIndex LSP = SA.getLastSplitPoint(MBBNum);
1599 assert((!IntvOut || !EnterAfter || EnterAfter < LSP) && "Impossible intf");
1601 if (IntvIn != IntvOut && (!LeaveBefore || !EnterAfter ||
1602 LeaveBefore.getBaseIndex() > EnterAfter.getBoundaryIndex())) {
1603 DEBUG(dbgs() << ", switch avoiding interference.\n");
1605 // >>>> <<<< Non-overlapping EnterAfter/LeaveBefore interference.
1606 // |-----------| Live through.
1607 // ------======= Switch intervals between interference.
1609 selectIntv(IntvOut);
1611 if (LeaveBefore && LeaveBefore < LSP) {
1612 Idx = enterIntvBefore(LeaveBefore);
1615 Idx = enterIntvAtEnd(*MBB);
1618 useIntv(Start, Idx);
1619 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1620 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1624 DEBUG(dbgs() << ", create local intv for interference.\n");
1626 // >>><><><><<<< Overlapping EnterAfter/LeaveBefore interference.
1627 // |-----------| Live through.
1628 // ==---------== Switch intervals before/after interference.
1630 assert(LeaveBefore <= EnterAfter && "Missed case");
1632 selectIntv(IntvOut);
1633 SlotIndex Idx = enterIntvAfter(EnterAfter);
1635 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1638 Idx = leaveIntvBefore(LeaveBefore);
1639 useIntv(Start, Idx);
1640 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1644 void SplitEditor::splitRegInBlock(const SplitAnalysis::BlockInfo &BI,
1645 unsigned IntvIn, SlotIndex LeaveBefore) {
1646 SlotIndex Start, Stop;
1647 std::tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
1649 DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " [" << Start << ';' << Stop
1650 << "), uses " << BI.FirstInstr << '-' << BI.LastInstr
1651 << ", reg-in " << IntvIn << ", leave before " << LeaveBefore
1652 << (BI.LiveOut ? ", stack-out" : ", killed in block"));
1654 assert(IntvIn && "Must have register in");
1655 assert(BI.LiveIn && "Must be live-in");
1656 assert((!LeaveBefore || LeaveBefore > Start) && "Bad interference");
1658 if (!BI.LiveOut && (!LeaveBefore || LeaveBefore >= BI.LastInstr)) {
1659 DEBUG(dbgs() << " before interference.\n");
1661 // <<< Interference after kill.
1662 // |---o---x | Killed in block.
1663 // ========= Use IntvIn everywhere.
1666 useIntv(Start, BI.LastInstr);
1670 SlotIndex LSP = SA.getLastSplitPoint(BI.MBB->getNumber());
1672 if (!LeaveBefore || LeaveBefore > BI.LastInstr.getBoundaryIndex()) {
1674 // <<< Possible interference after last use.
1675 // |---o---o---| Live-out on stack.
1676 // =========____ Leave IntvIn after last use.
1678 // < Interference after last use.
1679 // |---o---o--o| Live-out on stack, late last use.
1680 // ============ Copy to stack after LSP, overlap IntvIn.
1681 // \_____ Stack interval is live-out.
1683 if (BI.LastInstr < LSP) {
1684 DEBUG(dbgs() << ", spill after last use before interference.\n");
1686 SlotIndex Idx = leaveIntvAfter(BI.LastInstr);
1687 useIntv(Start, Idx);
1688 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1690 DEBUG(dbgs() << ", spill before last split point.\n");
1692 SlotIndex Idx = leaveIntvBefore(LSP);
1693 overlapIntv(Idx, BI.LastInstr);
1694 useIntv(Start, Idx);
1695 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1700 // The interference is overlapping somewhere we wanted to use IntvIn. That
1701 // means we need to create a local interval that can be allocated a
1702 // different register.
1703 unsigned LocalIntv = openIntv();
1705 DEBUG(dbgs() << ", creating local interval " << LocalIntv << ".\n");
1707 if (!BI.LiveOut || BI.LastInstr < LSP) {
1709 // <<<<<<< Interference overlapping uses.
1710 // |---o---o---| Live-out on stack.
1711 // =====----____ Leave IntvIn before interference, then spill.
1713 SlotIndex To = leaveIntvAfter(BI.LastInstr);
1714 SlotIndex From = enterIntvBefore(LeaveBefore);
1717 useIntv(Start, From);
1718 assert((!LeaveBefore || From <= LeaveBefore) && "Interference");
1722 // <<<<<<< Interference overlapping uses.
1723 // |---o---o--o| Live-out on stack, late last use.
1724 // =====------- Copy to stack before LSP, overlap LocalIntv.
1725 // \_____ Stack interval is live-out.
1727 SlotIndex To = leaveIntvBefore(LSP);
1728 overlapIntv(To, BI.LastInstr);
1729 SlotIndex From = enterIntvBefore(std::min(To, LeaveBefore));
1732 useIntv(Start, From);
1733 assert((!LeaveBefore || From <= LeaveBefore) && "Interference");
1736 void SplitEditor::splitRegOutBlock(const SplitAnalysis::BlockInfo &BI,
1737 unsigned IntvOut, SlotIndex EnterAfter) {
1738 SlotIndex Start, Stop;
1739 std::tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
1741 DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " [" << Start << ';' << Stop
1742 << "), uses " << BI.FirstInstr << '-' << BI.LastInstr
1743 << ", reg-out " << IntvOut << ", enter after " << EnterAfter
1744 << (BI.LiveIn ? ", stack-in" : ", defined in block"));
1746 SlotIndex LSP = SA.getLastSplitPoint(BI.MBB->getNumber());
1748 assert(IntvOut && "Must have register out");
1749 assert(BI.LiveOut && "Must be live-out");
1750 assert((!EnterAfter || EnterAfter < LSP) && "Bad interference");
1752 if (!BI.LiveIn && (!EnterAfter || EnterAfter <= BI.FirstInstr)) {
1753 DEBUG(dbgs() << " after interference.\n");
1755 // >>>> Interference before def.
1756 // | o---o---| Defined in block.
1757 // ========= Use IntvOut everywhere.
1759 selectIntv(IntvOut);
1760 useIntv(BI.FirstInstr, Stop);
1764 if (!EnterAfter || EnterAfter < BI.FirstInstr.getBaseIndex()) {
1765 DEBUG(dbgs() << ", reload after interference.\n");
1767 // >>>> Interference before def.
1768 // |---o---o---| Live-through, stack-in.
1769 // ____========= Enter IntvOut before first use.
1771 selectIntv(IntvOut);
1772 SlotIndex Idx = enterIntvBefore(std::min(LSP, BI.FirstInstr));
1774 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1778 // The interference is overlapping somewhere we wanted to use IntvOut. That
1779 // means we need to create a local interval that can be allocated a
1780 // different register.
1781 DEBUG(dbgs() << ", interference overlaps uses.\n");
1783 // >>>>>>> Interference overlapping uses.
1784 // |---o---o---| Live-through, stack-in.
1785 // ____---====== Create local interval for interference range.
1787 selectIntv(IntvOut);
1788 SlotIndex Idx = enterIntvAfter(EnterAfter);
1790 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1793 SlotIndex From = enterIntvBefore(std::min(Idx, BI.FirstInstr));