1 //===- TailDuplicator.cpp - Duplicate blocks into predecessors' tails -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This utility class duplicates basic blocks ending in unconditional branches
11 // into the tails of their predecessors.
13 //===----------------------------------------------------------------------===//
15 #include "llvm/ADT/DenseMap.h"
16 #include "llvm/ADT/DenseSet.h"
17 #include "llvm/ADT/SetVector.h"
18 #include "llvm/ADT/SmallPtrSet.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/ADT/Statistic.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/CodeGen/MachineBasicBlock.h"
23 #include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineOperand.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/MachineSSAUpdater.h"
30 #include "llvm/CodeGen/TailDuplicator.h"
31 #include "llvm/IR/DebugLoc.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetSubtargetInfo.h"
47 #define DEBUG_TYPE "tailduplication"
49 STATISTIC(NumTails, "Number of tails duplicated");
50 STATISTIC(NumTailDups, "Number of tail duplicated blocks");
51 STATISTIC(NumTailDupAdded,
52 "Number of instructions added due to tail duplication");
53 STATISTIC(NumTailDupRemoved,
54 "Number of instructions removed due to tail duplication");
55 STATISTIC(NumDeadBlocks, "Number of dead blocks removed");
56 STATISTIC(NumAddedPHIs, "Number of phis added");
58 // Heuristic for tail duplication.
59 static cl::opt<unsigned> TailDuplicateSize(
61 cl::desc("Maximum instructions to consider tail duplicating"), cl::init(2),
64 static cl::opt<unsigned> TailDupIndirectBranchSize(
65 "tail-dup-indirect-size",
66 cl::desc("Maximum instructions to consider tail duplicating blocks that "
67 "end with indirect branches."), cl::init(20),
71 TailDupVerify("tail-dup-verify",
72 cl::desc("Verify sanity of PHI instructions during taildup"),
73 cl::init(false), cl::Hidden);
75 static cl::opt<unsigned> TailDupLimit("tail-dup-limit", cl::init(~0U),
78 void TailDuplicator::initMF(MachineFunction &MFin,
79 const MachineBranchProbabilityInfo *MBPIin,
80 bool LayoutModeIn, unsigned TailDupSizeIn) {
82 TII = MF->getSubtarget().getInstrInfo();
83 TRI = MF->getSubtarget().getRegisterInfo();
84 MRI = &MF->getRegInfo();
87 TailDupSize = TailDupSizeIn;
89 assert(MBPI != nullptr && "Machine Branch Probability Info required");
91 LayoutMode = LayoutModeIn;
92 PreRegAlloc = MRI->isSSA();
95 static void VerifyPHIs(MachineFunction &MF, bool CheckExtra) {
96 for (MachineFunction::iterator I = ++MF.begin(), E = MF.end(); I != E; ++I) {
97 MachineBasicBlock *MBB = &*I;
98 SmallSetVector<MachineBasicBlock *, 8> Preds(MBB->pred_begin(),
100 MachineBasicBlock::iterator MI = MBB->begin();
101 while (MI != MBB->end()) {
104 for (MachineBasicBlock *PredBB : Preds) {
106 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i += 2) {
107 MachineBasicBlock *PHIBB = MI->getOperand(i + 1).getMBB();
108 if (PHIBB == PredBB) {
114 dbgs() << "Malformed PHI in BB#" << MBB->getNumber() << ": " << *MI;
115 dbgs() << " missing input from predecessor BB#"
116 << PredBB->getNumber() << '\n';
117 llvm_unreachable(nullptr);
121 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i += 2) {
122 MachineBasicBlock *PHIBB = MI->getOperand(i + 1).getMBB();
123 if (CheckExtra && !Preds.count(PHIBB)) {
124 dbgs() << "Warning: malformed PHI in BB#" << MBB->getNumber() << ": "
126 dbgs() << " extra input from predecessor BB#" << PHIBB->getNumber()
128 llvm_unreachable(nullptr);
130 if (PHIBB->getNumber() < 0) {
131 dbgs() << "Malformed PHI in BB#" << MBB->getNumber() << ": " << *MI;
132 dbgs() << " non-existing BB#" << PHIBB->getNumber() << '\n';
133 llvm_unreachable(nullptr);
141 /// Tail duplicate the block and cleanup.
142 /// \p IsSimple - return value of isSimpleBB
143 /// \p MBB - block to be duplicated
144 /// \p ForcedLayoutPred - If non-null, treat this block as the layout
145 /// predecessor, instead of using the ordering in MF
146 /// \p DuplicatedPreds - if non-null, \p DuplicatedPreds will contain a list of
147 /// all Preds that received a copy of \p MBB.
148 /// \p RemovalCallback - if non-null, called just before MBB is deleted.
149 bool TailDuplicator::tailDuplicateAndUpdate(
150 bool IsSimple, MachineBasicBlock *MBB,
151 MachineBasicBlock *ForcedLayoutPred,
152 SmallVectorImpl<MachineBasicBlock*> *DuplicatedPreds,
153 function_ref<void(MachineBasicBlock *)> *RemovalCallback) {
154 // Save the successors list.
155 SmallSetVector<MachineBasicBlock *, 8> Succs(MBB->succ_begin(),
158 SmallVector<MachineBasicBlock *, 8> TDBBs;
159 SmallVector<MachineInstr *, 16> Copies;
160 if (!tailDuplicate(IsSimple, MBB, ForcedLayoutPred, TDBBs, Copies))
165 SmallVector<MachineInstr *, 8> NewPHIs;
166 MachineSSAUpdater SSAUpdate(*MF, &NewPHIs);
168 // TailBB's immediate successors are now successors of those predecessors
169 // which duplicated TailBB. Add the predecessors as sources to the PHI
171 bool isDead = MBB->pred_empty() && !MBB->hasAddressTaken();
173 updateSuccessorsPHIs(MBB, isDead, TDBBs, Succs);
175 // If it is dead, remove it.
177 NumTailDupRemoved += MBB->size();
178 removeDeadBlock(MBB, RemovalCallback);
183 if (!SSAUpdateVRs.empty()) {
184 for (unsigned i = 0, e = SSAUpdateVRs.size(); i != e; ++i) {
185 unsigned VReg = SSAUpdateVRs[i];
186 SSAUpdate.Initialize(VReg);
188 // If the original definition is still around, add it as an available
190 MachineInstr *DefMI = MRI->getVRegDef(VReg);
191 MachineBasicBlock *DefBB = nullptr;
193 DefBB = DefMI->getParent();
194 SSAUpdate.AddAvailableValue(DefBB, VReg);
197 // Add the new vregs as available values.
198 DenseMap<unsigned, AvailableValsTy>::iterator LI =
199 SSAUpdateVals.find(VReg);
200 for (unsigned j = 0, ee = LI->second.size(); j != ee; ++j) {
201 MachineBasicBlock *SrcBB = LI->second[j].first;
202 unsigned SrcReg = LI->second[j].second;
203 SSAUpdate.AddAvailableValue(SrcBB, SrcReg);
206 // Rewrite uses that are outside of the original def's block.
207 MachineRegisterInfo::use_iterator UI = MRI->use_begin(VReg);
208 while (UI != MRI->use_end()) {
209 MachineOperand &UseMO = *UI;
210 MachineInstr *UseMI = UseMO.getParent();
212 if (UseMI->isDebugValue()) {
213 // SSAUpdate can replace the use with an undef. That creates
214 // a debug instruction that is a kill.
215 // FIXME: Should it SSAUpdate job to delete debug instructions
216 // instead of replacing the use with undef?
217 UseMI->eraseFromParent();
220 if (UseMI->getParent() == DefBB && !UseMI->isPHI())
222 SSAUpdate.RewriteUse(UseMO);
226 SSAUpdateVRs.clear();
227 SSAUpdateVals.clear();
230 // Eliminate some of the copies inserted by tail duplication to maintain
232 for (unsigned i = 0, e = Copies.size(); i != e; ++i) {
233 MachineInstr *Copy = Copies[i];
236 unsigned Dst = Copy->getOperand(0).getReg();
237 unsigned Src = Copy->getOperand(1).getReg();
238 if (MRI->hasOneNonDBGUse(Src) &&
239 MRI->constrainRegClass(Src, MRI->getRegClass(Dst))) {
240 // Copy is the only use. Do trivial copy propagation here.
241 MRI->replaceRegWith(Dst, Src);
242 Copy->eraseFromParent();
247 NumAddedPHIs += NewPHIs.size();
250 *DuplicatedPreds = std::move(TDBBs);
255 /// Look for small blocks that are unconditionally branched to and do not fall
256 /// through. Tail-duplicate their instructions into their predecessors to
257 /// eliminate (dynamic) branches.
258 bool TailDuplicator::tailDuplicateBlocks() {
259 bool MadeChange = false;
261 if (PreRegAlloc && TailDupVerify) {
262 DEBUG(dbgs() << "\n*** Before tail-duplicating\n");
263 VerifyPHIs(*MF, true);
266 for (MachineFunction::iterator I = ++MF->begin(), E = MF->end(); I != E;) {
267 MachineBasicBlock *MBB = &*I++;
269 if (NumTails == TailDupLimit)
272 bool IsSimple = isSimpleBB(MBB);
274 if (!shouldTailDuplicate(IsSimple, *MBB))
277 MadeChange |= tailDuplicateAndUpdate(IsSimple, MBB, nullptr);
280 if (PreRegAlloc && TailDupVerify)
281 VerifyPHIs(*MF, false);
286 static bool isDefLiveOut(unsigned Reg, MachineBasicBlock *BB,
287 const MachineRegisterInfo *MRI) {
288 for (MachineInstr &UseMI : MRI->use_instructions(Reg)) {
289 if (UseMI.isDebugValue())
291 if (UseMI.getParent() != BB)
297 static unsigned getPHISrcRegOpIdx(MachineInstr *MI, MachineBasicBlock *SrcBB) {
298 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i += 2)
299 if (MI->getOperand(i + 1).getMBB() == SrcBB)
304 // Remember which registers are used by phis in this block. This is
305 // used to determine which registers are liveout while modifying the
306 // block (which is why we need to copy the information).
307 static void getRegsUsedByPHIs(const MachineBasicBlock &BB,
308 DenseSet<unsigned> *UsedByPhi) {
309 for (const auto &MI : BB) {
312 for (unsigned i = 1, e = MI.getNumOperands(); i != e; i += 2) {
313 unsigned SrcReg = MI.getOperand(i).getReg();
314 UsedByPhi->insert(SrcReg);
319 /// Add a definition and source virtual registers pair for SSA update.
320 void TailDuplicator::addSSAUpdateEntry(unsigned OrigReg, unsigned NewReg,
321 MachineBasicBlock *BB) {
322 DenseMap<unsigned, AvailableValsTy>::iterator LI =
323 SSAUpdateVals.find(OrigReg);
324 if (LI != SSAUpdateVals.end())
325 LI->second.push_back(std::make_pair(BB, NewReg));
327 AvailableValsTy Vals;
328 Vals.push_back(std::make_pair(BB, NewReg));
329 SSAUpdateVals.insert(std::make_pair(OrigReg, Vals));
330 SSAUpdateVRs.push_back(OrigReg);
334 /// Process PHI node in TailBB by turning it into a copy in PredBB. Remember the
335 /// source register that's contributed by PredBB and update SSA update map.
336 void TailDuplicator::processPHI(
337 MachineInstr *MI, MachineBasicBlock *TailBB, MachineBasicBlock *PredBB,
338 DenseMap<unsigned, RegSubRegPair> &LocalVRMap,
339 SmallVectorImpl<std::pair<unsigned, RegSubRegPair>> &Copies,
340 const DenseSet<unsigned> &RegsUsedByPhi, bool Remove) {
341 unsigned DefReg = MI->getOperand(0).getReg();
342 unsigned SrcOpIdx = getPHISrcRegOpIdx(MI, PredBB);
343 assert(SrcOpIdx && "Unable to find matching PHI source?");
344 unsigned SrcReg = MI->getOperand(SrcOpIdx).getReg();
345 unsigned SrcSubReg = MI->getOperand(SrcOpIdx).getSubReg();
346 const TargetRegisterClass *RC = MRI->getRegClass(DefReg);
347 LocalVRMap.insert(std::make_pair(DefReg, RegSubRegPair(SrcReg, SrcSubReg)));
349 // Insert a copy from source to the end of the block. The def register is the
350 // available value liveout of the block.
351 unsigned NewDef = MRI->createVirtualRegister(RC);
352 Copies.push_back(std::make_pair(NewDef, RegSubRegPair(SrcReg, SrcSubReg)));
353 if (isDefLiveOut(DefReg, TailBB, MRI) || RegsUsedByPhi.count(DefReg))
354 addSSAUpdateEntry(DefReg, NewDef, PredBB);
359 // Remove PredBB from the PHI node.
360 MI->RemoveOperand(SrcOpIdx + 1);
361 MI->RemoveOperand(SrcOpIdx);
362 if (MI->getNumOperands() == 1)
363 MI->eraseFromParent();
366 /// Duplicate a TailBB instruction to PredBB and update
367 /// the source operands due to earlier PHI translation.
368 void TailDuplicator::duplicateInstruction(
369 MachineInstr *MI, MachineBasicBlock *TailBB, MachineBasicBlock *PredBB,
370 DenseMap<unsigned, RegSubRegPair> &LocalVRMap,
371 const DenseSet<unsigned> &UsedByPhi) {
372 MachineInstr *NewMI = TII->duplicate(*MI, *MF);
374 for (unsigned i = 0, e = NewMI->getNumOperands(); i != e; ++i) {
375 MachineOperand &MO = NewMI->getOperand(i);
378 unsigned Reg = MO.getReg();
379 if (!TargetRegisterInfo::isVirtualRegister(Reg))
382 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
383 unsigned NewReg = MRI->createVirtualRegister(RC);
385 LocalVRMap.insert(std::make_pair(Reg, RegSubRegPair(NewReg, 0)));
386 if (isDefLiveOut(Reg, TailBB, MRI) || UsedByPhi.count(Reg))
387 addSSAUpdateEntry(Reg, NewReg, PredBB);
389 auto VI = LocalVRMap.find(Reg);
390 if (VI != LocalVRMap.end()) {
391 // Need to make sure that the register class of the mapped register
392 // will satisfy the constraints of the class of the register being
394 auto *OrigRC = MRI->getRegClass(Reg);
395 auto *MappedRC = MRI->getRegClass(VI->second.Reg);
396 const TargetRegisterClass *ConstrRC;
397 if (VI->second.SubReg != 0) {
398 ConstrRC = TRI->getMatchingSuperRegClass(MappedRC, OrigRC,
401 // The actual constraining (as in "find appropriate new class")
402 // is done by getMatchingSuperRegClass, so now we only need to
403 // change the class of the mapped register.
404 MRI->setRegClass(VI->second.Reg, ConstrRC);
407 // For mapped registers that do not have sub-registers, simply
408 // restrict their class to match the original one.
409 ConstrRC = MRI->constrainRegClass(VI->second.Reg, OrigRC);
413 // If the class constraining succeeded, we can simply replace
414 // the old register with the mapped one.
415 MO.setReg(VI->second.Reg);
416 // We have Reg -> VI.Reg:VI.SubReg, so if Reg is used with a
417 // sub-register, we need to compose the sub-register indices.
418 MO.setSubReg(TRI->composeSubRegIndices(MO.getSubReg(),
421 // The direct replacement is not possible, due to failing register
422 // class constraints. An explicit COPY is necessary. Create one
423 // that can be reused
424 auto *NewRC = MI->getRegClassConstraint(i, TII, TRI);
425 if (NewRC == nullptr)
427 unsigned NewReg = MRI->createVirtualRegister(NewRC);
428 BuildMI(*PredBB, MI, MI->getDebugLoc(),
429 TII->get(TargetOpcode::COPY), NewReg)
430 .addReg(VI->second.Reg, 0, VI->second.SubReg);
431 LocalVRMap.erase(VI);
432 LocalVRMap.insert(std::make_pair(Reg, RegSubRegPair(NewReg, 0)));
434 // The composed VI.Reg:VI.SubReg is replaced with NewReg, which
435 // is equivalent to the whole register Reg. Hence, Reg:subreg
436 // is same as NewReg:subreg, so keep the sub-register index
439 // Clear any kill flags from this operand. The new register could
440 // have uses after this one, so kills are not valid here.
446 PredBB->insert(PredBB->instr_end(), NewMI);
449 /// After FromBB is tail duplicated into its predecessor blocks, the successors
450 /// have gained new predecessors. Update the PHI instructions in them
452 void TailDuplicator::updateSuccessorsPHIs(
453 MachineBasicBlock *FromBB, bool isDead,
454 SmallVectorImpl<MachineBasicBlock *> &TDBBs,
455 SmallSetVector<MachineBasicBlock *, 8> &Succs) {
456 for (MachineBasicBlock *SuccBB : Succs) {
457 for (MachineInstr &MI : *SuccBB) {
460 MachineInstrBuilder MIB(*FromBB->getParent(), MI);
462 for (unsigned i = 1, e = MI.getNumOperands(); i != e; i += 2) {
463 MachineOperand &MO = MI.getOperand(i + 1);
464 if (MO.getMBB() == FromBB) {
471 MachineOperand &MO0 = MI.getOperand(Idx);
472 unsigned Reg = MO0.getReg();
474 // Folded into the previous BB.
475 // There could be duplicate phi source entries. FIXME: Should sdisel
476 // or earlier pass fixed this?
477 for (unsigned i = MI.getNumOperands() - 2; i != Idx; i -= 2) {
478 MachineOperand &MO = MI.getOperand(i + 1);
479 if (MO.getMBB() == FromBB) {
480 MI.RemoveOperand(i + 1);
487 // If Idx is set, the operands at Idx and Idx+1 must be removed.
488 // We reuse the location to avoid expensive RemoveOperand calls.
490 DenseMap<unsigned, AvailableValsTy>::iterator LI =
491 SSAUpdateVals.find(Reg);
492 if (LI != SSAUpdateVals.end()) {
493 // This register is defined in the tail block.
494 for (unsigned j = 0, ee = LI->second.size(); j != ee; ++j) {
495 MachineBasicBlock *SrcBB = LI->second[j].first;
496 // If we didn't duplicate a bb into a particular predecessor, we
497 // might still have added an entry to SSAUpdateVals to correcly
498 // recompute SSA. If that case, avoid adding a dummy extra argument
500 if (!SrcBB->isSuccessor(SuccBB))
503 unsigned SrcReg = LI->second[j].second;
505 MI.getOperand(Idx).setReg(SrcReg);
506 MI.getOperand(Idx + 1).setMBB(SrcBB);
509 MIB.addReg(SrcReg).addMBB(SrcBB);
513 // Live in tail block, must also be live in predecessors.
514 for (unsigned j = 0, ee = TDBBs.size(); j != ee; ++j) {
515 MachineBasicBlock *SrcBB = TDBBs[j];
517 MI.getOperand(Idx).setReg(Reg);
518 MI.getOperand(Idx + 1).setMBB(SrcBB);
521 MIB.addReg(Reg).addMBB(SrcBB);
526 MI.RemoveOperand(Idx + 1);
527 MI.RemoveOperand(Idx);
533 /// Determine if it is profitable to duplicate this block.
534 bool TailDuplicator::shouldTailDuplicate(bool IsSimple,
535 MachineBasicBlock &TailBB) {
536 // When doing tail-duplication during layout, the block ordering is in flux,
537 // so canFallThrough returns a result based on incorrect information and
538 // should just be ignored.
539 if (!LayoutMode && TailBB.canFallThrough())
542 // Don't try to tail-duplicate single-block loops.
543 if (TailBB.isSuccessor(&TailBB))
546 // Set the limit on the cost to duplicate. When optimizing for size,
547 // duplicate only one, because one branch instruction can be eliminated to
548 // compensate for the duplication.
549 unsigned MaxDuplicateCount;
550 if (TailDupSize == 0 &&
551 TailDuplicateSize.getNumOccurrences() == 0 &&
552 MF->getFunction()->optForSize())
553 MaxDuplicateCount = 1;
554 else if (TailDupSize == 0)
555 MaxDuplicateCount = TailDuplicateSize;
557 MaxDuplicateCount = TailDupSize;
559 // If the block to be duplicated ends in an unanalyzable fallthrough, don't
561 // A similar check is necessary in MachineBlockPlacement to make sure pairs of
562 // blocks with unanalyzable fallthrough get layed out contiguously.
563 MachineBasicBlock *PredTBB = nullptr, *PredFBB = nullptr;
564 SmallVector<MachineOperand, 4> PredCond;
565 if (TII->analyzeBranch(TailBB, PredTBB, PredFBB, PredCond) &&
566 TailBB.canFallThrough())
569 // If the target has hardware branch prediction that can handle indirect
570 // branches, duplicating them can often make them predictable when there
571 // are common paths through the code. The limit needs to be high enough
572 // to allow undoing the effects of tail merging and other optimizations
573 // that rearrange the predecessors of the indirect branch.
575 bool HasIndirectbr = false;
577 HasIndirectbr = TailBB.back().isIndirectBranch();
579 if (HasIndirectbr && PreRegAlloc)
580 MaxDuplicateCount = TailDupIndirectBranchSize;
582 // Check the instructions in the block to determine whether tail-duplication
583 // is invalid or unlikely to be profitable.
584 unsigned InstrCount = 0;
585 for (MachineInstr &MI : TailBB) {
586 // Non-duplicable things shouldn't be tail-duplicated.
587 if (MI.isNotDuplicable())
590 // Convergent instructions can be duplicated only if doing so doesn't add
591 // new control dependencies, which is what we're going to do here.
592 if (MI.isConvergent())
595 // Do not duplicate 'return' instructions if this is a pre-regalloc run.
596 // A return may expand into a lot more instructions (e.g. reload of callee
597 // saved registers) after PEI.
598 if (PreRegAlloc && MI.isReturn())
601 // Avoid duplicating calls before register allocation. Calls presents a
602 // barrier to register allocation so duplicating them may end up increasing
604 if (PreRegAlloc && MI.isCall())
607 if (!MI.isPHI() && !MI.isDebugValue())
610 if (InstrCount > MaxDuplicateCount)
614 // Check if any of the successors of TailBB has a PHI node in which the
615 // value corresponding to TailBB uses a subregister.
616 // If a phi node uses a register paired with a subregister, the actual
617 // "value type" of the phi may differ from the type of the register without
618 // any subregisters. Due to a bug, tail duplication may add a new operand
619 // without a necessary subregister, producing an invalid code. This is
620 // demonstrated by test/CodeGen/Hexagon/tail-dup-subreg-abort.ll.
621 // Disable tail duplication for this case for now, until the problem is
623 for (auto SB : TailBB.successors()) {
624 for (auto &I : *SB) {
627 unsigned Idx = getPHISrcRegOpIdx(&I, &TailBB);
629 MachineOperand &PU = I.getOperand(Idx);
630 if (PU.getSubReg() != 0)
635 if (HasIndirectbr && PreRegAlloc)
644 return canCompletelyDuplicateBB(TailBB);
647 /// True if this BB has only one unconditional jump.
648 bool TailDuplicator::isSimpleBB(MachineBasicBlock *TailBB) {
649 if (TailBB->succ_size() != 1)
651 if (TailBB->pred_empty())
653 MachineBasicBlock::iterator I = TailBB->getFirstNonDebugInstr();
654 if (I == TailBB->end())
656 return I->isUnconditionalBranch();
659 static bool bothUsedInPHI(const MachineBasicBlock &A,
660 const SmallPtrSet<MachineBasicBlock *, 8> &SuccsB) {
661 for (MachineBasicBlock *BB : A.successors())
662 if (SuccsB.count(BB) && !BB->empty() && BB->begin()->isPHI())
668 bool TailDuplicator::canCompletelyDuplicateBB(MachineBasicBlock &BB) {
669 for (MachineBasicBlock *PredBB : BB.predecessors()) {
670 if (PredBB->succ_size() > 1)
673 MachineBasicBlock *PredTBB = nullptr, *PredFBB = nullptr;
674 SmallVector<MachineOperand, 4> PredCond;
675 if (TII->analyzeBranch(*PredBB, PredTBB, PredFBB, PredCond))
678 if (!PredCond.empty())
684 bool TailDuplicator::duplicateSimpleBB(
685 MachineBasicBlock *TailBB, SmallVectorImpl<MachineBasicBlock *> &TDBBs,
686 const DenseSet<unsigned> &UsedByPhi,
687 SmallVectorImpl<MachineInstr *> &Copies) {
688 SmallPtrSet<MachineBasicBlock *, 8> Succs(TailBB->succ_begin(),
690 SmallVector<MachineBasicBlock *, 8> Preds(TailBB->pred_begin(),
692 bool Changed = false;
693 for (MachineBasicBlock *PredBB : Preds) {
694 if (PredBB->hasEHPadSuccessor())
697 if (bothUsedInPHI(*PredBB, Succs))
700 MachineBasicBlock *PredTBB = nullptr, *PredFBB = nullptr;
701 SmallVector<MachineOperand, 4> PredCond;
702 if (TII->analyzeBranch(*PredBB, PredTBB, PredFBB, PredCond))
706 DEBUG(dbgs() << "\nTail-duplicating into PredBB: " << *PredBB
707 << "From simple Succ: " << *TailBB);
709 MachineBasicBlock *NewTarget = *TailBB->succ_begin();
710 MachineBasicBlock *NextBB = PredBB->getNextNode();
712 // Make PredFBB explicit.
713 if (PredCond.empty())
716 // Make fall through explicit.
723 if (PredFBB == TailBB)
725 if (PredTBB == TailBB)
728 // Make the branch unconditional if possible
729 if (PredTBB == PredFBB) {
734 // Avoid adding fall through branches.
735 if (PredFBB == NextBB)
737 if (PredTBB == NextBB && PredFBB == nullptr)
740 auto DL = PredBB->findBranchDebugLoc();
741 TII->removeBranch(*PredBB);
743 if (!PredBB->isSuccessor(NewTarget))
744 PredBB->replaceSuccessor(TailBB, NewTarget);
746 PredBB->removeSuccessor(TailBB, true);
747 assert(PredBB->succ_size() <= 1);
751 TII->insertBranch(*PredBB, PredTBB, PredFBB, PredCond, DL);
753 TDBBs.push_back(PredBB);
758 bool TailDuplicator::canTailDuplicate(MachineBasicBlock *TailBB,
759 MachineBasicBlock *PredBB) {
760 // EH edges are ignored by analyzeBranch.
761 if (PredBB->succ_size() > 1)
764 MachineBasicBlock *PredTBB = nullptr, *PredFBB = nullptr;
765 SmallVector<MachineOperand, 4> PredCond;
766 if (TII->analyzeBranch(*PredBB, PredTBB, PredFBB, PredCond))
768 if (!PredCond.empty())
773 /// If it is profitable, duplicate TailBB's contents in each
774 /// of its predecessors.
775 /// \p IsSimple result of isSimpleBB
776 /// \p TailBB Block to be duplicated.
777 /// \p ForcedLayoutPred When non-null, use this block as the layout predecessor
778 /// instead of the previous block in MF's order.
779 /// \p TDBBs A vector to keep track of all blocks tail-duplicated
781 /// \p Copies A vector of copy instructions inserted. Used later to
782 /// walk all the inserted copies and remove redundant ones.
783 bool TailDuplicator::tailDuplicate(bool IsSimple, MachineBasicBlock *TailBB,
784 MachineBasicBlock *ForcedLayoutPred,
785 SmallVectorImpl<MachineBasicBlock *> &TDBBs,
786 SmallVectorImpl<MachineInstr *> &Copies) {
787 DEBUG(dbgs() << "\n*** Tail-duplicating BB#" << TailBB->getNumber() << '\n');
789 DenseSet<unsigned> UsedByPhi;
790 getRegsUsedByPHIs(*TailBB, &UsedByPhi);
793 return duplicateSimpleBB(TailBB, TDBBs, UsedByPhi, Copies);
795 // Iterate through all the unique predecessors and tail-duplicate this
796 // block into them, if possible. Copying the list ahead of time also
797 // avoids trouble with the predecessor list reallocating.
798 bool Changed = false;
799 SmallSetVector<MachineBasicBlock *, 8> Preds(TailBB->pred_begin(),
801 for (MachineBasicBlock *PredBB : Preds) {
802 assert(TailBB != PredBB &&
803 "Single-block loop should have been rejected earlier!");
805 if (!canTailDuplicate(TailBB, PredBB))
808 // Don't duplicate into a fall-through predecessor (at least for now).
809 bool IsLayoutSuccessor = false;
810 if (ForcedLayoutPred)
811 IsLayoutSuccessor = (ForcedLayoutPred == PredBB);
812 else if (PredBB->isLayoutSuccessor(TailBB) && PredBB->canFallThrough())
813 IsLayoutSuccessor = true;
814 if (IsLayoutSuccessor)
817 DEBUG(dbgs() << "\nTail-duplicating into PredBB: " << *PredBB
818 << "From Succ: " << *TailBB);
820 TDBBs.push_back(PredBB);
822 // Remove PredBB's unconditional branch.
823 TII->removeBranch(*PredBB);
825 // Clone the contents of TailBB into PredBB.
826 DenseMap<unsigned, RegSubRegPair> LocalVRMap;
827 SmallVector<std::pair<unsigned, RegSubRegPair>, 4> CopyInfos;
828 // Use instr_iterator here to properly handle bundles, e.g.
829 // ARM Thumb2 IT block.
830 MachineBasicBlock::instr_iterator I = TailBB->instr_begin();
831 while (I != TailBB->instr_end()) {
832 MachineInstr *MI = &*I;
835 // Replace the uses of the def of the PHI with the register coming
837 processPHI(MI, TailBB, PredBB, LocalVRMap, CopyInfos, UsedByPhi, true);
839 // Replace def of virtual registers with new registers, and update
840 // uses with PHI source register or the new registers.
841 duplicateInstruction(MI, TailBB, PredBB, LocalVRMap, UsedByPhi);
844 appendCopies(PredBB, CopyInfos, Copies);
847 MachineBasicBlock *PredTBB = nullptr, *PredFBB = nullptr;
848 SmallVector<MachineOperand, 4> PredCond;
849 TII->analyzeBranch(*PredBB, PredTBB, PredFBB, PredCond);
851 NumTailDupAdded += TailBB->size() - 1; // subtract one for removed branch
854 PredBB->removeSuccessor(PredBB->succ_begin());
855 assert(PredBB->succ_empty() &&
856 "TailDuplicate called on block with multiple successors!");
857 for (MachineBasicBlock *Succ : TailBB->successors())
858 PredBB->addSuccessor(Succ, MBPI->getEdgeProbability(TailBB, Succ));
864 // If TailBB was duplicated into all its predecessors except for the prior
865 // block, which falls through unconditionally, move the contents of this
866 // block into the prior block.
867 MachineBasicBlock *PrevBB = ForcedLayoutPred;
869 PrevBB = &*std::prev(TailBB->getIterator());
870 MachineBasicBlock *PriorTBB = nullptr, *PriorFBB = nullptr;
871 SmallVector<MachineOperand, 4> PriorCond;
872 // This has to check PrevBB->succ_size() because EH edges are ignored by
874 if (PrevBB->succ_size() == 1 &&
875 // Layout preds are not always CFG preds. Check.
876 *PrevBB->succ_begin() == TailBB &&
877 !TII->analyzeBranch(*PrevBB, PriorTBB, PriorFBB, PriorCond) &&
879 (!PriorTBB || PriorTBB == TailBB) &&
880 TailBB->pred_size() == 1 &&
881 !TailBB->hasAddressTaken()) {
882 DEBUG(dbgs() << "\nMerging into block: " << *PrevBB
883 << "From MBB: " << *TailBB);
884 // There may be a branch to the layout successor. This is unlikely but it
885 // happens. The correct thing to do is to remove the branch before
886 // duplicating the instructions in all cases.
887 TII->removeBranch(*PrevBB);
889 DenseMap<unsigned, RegSubRegPair> LocalVRMap;
890 SmallVector<std::pair<unsigned, RegSubRegPair>, 4> CopyInfos;
891 MachineBasicBlock::iterator I = TailBB->begin();
892 // Process PHI instructions first.
893 while (I != TailBB->end() && I->isPHI()) {
894 // Replace the uses of the def of the PHI with the register coming
896 MachineInstr *MI = &*I++;
897 processPHI(MI, TailBB, PrevBB, LocalVRMap, CopyInfos, UsedByPhi, true);
900 // Now copy the non-PHI instructions.
901 while (I != TailBB->end()) {
902 // Replace def of virtual registers with new registers, and update
903 // uses with PHI source register or the new registers.
904 MachineInstr *MI = &*I++;
905 assert(!MI->isBundle() && "Not expecting bundles before regalloc!");
906 duplicateInstruction(MI, TailBB, PrevBB, LocalVRMap, UsedByPhi);
907 MI->eraseFromParent();
909 appendCopies(PrevBB, CopyInfos, Copies);
911 TII->removeBranch(*PrevBB);
912 // No PHIs to worry about, just splice the instructions over.
913 PrevBB->splice(PrevBB->end(), TailBB, TailBB->begin(), TailBB->end());
915 PrevBB->removeSuccessor(PrevBB->succ_begin());
916 assert(PrevBB->succ_empty());
917 PrevBB->transferSuccessors(TailBB);
918 TDBBs.push_back(PrevBB);
922 // If this is after register allocation, there are no phis to fix.
926 // If we made no changes so far, we are safe.
930 // Handle the nasty case in that we duplicated a block that is part of a loop
931 // into some but not all of its predecessors. For example:
935 // if we duplicate 2 into 1 but not into 3, we end up with
936 // 12 -> 3 <-> 2 -> rest |
939 // If there was a "var = phi(1, 3)" in 2, it has to be ultimately replaced
940 // with a phi in 3 (which now dominates 2).
941 // What we do here is introduce a copy in 3 of the register defined by the
942 // phi, just like when we are duplicating 2 into 3, but we don't copy any
943 // real instructions or remove the 3 -> 2 edge from the phi in 2.
944 for (MachineBasicBlock *PredBB : Preds) {
945 if (is_contained(TDBBs, PredBB))
949 if (PredBB->succ_size() != 1)
952 DenseMap<unsigned, RegSubRegPair> LocalVRMap;
953 SmallVector<std::pair<unsigned, RegSubRegPair>, 4> CopyInfos;
954 MachineBasicBlock::iterator I = TailBB->begin();
955 // Process PHI instructions first.
956 while (I != TailBB->end() && I->isPHI()) {
957 // Replace the uses of the def of the PHI with the register coming
959 MachineInstr *MI = &*I++;
960 processPHI(MI, TailBB, PredBB, LocalVRMap, CopyInfos, UsedByPhi, false);
962 appendCopies(PredBB, CopyInfos, Copies);
968 /// At the end of the block \p MBB generate COPY instructions between registers
969 /// described by \p CopyInfos. Append resulting instructions to \p Copies.
970 void TailDuplicator::appendCopies(MachineBasicBlock *MBB,
971 SmallVectorImpl<std::pair<unsigned,RegSubRegPair>> &CopyInfos,
972 SmallVectorImpl<MachineInstr*> &Copies) {
973 MachineBasicBlock::iterator Loc = MBB->getFirstTerminator();
974 const MCInstrDesc &CopyD = TII->get(TargetOpcode::COPY);
975 for (auto &CI : CopyInfos) {
976 auto C = BuildMI(*MBB, Loc, DebugLoc(), CopyD, CI.first)
977 .addReg(CI.second.Reg, 0, CI.second.SubReg);
982 /// Remove the specified dead machine basic block from the function, updating
984 void TailDuplicator::removeDeadBlock(
985 MachineBasicBlock *MBB,
986 function_ref<void(MachineBasicBlock *)> *RemovalCallback) {
987 assert(MBB->pred_empty() && "MBB must be dead!");
988 DEBUG(dbgs() << "\nRemoving MBB: " << *MBB);
991 (*RemovalCallback)(MBB);
993 // Remove all successors.
994 while (!MBB->succ_empty())
995 MBB->removeSuccessor(MBB->succ_end() - 1);
998 MBB->eraseFromParent();