1 //===-- TargetInstrInfo.cpp - Target Instruction Information --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetInstrInfo.h"
15 #include "llvm/CodeGen/MachineFrameInfo.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineMemOperand.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/CodeGen/PseudoSourceValue.h"
20 #include "llvm/CodeGen/ScoreboardHazardRecognizer.h"
21 #include "llvm/CodeGen/StackMaps.h"
22 #include "llvm/CodeGen/TargetSchedule.h"
23 #include "llvm/IR/DataLayout.h"
24 #include "llvm/MC/MCAsmInfo.h"
25 #include "llvm/MC/MCInstrItineraries.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/Target/TargetFrameLowering.h"
30 #include "llvm/Target/TargetLowering.h"
31 #include "llvm/Target/TargetMachine.h"
32 #include "llvm/Target/TargetRegisterInfo.h"
37 static cl::opt<bool> DisableHazardRecognizer(
38 "disable-sched-hazard", cl::Hidden, cl::init(false),
39 cl::desc("Disable hazard detection during preRA scheduling"));
41 TargetInstrInfo::~TargetInstrInfo() {
44 const TargetRegisterClass*
45 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
46 const TargetRegisterInfo *TRI,
47 const MachineFunction &MF) const {
48 if (OpNum >= MCID.getNumOperands())
51 short RegClass = MCID.OpInfo[OpNum].RegClass;
52 if (MCID.OpInfo[OpNum].isLookupPtrRegClass())
53 return TRI->getPointerRegClass(MF, RegClass);
55 // Instructions like INSERT_SUBREG do not have fixed register classes.
59 // Otherwise just look it up normally.
60 return TRI->getRegClass(RegClass);
63 /// insertNoop - Insert a noop into the instruction stream at the specified
65 void TargetInstrInfo::insertNoop(MachineBasicBlock &MBB,
66 MachineBasicBlock::iterator MI) const {
67 llvm_unreachable("Target didn't implement insertNoop!");
70 /// Measure the specified inline asm to determine an approximation of its
72 /// Comments (which run till the next SeparatorString or newline) do not
73 /// count as an instruction.
74 /// Any other non-whitespace text is considered an instruction, with
75 /// multiple instructions separated by SeparatorString or newlines.
76 /// Variable-length instructions are not handled here; this function
77 /// may be overloaded in the target code to do that.
78 unsigned TargetInstrInfo::getInlineAsmLength(const char *Str,
79 const MCAsmInfo &MAI) const {
80 // Count the number of instructions in the asm.
81 bool atInsnStart = true;
82 unsigned InstCount = 0;
84 if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
85 strlen(MAI.getSeparatorString())) == 0) {
87 } else if (strncmp(Str, MAI.getCommentString().data(),
88 MAI.getCommentString().size()) == 0) {
89 // Stop counting as an instruction after a comment until the next
94 if (atInsnStart && !std::isspace(static_cast<unsigned char>(*Str))) {
100 return InstCount * MAI.getMaxInstLength();
103 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything
104 /// after it, replacing it with an unconditional branch to NewDest.
106 TargetInstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
107 MachineBasicBlock *NewDest) const {
108 MachineBasicBlock *MBB = Tail->getParent();
110 // Remove all the old successors of MBB from the CFG.
111 while (!MBB->succ_empty())
112 MBB->removeSuccessor(MBB->succ_begin());
114 // Save off the debug loc before erasing the instruction.
115 DebugLoc DL = Tail->getDebugLoc();
117 // Remove all the dead instructions from the end of MBB.
118 MBB->erase(Tail, MBB->end());
120 // If MBB isn't immediately before MBB, insert a branch to it.
121 if (++MachineFunction::iterator(MBB) != MachineFunction::iterator(NewDest))
122 insertBranch(*MBB, NewDest, nullptr, SmallVector<MachineOperand, 0>(), DL);
123 MBB->addSuccessor(NewDest);
126 MachineInstr *TargetInstrInfo::commuteInstructionImpl(MachineInstr &MI,
127 bool NewMI, unsigned Idx1,
128 unsigned Idx2) const {
129 const MCInstrDesc &MCID = MI.getDesc();
130 bool HasDef = MCID.getNumDefs();
131 if (HasDef && !MI.getOperand(0).isReg())
132 // No idea how to commute this instruction. Target should implement its own.
135 unsigned CommutableOpIdx1 = Idx1; (void)CommutableOpIdx1;
136 unsigned CommutableOpIdx2 = Idx2; (void)CommutableOpIdx2;
137 assert(findCommutedOpIndices(MI, CommutableOpIdx1, CommutableOpIdx2) &&
138 CommutableOpIdx1 == Idx1 && CommutableOpIdx2 == Idx2 &&
139 "TargetInstrInfo::CommuteInstructionImpl(): not commutable operands.");
140 assert(MI.getOperand(Idx1).isReg() && MI.getOperand(Idx2).isReg() &&
141 "This only knows how to commute register operands so far");
143 unsigned Reg0 = HasDef ? MI.getOperand(0).getReg() : 0;
144 unsigned Reg1 = MI.getOperand(Idx1).getReg();
145 unsigned Reg2 = MI.getOperand(Idx2).getReg();
146 unsigned SubReg0 = HasDef ? MI.getOperand(0).getSubReg() : 0;
147 unsigned SubReg1 = MI.getOperand(Idx1).getSubReg();
148 unsigned SubReg2 = MI.getOperand(Idx2).getSubReg();
149 bool Reg1IsKill = MI.getOperand(Idx1).isKill();
150 bool Reg2IsKill = MI.getOperand(Idx2).isKill();
151 bool Reg1IsUndef = MI.getOperand(Idx1).isUndef();
152 bool Reg2IsUndef = MI.getOperand(Idx2).isUndef();
153 bool Reg1IsInternal = MI.getOperand(Idx1).isInternalRead();
154 bool Reg2IsInternal = MI.getOperand(Idx2).isInternalRead();
155 // If destination is tied to either of the commuted source register, then
156 // it must be updated.
157 if (HasDef && Reg0 == Reg1 &&
158 MI.getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) {
162 } else if (HasDef && Reg0 == Reg2 &&
163 MI.getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) {
169 MachineInstr *CommutedMI = nullptr;
171 // Create a new instruction.
172 MachineFunction &MF = *MI.getParent()->getParent();
173 CommutedMI = MF.CloneMachineInstr(&MI);
179 CommutedMI->getOperand(0).setReg(Reg0);
180 CommutedMI->getOperand(0).setSubReg(SubReg0);
182 CommutedMI->getOperand(Idx2).setReg(Reg1);
183 CommutedMI->getOperand(Idx1).setReg(Reg2);
184 CommutedMI->getOperand(Idx2).setSubReg(SubReg1);
185 CommutedMI->getOperand(Idx1).setSubReg(SubReg2);
186 CommutedMI->getOperand(Idx2).setIsKill(Reg1IsKill);
187 CommutedMI->getOperand(Idx1).setIsKill(Reg2IsKill);
188 CommutedMI->getOperand(Idx2).setIsUndef(Reg1IsUndef);
189 CommutedMI->getOperand(Idx1).setIsUndef(Reg2IsUndef);
190 CommutedMI->getOperand(Idx2).setIsInternalRead(Reg1IsInternal);
191 CommutedMI->getOperand(Idx1).setIsInternalRead(Reg2IsInternal);
195 MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr &MI, bool NewMI,
197 unsigned OpIdx2) const {
198 // If OpIdx1 or OpIdx2 is not specified, then this method is free to choose
199 // any commutable operand, which is done in findCommutedOpIndices() method
201 if ((OpIdx1 == CommuteAnyOperandIndex || OpIdx2 == CommuteAnyOperandIndex) &&
202 !findCommutedOpIndices(MI, OpIdx1, OpIdx2)) {
203 assert(MI.isCommutable() &&
204 "Precondition violation: MI must be commutable.");
207 return commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
210 bool TargetInstrInfo::fixCommutedOpIndices(unsigned &ResultIdx1,
211 unsigned &ResultIdx2,
212 unsigned CommutableOpIdx1,
213 unsigned CommutableOpIdx2) {
214 if (ResultIdx1 == CommuteAnyOperandIndex &&
215 ResultIdx2 == CommuteAnyOperandIndex) {
216 ResultIdx1 = CommutableOpIdx1;
217 ResultIdx2 = CommutableOpIdx2;
218 } else if (ResultIdx1 == CommuteAnyOperandIndex) {
219 if (ResultIdx2 == CommutableOpIdx1)
220 ResultIdx1 = CommutableOpIdx2;
221 else if (ResultIdx2 == CommutableOpIdx2)
222 ResultIdx1 = CommutableOpIdx1;
225 } else if (ResultIdx2 == CommuteAnyOperandIndex) {
226 if (ResultIdx1 == CommutableOpIdx1)
227 ResultIdx2 = CommutableOpIdx2;
228 else if (ResultIdx1 == CommutableOpIdx2)
229 ResultIdx2 = CommutableOpIdx1;
233 // Check that the result operand indices match the given commutable
235 return (ResultIdx1 == CommutableOpIdx1 && ResultIdx2 == CommutableOpIdx2) ||
236 (ResultIdx1 == CommutableOpIdx2 && ResultIdx2 == CommutableOpIdx1);
241 bool TargetInstrInfo::findCommutedOpIndices(MachineInstr &MI,
243 unsigned &SrcOpIdx2) const {
244 assert(!MI.isBundle() &&
245 "TargetInstrInfo::findCommutedOpIndices() can't handle bundles");
247 const MCInstrDesc &MCID = MI.getDesc();
248 if (!MCID.isCommutable())
251 // This assumes v0 = op v1, v2 and commuting would swap v1 and v2. If this
252 // is not true, then the target must implement this.
253 unsigned CommutableOpIdx1 = MCID.getNumDefs();
254 unsigned CommutableOpIdx2 = CommutableOpIdx1 + 1;
255 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
256 CommutableOpIdx1, CommutableOpIdx2))
259 if (!MI.getOperand(SrcOpIdx1).isReg() || !MI.getOperand(SrcOpIdx2).isReg())
265 bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
266 if (!MI.isTerminator()) return false;
268 // Conditional branch is a special case.
269 if (MI.isBranch() && !MI.isBarrier())
271 if (!MI.isPredicable())
273 return !isPredicated(MI);
276 bool TargetInstrInfo::PredicateInstruction(
277 MachineInstr &MI, ArrayRef<MachineOperand> Pred) const {
278 bool MadeChange = false;
280 assert(!MI.isBundle() &&
281 "TargetInstrInfo::PredicateInstruction() can't handle bundles");
283 const MCInstrDesc &MCID = MI.getDesc();
284 if (!MI.isPredicable())
287 for (unsigned j = 0, i = 0, e = MI.getNumOperands(); i != e; ++i) {
288 if (MCID.OpInfo[i].isPredicate()) {
289 MachineOperand &MO = MI.getOperand(i);
291 MO.setReg(Pred[j].getReg());
293 } else if (MO.isImm()) {
294 MO.setImm(Pred[j].getImm());
296 } else if (MO.isMBB()) {
297 MO.setMBB(Pred[j].getMBB());
306 bool TargetInstrInfo::hasLoadFromStackSlot(const MachineInstr &MI,
307 const MachineMemOperand *&MMO,
308 int &FrameIndex) const {
309 for (MachineInstr::mmo_iterator o = MI.memoperands_begin(),
310 oe = MI.memoperands_end();
312 if ((*o)->isLoad()) {
313 if (const FixedStackPseudoSourceValue *Value =
314 dyn_cast_or_null<FixedStackPseudoSourceValue>(
315 (*o)->getPseudoValue())) {
316 FrameIndex = Value->getFrameIndex();
325 bool TargetInstrInfo::hasStoreToStackSlot(const MachineInstr &MI,
326 const MachineMemOperand *&MMO,
327 int &FrameIndex) const {
328 for (MachineInstr::mmo_iterator o = MI.memoperands_begin(),
329 oe = MI.memoperands_end();
331 if ((*o)->isStore()) {
332 if (const FixedStackPseudoSourceValue *Value =
333 dyn_cast_or_null<FixedStackPseudoSourceValue>(
334 (*o)->getPseudoValue())) {
335 FrameIndex = Value->getFrameIndex();
344 bool TargetInstrInfo::getStackSlotRange(const TargetRegisterClass *RC,
345 unsigned SubIdx, unsigned &Size,
347 const MachineFunction &MF) const {
349 Size = RC->getSize();
353 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
354 unsigned BitSize = TRI->getSubRegIdxSize(SubIdx);
355 // Convert bit size to byte size to be consistent with
356 // MCRegisterClass::getSize().
360 int BitOffset = TRI->getSubRegIdxOffset(SubIdx);
361 if (BitOffset < 0 || BitOffset % 8)
365 Offset = (unsigned)BitOffset / 8;
367 assert(RC->getSize() >= (Offset + Size) && "bad subregister range");
369 if (!MF.getDataLayout().isLittleEndian()) {
370 Offset = RC->getSize() - (Offset + Size);
375 void TargetInstrInfo::reMaterialize(MachineBasicBlock &MBB,
376 MachineBasicBlock::iterator I,
377 unsigned DestReg, unsigned SubIdx,
378 const MachineInstr &Orig,
379 const TargetRegisterInfo &TRI) const {
380 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
381 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
385 bool TargetInstrInfo::produceSameValue(const MachineInstr &MI0,
386 const MachineInstr &MI1,
387 const MachineRegisterInfo *MRI) const {
388 return MI0.isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
391 MachineInstr *TargetInstrInfo::duplicate(MachineInstr &Orig,
392 MachineFunction &MF) const {
393 assert(!Orig.isNotDuplicable() && "Instruction cannot be duplicated");
394 return MF.CloneMachineInstr(&Orig);
397 // If the COPY instruction in MI can be folded to a stack operation, return
398 // the register class to use.
399 static const TargetRegisterClass *canFoldCopy(const MachineInstr &MI,
401 assert(MI.isCopy() && "MI must be a COPY instruction");
402 if (MI.getNumOperands() != 2)
404 assert(FoldIdx<2 && "FoldIdx refers no nonexistent operand");
406 const MachineOperand &FoldOp = MI.getOperand(FoldIdx);
407 const MachineOperand &LiveOp = MI.getOperand(1 - FoldIdx);
409 if (FoldOp.getSubReg() || LiveOp.getSubReg())
412 unsigned FoldReg = FoldOp.getReg();
413 unsigned LiveReg = LiveOp.getReg();
415 assert(TargetRegisterInfo::isVirtualRegister(FoldReg) &&
416 "Cannot fold physregs");
418 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
419 const TargetRegisterClass *RC = MRI.getRegClass(FoldReg);
421 if (TargetRegisterInfo::isPhysicalRegister(LiveOp.getReg()))
422 return RC->contains(LiveOp.getReg()) ? RC : nullptr;
424 if (RC->hasSubClassEq(MRI.getRegClass(LiveReg)))
427 // FIXME: Allow folding when register classes are memory compatible.
431 void TargetInstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
432 llvm_unreachable("Not a MachO target");
435 static MachineInstr *foldPatchpoint(MachineFunction &MF, MachineInstr &MI,
436 ArrayRef<unsigned> Ops, int FrameIndex,
437 const TargetInstrInfo &TII) {
438 unsigned StartIdx = 0;
439 switch (MI.getOpcode()) {
440 case TargetOpcode::STACKMAP: {
441 // StackMapLiveValues are foldable
442 StartIdx = StackMapOpers(&MI).getVarIdx();
445 case TargetOpcode::PATCHPOINT: {
446 // For PatchPoint, the call args are not foldable (even if reported in the
447 // stackmap e.g. via anyregcc).
448 StartIdx = PatchPointOpers(&MI).getVarIdx();
451 case TargetOpcode::STATEPOINT: {
452 // For statepoints, fold deopt and gc arguments, but not call arguments.
453 StartIdx = StatepointOpers(&MI).getVarIdx();
457 llvm_unreachable("unexpected stackmap opcode");
460 // Return false if any operands requested for folding are not foldable (not
461 // part of the stackmap's live values).
462 for (unsigned Op : Ops) {
467 MachineInstr *NewMI =
468 MF.CreateMachineInstr(TII.get(MI.getOpcode()), MI.getDebugLoc(), true);
469 MachineInstrBuilder MIB(MF, NewMI);
471 // No need to fold return, the meta data, and function arguments
472 for (unsigned i = 0; i < StartIdx; ++i)
473 MIB.addOperand(MI.getOperand(i));
475 for (unsigned i = StartIdx; i < MI.getNumOperands(); ++i) {
476 MachineOperand &MO = MI.getOperand(i);
477 if (is_contained(Ops, i)) {
479 unsigned SpillOffset;
480 // Compute the spill slot size and offset.
481 const TargetRegisterClass *RC =
482 MF.getRegInfo().getRegClass(MO.getReg());
484 TII.getStackSlotRange(RC, MO.getSubReg(), SpillSize, SpillOffset, MF);
486 report_fatal_error("cannot spill patchpoint subregister operand");
487 MIB.addImm(StackMaps::IndirectMemRefOp);
488 MIB.addImm(SpillSize);
489 MIB.addFrameIndex(FrameIndex);
490 MIB.addImm(SpillOffset);
498 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
499 /// slot into the specified machine instruction for the specified operand(s).
500 /// If this is possible, a new instruction is returned with the specified
501 /// operand folded, otherwise NULL is returned. The client is responsible for
502 /// removing the old instruction and adding the new one in the instruction
504 MachineInstr *TargetInstrInfo::foldMemoryOperand(MachineInstr &MI,
505 ArrayRef<unsigned> Ops, int FI,
506 LiveIntervals *LIS) const {
507 auto Flags = MachineMemOperand::MONone;
508 for (unsigned i = 0, e = Ops.size(); i != e; ++i)
509 if (MI.getOperand(Ops[i]).isDef())
510 Flags |= MachineMemOperand::MOStore;
512 Flags |= MachineMemOperand::MOLoad;
514 MachineBasicBlock *MBB = MI.getParent();
515 assert(MBB && "foldMemoryOperand needs an inserted instruction");
516 MachineFunction &MF = *MBB->getParent();
518 // If we're not folding a load into a subreg, the size of the load is the
519 // size of the spill slot. But if we are, we need to figure out what the
520 // actual load size is.
522 const MachineFrameInfo &MFI = MF.getFrameInfo();
523 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
525 if (Flags & MachineMemOperand::MOStore) {
526 MemSize = MFI.getObjectSize(FI);
528 for (unsigned Idx : Ops) {
529 int64_t OpSize = MFI.getObjectSize(FI);
531 if (auto SubReg = MI.getOperand(Idx).getSubReg()) {
532 unsigned SubRegSize = TRI->getSubRegIdxSize(SubReg);
533 if (SubRegSize > 0 && !(SubRegSize % 8))
534 OpSize = SubRegSize / 8;
537 MemSize = std::max(MemSize, OpSize);
541 assert(MemSize && "Did not expect a zero-sized stack slot");
543 MachineInstr *NewMI = nullptr;
545 if (MI.getOpcode() == TargetOpcode::STACKMAP ||
546 MI.getOpcode() == TargetOpcode::PATCHPOINT ||
547 MI.getOpcode() == TargetOpcode::STATEPOINT) {
548 // Fold stackmap/patchpoint.
549 NewMI = foldPatchpoint(MF, MI, Ops, FI, *this);
551 MBB->insert(MI, NewMI);
553 // Ask the target to do the actual folding.
554 NewMI = foldMemoryOperandImpl(MF, MI, Ops, MI, FI, LIS);
558 NewMI->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
559 // Add a memory operand, foldMemoryOperandImpl doesn't do that.
560 assert((!(Flags & MachineMemOperand::MOStore) ||
561 NewMI->mayStore()) &&
562 "Folded a def to a non-store!");
563 assert((!(Flags & MachineMemOperand::MOLoad) ||
565 "Folded a use to a non-load!");
566 assert(MFI.getObjectOffset(FI) != -1);
567 MachineMemOperand *MMO = MF.getMachineMemOperand(
568 MachinePointerInfo::getFixedStack(MF, FI), Flags, MemSize,
569 MFI.getObjectAlignment(FI));
570 NewMI->addMemOperand(MF, MMO);
575 // Straight COPY may fold as load/store.
576 if (!MI.isCopy() || Ops.size() != 1)
579 const TargetRegisterClass *RC = canFoldCopy(MI, Ops[0]);
583 const MachineOperand &MO = MI.getOperand(1 - Ops[0]);
584 MachineBasicBlock::iterator Pos = MI;
586 if (Flags == MachineMemOperand::MOStore)
587 storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI);
589 loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, TRI);
593 bool TargetInstrInfo::hasReassociableOperands(
594 const MachineInstr &Inst, const MachineBasicBlock *MBB) const {
595 const MachineOperand &Op1 = Inst.getOperand(1);
596 const MachineOperand &Op2 = Inst.getOperand(2);
597 const MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
599 // We need virtual register definitions for the operands that we will
601 MachineInstr *MI1 = nullptr;
602 MachineInstr *MI2 = nullptr;
603 if (Op1.isReg() && TargetRegisterInfo::isVirtualRegister(Op1.getReg()))
604 MI1 = MRI.getUniqueVRegDef(Op1.getReg());
605 if (Op2.isReg() && TargetRegisterInfo::isVirtualRegister(Op2.getReg()))
606 MI2 = MRI.getUniqueVRegDef(Op2.getReg());
608 // And they need to be in the trace (otherwise, they won't have a depth).
609 return MI1 && MI2 && MI1->getParent() == MBB && MI2->getParent() == MBB;
612 bool TargetInstrInfo::hasReassociableSibling(const MachineInstr &Inst,
613 bool &Commuted) const {
614 const MachineBasicBlock *MBB = Inst.getParent();
615 const MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
616 MachineInstr *MI1 = MRI.getUniqueVRegDef(Inst.getOperand(1).getReg());
617 MachineInstr *MI2 = MRI.getUniqueVRegDef(Inst.getOperand(2).getReg());
618 unsigned AssocOpcode = Inst.getOpcode();
620 // If only one operand has the same opcode and it's the second source operand,
621 // the operands must be commuted.
622 Commuted = MI1->getOpcode() != AssocOpcode && MI2->getOpcode() == AssocOpcode;
626 // 1. The previous instruction must be the same type as Inst.
627 // 2. The previous instruction must have virtual register definitions for its
628 // operands in the same basic block as Inst.
629 // 3. The previous instruction's result must only be used by Inst.
630 return MI1->getOpcode() == AssocOpcode &&
631 hasReassociableOperands(*MI1, MBB) &&
632 MRI.hasOneNonDBGUse(MI1->getOperand(0).getReg());
635 // 1. The operation must be associative and commutative.
636 // 2. The instruction must have virtual register definitions for its
637 // operands in the same basic block.
638 // 3. The instruction must have a reassociable sibling.
639 bool TargetInstrInfo::isReassociationCandidate(const MachineInstr &Inst,
640 bool &Commuted) const {
641 return isAssociativeAndCommutative(Inst) &&
642 hasReassociableOperands(Inst, Inst.getParent()) &&
643 hasReassociableSibling(Inst, Commuted);
646 // The concept of the reassociation pass is that these operations can benefit
647 // from this kind of transformation:
657 // breaking the dependency between A and B, allowing them to be executed in
658 // parallel (or back-to-back in a pipeline) instead of depending on each other.
660 // FIXME: This has the potential to be expensive (compile time) while not
661 // improving the code at all. Some ways to limit the overhead:
662 // 1. Track successful transforms; bail out if hit rate gets too low.
663 // 2. Only enable at -O3 or some other non-default optimization level.
664 // 3. Pre-screen pattern candidates here: if an operand of the previous
665 // instruction is known to not increase the critical path, then don't match
667 bool TargetInstrInfo::getMachineCombinerPatterns(
669 SmallVectorImpl<MachineCombinerPattern> &Patterns) const {
671 if (isReassociationCandidate(Root, Commute)) {
672 // We found a sequence of instructions that may be suitable for a
673 // reassociation of operands to increase ILP. Specify each commutation
674 // possibility for the Prev instruction in the sequence and let the
675 // machine combiner decide if changing the operands is worthwhile.
677 Patterns.push_back(MachineCombinerPattern::REASSOC_AX_YB);
678 Patterns.push_back(MachineCombinerPattern::REASSOC_XA_YB);
680 Patterns.push_back(MachineCombinerPattern::REASSOC_AX_BY);
681 Patterns.push_back(MachineCombinerPattern::REASSOC_XA_BY);
688 /// Return true when a code sequence can improve loop throughput.
690 TargetInstrInfo::isThroughputPattern(MachineCombinerPattern Pattern) const {
693 /// Attempt the reassociation transformation to reduce critical path length.
694 /// See the above comments before getMachineCombinerPatterns().
695 void TargetInstrInfo::reassociateOps(
696 MachineInstr &Root, MachineInstr &Prev,
697 MachineCombinerPattern Pattern,
698 SmallVectorImpl<MachineInstr *> &InsInstrs,
699 SmallVectorImpl<MachineInstr *> &DelInstrs,
700 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
701 MachineFunction *MF = Root.getParent()->getParent();
702 MachineRegisterInfo &MRI = MF->getRegInfo();
703 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
704 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
705 const TargetRegisterClass *RC = Root.getRegClassConstraint(0, TII, TRI);
707 // This array encodes the operand index for each parameter because the
708 // operands may be commuted. Each row corresponds to a pattern value,
709 // and each column specifies the index of A, B, X, Y.
710 unsigned OpIdx[4][4] = {
719 case MachineCombinerPattern::REASSOC_AX_BY: Row = 0; break;
720 case MachineCombinerPattern::REASSOC_AX_YB: Row = 1; break;
721 case MachineCombinerPattern::REASSOC_XA_BY: Row = 2; break;
722 case MachineCombinerPattern::REASSOC_XA_YB: Row = 3; break;
723 default: llvm_unreachable("unexpected MachineCombinerPattern");
726 MachineOperand &OpA = Prev.getOperand(OpIdx[Row][0]);
727 MachineOperand &OpB = Root.getOperand(OpIdx[Row][1]);
728 MachineOperand &OpX = Prev.getOperand(OpIdx[Row][2]);
729 MachineOperand &OpY = Root.getOperand(OpIdx[Row][3]);
730 MachineOperand &OpC = Root.getOperand(0);
732 unsigned RegA = OpA.getReg();
733 unsigned RegB = OpB.getReg();
734 unsigned RegX = OpX.getReg();
735 unsigned RegY = OpY.getReg();
736 unsigned RegC = OpC.getReg();
738 if (TargetRegisterInfo::isVirtualRegister(RegA))
739 MRI.constrainRegClass(RegA, RC);
740 if (TargetRegisterInfo::isVirtualRegister(RegB))
741 MRI.constrainRegClass(RegB, RC);
742 if (TargetRegisterInfo::isVirtualRegister(RegX))
743 MRI.constrainRegClass(RegX, RC);
744 if (TargetRegisterInfo::isVirtualRegister(RegY))
745 MRI.constrainRegClass(RegY, RC);
746 if (TargetRegisterInfo::isVirtualRegister(RegC))
747 MRI.constrainRegClass(RegC, RC);
749 // Create a new virtual register for the result of (X op Y) instead of
750 // recycling RegB because the MachineCombiner's computation of the critical
751 // path requires a new register definition rather than an existing one.
752 unsigned NewVR = MRI.createVirtualRegister(RC);
753 InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));
755 unsigned Opcode = Root.getOpcode();
756 bool KillA = OpA.isKill();
757 bool KillX = OpX.isKill();
758 bool KillY = OpY.isKill();
760 // Create new instructions for insertion.
761 MachineInstrBuilder MIB1 =
762 BuildMI(*MF, Prev.getDebugLoc(), TII->get(Opcode), NewVR)
763 .addReg(RegX, getKillRegState(KillX))
764 .addReg(RegY, getKillRegState(KillY));
765 MachineInstrBuilder MIB2 =
766 BuildMI(*MF, Root.getDebugLoc(), TII->get(Opcode), RegC)
767 .addReg(RegA, getKillRegState(KillA))
768 .addReg(NewVR, getKillRegState(true));
770 setSpecialOperandAttr(Root, Prev, *MIB1, *MIB2);
772 // Record new instructions for insertion and old instructions for deletion.
773 InsInstrs.push_back(MIB1);
774 InsInstrs.push_back(MIB2);
775 DelInstrs.push_back(&Prev);
776 DelInstrs.push_back(&Root);
779 void TargetInstrInfo::genAlternativeCodeSequence(
780 MachineInstr &Root, MachineCombinerPattern Pattern,
781 SmallVectorImpl<MachineInstr *> &InsInstrs,
782 SmallVectorImpl<MachineInstr *> &DelInstrs,
783 DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const {
784 MachineRegisterInfo &MRI = Root.getParent()->getParent()->getRegInfo();
786 // Select the previous instruction in the sequence based on the input pattern.
787 MachineInstr *Prev = nullptr;
789 case MachineCombinerPattern::REASSOC_AX_BY:
790 case MachineCombinerPattern::REASSOC_XA_BY:
791 Prev = MRI.getUniqueVRegDef(Root.getOperand(1).getReg());
793 case MachineCombinerPattern::REASSOC_AX_YB:
794 case MachineCombinerPattern::REASSOC_XA_YB:
795 Prev = MRI.getUniqueVRegDef(Root.getOperand(2).getReg());
801 assert(Prev && "Unknown pattern for machine combiner");
803 reassociateOps(Root, *Prev, Pattern, InsInstrs, DelInstrs, InstIdxForVirtReg);
806 /// foldMemoryOperand - Same as the previous version except it allows folding
807 /// of any load and store from / to any address, not just from a specific
809 MachineInstr *TargetInstrInfo::foldMemoryOperand(MachineInstr &MI,
810 ArrayRef<unsigned> Ops,
811 MachineInstr &LoadMI,
812 LiveIntervals *LIS) const {
813 assert(LoadMI.canFoldAsLoad() && "LoadMI isn't foldable!");
815 for (unsigned i = 0, e = Ops.size(); i != e; ++i)
816 assert(MI.getOperand(Ops[i]).isUse() && "Folding load into def!");
818 MachineBasicBlock &MBB = *MI.getParent();
819 MachineFunction &MF = *MBB.getParent();
821 // Ask the target to do the actual folding.
822 MachineInstr *NewMI = nullptr;
825 if ((MI.getOpcode() == TargetOpcode::STACKMAP ||
826 MI.getOpcode() == TargetOpcode::PATCHPOINT ||
827 MI.getOpcode() == TargetOpcode::STATEPOINT) &&
828 isLoadFromStackSlot(LoadMI, FrameIndex)) {
829 // Fold stackmap/patchpoint.
830 NewMI = foldPatchpoint(MF, MI, Ops, FrameIndex, *this);
832 NewMI = &*MBB.insert(MI, NewMI);
834 // Ask the target to do the actual folding.
835 NewMI = foldMemoryOperandImpl(MF, MI, Ops, MI, LoadMI, LIS);
838 if (!NewMI) return nullptr;
840 // Copy the memoperands from the load to the folded instruction.
841 if (MI.memoperands_empty()) {
842 NewMI->setMemRefs(LoadMI.memoperands_begin(), LoadMI.memoperands_end());
845 // Handle the rare case of folding multiple loads.
846 NewMI->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
847 for (MachineInstr::mmo_iterator I = LoadMI.memoperands_begin(),
848 E = LoadMI.memoperands_end();
850 NewMI->addMemOperand(MF, *I);
856 bool TargetInstrInfo::isReallyTriviallyReMaterializableGeneric(
857 const MachineInstr &MI, AliasAnalysis *AA) const {
858 const MachineFunction &MF = *MI.getParent()->getParent();
859 const MachineRegisterInfo &MRI = MF.getRegInfo();
861 // Remat clients assume operand 0 is the defined register.
862 if (!MI.getNumOperands() || !MI.getOperand(0).isReg())
864 unsigned DefReg = MI.getOperand(0).getReg();
866 // A sub-register definition can only be rematerialized if the instruction
867 // doesn't read the other parts of the register. Otherwise it is really a
868 // read-modify-write operation on the full virtual register which cannot be
870 if (TargetRegisterInfo::isVirtualRegister(DefReg) &&
871 MI.getOperand(0).getSubReg() && MI.readsVirtualRegister(DefReg))
874 // A load from a fixed stack slot can be rematerialized. This may be
875 // redundant with subsequent checks, but it's target-independent,
876 // simple, and a common case.
878 if (isLoadFromStackSlot(MI, FrameIdx) &&
879 MF.getFrameInfo().isImmutableObjectIndex(FrameIdx))
882 // Avoid instructions obviously unsafe for remat.
883 if (MI.isNotDuplicable() || MI.mayStore() || MI.hasUnmodeledSideEffects())
886 // Don't remat inline asm. We have no idea how expensive it is
887 // even if it's side effect free.
888 if (MI.isInlineAsm())
891 // Avoid instructions which load from potentially varying memory.
892 if (MI.mayLoad() && !MI.isDereferenceableInvariantLoad(AA))
895 // If any of the registers accessed are non-constant, conservatively assume
896 // the instruction is not rematerializable.
897 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
898 const MachineOperand &MO = MI.getOperand(i);
899 if (!MO.isReg()) continue;
900 unsigned Reg = MO.getReg();
904 // Check for a well-behaved physical register.
905 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
907 // If the physreg has no defs anywhere, it's just an ambient register
908 // and we can freely move its uses. Alternatively, if it's allocatable,
909 // it could get allocated to something with a def during allocation.
910 if (!MRI.isConstantPhysReg(Reg))
913 // A physreg def. We can't remat it.
919 // Only allow one virtual-register def. There may be multiple defs of the
920 // same virtual register, though.
921 if (MO.isDef() && Reg != DefReg)
924 // Don't allow any virtual-register uses. Rematting an instruction with
925 // virtual register uses would length the live ranges of the uses, which
926 // is not necessarily a good idea, certainly not "trivial".
931 // Everything checked out.
935 int TargetInstrInfo::getSPAdjust(const MachineInstr &MI) const {
936 const MachineFunction *MF = MI.getParent()->getParent();
937 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
938 bool StackGrowsDown =
939 TFI->getStackGrowthDirection() == TargetFrameLowering::StackGrowsDown;
941 unsigned FrameSetupOpcode = getCallFrameSetupOpcode();
942 unsigned FrameDestroyOpcode = getCallFrameDestroyOpcode();
944 if (MI.getOpcode() != FrameSetupOpcode &&
945 MI.getOpcode() != FrameDestroyOpcode)
948 int SPAdj = MI.getOperand(0).getImm();
949 SPAdj = TFI->alignSPAdjust(SPAdj);
951 if ((!StackGrowsDown && MI.getOpcode() == FrameSetupOpcode) ||
952 (StackGrowsDown && MI.getOpcode() == FrameDestroyOpcode))
958 /// isSchedulingBoundary - Test if the given instruction should be
959 /// considered a scheduling boundary. This primarily includes labels
961 bool TargetInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
962 const MachineBasicBlock *MBB,
963 const MachineFunction &MF) const {
964 // Terminators and labels can't be scheduled around.
965 if (MI.isTerminator() || MI.isPosition())
968 // Don't attempt to schedule around any instruction that defines
969 // a stack-oriented pointer, as it's unlikely to be profitable. This
970 // saves compile time, because it doesn't require every single
971 // stack slot reference to depend on the instruction that does the
973 const TargetLowering &TLI = *MF.getSubtarget().getTargetLowering();
974 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
975 return MI.modifiesRegister(TLI.getStackPointerRegisterToSaveRestore(), TRI);
978 // Provide a global flag for disabling the PreRA hazard recognizer that targets
979 // may choose to honor.
980 bool TargetInstrInfo::usePreRAHazardRecognizer() const {
981 return !DisableHazardRecognizer;
984 // Default implementation of CreateTargetRAHazardRecognizer.
985 ScheduleHazardRecognizer *TargetInstrInfo::
986 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
987 const ScheduleDAG *DAG) const {
988 // Dummy hazard recognizer allows all instructions to issue.
989 return new ScheduleHazardRecognizer();
992 // Default implementation of CreateTargetMIHazardRecognizer.
993 ScheduleHazardRecognizer *TargetInstrInfo::
994 CreateTargetMIHazardRecognizer(const InstrItineraryData *II,
995 const ScheduleDAG *DAG) const {
996 return (ScheduleHazardRecognizer *)
997 new ScoreboardHazardRecognizer(II, DAG, "misched");
1000 // Default implementation of CreateTargetPostRAHazardRecognizer.
1001 ScheduleHazardRecognizer *TargetInstrInfo::
1002 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
1003 const ScheduleDAG *DAG) const {
1004 return (ScheduleHazardRecognizer *)
1005 new ScoreboardHazardRecognizer(II, DAG, "post-RA-sched");
1008 //===----------------------------------------------------------------------===//
1009 // SelectionDAG latency interface.
1010 //===----------------------------------------------------------------------===//
1013 TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
1014 SDNode *DefNode, unsigned DefIdx,
1015 SDNode *UseNode, unsigned UseIdx) const {
1016 if (!ItinData || ItinData->isEmpty())
1019 if (!DefNode->isMachineOpcode())
1022 unsigned DefClass = get(DefNode->getMachineOpcode()).getSchedClass();
1023 if (!UseNode->isMachineOpcode())
1024 return ItinData->getOperandCycle(DefClass, DefIdx);
1025 unsigned UseClass = get(UseNode->getMachineOpcode()).getSchedClass();
1026 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
1029 int TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
1031 if (!ItinData || ItinData->isEmpty())
1034 if (!N->isMachineOpcode())
1037 return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass());
1040 //===----------------------------------------------------------------------===//
1041 // MachineInstr latency interface.
1042 //===----------------------------------------------------------------------===//
1044 unsigned TargetInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
1045 const MachineInstr &MI) const {
1046 if (!ItinData || ItinData->isEmpty())
1049 unsigned Class = MI.getDesc().getSchedClass();
1050 int UOps = ItinData->Itineraries[Class].NumMicroOps;
1054 // The # of u-ops is dynamically determined. The specific target should
1055 // override this function to return the right number.
1059 /// Return the default expected latency for a def based on it's opcode.
1060 unsigned TargetInstrInfo::defaultDefLatency(const MCSchedModel &SchedModel,
1061 const MachineInstr &DefMI) const {
1062 if (DefMI.isTransient())
1064 if (DefMI.mayLoad())
1065 return SchedModel.LoadLatency;
1066 if (isHighLatencyDef(DefMI.getOpcode()))
1067 return SchedModel.HighLatency;
1071 unsigned TargetInstrInfo::getPredicationCost(const MachineInstr &) const {
1075 unsigned TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
1076 const MachineInstr &MI,
1077 unsigned *PredCost) const {
1078 // Default to one cycle for no itinerary. However, an "empty" itinerary may
1079 // still have a MinLatency property, which getStageLatency checks.
1081 return MI.mayLoad() ? 2 : 1;
1083 return ItinData->getStageLatency(MI.getDesc().getSchedClass());
1086 bool TargetInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel,
1087 const MachineInstr &DefMI,
1088 unsigned DefIdx) const {
1089 const InstrItineraryData *ItinData = SchedModel.getInstrItineraries();
1090 if (!ItinData || ItinData->isEmpty())
1093 unsigned DefClass = DefMI.getDesc().getSchedClass();
1094 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
1095 return (DefCycle != -1 && DefCycle <= 1);
1098 /// Both DefMI and UseMI must be valid. By default, call directly to the
1099 /// itinerary. This may be overriden by the target.
1100 int TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
1101 const MachineInstr &DefMI,
1103 const MachineInstr &UseMI,
1104 unsigned UseIdx) const {
1105 unsigned DefClass = DefMI.getDesc().getSchedClass();
1106 unsigned UseClass = UseMI.getDesc().getSchedClass();
1107 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
1110 /// If we can determine the operand latency from the def only, without itinerary
1111 /// lookup, do so. Otherwise return -1.
1112 int TargetInstrInfo::computeDefOperandLatency(
1113 const InstrItineraryData *ItinData, const MachineInstr &DefMI) const {
1115 // Let the target hook getInstrLatency handle missing itineraries.
1117 return getInstrLatency(ItinData, DefMI);
1119 if(ItinData->isEmpty())
1120 return defaultDefLatency(ItinData->SchedModel, DefMI);
1122 // ...operand lookup required
1126 bool TargetInstrInfo::getRegSequenceInputs(
1127 const MachineInstr &MI, unsigned DefIdx,
1128 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
1129 assert((MI.isRegSequence() ||
1130 MI.isRegSequenceLike()) && "Instruction do not have the proper type");
1132 if (!MI.isRegSequence())
1133 return getRegSequenceLikeInputs(MI, DefIdx, InputRegs);
1135 // We are looking at:
1136 // Def = REG_SEQUENCE v0, sub0, v1, sub1, ...
1137 assert(DefIdx == 0 && "REG_SEQUENCE only has one def");
1138 for (unsigned OpIdx = 1, EndOpIdx = MI.getNumOperands(); OpIdx != EndOpIdx;
1140 const MachineOperand &MOReg = MI.getOperand(OpIdx);
1141 const MachineOperand &MOSubIdx = MI.getOperand(OpIdx + 1);
1142 assert(MOSubIdx.isImm() &&
1143 "One of the subindex of the reg_sequence is not an immediate");
1144 // Record Reg:SubReg, SubIdx.
1145 InputRegs.push_back(RegSubRegPairAndIdx(MOReg.getReg(), MOReg.getSubReg(),
1146 (unsigned)MOSubIdx.getImm()));
1151 bool TargetInstrInfo::getExtractSubregInputs(
1152 const MachineInstr &MI, unsigned DefIdx,
1153 RegSubRegPairAndIdx &InputReg) const {
1154 assert((MI.isExtractSubreg() ||
1155 MI.isExtractSubregLike()) && "Instruction do not have the proper type");
1157 if (!MI.isExtractSubreg())
1158 return getExtractSubregLikeInputs(MI, DefIdx, InputReg);
1160 // We are looking at:
1161 // Def = EXTRACT_SUBREG v0.sub1, sub0.
1162 assert(DefIdx == 0 && "EXTRACT_SUBREG only has one def");
1163 const MachineOperand &MOReg = MI.getOperand(1);
1164 const MachineOperand &MOSubIdx = MI.getOperand(2);
1165 assert(MOSubIdx.isImm() &&
1166 "The subindex of the extract_subreg is not an immediate");
1168 InputReg.Reg = MOReg.getReg();
1169 InputReg.SubReg = MOReg.getSubReg();
1170 InputReg.SubIdx = (unsigned)MOSubIdx.getImm();
1174 bool TargetInstrInfo::getInsertSubregInputs(
1175 const MachineInstr &MI, unsigned DefIdx,
1176 RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const {
1177 assert((MI.isInsertSubreg() ||
1178 MI.isInsertSubregLike()) && "Instruction do not have the proper type");
1180 if (!MI.isInsertSubreg())
1181 return getInsertSubregLikeInputs(MI, DefIdx, BaseReg, InsertedReg);
1183 // We are looking at:
1184 // Def = INSERT_SEQUENCE v0, v1, sub0.
1185 assert(DefIdx == 0 && "INSERT_SUBREG only has one def");
1186 const MachineOperand &MOBaseReg = MI.getOperand(1);
1187 const MachineOperand &MOInsertedReg = MI.getOperand(2);
1188 const MachineOperand &MOSubIdx = MI.getOperand(3);
1189 assert(MOSubIdx.isImm() &&
1190 "One of the subindex of the reg_sequence is not an immediate");
1191 BaseReg.Reg = MOBaseReg.getReg();
1192 BaseReg.SubReg = MOBaseReg.getSubReg();
1194 InsertedReg.Reg = MOInsertedReg.getReg();
1195 InsertedReg.SubReg = MOInsertedReg.getSubReg();
1196 InsertedReg.SubIdx = (unsigned)MOSubIdx.getImm();