1 //===-- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLoweringBase class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/StringExtras.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/CodeGen/Analysis.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineJumpTableInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/StackMaps.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/DerivedTypes.h"
28 #include "llvm/IR/GlobalVariable.h"
29 #include "llvm/IR/Mangler.h"
30 #include "llvm/MC/MCAsmInfo.h"
31 #include "llvm/MC/MCContext.h"
32 #include "llvm/MC/MCExpr.h"
33 #include "llvm/Support/BranchProbability.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Target/TargetLoweringObjectFile.h"
38 #include "llvm/Target/TargetMachine.h"
39 #include "llvm/Target/TargetRegisterInfo.h"
40 #include "llvm/Target/TargetSubtargetInfo.h"
44 static cl::opt<bool> JumpIsExpensiveOverride(
45 "jump-is-expensive", cl::init(false),
46 cl::desc("Do not create extra branches to split comparison logic."),
49 static cl::opt<unsigned> MinimumJumpTableEntries
50 ("min-jump-table-entries", cl::init(4), cl::Hidden,
51 cl::desc("Set minimum number of entries to use a jump table."));
53 static cl::opt<unsigned> MaximumJumpTableSize
54 ("max-jump-table-size", cl::init(0), cl::Hidden,
55 cl::desc("Set maximum size of jump tables; zero for no limit."));
57 /// Minimum jump table density for normal functions.
58 static cl::opt<unsigned>
59 JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden,
60 cl::desc("Minimum density for building a jump table in "
61 "a normal function"));
63 /// Minimum jump table density for -Os or -Oz functions.
64 static cl::opt<unsigned> OptsizeJumpTableDensity(
65 "optsize-jump-table-density", cl::init(40), cl::Hidden,
66 cl::desc("Minimum density for building a jump table in "
67 "an optsize function"));
69 // Although this default value is arbitrary, it is not random. It is assumed
70 // that a condition that evaluates the same way by a higher percentage than this
71 // is best represented as control flow. Therefore, the default value N should be
72 // set such that the win from N% correct executions is greater than the loss
73 // from (100 - N)% mispredicted executions for the majority of intended targets.
74 static cl::opt<int> MinPercentageForPredictableBranch(
75 "min-predictable-branch", cl::init(99),
76 cl::desc("Minimum percentage (0-100) that a condition must be either true "
77 "or false to assume that the condition is predictable"),
80 /// InitLibcallNames - Set default libcall names.
82 static void InitLibcallNames(const char **Names, const Triple &TT) {
83 Names[RTLIB::SHL_I16] = "__ashlhi3";
84 Names[RTLIB::SHL_I32] = "__ashlsi3";
85 Names[RTLIB::SHL_I64] = "__ashldi3";
86 Names[RTLIB::SHL_I128] = "__ashlti3";
87 Names[RTLIB::SRL_I16] = "__lshrhi3";
88 Names[RTLIB::SRL_I32] = "__lshrsi3";
89 Names[RTLIB::SRL_I64] = "__lshrdi3";
90 Names[RTLIB::SRL_I128] = "__lshrti3";
91 Names[RTLIB::SRA_I16] = "__ashrhi3";
92 Names[RTLIB::SRA_I32] = "__ashrsi3";
93 Names[RTLIB::SRA_I64] = "__ashrdi3";
94 Names[RTLIB::SRA_I128] = "__ashrti3";
95 Names[RTLIB::MUL_I8] = "__mulqi3";
96 Names[RTLIB::MUL_I16] = "__mulhi3";
97 Names[RTLIB::MUL_I32] = "__mulsi3";
98 Names[RTLIB::MUL_I64] = "__muldi3";
99 Names[RTLIB::MUL_I128] = "__multi3";
100 Names[RTLIB::MULO_I32] = "__mulosi4";
101 Names[RTLIB::MULO_I64] = "__mulodi4";
102 Names[RTLIB::MULO_I128] = "__muloti4";
103 Names[RTLIB::SDIV_I8] = "__divqi3";
104 Names[RTLIB::SDIV_I16] = "__divhi3";
105 Names[RTLIB::SDIV_I32] = "__divsi3";
106 Names[RTLIB::SDIV_I64] = "__divdi3";
107 Names[RTLIB::SDIV_I128] = "__divti3";
108 Names[RTLIB::UDIV_I8] = "__udivqi3";
109 Names[RTLIB::UDIV_I16] = "__udivhi3";
110 Names[RTLIB::UDIV_I32] = "__udivsi3";
111 Names[RTLIB::UDIV_I64] = "__udivdi3";
112 Names[RTLIB::UDIV_I128] = "__udivti3";
113 Names[RTLIB::SREM_I8] = "__modqi3";
114 Names[RTLIB::SREM_I16] = "__modhi3";
115 Names[RTLIB::SREM_I32] = "__modsi3";
116 Names[RTLIB::SREM_I64] = "__moddi3";
117 Names[RTLIB::SREM_I128] = "__modti3";
118 Names[RTLIB::UREM_I8] = "__umodqi3";
119 Names[RTLIB::UREM_I16] = "__umodhi3";
120 Names[RTLIB::UREM_I32] = "__umodsi3";
121 Names[RTLIB::UREM_I64] = "__umoddi3";
122 Names[RTLIB::UREM_I128] = "__umodti3";
124 Names[RTLIB::NEG_I32] = "__negsi2";
125 Names[RTLIB::NEG_I64] = "__negdi2";
126 Names[RTLIB::ADD_F32] = "__addsf3";
127 Names[RTLIB::ADD_F64] = "__adddf3";
128 Names[RTLIB::ADD_F80] = "__addxf3";
129 Names[RTLIB::ADD_F128] = "__addtf3";
130 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
131 Names[RTLIB::SUB_F32] = "__subsf3";
132 Names[RTLIB::SUB_F64] = "__subdf3";
133 Names[RTLIB::SUB_F80] = "__subxf3";
134 Names[RTLIB::SUB_F128] = "__subtf3";
135 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
136 Names[RTLIB::MUL_F32] = "__mulsf3";
137 Names[RTLIB::MUL_F64] = "__muldf3";
138 Names[RTLIB::MUL_F80] = "__mulxf3";
139 Names[RTLIB::MUL_F128] = "__multf3";
140 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
141 Names[RTLIB::DIV_F32] = "__divsf3";
142 Names[RTLIB::DIV_F64] = "__divdf3";
143 Names[RTLIB::DIV_F80] = "__divxf3";
144 Names[RTLIB::DIV_F128] = "__divtf3";
145 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
146 Names[RTLIB::REM_F32] = "fmodf";
147 Names[RTLIB::REM_F64] = "fmod";
148 Names[RTLIB::REM_F80] = "fmodl";
149 Names[RTLIB::REM_F128] = "fmodl";
150 Names[RTLIB::REM_PPCF128] = "fmodl";
151 Names[RTLIB::FMA_F32] = "fmaf";
152 Names[RTLIB::FMA_F64] = "fma";
153 Names[RTLIB::FMA_F80] = "fmal";
154 Names[RTLIB::FMA_F128] = "fmal";
155 Names[RTLIB::FMA_PPCF128] = "fmal";
156 Names[RTLIB::POWI_F32] = "__powisf2";
157 Names[RTLIB::POWI_F64] = "__powidf2";
158 Names[RTLIB::POWI_F80] = "__powixf2";
159 Names[RTLIB::POWI_F128] = "__powitf2";
160 Names[RTLIB::POWI_PPCF128] = "__powitf2";
161 Names[RTLIB::SQRT_F32] = "sqrtf";
162 Names[RTLIB::SQRT_F64] = "sqrt";
163 Names[RTLIB::SQRT_F80] = "sqrtl";
164 Names[RTLIB::SQRT_F128] = "sqrtl";
165 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
166 Names[RTLIB::LOG_F32] = "logf";
167 Names[RTLIB::LOG_F64] = "log";
168 Names[RTLIB::LOG_F80] = "logl";
169 Names[RTLIB::LOG_F128] = "logl";
170 Names[RTLIB::LOG_PPCF128] = "logl";
171 Names[RTLIB::LOG2_F32] = "log2f";
172 Names[RTLIB::LOG2_F64] = "log2";
173 Names[RTLIB::LOG2_F80] = "log2l";
174 Names[RTLIB::LOG2_F128] = "log2l";
175 Names[RTLIB::LOG2_PPCF128] = "log2l";
176 Names[RTLIB::LOG10_F32] = "log10f";
177 Names[RTLIB::LOG10_F64] = "log10";
178 Names[RTLIB::LOG10_F80] = "log10l";
179 Names[RTLIB::LOG10_F128] = "log10l";
180 Names[RTLIB::LOG10_PPCF128] = "log10l";
181 Names[RTLIB::EXP_F32] = "expf";
182 Names[RTLIB::EXP_F64] = "exp";
183 Names[RTLIB::EXP_F80] = "expl";
184 Names[RTLIB::EXP_F128] = "expl";
185 Names[RTLIB::EXP_PPCF128] = "expl";
186 Names[RTLIB::EXP2_F32] = "exp2f";
187 Names[RTLIB::EXP2_F64] = "exp2";
188 Names[RTLIB::EXP2_F80] = "exp2l";
189 Names[RTLIB::EXP2_F128] = "exp2l";
190 Names[RTLIB::EXP2_PPCF128] = "exp2l";
191 Names[RTLIB::SIN_F32] = "sinf";
192 Names[RTLIB::SIN_F64] = "sin";
193 Names[RTLIB::SIN_F80] = "sinl";
194 Names[RTLIB::SIN_F128] = "sinl";
195 Names[RTLIB::SIN_PPCF128] = "sinl";
196 Names[RTLIB::COS_F32] = "cosf";
197 Names[RTLIB::COS_F64] = "cos";
198 Names[RTLIB::COS_F80] = "cosl";
199 Names[RTLIB::COS_F128] = "cosl";
200 Names[RTLIB::COS_PPCF128] = "cosl";
201 Names[RTLIB::POW_F32] = "powf";
202 Names[RTLIB::POW_F64] = "pow";
203 Names[RTLIB::POW_F80] = "powl";
204 Names[RTLIB::POW_F128] = "powl";
205 Names[RTLIB::POW_PPCF128] = "powl";
206 Names[RTLIB::CEIL_F32] = "ceilf";
207 Names[RTLIB::CEIL_F64] = "ceil";
208 Names[RTLIB::CEIL_F80] = "ceill";
209 Names[RTLIB::CEIL_F128] = "ceill";
210 Names[RTLIB::CEIL_PPCF128] = "ceill";
211 Names[RTLIB::TRUNC_F32] = "truncf";
212 Names[RTLIB::TRUNC_F64] = "trunc";
213 Names[RTLIB::TRUNC_F80] = "truncl";
214 Names[RTLIB::TRUNC_F128] = "truncl";
215 Names[RTLIB::TRUNC_PPCF128] = "truncl";
216 Names[RTLIB::RINT_F32] = "rintf";
217 Names[RTLIB::RINT_F64] = "rint";
218 Names[RTLIB::RINT_F80] = "rintl";
219 Names[RTLIB::RINT_F128] = "rintl";
220 Names[RTLIB::RINT_PPCF128] = "rintl";
221 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
222 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
223 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
224 Names[RTLIB::NEARBYINT_F128] = "nearbyintl";
225 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
226 Names[RTLIB::ROUND_F32] = "roundf";
227 Names[RTLIB::ROUND_F64] = "round";
228 Names[RTLIB::ROUND_F80] = "roundl";
229 Names[RTLIB::ROUND_F128] = "roundl";
230 Names[RTLIB::ROUND_PPCF128] = "roundl";
231 Names[RTLIB::FLOOR_F32] = "floorf";
232 Names[RTLIB::FLOOR_F64] = "floor";
233 Names[RTLIB::FLOOR_F80] = "floorl";
234 Names[RTLIB::FLOOR_F128] = "floorl";
235 Names[RTLIB::FLOOR_PPCF128] = "floorl";
236 Names[RTLIB::FMIN_F32] = "fminf";
237 Names[RTLIB::FMIN_F64] = "fmin";
238 Names[RTLIB::FMIN_F80] = "fminl";
239 Names[RTLIB::FMIN_F128] = "fminl";
240 Names[RTLIB::FMIN_PPCF128] = "fminl";
241 Names[RTLIB::FMAX_F32] = "fmaxf";
242 Names[RTLIB::FMAX_F64] = "fmax";
243 Names[RTLIB::FMAX_F80] = "fmaxl";
244 Names[RTLIB::FMAX_F128] = "fmaxl";
245 Names[RTLIB::FMAX_PPCF128] = "fmaxl";
246 Names[RTLIB::ROUND_F32] = "roundf";
247 Names[RTLIB::ROUND_F64] = "round";
248 Names[RTLIB::ROUND_F80] = "roundl";
249 Names[RTLIB::ROUND_F128] = "roundl";
250 Names[RTLIB::ROUND_PPCF128] = "roundl";
251 Names[RTLIB::COPYSIGN_F32] = "copysignf";
252 Names[RTLIB::COPYSIGN_F64] = "copysign";
253 Names[RTLIB::COPYSIGN_F80] = "copysignl";
254 Names[RTLIB::COPYSIGN_F128] = "copysignl";
255 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
256 Names[RTLIB::FPEXT_F32_PPCF128] = "__gcc_stoq";
257 Names[RTLIB::FPEXT_F64_PPCF128] = "__gcc_dtoq";
258 Names[RTLIB::FPEXT_F64_F128] = "__extenddftf2";
259 Names[RTLIB::FPEXT_F32_F128] = "__extendsftf2";
260 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
261 if (TT.isOSDarwin()) {
262 // For f16/f32 conversions, Darwin uses the standard naming scheme, instead
263 // of the gnueabi-style __gnu_*_ieee.
264 // FIXME: What about other targets?
265 Names[RTLIB::FPEXT_F16_F32] = "__extendhfsf2";
266 Names[RTLIB::FPROUND_F32_F16] = "__truncsfhf2";
268 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
269 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
271 Names[RTLIB::FPROUND_F64_F16] = "__truncdfhf2";
272 Names[RTLIB::FPROUND_F80_F16] = "__truncxfhf2";
273 Names[RTLIB::FPROUND_F128_F16] = "__trunctfhf2";
274 Names[RTLIB::FPROUND_PPCF128_F16] = "__trunctfhf2";
275 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
276 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
277 Names[RTLIB::FPROUND_F128_F32] = "__trunctfsf2";
278 Names[RTLIB::FPROUND_PPCF128_F32] = "__gcc_qtos";
279 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
280 Names[RTLIB::FPROUND_F128_F64] = "__trunctfdf2";
281 Names[RTLIB::FPROUND_PPCF128_F64] = "__gcc_qtod";
282 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
283 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
284 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
285 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
286 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
287 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
288 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
289 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
290 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
291 Names[RTLIB::FPTOSINT_F128_I32] = "__fixtfsi";
292 Names[RTLIB::FPTOSINT_F128_I64] = "__fixtfdi";
293 Names[RTLIB::FPTOSINT_F128_I128] = "__fixtfti";
294 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__gcc_qtou";
295 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
296 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
297 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
298 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
299 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
300 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
301 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
302 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
303 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
304 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
305 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
306 Names[RTLIB::FPTOUINT_F128_I32] = "__fixunstfsi";
307 Names[RTLIB::FPTOUINT_F128_I64] = "__fixunstfdi";
308 Names[RTLIB::FPTOUINT_F128_I128] = "__fixunstfti";
309 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
310 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
311 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
312 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
313 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
314 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
315 Names[RTLIB::SINTTOFP_I32_F128] = "__floatsitf";
316 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__gcc_itoq";
317 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
318 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
319 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
320 Names[RTLIB::SINTTOFP_I64_F128] = "__floatditf";
321 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
322 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
323 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
324 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
325 Names[RTLIB::SINTTOFP_I128_F128] = "__floattitf";
326 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
327 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
328 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
329 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
330 Names[RTLIB::UINTTOFP_I32_F128] = "__floatunsitf";
331 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__gcc_utoq";
332 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
333 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
334 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
335 Names[RTLIB::UINTTOFP_I64_F128] = "__floatunditf";
336 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
337 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
338 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
339 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
340 Names[RTLIB::UINTTOFP_I128_F128] = "__floatuntitf";
341 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
342 Names[RTLIB::OEQ_F32] = "__eqsf2";
343 Names[RTLIB::OEQ_F64] = "__eqdf2";
344 Names[RTLIB::OEQ_F128] = "__eqtf2";
345 Names[RTLIB::OEQ_PPCF128] = "__gcc_qeq";
346 Names[RTLIB::UNE_F32] = "__nesf2";
347 Names[RTLIB::UNE_F64] = "__nedf2";
348 Names[RTLIB::UNE_F128] = "__netf2";
349 Names[RTLIB::UNE_PPCF128] = "__gcc_qne";
350 Names[RTLIB::OGE_F32] = "__gesf2";
351 Names[RTLIB::OGE_F64] = "__gedf2";
352 Names[RTLIB::OGE_F128] = "__getf2";
353 Names[RTLIB::OGE_PPCF128] = "__gcc_qge";
354 Names[RTLIB::OLT_F32] = "__ltsf2";
355 Names[RTLIB::OLT_F64] = "__ltdf2";
356 Names[RTLIB::OLT_F128] = "__lttf2";
357 Names[RTLIB::OLT_PPCF128] = "__gcc_qlt";
358 Names[RTLIB::OLE_F32] = "__lesf2";
359 Names[RTLIB::OLE_F64] = "__ledf2";
360 Names[RTLIB::OLE_F128] = "__letf2";
361 Names[RTLIB::OLE_PPCF128] = "__gcc_qle";
362 Names[RTLIB::OGT_F32] = "__gtsf2";
363 Names[RTLIB::OGT_F64] = "__gtdf2";
364 Names[RTLIB::OGT_F128] = "__gttf2";
365 Names[RTLIB::OGT_PPCF128] = "__gcc_qgt";
366 Names[RTLIB::UO_F32] = "__unordsf2";
367 Names[RTLIB::UO_F64] = "__unorddf2";
368 Names[RTLIB::UO_F128] = "__unordtf2";
369 Names[RTLIB::UO_PPCF128] = "__gcc_qunord";
370 Names[RTLIB::O_F32] = "__unordsf2";
371 Names[RTLIB::O_F64] = "__unorddf2";
372 Names[RTLIB::O_F128] = "__unordtf2";
373 Names[RTLIB::O_PPCF128] = "__gcc_qunord";
374 Names[RTLIB::MEMCPY] = "memcpy";
375 Names[RTLIB::MEMMOVE] = "memmove";
376 Names[RTLIB::MEMSET] = "memset";
377 Names[RTLIB::MEMCPY_ELEMENT_ATOMIC_1] = "__llvm_memcpy_element_atomic_1";
378 Names[RTLIB::MEMCPY_ELEMENT_ATOMIC_2] = "__llvm_memcpy_element_atomic_2";
379 Names[RTLIB::MEMCPY_ELEMENT_ATOMIC_4] = "__llvm_memcpy_element_atomic_4";
380 Names[RTLIB::MEMCPY_ELEMENT_ATOMIC_8] = "__llvm_memcpy_element_atomic_8";
381 Names[RTLIB::MEMCPY_ELEMENT_ATOMIC_16] = "__llvm_memcpy_element_atomic_16";
382 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
383 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
384 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
385 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
386 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
387 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16] = "__sync_val_compare_and_swap_16";
388 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
389 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
390 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
391 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
392 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_16] = "__sync_lock_test_and_set_16";
393 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
394 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
395 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
396 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
397 Names[RTLIB::SYNC_FETCH_AND_ADD_16] = "__sync_fetch_and_add_16";
398 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
399 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
400 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
401 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
402 Names[RTLIB::SYNC_FETCH_AND_SUB_16] = "__sync_fetch_and_sub_16";
403 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
404 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
405 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
406 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
407 Names[RTLIB::SYNC_FETCH_AND_AND_16] = "__sync_fetch_and_and_16";
408 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
409 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
410 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
411 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
412 Names[RTLIB::SYNC_FETCH_AND_OR_16] = "__sync_fetch_and_or_16";
413 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
414 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
415 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4";
416 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
417 Names[RTLIB::SYNC_FETCH_AND_XOR_16] = "__sync_fetch_and_xor_16";
418 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
419 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
420 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
421 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
422 Names[RTLIB::SYNC_FETCH_AND_NAND_16] = "__sync_fetch_and_nand_16";
423 Names[RTLIB::SYNC_FETCH_AND_MAX_1] = "__sync_fetch_and_max_1";
424 Names[RTLIB::SYNC_FETCH_AND_MAX_2] = "__sync_fetch_and_max_2";
425 Names[RTLIB::SYNC_FETCH_AND_MAX_4] = "__sync_fetch_and_max_4";
426 Names[RTLIB::SYNC_FETCH_AND_MAX_8] = "__sync_fetch_and_max_8";
427 Names[RTLIB::SYNC_FETCH_AND_MAX_16] = "__sync_fetch_and_max_16";
428 Names[RTLIB::SYNC_FETCH_AND_UMAX_1] = "__sync_fetch_and_umax_1";
429 Names[RTLIB::SYNC_FETCH_AND_UMAX_2] = "__sync_fetch_and_umax_2";
430 Names[RTLIB::SYNC_FETCH_AND_UMAX_4] = "__sync_fetch_and_umax_4";
431 Names[RTLIB::SYNC_FETCH_AND_UMAX_8] = "__sync_fetch_and_umax_8";
432 Names[RTLIB::SYNC_FETCH_AND_UMAX_16] = "__sync_fetch_and_umax_16";
433 Names[RTLIB::SYNC_FETCH_AND_MIN_1] = "__sync_fetch_and_min_1";
434 Names[RTLIB::SYNC_FETCH_AND_MIN_2] = "__sync_fetch_and_min_2";
435 Names[RTLIB::SYNC_FETCH_AND_MIN_4] = "__sync_fetch_and_min_4";
436 Names[RTLIB::SYNC_FETCH_AND_MIN_8] = "__sync_fetch_and_min_8";
437 Names[RTLIB::SYNC_FETCH_AND_MIN_16] = "__sync_fetch_and_min_16";
438 Names[RTLIB::SYNC_FETCH_AND_UMIN_1] = "__sync_fetch_and_umin_1";
439 Names[RTLIB::SYNC_FETCH_AND_UMIN_2] = "__sync_fetch_and_umin_2";
440 Names[RTLIB::SYNC_FETCH_AND_UMIN_4] = "__sync_fetch_and_umin_4";
441 Names[RTLIB::SYNC_FETCH_AND_UMIN_8] = "__sync_fetch_and_umin_8";
442 Names[RTLIB::SYNC_FETCH_AND_UMIN_16] = "__sync_fetch_and_umin_16";
444 Names[RTLIB::ATOMIC_LOAD] = "__atomic_load";
445 Names[RTLIB::ATOMIC_LOAD_1] = "__atomic_load_1";
446 Names[RTLIB::ATOMIC_LOAD_2] = "__atomic_load_2";
447 Names[RTLIB::ATOMIC_LOAD_4] = "__atomic_load_4";
448 Names[RTLIB::ATOMIC_LOAD_8] = "__atomic_load_8";
449 Names[RTLIB::ATOMIC_LOAD_16] = "__atomic_load_16";
451 Names[RTLIB::ATOMIC_STORE] = "__atomic_store";
452 Names[RTLIB::ATOMIC_STORE_1] = "__atomic_store_1";
453 Names[RTLIB::ATOMIC_STORE_2] = "__atomic_store_2";
454 Names[RTLIB::ATOMIC_STORE_4] = "__atomic_store_4";
455 Names[RTLIB::ATOMIC_STORE_8] = "__atomic_store_8";
456 Names[RTLIB::ATOMIC_STORE_16] = "__atomic_store_16";
458 Names[RTLIB::ATOMIC_EXCHANGE] = "__atomic_exchange";
459 Names[RTLIB::ATOMIC_EXCHANGE_1] = "__atomic_exchange_1";
460 Names[RTLIB::ATOMIC_EXCHANGE_2] = "__atomic_exchange_2";
461 Names[RTLIB::ATOMIC_EXCHANGE_4] = "__atomic_exchange_4";
462 Names[RTLIB::ATOMIC_EXCHANGE_8] = "__atomic_exchange_8";
463 Names[RTLIB::ATOMIC_EXCHANGE_16] = "__atomic_exchange_16";
465 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE] = "__atomic_compare_exchange";
466 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_1] = "__atomic_compare_exchange_1";
467 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_2] = "__atomic_compare_exchange_2";
468 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_4] = "__atomic_compare_exchange_4";
469 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_8] = "__atomic_compare_exchange_8";
470 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_16] = "__atomic_compare_exchange_16";
472 Names[RTLIB::ATOMIC_FETCH_ADD_1] = "__atomic_fetch_add_1";
473 Names[RTLIB::ATOMIC_FETCH_ADD_2] = "__atomic_fetch_add_2";
474 Names[RTLIB::ATOMIC_FETCH_ADD_4] = "__atomic_fetch_add_4";
475 Names[RTLIB::ATOMIC_FETCH_ADD_8] = "__atomic_fetch_add_8";
476 Names[RTLIB::ATOMIC_FETCH_ADD_16] = "__atomic_fetch_add_16";
477 Names[RTLIB::ATOMIC_FETCH_SUB_1] = "__atomic_fetch_sub_1";
478 Names[RTLIB::ATOMIC_FETCH_SUB_2] = "__atomic_fetch_sub_2";
479 Names[RTLIB::ATOMIC_FETCH_SUB_4] = "__atomic_fetch_sub_4";
480 Names[RTLIB::ATOMIC_FETCH_SUB_8] = "__atomic_fetch_sub_8";
481 Names[RTLIB::ATOMIC_FETCH_SUB_16] = "__atomic_fetch_sub_16";
482 Names[RTLIB::ATOMIC_FETCH_AND_1] = "__atomic_fetch_and_1";
483 Names[RTLIB::ATOMIC_FETCH_AND_2] = "__atomic_fetch_and_2";
484 Names[RTLIB::ATOMIC_FETCH_AND_4] = "__atomic_fetch_and_4";
485 Names[RTLIB::ATOMIC_FETCH_AND_8] = "__atomic_fetch_and_8";
486 Names[RTLIB::ATOMIC_FETCH_AND_16] = "__atomic_fetch_and_16";
487 Names[RTLIB::ATOMIC_FETCH_OR_1] = "__atomic_fetch_or_1";
488 Names[RTLIB::ATOMIC_FETCH_OR_2] = "__atomic_fetch_or_2";
489 Names[RTLIB::ATOMIC_FETCH_OR_4] = "__atomic_fetch_or_4";
490 Names[RTLIB::ATOMIC_FETCH_OR_8] = "__atomic_fetch_or_8";
491 Names[RTLIB::ATOMIC_FETCH_OR_16] = "__atomic_fetch_or_16";
492 Names[RTLIB::ATOMIC_FETCH_XOR_1] = "__atomic_fetch_xor_1";
493 Names[RTLIB::ATOMIC_FETCH_XOR_2] = "__atomic_fetch_xor_2";
494 Names[RTLIB::ATOMIC_FETCH_XOR_4] = "__atomic_fetch_xor_4";
495 Names[RTLIB::ATOMIC_FETCH_XOR_8] = "__atomic_fetch_xor_8";
496 Names[RTLIB::ATOMIC_FETCH_XOR_16] = "__atomic_fetch_xor_16";
497 Names[RTLIB::ATOMIC_FETCH_NAND_1] = "__atomic_fetch_nand_1";
498 Names[RTLIB::ATOMIC_FETCH_NAND_2] = "__atomic_fetch_nand_2";
499 Names[RTLIB::ATOMIC_FETCH_NAND_4] = "__atomic_fetch_nand_4";
500 Names[RTLIB::ATOMIC_FETCH_NAND_8] = "__atomic_fetch_nand_8";
501 Names[RTLIB::ATOMIC_FETCH_NAND_16] = "__atomic_fetch_nand_16";
503 if (TT.isGNUEnvironment()) {
504 Names[RTLIB::SINCOS_F32] = "sincosf";
505 Names[RTLIB::SINCOS_F64] = "sincos";
506 Names[RTLIB::SINCOS_F80] = "sincosl";
507 Names[RTLIB::SINCOS_F128] = "sincosl";
508 Names[RTLIB::SINCOS_PPCF128] = "sincosl";
511 if (!TT.isOSOpenBSD()) {
512 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = "__stack_chk_fail";
515 Names[RTLIB::DEOPTIMIZE] = "__llvm_deoptimize";
518 /// Set default libcall CallingConvs.
519 static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
520 for (int LC = 0; LC < RTLIB::UNKNOWN_LIBCALL; ++LC)
521 CCs[LC] = CallingConv::C;
524 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
525 /// UNKNOWN_LIBCALL if there is none.
526 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
527 if (OpVT == MVT::f16) {
528 if (RetVT == MVT::f32)
529 return FPEXT_F16_F32;
530 } else if (OpVT == MVT::f32) {
531 if (RetVT == MVT::f64)
532 return FPEXT_F32_F64;
533 if (RetVT == MVT::f128)
534 return FPEXT_F32_F128;
535 if (RetVT == MVT::ppcf128)
536 return FPEXT_F32_PPCF128;
537 } else if (OpVT == MVT::f64) {
538 if (RetVT == MVT::f128)
539 return FPEXT_F64_F128;
540 else if (RetVT == MVT::ppcf128)
541 return FPEXT_F64_PPCF128;
544 return UNKNOWN_LIBCALL;
547 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
548 /// UNKNOWN_LIBCALL if there is none.
549 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
550 if (RetVT == MVT::f16) {
551 if (OpVT == MVT::f32)
552 return FPROUND_F32_F16;
553 if (OpVT == MVT::f64)
554 return FPROUND_F64_F16;
555 if (OpVT == MVT::f80)
556 return FPROUND_F80_F16;
557 if (OpVT == MVT::f128)
558 return FPROUND_F128_F16;
559 if (OpVT == MVT::ppcf128)
560 return FPROUND_PPCF128_F16;
561 } else if (RetVT == MVT::f32) {
562 if (OpVT == MVT::f64)
563 return FPROUND_F64_F32;
564 if (OpVT == MVT::f80)
565 return FPROUND_F80_F32;
566 if (OpVT == MVT::f128)
567 return FPROUND_F128_F32;
568 if (OpVT == MVT::ppcf128)
569 return FPROUND_PPCF128_F32;
570 } else if (RetVT == MVT::f64) {
571 if (OpVT == MVT::f80)
572 return FPROUND_F80_F64;
573 if (OpVT == MVT::f128)
574 return FPROUND_F128_F64;
575 if (OpVT == MVT::ppcf128)
576 return FPROUND_PPCF128_F64;
579 return UNKNOWN_LIBCALL;
582 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
583 /// UNKNOWN_LIBCALL if there is none.
584 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
585 if (OpVT == MVT::f32) {
586 if (RetVT == MVT::i32)
587 return FPTOSINT_F32_I32;
588 if (RetVT == MVT::i64)
589 return FPTOSINT_F32_I64;
590 if (RetVT == MVT::i128)
591 return FPTOSINT_F32_I128;
592 } else if (OpVT == MVT::f64) {
593 if (RetVT == MVT::i32)
594 return FPTOSINT_F64_I32;
595 if (RetVT == MVT::i64)
596 return FPTOSINT_F64_I64;
597 if (RetVT == MVT::i128)
598 return FPTOSINT_F64_I128;
599 } else if (OpVT == MVT::f80) {
600 if (RetVT == MVT::i32)
601 return FPTOSINT_F80_I32;
602 if (RetVT == MVT::i64)
603 return FPTOSINT_F80_I64;
604 if (RetVT == MVT::i128)
605 return FPTOSINT_F80_I128;
606 } else if (OpVT == MVT::f128) {
607 if (RetVT == MVT::i32)
608 return FPTOSINT_F128_I32;
609 if (RetVT == MVT::i64)
610 return FPTOSINT_F128_I64;
611 if (RetVT == MVT::i128)
612 return FPTOSINT_F128_I128;
613 } else if (OpVT == MVT::ppcf128) {
614 if (RetVT == MVT::i32)
615 return FPTOSINT_PPCF128_I32;
616 if (RetVT == MVT::i64)
617 return FPTOSINT_PPCF128_I64;
618 if (RetVT == MVT::i128)
619 return FPTOSINT_PPCF128_I128;
621 return UNKNOWN_LIBCALL;
624 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
625 /// UNKNOWN_LIBCALL if there is none.
626 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
627 if (OpVT == MVT::f32) {
628 if (RetVT == MVT::i32)
629 return FPTOUINT_F32_I32;
630 if (RetVT == MVT::i64)
631 return FPTOUINT_F32_I64;
632 if (RetVT == MVT::i128)
633 return FPTOUINT_F32_I128;
634 } else if (OpVT == MVT::f64) {
635 if (RetVT == MVT::i32)
636 return FPTOUINT_F64_I32;
637 if (RetVT == MVT::i64)
638 return FPTOUINT_F64_I64;
639 if (RetVT == MVT::i128)
640 return FPTOUINT_F64_I128;
641 } else if (OpVT == MVT::f80) {
642 if (RetVT == MVT::i32)
643 return FPTOUINT_F80_I32;
644 if (RetVT == MVT::i64)
645 return FPTOUINT_F80_I64;
646 if (RetVT == MVT::i128)
647 return FPTOUINT_F80_I128;
648 } else if (OpVT == MVT::f128) {
649 if (RetVT == MVT::i32)
650 return FPTOUINT_F128_I32;
651 if (RetVT == MVT::i64)
652 return FPTOUINT_F128_I64;
653 if (RetVT == MVT::i128)
654 return FPTOUINT_F128_I128;
655 } else if (OpVT == MVT::ppcf128) {
656 if (RetVT == MVT::i32)
657 return FPTOUINT_PPCF128_I32;
658 if (RetVT == MVT::i64)
659 return FPTOUINT_PPCF128_I64;
660 if (RetVT == MVT::i128)
661 return FPTOUINT_PPCF128_I128;
663 return UNKNOWN_LIBCALL;
666 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
667 /// UNKNOWN_LIBCALL if there is none.
668 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
669 if (OpVT == MVT::i32) {
670 if (RetVT == MVT::f32)
671 return SINTTOFP_I32_F32;
672 if (RetVT == MVT::f64)
673 return SINTTOFP_I32_F64;
674 if (RetVT == MVT::f80)
675 return SINTTOFP_I32_F80;
676 if (RetVT == MVT::f128)
677 return SINTTOFP_I32_F128;
678 if (RetVT == MVT::ppcf128)
679 return SINTTOFP_I32_PPCF128;
680 } else if (OpVT == MVT::i64) {
681 if (RetVT == MVT::f32)
682 return SINTTOFP_I64_F32;
683 if (RetVT == MVT::f64)
684 return SINTTOFP_I64_F64;
685 if (RetVT == MVT::f80)
686 return SINTTOFP_I64_F80;
687 if (RetVT == MVT::f128)
688 return SINTTOFP_I64_F128;
689 if (RetVT == MVT::ppcf128)
690 return SINTTOFP_I64_PPCF128;
691 } else if (OpVT == MVT::i128) {
692 if (RetVT == MVT::f32)
693 return SINTTOFP_I128_F32;
694 if (RetVT == MVT::f64)
695 return SINTTOFP_I128_F64;
696 if (RetVT == MVT::f80)
697 return SINTTOFP_I128_F80;
698 if (RetVT == MVT::f128)
699 return SINTTOFP_I128_F128;
700 if (RetVT == MVT::ppcf128)
701 return SINTTOFP_I128_PPCF128;
703 return UNKNOWN_LIBCALL;
706 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
707 /// UNKNOWN_LIBCALL if there is none.
708 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
709 if (OpVT == MVT::i32) {
710 if (RetVT == MVT::f32)
711 return UINTTOFP_I32_F32;
712 if (RetVT == MVT::f64)
713 return UINTTOFP_I32_F64;
714 if (RetVT == MVT::f80)
715 return UINTTOFP_I32_F80;
716 if (RetVT == MVT::f128)
717 return UINTTOFP_I32_F128;
718 if (RetVT == MVT::ppcf128)
719 return UINTTOFP_I32_PPCF128;
720 } else if (OpVT == MVT::i64) {
721 if (RetVT == MVT::f32)
722 return UINTTOFP_I64_F32;
723 if (RetVT == MVT::f64)
724 return UINTTOFP_I64_F64;
725 if (RetVT == MVT::f80)
726 return UINTTOFP_I64_F80;
727 if (RetVT == MVT::f128)
728 return UINTTOFP_I64_F128;
729 if (RetVT == MVT::ppcf128)
730 return UINTTOFP_I64_PPCF128;
731 } else if (OpVT == MVT::i128) {
732 if (RetVT == MVT::f32)
733 return UINTTOFP_I128_F32;
734 if (RetVT == MVT::f64)
735 return UINTTOFP_I128_F64;
736 if (RetVT == MVT::f80)
737 return UINTTOFP_I128_F80;
738 if (RetVT == MVT::f128)
739 return UINTTOFP_I128_F128;
740 if (RetVT == MVT::ppcf128)
741 return UINTTOFP_I128_PPCF128;
743 return UNKNOWN_LIBCALL;
746 RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) {
747 #define OP_TO_LIBCALL(Name, Enum) \
749 switch (VT.SimpleTy) { \
751 return UNKNOWN_LIBCALL; \
765 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET)
766 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP)
767 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD)
768 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB)
769 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND)
770 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR)
771 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR)
772 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND)
773 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX)
774 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX)
775 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN)
776 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN)
781 return UNKNOWN_LIBCALL;
784 RTLIB::Libcall RTLIB::getMEMCPY_ELEMENT_ATOMIC(uint64_t ElementSize) {
785 switch (ElementSize) {
787 return MEMCPY_ELEMENT_ATOMIC_1;
789 return MEMCPY_ELEMENT_ATOMIC_2;
791 return MEMCPY_ELEMENT_ATOMIC_4;
793 return MEMCPY_ELEMENT_ATOMIC_8;
795 return MEMCPY_ELEMENT_ATOMIC_16;
797 return UNKNOWN_LIBCALL;
802 /// InitCmpLibcallCCs - Set default comparison libcall CC.
804 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
805 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
806 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
807 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
808 CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
809 CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ;
810 CCs[RTLIB::UNE_F32] = ISD::SETNE;
811 CCs[RTLIB::UNE_F64] = ISD::SETNE;
812 CCs[RTLIB::UNE_F128] = ISD::SETNE;
813 CCs[RTLIB::UNE_PPCF128] = ISD::SETNE;
814 CCs[RTLIB::OGE_F32] = ISD::SETGE;
815 CCs[RTLIB::OGE_F64] = ISD::SETGE;
816 CCs[RTLIB::OGE_F128] = ISD::SETGE;
817 CCs[RTLIB::OGE_PPCF128] = ISD::SETGE;
818 CCs[RTLIB::OLT_F32] = ISD::SETLT;
819 CCs[RTLIB::OLT_F64] = ISD::SETLT;
820 CCs[RTLIB::OLT_F128] = ISD::SETLT;
821 CCs[RTLIB::OLT_PPCF128] = ISD::SETLT;
822 CCs[RTLIB::OLE_F32] = ISD::SETLE;
823 CCs[RTLIB::OLE_F64] = ISD::SETLE;
824 CCs[RTLIB::OLE_F128] = ISD::SETLE;
825 CCs[RTLIB::OLE_PPCF128] = ISD::SETLE;
826 CCs[RTLIB::OGT_F32] = ISD::SETGT;
827 CCs[RTLIB::OGT_F64] = ISD::SETGT;
828 CCs[RTLIB::OGT_F128] = ISD::SETGT;
829 CCs[RTLIB::OGT_PPCF128] = ISD::SETGT;
830 CCs[RTLIB::UO_F32] = ISD::SETNE;
831 CCs[RTLIB::UO_F64] = ISD::SETNE;
832 CCs[RTLIB::UO_F128] = ISD::SETNE;
833 CCs[RTLIB::UO_PPCF128] = ISD::SETNE;
834 CCs[RTLIB::O_F32] = ISD::SETEQ;
835 CCs[RTLIB::O_F64] = ISD::SETEQ;
836 CCs[RTLIB::O_F128] = ISD::SETEQ;
837 CCs[RTLIB::O_PPCF128] = ISD::SETEQ;
840 /// NOTE: The TargetMachine owns TLOF.
841 TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm) : TM(tm) {
844 // Perform these initializations only once.
845 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove = 8;
846 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize
847 = MaxStoresPerMemmoveOptSize = 4;
848 UseUnderscoreSetJmp = false;
849 UseUnderscoreLongJmp = false;
850 HasMultipleConditionRegisters = false;
851 HasExtractBitsInsn = false;
852 JumpIsExpensive = JumpIsExpensiveOverride;
853 PredictableSelectIsExpensive = false;
854 EnableExtLdPromotion = false;
855 HasFloatingPointExceptions = true;
856 StackPointerRegisterToSaveRestore = 0;
857 BooleanContents = UndefinedBooleanContent;
858 BooleanFloatContents = UndefinedBooleanContent;
859 BooleanVectorContents = UndefinedBooleanContent;
860 SchedPreferenceInfo = Sched::ILP;
862 JumpBufAlignment = 0;
863 MinFunctionAlignment = 0;
864 PrefFunctionAlignment = 0;
865 PrefLoopAlignment = 0;
866 GatherAllAliasesMaxDepth = 18;
867 MinStackArgumentAlignment = 1;
868 // TODO: the default will be switched to 0 in the next commit, along
869 // with the Target-specific changes necessary.
870 MaxAtomicSizeInBitsSupported = 1024;
872 MinCmpXchgSizeInBits = 0;
874 std::fill(std::begin(LibcallRoutineNames), std::end(LibcallRoutineNames), nullptr);
876 InitLibcallNames(LibcallRoutineNames, TM.getTargetTriple());
877 InitCmpLibcallCCs(CmpLibcallCCs);
878 InitLibcallCallingConvs(LibcallCallingConvs);
881 void TargetLoweringBase::initActions() {
882 // All operations default to being supported.
883 memset(OpActions, 0, sizeof(OpActions));
884 memset(LoadExtActions, 0, sizeof(LoadExtActions));
885 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
886 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
887 memset(CondCodeActions, 0, sizeof(CondCodeActions));
888 std::fill(std::begin(RegClassForVT), std::end(RegClassForVT), nullptr);
889 std::fill(std::begin(TargetDAGCombineArray),
890 std::end(TargetDAGCombineArray), 0);
892 // Set default actions for various operations.
893 for (MVT VT : MVT::all_valuetypes()) {
894 // Default all indexed load / store to expand.
895 for (unsigned IM = (unsigned)ISD::PRE_INC;
896 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
897 setIndexedLoadAction(IM, VT, Expand);
898 setIndexedStoreAction(IM, VT, Expand);
901 // Most backends expect to see the node which just returns the value loaded.
902 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand);
904 // These operations default to expand.
905 setOperationAction(ISD::FGETSIGN, VT, Expand);
906 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand);
907 setOperationAction(ISD::FMINNUM, VT, Expand);
908 setOperationAction(ISD::FMAXNUM, VT, Expand);
909 setOperationAction(ISD::FMINNAN, VT, Expand);
910 setOperationAction(ISD::FMAXNAN, VT, Expand);
911 setOperationAction(ISD::FMAD, VT, Expand);
912 setOperationAction(ISD::SMIN, VT, Expand);
913 setOperationAction(ISD::SMAX, VT, Expand);
914 setOperationAction(ISD::UMIN, VT, Expand);
915 setOperationAction(ISD::UMAX, VT, Expand);
916 setOperationAction(ISD::ABS, VT, Expand);
918 // Overflow operations default to expand
919 setOperationAction(ISD::SADDO, VT, Expand);
920 setOperationAction(ISD::SSUBO, VT, Expand);
921 setOperationAction(ISD::UADDO, VT, Expand);
922 setOperationAction(ISD::USUBO, VT, Expand);
923 setOperationAction(ISD::SMULO, VT, Expand);
924 setOperationAction(ISD::UMULO, VT, Expand);
926 // ADDCARRY operations default to expand
927 setOperationAction(ISD::ADDCARRY, VT, Expand);
928 setOperationAction(ISD::SUBCARRY, VT, Expand);
930 // These default to Expand so they will be expanded to CTLZ/CTTZ by default.
931 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
932 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
934 setOperationAction(ISD::BITREVERSE, VT, Expand);
936 // These library functions default to expand.
937 setOperationAction(ISD::FROUND, VT, Expand);
938 setOperationAction(ISD::FPOWI, VT, Expand);
940 // These operations default to expand for vector types.
942 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
943 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, VT, Expand);
944 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand);
945 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Expand);
948 // For most targets @llvm.get.dynamic.area.offset just returns 0.
949 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, VT, Expand);
952 // Most targets ignore the @llvm.prefetch intrinsic.
953 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
955 // Most targets also ignore the @llvm.readcyclecounter intrinsic.
956 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Expand);
958 // ConstantFP nodes default to expand. Targets can either change this to
959 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
960 // to optimize expansions for certain constants.
961 setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
962 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
963 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
964 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
965 setOperationAction(ISD::ConstantFP, MVT::f128, Expand);
967 // These library functions default to expand.
968 for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) {
969 setOperationAction(ISD::FLOG , VT, Expand);
970 setOperationAction(ISD::FLOG2, VT, Expand);
971 setOperationAction(ISD::FLOG10, VT, Expand);
972 setOperationAction(ISD::FEXP , VT, Expand);
973 setOperationAction(ISD::FEXP2, VT, Expand);
974 setOperationAction(ISD::FFLOOR, VT, Expand);
975 setOperationAction(ISD::FNEARBYINT, VT, Expand);
976 setOperationAction(ISD::FCEIL, VT, Expand);
977 setOperationAction(ISD::FRINT, VT, Expand);
978 setOperationAction(ISD::FTRUNC, VT, Expand);
979 setOperationAction(ISD::FROUND, VT, Expand);
982 // Default ISD::TRAP to expand (which turns it into abort).
983 setOperationAction(ISD::TRAP, MVT::Other, Expand);
985 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
986 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
988 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand);
991 MVT TargetLoweringBase::getScalarShiftAmountTy(const DataLayout &DL,
993 return MVT::getIntegerVT(8 * DL.getPointerSize(0));
996 EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy,
997 const DataLayout &DL) const {
998 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
999 if (LHSTy.isVector())
1001 return getScalarShiftAmountTy(DL, LHSTy);
1004 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
1005 assert(isTypeLegal(VT));
1017 void TargetLoweringBase::setJumpIsExpensive(bool isExpensive) {
1018 // If the command-line option was specified, ignore this request.
1019 if (!JumpIsExpensiveOverride.getNumOccurrences())
1020 JumpIsExpensive = isExpensive;
1023 TargetLoweringBase::LegalizeKind
1024 TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
1025 // If this is a simple type, use the ComputeRegisterProp mechanism.
1026 if (VT.isSimple()) {
1027 MVT SVT = VT.getSimpleVT();
1028 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
1029 MVT NVT = TransformToType[SVT.SimpleTy];
1030 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
1032 assert((LA == TypeLegal || LA == TypeSoftenFloat ||
1033 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger) &&
1034 "Promote may not follow Expand or Promote");
1036 if (LA == TypeSplitVector)
1037 return LegalizeKind(LA,
1038 EVT::getVectorVT(Context, SVT.getVectorElementType(),
1039 SVT.getVectorNumElements() / 2));
1040 if (LA == TypeScalarizeVector)
1041 return LegalizeKind(LA, SVT.getVectorElementType());
1042 return LegalizeKind(LA, NVT);
1045 // Handle Extended Scalar Types.
1046 if (!VT.isVector()) {
1047 assert(VT.isInteger() && "Float types must be simple");
1048 unsigned BitSize = VT.getSizeInBits();
1049 // First promote to a power-of-two size, then expand if necessary.
1050 if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
1051 EVT NVT = VT.getRoundIntegerType(Context);
1052 assert(NVT != VT && "Unable to round integer VT");
1053 LegalizeKind NextStep = getTypeConversion(Context, NVT);
1054 // Avoid multi-step promotion.
1055 if (NextStep.first == TypePromoteInteger)
1057 // Return rounded integer type.
1058 return LegalizeKind(TypePromoteInteger, NVT);
1061 return LegalizeKind(TypeExpandInteger,
1062 EVT::getIntegerVT(Context, VT.getSizeInBits() / 2));
1065 // Handle vector types.
1066 unsigned NumElts = VT.getVectorNumElements();
1067 EVT EltVT = VT.getVectorElementType();
1069 // Vectors with only one element are always scalarized.
1071 return LegalizeKind(TypeScalarizeVector, EltVT);
1073 // Try to widen vector elements until the element type is a power of two and
1074 // promote it to a legal type later on, for example:
1075 // <3 x i8> -> <4 x i8> -> <4 x i32>
1076 if (EltVT.isInteger()) {
1077 // Vectors with a number of elements that is not a power of two are always
1078 // widened, for example <3 x i8> -> <4 x i8>.
1079 if (!VT.isPow2VectorType()) {
1080 NumElts = (unsigned)NextPowerOf2(NumElts);
1081 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
1082 return LegalizeKind(TypeWidenVector, NVT);
1085 // Examine the element type.
1086 LegalizeKind LK = getTypeConversion(Context, EltVT);
1088 // If type is to be expanded, split the vector.
1089 // <4 x i140> -> <2 x i140>
1090 if (LK.first == TypeExpandInteger)
1091 return LegalizeKind(TypeSplitVector,
1092 EVT::getVectorVT(Context, EltVT, NumElts / 2));
1094 // Promote the integer element types until a legal vector type is found
1095 // or until the element integer type is too big. If a legal type was not
1096 // found, fallback to the usual mechanism of widening/splitting the
1098 EVT OldEltVT = EltVT;
1100 // Increase the bitwidth of the element to the next pow-of-two
1101 // (which is greater than 8 bits).
1102 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits())
1103 .getRoundIntegerType(Context);
1105 // Stop trying when getting a non-simple element type.
1106 // Note that vector elements may be greater than legal vector element
1107 // types. Example: X86 XMM registers hold 64bit element on 32bit
1109 if (!EltVT.isSimple())
1112 // Build a new vector type and check if it is legal.
1113 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1114 // Found a legal promoted vector type.
1115 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
1116 return LegalizeKind(TypePromoteInteger,
1117 EVT::getVectorVT(Context, EltVT, NumElts));
1120 // Reset the type to the unexpanded type if we did not find a legal vector
1121 // type with a promoted vector element type.
1125 // Try to widen the vector until a legal type is found.
1126 // If there is no wider legal type, split the vector.
1128 // Round up to the next power of 2.
1129 NumElts = (unsigned)NextPowerOf2(NumElts);
1131 // If there is no simple vector type with this many elements then there
1132 // cannot be a larger legal vector type. Note that this assumes that
1133 // there are no skipped intermediate vector types in the simple types.
1134 if (!EltVT.isSimple())
1136 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1137 if (LargerVector == MVT())
1140 // If this type is legal then widen the vector.
1141 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
1142 return LegalizeKind(TypeWidenVector, LargerVector);
1145 // Widen odd vectors to next power of two.
1146 if (!VT.isPow2VectorType()) {
1147 EVT NVT = VT.getPow2VectorType(Context);
1148 return LegalizeKind(TypeWidenVector, NVT);
1151 // Vectors with illegal element types are expanded.
1152 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
1153 return LegalizeKind(TypeSplitVector, NVT);
1156 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
1157 unsigned &NumIntermediates,
1159 TargetLoweringBase *TLI) {
1160 // Figure out the right, legal destination reg to copy into.
1161 unsigned NumElts = VT.getVectorNumElements();
1162 MVT EltTy = VT.getVectorElementType();
1164 unsigned NumVectorRegs = 1;
1166 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1167 // could break down into LHS/RHS like LegalizeDAG does.
1168 if (!isPowerOf2_32(NumElts)) {
1169 NumVectorRegs = NumElts;
1173 // Divide the input until we get to a supported size. This will always
1174 // end with a scalar if the target doesn't support vectors.
1175 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
1177 NumVectorRegs <<= 1;
1180 NumIntermediates = NumVectorRegs;
1182 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
1183 if (!TLI->isTypeLegal(NewVT))
1185 IntermediateVT = NewVT;
1187 unsigned NewVTSize = NewVT.getSizeInBits();
1189 // Convert sizes such as i33 to i64.
1190 if (!isPowerOf2_32(NewVTSize))
1191 NewVTSize = NextPowerOf2(NewVTSize);
1193 MVT DestVT = TLI->getRegisterType(NewVT);
1194 RegisterVT = DestVT;
1195 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1196 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1198 // Otherwise, promotion or legal types use the same number of registers as
1199 // the vector decimated to the appropriate level.
1200 return NumVectorRegs;
1203 /// isLegalRC - Return true if the value types that can be represented by the
1204 /// specified register class are all legal.
1205 bool TargetLoweringBase::isLegalRC(const TargetRegisterInfo &TRI,
1206 const TargetRegisterClass &RC) const {
1207 for (auto I = TRI.legalclasstypes_begin(RC); *I != MVT::Other; ++I)
1208 if (isTypeLegal(*I))
1213 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
1214 /// sequence of memory operands that is recognized by PrologEpilogInserter.
1216 TargetLoweringBase::emitPatchPoint(MachineInstr &InitialMI,
1217 MachineBasicBlock *MBB) const {
1218 MachineInstr *MI = &InitialMI;
1219 MachineFunction &MF = *MI->getParent()->getParent();
1220 MachineFrameInfo &MFI = MF.getFrameInfo();
1222 // We're handling multiple types of operands here:
1223 // PATCHPOINT MetaArgs - live-in, read only, direct
1224 // STATEPOINT Deopt Spill - live-through, read only, indirect
1225 // STATEPOINT Deopt Alloca - live-through, read only, direct
1226 // (We're currently conservative and mark the deopt slots read/write in
1228 // STATEPOINT GC Spill - live-through, read/write, indirect
1229 // STATEPOINT GC Alloca - live-through, read/write, direct
1230 // The live-in vs live-through is handled already (the live through ones are
1231 // all stack slots), but we need to handle the different type of stackmap
1232 // operands and memory effects here.
1234 // MI changes inside this loop as we grow operands.
1235 for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) {
1236 MachineOperand &MO = MI->getOperand(OperIdx);
1240 // foldMemoryOperand builds a new MI after replacing a single FI operand
1241 // with the canonical set of five x86 addressing-mode operands.
1242 int FI = MO.getIndex();
1243 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
1245 // Copy operands before the frame-index.
1246 for (unsigned i = 0; i < OperIdx; ++i)
1247 MIB.add(MI->getOperand(i));
1248 // Add frame index operands recognized by stackmaps.cpp
1249 if (MFI.isStatepointSpillSlotObjectIndex(FI)) {
1250 // indirect-mem-ref tag, size, #FI, offset.
1251 // Used for spills inserted by StatepointLowering. This codepath is not
1252 // used for patchpoints/stackmaps at all, for these spilling is done via
1253 // foldMemoryOperand callback only.
1254 assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity");
1255 MIB.addImm(StackMaps::IndirectMemRefOp);
1256 MIB.addImm(MFI.getObjectSize(FI));
1257 MIB.add(MI->getOperand(OperIdx));
1260 // direct-mem-ref tag, #FI, offset.
1261 // Used by patchpoint, and direct alloca arguments to statepoints
1262 MIB.addImm(StackMaps::DirectMemRefOp);
1263 MIB.add(MI->getOperand(OperIdx));
1266 // Copy the operands after the frame index.
1267 for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i)
1268 MIB.add(MI->getOperand(i));
1270 // Inherit previous memory operands.
1271 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
1272 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
1274 // Add a new memory operand for this FI.
1275 assert(MFI.getObjectOffset(FI) != -1);
1277 auto Flags = MachineMemOperand::MOLoad;
1278 if (MI->getOpcode() == TargetOpcode::STATEPOINT) {
1279 Flags |= MachineMemOperand::MOStore;
1280 Flags |= MachineMemOperand::MOVolatile;
1282 MachineMemOperand *MMO = MF.getMachineMemOperand(
1283 MachinePointerInfo::getFixedStack(MF, FI), Flags,
1284 MF.getDataLayout().getPointerSize(), MFI.getObjectAlignment(FI));
1285 MIB->addMemOperand(MF, MMO);
1287 // Replace the instruction and update the operand index.
1288 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
1289 OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1;
1290 MI->eraseFromParent();
1296 /// findRepresentativeClass - Return the largest legal super-reg register class
1297 /// of the register class for the specified type and its associated "cost".
1298 // This function is in TargetLowering because it uses RegClassForVT which would
1299 // need to be moved to TargetRegisterInfo and would necessitate moving
1300 // isTypeLegal over as well - a massive change that would just require
1301 // TargetLowering having a TargetRegisterInfo class member that it would use.
1302 std::pair<const TargetRegisterClass *, uint8_t>
1303 TargetLoweringBase::findRepresentativeClass(const TargetRegisterInfo *TRI,
1305 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1307 return std::make_pair(RC, 0);
1309 // Compute the set of all super-register classes.
1310 BitVector SuperRegRC(TRI->getNumRegClasses());
1311 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
1312 SuperRegRC.setBitsInMask(RCI.getMask());
1314 // Find the first legal register class with the largest spill size.
1315 const TargetRegisterClass *BestRC = RC;
1316 for (unsigned i : SuperRegRC.set_bits()) {
1317 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1318 // We want the largest possible spill size.
1319 if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC))
1321 if (!isLegalRC(*TRI, *SuperRC))
1325 return std::make_pair(BestRC, 1);
1328 /// computeRegisterProperties - Once all of the register classes are added,
1329 /// this allows us to compute derived properties we expose.
1330 void TargetLoweringBase::computeRegisterProperties(
1331 const TargetRegisterInfo *TRI) {
1332 static_assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE,
1333 "Too many value types for ValueTypeActions to hold!");
1335 // Everything defaults to needing one register.
1336 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1337 NumRegistersForVT[i] = 1;
1338 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
1340 // ...except isVoid, which doesn't need any registers.
1341 NumRegistersForVT[MVT::isVoid] = 0;
1343 // Find the largest integer register class.
1344 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
1345 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
1346 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1348 // Every integer value type larger than this largest register takes twice as
1349 // many registers to represent as the previous ValueType.
1350 for (unsigned ExpandedReg = LargestIntReg + 1;
1351 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1352 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1353 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1354 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1355 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg,
1359 // Inspect all of the ValueType's smaller than the largest integer
1360 // register to see which ones need promotion.
1361 unsigned LegalIntReg = LargestIntReg;
1362 for (unsigned IntReg = LargestIntReg - 1;
1363 IntReg >= (unsigned)MVT::i1; --IntReg) {
1364 MVT IVT = (MVT::SimpleValueType)IntReg;
1365 if (isTypeLegal(IVT)) {
1366 LegalIntReg = IntReg;
1368 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1369 (const MVT::SimpleValueType)LegalIntReg;
1370 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
1374 // ppcf128 type is really two f64's.
1375 if (!isTypeLegal(MVT::ppcf128)) {
1376 if (isTypeLegal(MVT::f64)) {
1377 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1378 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1379 TransformToType[MVT::ppcf128] = MVT::f64;
1380 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
1382 NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];
1383 RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];
1384 TransformToType[MVT::ppcf128] = MVT::i128;
1385 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeSoftenFloat);
1389 // Decide how to handle f128. If the target does not have native f128 support,
1390 // expand it to i128 and we will be generating soft float library calls.
1391 if (!isTypeLegal(MVT::f128)) {
1392 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1393 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1394 TransformToType[MVT::f128] = MVT::i128;
1395 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
1398 // Decide how to handle f64. If the target does not have native f64 support,
1399 // expand it to i64 and we will be generating soft float library calls.
1400 if (!isTypeLegal(MVT::f64)) {
1401 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1402 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1403 TransformToType[MVT::f64] = MVT::i64;
1404 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
1407 // Decide how to handle f32. If the target does not have native f32 support,
1408 // expand it to i32 and we will be generating soft float library calls.
1409 if (!isTypeLegal(MVT::f32)) {
1410 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1411 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1412 TransformToType[MVT::f32] = MVT::i32;
1413 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
1416 // Decide how to handle f16. If the target does not have native f16 support,
1417 // promote it to f32, because there are no f16 library calls (except for
1419 if (!isTypeLegal(MVT::f16)) {
1420 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];
1421 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];
1422 TransformToType[MVT::f16] = MVT::f32;
1423 ValueTypeActions.setTypeAction(MVT::f16, TypePromoteFloat);
1426 // Loop over all of the vector value types to see which need transformations.
1427 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1428 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1429 MVT VT = (MVT::SimpleValueType) i;
1430 if (isTypeLegal(VT))
1433 MVT EltVT = VT.getVectorElementType();
1434 unsigned NElts = VT.getVectorNumElements();
1435 bool IsLegalWiderType = false;
1436 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1437 switch (PreferredAction) {
1438 case TypePromoteInteger: {
1439 // Try to promote the elements of integer vectors. If no legal
1440 // promotion was found, fall through to the widen-vector method.
1441 for (unsigned nVT = i + 1; nVT <= MVT::LAST_INTEGER_VECTOR_VALUETYPE; ++nVT) {
1442 MVT SVT = (MVT::SimpleValueType) nVT;
1443 // Promote vectors of integers to vectors with the same number
1444 // of elements, with a wider element type.
1445 if (SVT.getScalarSizeInBits() > EltVT.getSizeInBits() &&
1446 SVT.getVectorNumElements() == NElts && isTypeLegal(SVT)) {
1447 TransformToType[i] = SVT;
1448 RegisterTypeForVT[i] = SVT;
1449 NumRegistersForVT[i] = 1;
1450 ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
1451 IsLegalWiderType = true;
1455 if (IsLegalWiderType)
1458 case TypeWidenVector: {
1459 // Try to widen the vector.
1460 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1461 MVT SVT = (MVT::SimpleValueType) nVT;
1462 if (SVT.getVectorElementType() == EltVT
1463 && SVT.getVectorNumElements() > NElts && isTypeLegal(SVT)) {
1464 TransformToType[i] = SVT;
1465 RegisterTypeForVT[i] = SVT;
1466 NumRegistersForVT[i] = 1;
1467 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1468 IsLegalWiderType = true;
1472 if (IsLegalWiderType)
1475 case TypeSplitVector:
1476 case TypeScalarizeVector: {
1479 unsigned NumIntermediates;
1480 NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT,
1481 NumIntermediates, RegisterVT, this);
1482 RegisterTypeForVT[i] = RegisterVT;
1484 MVT NVT = VT.getPow2VectorType();
1486 // Type is already a power of 2. The default action is to split.
1487 TransformToType[i] = MVT::Other;
1488 if (PreferredAction == TypeScalarizeVector)
1489 ValueTypeActions.setTypeAction(VT, TypeScalarizeVector);
1490 else if (PreferredAction == TypeSplitVector)
1491 ValueTypeActions.setTypeAction(VT, TypeSplitVector);
1493 // Set type action according to the number of elements.
1494 ValueTypeActions.setTypeAction(VT, NElts == 1 ? TypeScalarizeVector
1497 TransformToType[i] = NVT;
1498 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1503 llvm_unreachable("Unknown vector legalization action!");
1507 // Determine the 'representative' register class for each value type.
1508 // An representative register class is the largest (meaning one which is
1509 // not a sub-register class / subreg register class) legal register class for
1510 // a group of value types. For example, on i386, i8, i16, and i32
1511 // representative would be GR32; while on x86_64 it's GR64.
1512 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1513 const TargetRegisterClass* RRC;
1515 std::tie(RRC, Cost) = findRepresentativeClass(TRI, (MVT::SimpleValueType)i);
1516 RepRegClassForVT[i] = RRC;
1517 RepRegClassCostForVT[i] = Cost;
1521 EVT TargetLoweringBase::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1523 assert(!VT.isVector() && "No default SetCC type for vectors!");
1524 return getPointerTy(DL).SimpleTy;
1527 MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const {
1528 return MVT::i32; // return the default value
1531 /// getVectorTypeBreakdown - Vector types are broken down into some number of
1532 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1533 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1534 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1536 /// This method returns the number of registers needed, and the VT for each
1537 /// register. It also returns the VT and quantity of the intermediate values
1538 /// before they are promoted/expanded.
1540 unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
1541 EVT &IntermediateVT,
1542 unsigned &NumIntermediates,
1543 MVT &RegisterVT) const {
1544 unsigned NumElts = VT.getVectorNumElements();
1546 // If there is a wider vector type with the same element type as this one,
1547 // or a promoted vector type that has the same number of elements which
1548 // are wider, then we should convert to that legal vector type.
1549 // This handles things like <2 x float> -> <4 x float> and
1550 // <4 x i1> -> <4 x i32>.
1551 LegalizeTypeAction TA = getTypeAction(Context, VT);
1552 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1553 EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1554 if (isTypeLegal(RegisterEVT)) {
1555 IntermediateVT = RegisterEVT;
1556 RegisterVT = RegisterEVT.getSimpleVT();
1557 NumIntermediates = 1;
1562 // Figure out the right, legal destination reg to copy into.
1563 EVT EltTy = VT.getVectorElementType();
1565 unsigned NumVectorRegs = 1;
1567 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1568 // could break down into LHS/RHS like LegalizeDAG does.
1569 if (!isPowerOf2_32(NumElts)) {
1570 NumVectorRegs = NumElts;
1574 // Divide the input until we get to a supported size. This will always
1575 // end with a scalar if the target doesn't support vectors.
1576 while (NumElts > 1 && !isTypeLegal(
1577 EVT::getVectorVT(Context, EltTy, NumElts))) {
1579 NumVectorRegs <<= 1;
1582 NumIntermediates = NumVectorRegs;
1584 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
1585 if (!isTypeLegal(NewVT))
1587 IntermediateVT = NewVT;
1589 MVT DestVT = getRegisterType(Context, NewVT);
1590 RegisterVT = DestVT;
1591 unsigned NewVTSize = NewVT.getSizeInBits();
1593 // Convert sizes such as i33 to i64.
1594 if (!isPowerOf2_32(NewVTSize))
1595 NewVTSize = NextPowerOf2(NewVTSize);
1597 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1598 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1600 // Otherwise, promotion or legal types use the same number of registers as
1601 // the vector decimated to the appropriate level.
1602 return NumVectorRegs;
1605 /// Get the EVTs and ArgFlags collections that represent the legalized return
1606 /// type of the given function. This does not require a DAG or a return value,
1607 /// and is suitable for use before any DAGs for the function are constructed.
1608 /// TODO: Move this out of TargetLowering.cpp.
1609 void llvm::GetReturnInfo(Type *ReturnType, AttributeList attr,
1610 SmallVectorImpl<ISD::OutputArg> &Outs,
1611 const TargetLowering &TLI, const DataLayout &DL) {
1612 SmallVector<EVT, 4> ValueVTs;
1613 ComputeValueVTs(TLI, DL, ReturnType, ValueVTs);
1614 unsigned NumValues = ValueVTs.size();
1615 if (NumValues == 0) return;
1617 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1618 EVT VT = ValueVTs[j];
1619 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1621 if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
1622 ExtendKind = ISD::SIGN_EXTEND;
1623 else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt))
1624 ExtendKind = ISD::ZERO_EXTEND;
1626 // FIXME: C calling convention requires the return type to be promoted to
1627 // at least 32-bit. But this is not necessary for non-C calling
1628 // conventions. The frontend should mark functions whose return values
1629 // require promoting with signext or zeroext attributes.
1630 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1631 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1632 if (VT.bitsLT(MinVT))
1636 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
1637 MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
1639 // 'inreg' on function refers to return value
1640 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1641 if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::InReg))
1644 // Propagate extension type if any
1645 if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
1647 else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt))
1650 for (unsigned i = 0; i < NumParts; ++i)
1651 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isFixed=*/true, 0, 0));
1655 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1656 /// function arguments in the caller parameter area. This is the actual
1657 /// alignment, not its logarithm.
1658 unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty,
1659 const DataLayout &DL) const {
1660 return DL.getABITypeAlignment(Ty);
1663 bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context,
1664 const DataLayout &DL, EVT VT,
1668 // Check if the specified alignment is sufficient based on the data layout.
1669 // TODO: While using the data layout works in practice, a better solution
1670 // would be to implement this check directly (make this a virtual function).
1671 // For example, the ABI alignment may change based on software platform while
1672 // this function should only be affected by hardware implementation.
1673 Type *Ty = VT.getTypeForEVT(Context);
1674 if (Alignment >= DL.getABITypeAlignment(Ty)) {
1675 // Assume that an access that meets the ABI-specified alignment is fast.
1676 if (Fast != nullptr)
1681 // This is a misaligned access.
1682 return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Fast);
1685 BranchProbability TargetLoweringBase::getPredictableBranchThreshold() const {
1686 return BranchProbability(MinPercentageForPredictableBranch, 100);
1689 //===----------------------------------------------------------------------===//
1690 // TargetTransformInfo Helpers
1691 //===----------------------------------------------------------------------===//
1693 int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const {
1694 enum InstructionOpcodes {
1695 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1696 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1697 #include "llvm/IR/Instruction.def"
1699 switch (static_cast<InstructionOpcodes>(Opcode)) {
1702 case Switch: return 0;
1703 case IndirectBr: return 0;
1704 case Invoke: return 0;
1705 case Resume: return 0;
1706 case Unreachable: return 0;
1707 case CleanupRet: return 0;
1708 case CatchRet: return 0;
1709 case CatchPad: return 0;
1710 case CatchSwitch: return 0;
1711 case CleanupPad: return 0;
1712 case Add: return ISD::ADD;
1713 case FAdd: return ISD::FADD;
1714 case Sub: return ISD::SUB;
1715 case FSub: return ISD::FSUB;
1716 case Mul: return ISD::MUL;
1717 case FMul: return ISD::FMUL;
1718 case UDiv: return ISD::UDIV;
1719 case SDiv: return ISD::SDIV;
1720 case FDiv: return ISD::FDIV;
1721 case URem: return ISD::UREM;
1722 case SRem: return ISD::SREM;
1723 case FRem: return ISD::FREM;
1724 case Shl: return ISD::SHL;
1725 case LShr: return ISD::SRL;
1726 case AShr: return ISD::SRA;
1727 case And: return ISD::AND;
1728 case Or: return ISD::OR;
1729 case Xor: return ISD::XOR;
1730 case Alloca: return 0;
1731 case Load: return ISD::LOAD;
1732 case Store: return ISD::STORE;
1733 case GetElementPtr: return 0;
1734 case Fence: return 0;
1735 case AtomicCmpXchg: return 0;
1736 case AtomicRMW: return 0;
1737 case Trunc: return ISD::TRUNCATE;
1738 case ZExt: return ISD::ZERO_EXTEND;
1739 case SExt: return ISD::SIGN_EXTEND;
1740 case FPToUI: return ISD::FP_TO_UINT;
1741 case FPToSI: return ISD::FP_TO_SINT;
1742 case UIToFP: return ISD::UINT_TO_FP;
1743 case SIToFP: return ISD::SINT_TO_FP;
1744 case FPTrunc: return ISD::FP_ROUND;
1745 case FPExt: return ISD::FP_EXTEND;
1746 case PtrToInt: return ISD::BITCAST;
1747 case IntToPtr: return ISD::BITCAST;
1748 case BitCast: return ISD::BITCAST;
1749 case AddrSpaceCast: return ISD::ADDRSPACECAST;
1750 case ICmp: return ISD::SETCC;
1751 case FCmp: return ISD::SETCC;
1753 case Call: return 0;
1754 case Select: return ISD::SELECT;
1755 case UserOp1: return 0;
1756 case UserOp2: return 0;
1757 case VAArg: return 0;
1758 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
1759 case InsertElement: return ISD::INSERT_VECTOR_ELT;
1760 case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1761 case ExtractValue: return ISD::MERGE_VALUES;
1762 case InsertValue: return ISD::MERGE_VALUES;
1763 case LandingPad: return 0;
1766 llvm_unreachable("Unknown instruction type encountered!");
1770 TargetLoweringBase::getTypeLegalizationCost(const DataLayout &DL,
1772 LLVMContext &C = Ty->getContext();
1773 EVT MTy = getValueType(DL, Ty);
1776 // We keep legalizing the type until we find a legal kind. We assume that
1777 // the only operation that costs anything is the split. After splitting
1778 // we need to handle two types.
1780 LegalizeKind LK = getTypeConversion(C, MTy);
1782 if (LK.first == TypeLegal)
1783 return std::make_pair(Cost, MTy.getSimpleVT());
1785 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger)
1788 // Do not loop with f128 type.
1789 if (MTy == LK.second)
1790 return std::make_pair(Cost, MTy.getSimpleVT());
1792 // Keep legalizing the type.
1797 Value *TargetLoweringBase::getDefaultSafeStackPointerLocation(IRBuilder<> &IRB,
1798 bool UseTLS) const {
1799 // compiler-rt provides a variable with a magic name. Targets that do not
1800 // link with compiler-rt may also provide such a variable.
1801 Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1802 const char *UnsafeStackPtrVar = "__safestack_unsafe_stack_ptr";
1803 auto UnsafeStackPtr =
1804 dyn_cast_or_null<GlobalVariable>(M->getNamedValue(UnsafeStackPtrVar));
1806 Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1808 if (!UnsafeStackPtr) {
1809 auto TLSModel = UseTLS ?
1810 GlobalValue::InitialExecTLSModel :
1811 GlobalValue::NotThreadLocal;
1812 // The global variable is not defined yet, define it ourselves.
1813 // We use the initial-exec TLS model because we do not support the
1814 // variable living anywhere other than in the main executable.
1815 UnsafeStackPtr = new GlobalVariable(
1816 *M, StackPtrTy, false, GlobalValue::ExternalLinkage, nullptr,
1817 UnsafeStackPtrVar, nullptr, TLSModel);
1819 // The variable exists, check its type and attributes.
1820 if (UnsafeStackPtr->getValueType() != StackPtrTy)
1821 report_fatal_error(Twine(UnsafeStackPtrVar) + " must have void* type");
1822 if (UseTLS != UnsafeStackPtr->isThreadLocal())
1823 report_fatal_error(Twine(UnsafeStackPtrVar) + " must " +
1824 (UseTLS ? "" : "not ") + "be thread-local");
1826 return UnsafeStackPtr;
1829 Value *TargetLoweringBase::getSafeStackPointerLocation(IRBuilder<> &IRB) const {
1830 if (!TM.getTargetTriple().isAndroid())
1831 return getDefaultSafeStackPointerLocation(IRB, true);
1833 // Android provides a libc function to retrieve the address of the current
1834 // thread's unsafe stack pointer.
1835 Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1836 Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1837 Value *Fn = M->getOrInsertFunction("__safestack_pointer_address",
1838 StackPtrTy->getPointerTo(0));
1839 return IRB.CreateCall(Fn);
1842 //===----------------------------------------------------------------------===//
1843 // Loop Strength Reduction hooks
1844 //===----------------------------------------------------------------------===//
1846 /// isLegalAddressingMode - Return true if the addressing mode represented
1847 /// by AM is legal for this target, for a load/store of the specified type.
1848 bool TargetLoweringBase::isLegalAddressingMode(const DataLayout &DL,
1849 const AddrMode &AM, Type *Ty,
1850 unsigned AS) const {
1851 // The default implementation of this implements a conservative RISCy, r+r and
1854 // Allows a sign-extended 16-bit immediate field.
1855 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1858 // No global is ever allowed as a base.
1862 // Only support r+r,
1864 case 0: // "r+i" or just "i", depending on HasBaseReg.
1867 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1869 // Otherwise we have r+r or r+i.
1872 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
1874 // Allow 2*r as r+r.
1876 default: // Don't allow n * r
1883 //===----------------------------------------------------------------------===//
1885 //===----------------------------------------------------------------------===//
1887 // For OpenBSD return its special guard variable. Otherwise return nullptr,
1888 // so that SelectionDAG handle SSP.
1889 Value *TargetLoweringBase::getIRStackGuard(IRBuilder<> &IRB) const {
1890 if (getTargetMachine().getTargetTriple().isOSOpenBSD()) {
1891 Module &M = *IRB.GetInsertBlock()->getParent()->getParent();
1892 PointerType *PtrTy = Type::getInt8PtrTy(M.getContext());
1893 return M.getOrInsertGlobal("__guard_local", PtrTy);
1898 // Currently only support "standard" __stack_chk_guard.
1899 // TODO: add LOAD_STACK_GUARD support.
1900 void TargetLoweringBase::insertSSPDeclarations(Module &M) const {
1901 M.getOrInsertGlobal("__stack_chk_guard", Type::getInt8PtrTy(M.getContext()));
1904 // Currently only support "standard" __stack_chk_guard.
1905 // TODO: add LOAD_STACK_GUARD support.
1906 Value *TargetLoweringBase::getSDagStackGuard(const Module &M) const {
1907 return M.getGlobalVariable("__stack_chk_guard", true);
1910 Value *TargetLoweringBase::getSSPStackGuardCheck(const Module &M) const {
1914 unsigned TargetLoweringBase::getMinimumJumpTableEntries() const {
1915 return MinimumJumpTableEntries;
1918 void TargetLoweringBase::setMinimumJumpTableEntries(unsigned Val) {
1919 MinimumJumpTableEntries = Val;
1922 unsigned TargetLoweringBase::getMinimumJumpTableDensity(bool OptForSize) const {
1923 return OptForSize ? OptsizeJumpTableDensity : JumpTableDensity;
1926 unsigned TargetLoweringBase::getMaximumJumpTableSize() const {
1927 return MaximumJumpTableSize;
1930 void TargetLoweringBase::setMaximumJumpTableSize(unsigned Val) {
1931 MaximumJumpTableSize = Val;
1934 //===----------------------------------------------------------------------===//
1935 // Reciprocal Estimates
1936 //===----------------------------------------------------------------------===//
1938 /// Get the reciprocal estimate attribute string for a function that will
1939 /// override the target defaults.
1940 static StringRef getRecipEstimateForFunc(MachineFunction &MF) {
1941 const Function *F = MF.getFunction();
1942 return F->getFnAttribute("reciprocal-estimates").getValueAsString();
1945 /// Construct a string for the given reciprocal operation of the given type.
1946 /// This string should match the corresponding option to the front-end's
1947 /// "-mrecip" flag assuming those strings have been passed through in an
1948 /// attribute string. For example, "vec-divf" for a division of a vXf32.
1949 static std::string getReciprocalOpName(bool IsSqrt, EVT VT) {
1950 std::string Name = VT.isVector() ? "vec-" : "";
1952 Name += IsSqrt ? "sqrt" : "div";
1954 // TODO: Handle "half" or other float types?
1955 if (VT.getScalarType() == MVT::f64) {
1958 assert(VT.getScalarType() == MVT::f32 &&
1959 "Unexpected FP type for reciprocal estimate");
1966 /// Return the character position and value (a single numeric character) of a
1967 /// customized refinement operation in the input string if it exists. Return
1968 /// false if there is no customized refinement step count.
1969 static bool parseRefinementStep(StringRef In, size_t &Position,
1971 const char RefStepToken = ':';
1972 Position = In.find(RefStepToken);
1973 if (Position == StringRef::npos)
1976 StringRef RefStepString = In.substr(Position + 1);
1977 // Allow exactly one numeric character for the additional refinement
1979 if (RefStepString.size() == 1) {
1980 char RefStepChar = RefStepString[0];
1981 if (RefStepChar >= '0' && RefStepChar <= '9') {
1982 Value = RefStepChar - '0';
1986 report_fatal_error("Invalid refinement step for -recip.");
1989 /// For the input attribute string, return one of the ReciprocalEstimate enum
1990 /// status values (enabled, disabled, or not specified) for this operation on
1991 /// the specified data type.
1992 static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override) {
1993 if (Override.empty())
1994 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1996 SmallVector<StringRef, 4> OverrideVector;
1997 SplitString(Override, OverrideVector, ",");
1998 unsigned NumArgs = OverrideVector.size();
2000 // Check if "all", "none", or "default" was specified.
2002 // Look for an optional setting of the number of refinement steps needed
2003 // for this type of reciprocal operation.
2006 if (parseRefinementStep(Override, RefPos, RefSteps)) {
2007 // Split the string for further processing.
2008 Override = Override.substr(0, RefPos);
2011 // All reciprocal types are enabled.
2012 if (Override == "all")
2013 return TargetLoweringBase::ReciprocalEstimate::Enabled;
2015 // All reciprocal types are disabled.
2016 if (Override == "none")
2017 return TargetLoweringBase::ReciprocalEstimate::Disabled;
2019 // Target defaults for enablement are used.
2020 if (Override == "default")
2021 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2024 // The attribute string may omit the size suffix ('f'/'d').
2025 std::string VTName = getReciprocalOpName(IsSqrt, VT);
2026 std::string VTNameNoSize = VTName;
2027 VTNameNoSize.pop_back();
2028 static const char DisabledPrefix = '!';
2030 for (StringRef RecipType : OverrideVector) {
2033 if (parseRefinementStep(RecipType, RefPos, RefSteps))
2034 RecipType = RecipType.substr(0, RefPos);
2036 // Ignore the disablement token for string matching.
2037 bool IsDisabled = RecipType[0] == DisabledPrefix;
2039 RecipType = RecipType.substr(1);
2041 if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
2042 return IsDisabled ? TargetLoweringBase::ReciprocalEstimate::Disabled
2043 : TargetLoweringBase::ReciprocalEstimate::Enabled;
2046 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2049 /// For the input attribute string, return the customized refinement step count
2050 /// for this operation on the specified data type. If the step count does not
2051 /// exist, return the ReciprocalEstimate enum value for unspecified.
2052 static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override) {
2053 if (Override.empty())
2054 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2056 SmallVector<StringRef, 4> OverrideVector;
2057 SplitString(Override, OverrideVector, ",");
2058 unsigned NumArgs = OverrideVector.size();
2060 // Check if "all", "default", or "none" was specified.
2062 // Look for an optional setting of the number of refinement steps needed
2063 // for this type of reciprocal operation.
2066 if (!parseRefinementStep(Override, RefPos, RefSteps))
2067 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2069 // Split the string for further processing.
2070 Override = Override.substr(0, RefPos);
2071 assert(Override != "none" &&
2072 "Disabled reciprocals, but specifed refinement steps?");
2074 // If this is a general override, return the specified number of steps.
2075 if (Override == "all" || Override == "default")
2079 // The attribute string may omit the size suffix ('f'/'d').
2080 std::string VTName = getReciprocalOpName(IsSqrt, VT);
2081 std::string VTNameNoSize = VTName;
2082 VTNameNoSize.pop_back();
2084 for (StringRef RecipType : OverrideVector) {
2087 if (!parseRefinementStep(RecipType, RefPos, RefSteps))
2090 RecipType = RecipType.substr(0, RefPos);
2091 if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
2095 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2098 int TargetLoweringBase::getRecipEstimateSqrtEnabled(EVT VT,
2099 MachineFunction &MF) const {
2100 return getOpEnabled(true, VT, getRecipEstimateForFunc(MF));
2103 int TargetLoweringBase::getRecipEstimateDivEnabled(EVT VT,
2104 MachineFunction &MF) const {
2105 return getOpEnabled(false, VT, getRecipEstimateForFunc(MF));
2108 int TargetLoweringBase::getSqrtRefinementSteps(EVT VT,
2109 MachineFunction &MF) const {
2110 return getOpRefinementSteps(true, VT, getRecipEstimateForFunc(MF));
2113 int TargetLoweringBase::getDivRefinementSteps(EVT VT,
2114 MachineFunction &MF) const {
2115 return getOpRefinementSteps(false, VT, getRecipEstimateForFunc(MF));
2118 void TargetLoweringBase::finalizeLowering(MachineFunction &MF) const {
2119 MF.getRegInfo().freezeReservedRegs(MF);
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