1 //===- TargetPassConfig.cpp - Target independent code generation passes ---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines interfaces to access the target independent code
11 // generation passes provided by the LLVM backend.
13 //===---------------------------------------------------------------------===//
15 #include "llvm/CodeGen/TargetPassConfig.h"
16 #include "llvm/ADT/DenseMap.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/StringRef.h"
19 #include "llvm/Analysis/BasicAliasAnalysis.h"
20 #include "llvm/Analysis/CFLAndersAliasAnalysis.h"
21 #include "llvm/Analysis/CFLSteensAliasAnalysis.h"
22 #include "llvm/Analysis/CallGraphSCCPass.h"
23 #include "llvm/Analysis/ScopedNoAliasAA.h"
24 #include "llvm/Analysis/TargetTransformInfo.h"
25 #include "llvm/Analysis/TypeBasedAliasAnalysis.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/CodeGen/MachinePassRegistry.h"
28 #include "llvm/CodeGen/Passes.h"
29 #include "llvm/CodeGen/RegAllocRegistry.h"
30 #include "llvm/IR/IRPrintingPasses.h"
31 #include "llvm/IR/LegacyPassManager.h"
32 #include "llvm/IR/Verifier.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCTargetOptions.h"
35 #include "llvm/Pass.h"
36 #include "llvm/Support/CodeGen.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/Compiler.h"
39 #include "llvm/Support/Debug.h"
40 #include "llvm/Support/ErrorHandling.h"
41 #include "llvm/Support/Threading.h"
42 #include "llvm/Target/TargetMachine.h"
43 #include "llvm/Transforms/Scalar.h"
44 #include "llvm/Transforms/Utils/SymbolRewriter.h"
50 cl::opt<bool> EnableIPRA("enable-ipra", cl::init(false), cl::Hidden,
51 cl::desc("Enable interprocedural register allocation "
52 "to reduce load/store at procedure calls."));
53 static cl::opt<bool> DisablePostRASched("disable-post-ra", cl::Hidden,
54 cl::desc("Disable Post Regalloc Scheduler"));
55 static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
56 cl::desc("Disable branch folding"));
57 static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
58 cl::desc("Disable tail duplication"));
59 static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
60 cl::desc("Disable pre-register allocation tail duplication"));
61 static cl::opt<bool> DisableBlockPlacement("disable-block-placement",
62 cl::Hidden, cl::desc("Disable probability-driven block placement"));
63 static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
64 cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
65 static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
66 cl::desc("Disable Stack Slot Coloring"));
67 static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
68 cl::desc("Disable Machine Dead Code Elimination"));
69 static cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden,
70 cl::desc("Disable Early If-conversion"));
71 static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
72 cl::desc("Disable Machine LICM"));
73 static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
74 cl::desc("Disable Machine Common Subexpression Elimination"));
75 static cl::opt<cl::boolOrDefault> OptimizeRegAlloc(
76 "optimize-regalloc", cl::Hidden,
77 cl::desc("Enable optimized register allocation compilation path."));
78 static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
80 cl::desc("Disable Machine LICM"));
81 static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
82 cl::desc("Disable Machine Sinking"));
83 static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
84 cl::desc("Disable Loop Strength Reduction Pass"));
85 static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting",
86 cl::Hidden, cl::desc("Disable ConstantHoisting"));
87 static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
88 cl::desc("Disable Codegen Prepare"));
89 static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
90 cl::desc("Disable Copy Propagation pass"));
91 static cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inlining",
92 cl::Hidden, cl::desc("Disable Partial Libcall Inlining"));
93 static cl::opt<bool> EnableImplicitNullChecks(
94 "enable-implicit-null-checks",
95 cl::desc("Fold null checks into faulting memory operations"),
96 cl::init(false), cl::Hidden);
98 EnableMergeICmps("enable-mergeicmps",
99 cl::desc("Merge ICmp chains into a single memcmp"),
100 cl::init(false), cl::Hidden);
101 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
102 cl::desc("Print LLVM IR produced by the loop-reduce pass"));
103 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
104 cl::desc("Print LLVM IR input to isel pass"));
105 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
106 cl::desc("Dump garbage collector data"));
107 static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
108 cl::desc("Verify generated machine code"),
111 static cl::opt<bool> EnableMachineOutliner("enable-machine-outliner",
113 cl::desc("Enable machine outliner"));
114 static cl::opt<bool> EnableLinkOnceODROutlining(
115 "enable-linkonceodr-outlining",
117 cl::desc("Enable the machine outliner on linkonceodr functions"),
119 // Enable or disable FastISel. Both options are needed, because
120 // FastISel is enabled by default with -fast, and we wish to be
121 // able to enable or disable fast-isel independently from -O0.
122 static cl::opt<cl::boolOrDefault>
123 EnableFastISelOption("fast-isel", cl::Hidden,
124 cl::desc("Enable the \"fast\" instruction selector"));
126 static cl::opt<cl::boolOrDefault>
127 EnableGlobalISel("global-isel", cl::Hidden,
128 cl::desc("Enable the \"global\" instruction selector"));
130 static cl::opt<std::string> PrintMachineInstrs(
131 "print-machineinstrs", cl::ValueOptional, cl::desc("Print machine instrs"),
132 cl::value_desc("pass-name"), cl::init("option-unspecified"), cl::Hidden);
134 static cl::opt<int> EnableGlobalISelAbort(
135 "global-isel-abort", cl::Hidden,
136 cl::desc("Enable abort calls when \"global\" instruction selection "
137 "fails to lower/select an instruction: 0 disable the abort, "
138 "1 enable the abort, and "
139 "2 disable the abort but emit a diagnostic on failure"),
142 // Temporary option to allow experimenting with MachineScheduler as a post-RA
143 // scheduler. Targets can "properly" enable this with
144 // substitutePass(&PostRASchedulerID, &PostMachineSchedulerID).
145 // Targets can return true in targetSchedulesPostRAScheduling() and
146 // insert a PostRA scheduling pass wherever it wants.
147 cl::opt<bool> MISchedPostRA("misched-postra", cl::Hidden,
148 cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"));
150 // Experimental option to run live interval analysis early.
151 static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden,
152 cl::desc("Run live interval analysis earlier in the pipeline"));
154 // Experimental option to use CFL-AA in codegen
155 enum class CFLAAType { None, Steensgaard, Andersen, Both };
156 static cl::opt<CFLAAType> UseCFLAA(
157 "use-cfl-aa-in-codegen", cl::init(CFLAAType::None), cl::Hidden,
158 cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"),
159 cl::values(clEnumValN(CFLAAType::None, "none", "Disable CFL-AA"),
160 clEnumValN(CFLAAType::Steensgaard, "steens",
161 "Enable unification-based CFL-AA"),
162 clEnumValN(CFLAAType::Andersen, "anders",
163 "Enable inclusion-based CFL-AA"),
164 clEnumValN(CFLAAType::Both, "both",
165 "Enable both variants of CFL-AA")));
167 /// Option names for limiting the codegen pipeline.
168 /// Those are used in error reporting and we didn't want
169 /// to duplicate their names all over the place.
170 const char *StartAfterOptName = "start-after";
171 const char *StartBeforeOptName = "start-before";
172 const char *StopAfterOptName = "stop-after";
173 const char *StopBeforeOptName = "stop-before";
175 static cl::opt<std::string>
176 StartAfterOpt(StringRef(StartAfterOptName),
177 cl::desc("Resume compilation after a specific pass"),
178 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
180 static cl::opt<std::string>
181 StartBeforeOpt(StringRef(StartBeforeOptName),
182 cl::desc("Resume compilation before a specific pass"),
183 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
185 static cl::opt<std::string>
186 StopAfterOpt(StringRef(StopAfterOptName),
187 cl::desc("Stop compilation after a specific pass"),
188 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
190 static cl::opt<std::string>
191 StopBeforeOpt(StringRef(StopBeforeOptName),
192 cl::desc("Stop compilation before a specific pass"),
193 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
195 /// Allow standard passes to be disabled by command line options. This supports
196 /// simple binary flags that either suppress the pass or do nothing.
197 /// i.e. -disable-mypass=false has no effect.
198 /// These should be converted to boolOrDefault in order to use applyOverride.
199 static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID,
202 return IdentifyingPassPtr();
206 /// Allow standard passes to be disabled by the command line, regardless of who
207 /// is adding the pass.
209 /// StandardID is the pass identified in the standard pass pipeline and provided
210 /// to addPass(). It may be a target-specific ID in the case that the target
211 /// directly adds its own pass, but in that case we harmlessly fall through.
213 /// TargetID is the pass that the target has configured to override StandardID.
215 /// StandardID may be a pseudo ID. In that case TargetID is the name of the real
216 /// pass to run. This allows multiple options to control a single pass depending
217 /// on where in the pipeline that pass is added.
218 static IdentifyingPassPtr overridePass(AnalysisID StandardID,
219 IdentifyingPassPtr TargetID) {
220 if (StandardID == &PostRASchedulerID)
221 return applyDisable(TargetID, DisablePostRASched);
223 if (StandardID == &BranchFolderPassID)
224 return applyDisable(TargetID, DisableBranchFold);
226 if (StandardID == &TailDuplicateID)
227 return applyDisable(TargetID, DisableTailDuplicate);
229 if (StandardID == &TargetPassConfig::EarlyTailDuplicateID)
230 return applyDisable(TargetID, DisableEarlyTailDup);
232 if (StandardID == &MachineBlockPlacementID)
233 return applyDisable(TargetID, DisableBlockPlacement);
235 if (StandardID == &StackSlotColoringID)
236 return applyDisable(TargetID, DisableSSC);
238 if (StandardID == &DeadMachineInstructionElimID)
239 return applyDisable(TargetID, DisableMachineDCE);
241 if (StandardID == &EarlyIfConverterID)
242 return applyDisable(TargetID, DisableEarlyIfConversion);
244 if (StandardID == &MachineLICMID)
245 return applyDisable(TargetID, DisableMachineLICM);
247 if (StandardID == &MachineCSEID)
248 return applyDisable(TargetID, DisableMachineCSE);
250 if (StandardID == &TargetPassConfig::PostRAMachineLICMID)
251 return applyDisable(TargetID, DisablePostRAMachineLICM);
253 if (StandardID == &MachineSinkingID)
254 return applyDisable(TargetID, DisableMachineSink);
256 if (StandardID == &MachineCopyPropagationID)
257 return applyDisable(TargetID, DisableCopyProp);
262 //===---------------------------------------------------------------------===//
264 //===---------------------------------------------------------------------===//
266 INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",
267 "Target Pass Configuration", false, false)
268 char TargetPassConfig::ID = 0;
271 char TargetPassConfig::EarlyTailDuplicateID = 0;
272 char TargetPassConfig::PostRAMachineLICMID = 0;
276 struct InsertedPass {
277 AnalysisID TargetPassID;
278 IdentifyingPassPtr InsertedPassID;
282 InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID,
283 bool VerifyAfter, bool PrintAfter)
284 : TargetPassID(TargetPassID), InsertedPassID(InsertedPassID),
285 VerifyAfter(VerifyAfter), PrintAfter(PrintAfter) {}
287 Pass *getInsertedPass() const {
288 assert(InsertedPassID.isValid() && "Illegal Pass ID!");
289 if (InsertedPassID.isInstance())
290 return InsertedPassID.getInstance();
291 Pass *NP = Pass::createPass(InsertedPassID.getID());
292 assert(NP && "Pass ID not registered");
297 } // end anonymous namespace
301 class PassConfigImpl {
303 // List of passes explicitly substituted by this target. Normally this is
304 // empty, but it is a convenient way to suppress or replace specific passes
305 // that are part of a standard pass pipeline without overridding the entire
306 // pipeline. This mechanism allows target options to inherit a standard pass's
307 // user interface. For example, a target may disable a standard pass by
308 // default by substituting a pass ID of zero, and the user may still enable
309 // that standard pass with an explicit command line option.
310 DenseMap<AnalysisID,IdentifyingPassPtr> TargetPasses;
312 /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
313 /// is inserted after each instance of the first one.
314 SmallVector<InsertedPass, 4> InsertedPasses;
317 } // end namespace llvm
319 // Out of line virtual method.
320 TargetPassConfig::~TargetPassConfig() {
324 static const PassInfo *getPassInfo(StringRef PassName) {
325 if (PassName.empty())
328 const PassRegistry &PR = *PassRegistry::getPassRegistry();
329 const PassInfo *PI = PR.getPassInfo(PassName);
331 report_fatal_error(Twine('\"') + Twine(PassName) +
332 Twine("\" pass is not registered."));
336 static AnalysisID getPassIDFromName(StringRef PassName) {
337 const PassInfo *PI = getPassInfo(PassName);
338 return PI ? PI->getTypeInfo() : nullptr;
341 void TargetPassConfig::setStartStopPasses() {
342 StartBefore = getPassIDFromName(StartBeforeOpt);
343 StartAfter = getPassIDFromName(StartAfterOpt);
344 StopBefore = getPassIDFromName(StopBeforeOpt);
345 StopAfter = getPassIDFromName(StopAfterOpt);
346 if (StartBefore && StartAfter)
347 report_fatal_error(Twine(StartBeforeOptName) + Twine(" and ") +
348 Twine(StartAfterOptName) + Twine(" specified!"));
349 if (StopBefore && StopAfter)
350 report_fatal_error(Twine(StopBeforeOptName) + Twine(" and ") +
351 Twine(StopAfterOptName) + Twine(" specified!"));
352 Started = (StartAfter == nullptr) && (StartBefore == nullptr);
355 // Out of line constructor provides default values for pass options and
356 // registers all common codegen passes.
357 TargetPassConfig::TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm)
358 : ImmutablePass(ID), PM(&pm), TM(&TM) {
359 Impl = new PassConfigImpl();
361 // Register all target independent codegen passes to activate their PassIDs,
362 // including this pass itself.
363 initializeCodeGen(*PassRegistry::getPassRegistry());
365 // Also register alias analysis passes required by codegen passes.
366 initializeBasicAAWrapperPassPass(*PassRegistry::getPassRegistry());
367 initializeAAResultsWrapperPassPass(*PassRegistry::getPassRegistry());
369 // Substitute Pseudo Pass IDs for real ones.
370 substitutePass(&EarlyTailDuplicateID, &TailDuplicateID);
371 substitutePass(&PostRAMachineLICMID, &MachineLICMID);
373 if (StringRef(PrintMachineInstrs.getValue()).equals(""))
374 TM.Options.PrintMachineCode = true;
376 if (EnableIPRA.getNumOccurrences())
377 TM.Options.EnableIPRA = EnableIPRA;
379 // If not explicitly specified, use target default.
380 TM.Options.EnableIPRA = TM.useIPRA();
383 if (TM.Options.EnableIPRA)
384 setRequiresCodeGenSCCOrder();
386 setStartStopPasses();
389 CodeGenOpt::Level TargetPassConfig::getOptLevel() const {
390 return TM->getOptLevel();
393 /// Insert InsertedPassID pass after TargetPassID.
394 void TargetPassConfig::insertPass(AnalysisID TargetPassID,
395 IdentifyingPassPtr InsertedPassID,
396 bool VerifyAfter, bool PrintAfter) {
397 assert(((!InsertedPassID.isInstance() &&
398 TargetPassID != InsertedPassID.getID()) ||
399 (InsertedPassID.isInstance() &&
400 TargetPassID != InsertedPassID.getInstance()->getPassID())) &&
401 "Insert a pass after itself!");
402 Impl->InsertedPasses.emplace_back(TargetPassID, InsertedPassID, VerifyAfter,
406 /// createPassConfig - Create a pass configuration object to be used by
407 /// addPassToEmitX methods for generating a pipeline of CodeGen passes.
409 /// Targets may override this to extend TargetPassConfig.
410 TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) {
411 return new TargetPassConfig(*this, PM);
414 TargetPassConfig::TargetPassConfig()
415 : ImmutablePass(ID) {
416 report_fatal_error("Trying to construct TargetPassConfig without a target "
417 "machine. Scheduling a CodeGen pass without a target "
421 bool TargetPassConfig::hasLimitedCodeGenPipeline() const {
422 return StartBefore || StartAfter || StopBefore || StopAfter;
426 TargetPassConfig::getLimitedCodeGenPipelineReason(const char *Separator) const {
427 if (!hasLimitedCodeGenPipeline())
428 return std::string();
430 static cl::opt<std::string> *PassNames[] = {&StartAfterOpt, &StartBeforeOpt,
431 &StopAfterOpt, &StopBeforeOpt};
432 static const char *OptNames[] = {StartAfterOptName, StartBeforeOptName,
433 StopAfterOptName, StopBeforeOptName};
435 for (int Idx = 0; Idx < 4; ++Idx)
436 if (!PassNames[Idx]->empty()) {
440 Res += OptNames[Idx];
445 // Helper to verify the analysis is really immutable.
446 void TargetPassConfig::setOpt(bool &Opt, bool Val) {
447 assert(!Initialized && "PassConfig is immutable");
451 void TargetPassConfig::substitutePass(AnalysisID StandardID,
452 IdentifyingPassPtr TargetID) {
453 Impl->TargetPasses[StandardID] = TargetID;
456 IdentifyingPassPtr TargetPassConfig::getPassSubstitution(AnalysisID ID) const {
457 DenseMap<AnalysisID, IdentifyingPassPtr>::const_iterator
458 I = Impl->TargetPasses.find(ID);
459 if (I == Impl->TargetPasses.end())
464 bool TargetPassConfig::isPassSubstitutedOrOverridden(AnalysisID ID) const {
465 IdentifyingPassPtr TargetID = getPassSubstitution(ID);
466 IdentifyingPassPtr FinalPtr = overridePass(ID, TargetID);
467 return !FinalPtr.isValid() || FinalPtr.isInstance() ||
468 FinalPtr.getID() != ID;
471 /// Add a pass to the PassManager if that pass is supposed to be run. If the
472 /// Started/Stopped flags indicate either that the compilation should start at
473 /// a later pass or that it should stop after an earlier pass, then do not add
474 /// the pass. Finally, compare the current pass against the StartAfter
475 /// and StopAfter options and change the Started/Stopped flags accordingly.
476 void TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) {
477 assert(!Initialized && "PassConfig is immutable");
479 // Cache the Pass ID here in case the pass manager finds this pass is
480 // redundant with ones already scheduled / available, and deletes it.
481 // Fundamentally, once we add the pass to the manager, we no longer own it
482 // and shouldn't reference it.
483 AnalysisID PassID = P->getPassID();
485 if (StartBefore == PassID)
487 if (StopBefore == PassID)
489 if (Started && !Stopped) {
491 // Construct banner message before PM->add() as that may delete the pass.
492 if (AddingMachinePasses && (printAfter || verifyAfter))
493 Banner = std::string("After ") + std::string(P->getPassName());
495 if (AddingMachinePasses) {
497 addPrintPass(Banner);
499 addVerifyPass(Banner);
502 // Add the passes after the pass P if there is any.
503 for (auto IP : Impl->InsertedPasses) {
504 if (IP.TargetPassID == PassID)
505 addPass(IP.getInsertedPass(), IP.VerifyAfter, IP.PrintAfter);
510 if (StopAfter == PassID)
512 if (StartAfter == PassID)
514 if (Stopped && !Started)
515 report_fatal_error("Cannot stop compilation after pass that is not run");
518 /// Add a CodeGen pass at this point in the pipeline after checking for target
519 /// and command line overrides.
521 /// addPass cannot return a pointer to the pass instance because is internal the
522 /// PassManager and the instance we create here may already be freed.
523 AnalysisID TargetPassConfig::addPass(AnalysisID PassID, bool verifyAfter,
525 IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
526 IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
527 if (!FinalPtr.isValid())
531 if (FinalPtr.isInstance())
532 P = FinalPtr.getInstance();
534 P = Pass::createPass(FinalPtr.getID());
536 llvm_unreachable("Pass ID not registered");
538 AnalysisID FinalID = P->getPassID();
539 addPass(P, verifyAfter, printAfter); // Ends the lifetime of P.
544 void TargetPassConfig::printAndVerify(const std::string &Banner) {
545 addPrintPass(Banner);
546 addVerifyPass(Banner);
549 void TargetPassConfig::addPrintPass(const std::string &Banner) {
550 if (TM->shouldPrintMachineCode())
551 PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
554 void TargetPassConfig::addVerifyPass(const std::string &Banner) {
555 bool Verify = VerifyMachineCode;
556 #ifdef EXPENSIVE_CHECKS
557 if (VerifyMachineCode == cl::BOU_UNSET)
558 Verify = TM->isMachineVerifierClean();
561 PM->add(createMachineVerifierPass(Banner));
564 /// Add common target configurable passes that perform LLVM IR to IR transforms
565 /// following machine independent optimization.
566 void TargetPassConfig::addIRPasses() {
568 case CFLAAType::Steensgaard:
569 addPass(createCFLSteensAAWrapperPass());
571 case CFLAAType::Andersen:
572 addPass(createCFLAndersAAWrapperPass());
574 case CFLAAType::Both:
575 addPass(createCFLAndersAAWrapperPass());
576 addPass(createCFLSteensAAWrapperPass());
582 // Basic AliasAnalysis support.
583 // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
584 // BasicAliasAnalysis wins if they disagree. This is intended to help
585 // support "obvious" type-punning idioms.
586 addPass(createTypeBasedAAWrapperPass());
587 addPass(createScopedNoAliasAAWrapperPass());
588 addPass(createBasicAAWrapperPass());
590 // Before running any passes, run the verifier to determine if the input
591 // coming from the front-end and/or optimizer is valid.
593 addPass(createVerifierPass());
595 // Run loop strength reduction before anything else.
596 if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
597 addPass(createLoopStrengthReducePass());
599 addPass(createPrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n"));
602 if (getOptLevel() != CodeGenOpt::None) {
603 // The MergeICmpsPass tries to create memcmp calls by grouping sequences of
604 // loads and compares. ExpandMemCmpPass then tries to expand those calls
605 // into optimally-sized loads and compares. The transforms are enabled by a
606 // target lowering hook.
607 if (EnableMergeICmps)
608 addPass(createMergeICmpsPass());
609 addPass(createExpandMemCmpPass());
612 // Run GC lowering passes for builtin collectors
613 // TODO: add a pass insertion point here
614 addPass(createGCLoweringPass());
615 addPass(createShadowStackGCLoweringPass());
617 // Make sure that no unreachable blocks are instruction selected.
618 addPass(createUnreachableBlockEliminationPass());
620 // Prepare expensive constants for SelectionDAG.
621 if (getOptLevel() != CodeGenOpt::None && !DisableConstantHoisting)
622 addPass(createConstantHoistingPass());
624 if (getOptLevel() != CodeGenOpt::None && !DisablePartialLibcallInlining)
625 addPass(createPartiallyInlineLibCallsPass());
627 // Instrument function entry and exit, e.g. with calls to mcount().
628 addPass(createPostInlineEntryExitInstrumenterPass());
630 // Add scalarization of target's unsupported masked memory intrinsics pass.
631 // the unsupported intrinsic will be replaced with a chain of basic blocks,
632 // that stores/loads element one-by-one if the appropriate mask bit is set.
633 addPass(createScalarizeMaskedMemIntrinPass());
635 // Expand reduction intrinsics into shuffle sequences if the target wants to.
636 addPass(createExpandReductionsPass());
639 /// Turn exception handling constructs into something the code generators can
641 void TargetPassConfig::addPassesToHandleExceptions() {
642 const MCAsmInfo *MCAI = TM->getMCAsmInfo();
643 assert(MCAI && "No MCAsmInfo");
644 switch (MCAI->getExceptionHandlingType()) {
645 case ExceptionHandling::SjLj:
646 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
647 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
648 // catch info can get misplaced when a selector ends up more than one block
649 // removed from the parent invoke(s). This could happen when a landing
650 // pad is shared by multiple invokes and is also a target of a normal
651 // edge from elsewhere.
652 addPass(createSjLjEHPreparePass());
654 case ExceptionHandling::DwarfCFI:
655 case ExceptionHandling::ARM:
656 addPass(createDwarfEHPass());
658 case ExceptionHandling::WinEH:
659 // We support using both GCC-style and MSVC-style exceptions on Windows, so
660 // add both preparation passes. Each pass will only actually run if it
661 // recognizes the personality function.
662 addPass(createWinEHPass());
663 addPass(createDwarfEHPass());
665 case ExceptionHandling::None:
666 addPass(createLowerInvokePass());
668 // The lower invoke pass may create unreachable code. Remove it.
669 addPass(createUnreachableBlockEliminationPass());
674 /// Add pass to prepare the LLVM IR for code generation. This should be done
675 /// before exception handling preparation passes.
676 void TargetPassConfig::addCodeGenPrepare() {
677 if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
678 addPass(createCodeGenPreparePass());
679 addPass(createRewriteSymbolsPass());
682 /// Add common passes that perform LLVM IR to IR transforms in preparation for
683 /// instruction selection.
684 void TargetPassConfig::addISelPrepare() {
687 // Force codegen to run according to the callgraph.
688 if (requiresCodeGenSCCOrder())
689 addPass(new DummyCGSCCPass);
691 // Add both the safe stack and the stack protection passes: each of them will
692 // only protect functions that have corresponding attributes.
693 addPass(createSafeStackPass());
694 addPass(createStackProtectorPass());
697 addPass(createPrintFunctionPass(
698 dbgs(), "\n\n*** Final LLVM Code input to ISel ***\n"));
700 // All passes which modify the LLVM IR are now complete; run the verifier
701 // to ensure that the IR is valid.
703 addPass(createVerifierPass());
706 bool TargetPassConfig::addCoreISelPasses() {
707 // Enable FastISel with -fast, but allow that to be overridden.
708 TM->setO0WantsFastISel(EnableFastISelOption != cl::BOU_FALSE);
709 if (EnableFastISelOption == cl::BOU_TRUE ||
710 (TM->getOptLevel() == CodeGenOpt::None && TM->getO0WantsFastISel()))
711 TM->setFastISel(true);
713 // Ask the target for an isel.
714 // Enable GlobalISel if the target wants to, but allow that to be overriden.
715 // Explicitly enabling fast-isel should override implicitly enabled
717 if (EnableGlobalISel == cl::BOU_TRUE ||
718 (EnableGlobalISel == cl::BOU_UNSET && isGlobalISelEnabled() &&
719 EnableFastISelOption != cl::BOU_TRUE)) {
720 TM->setFastISel(false);
722 if (addIRTranslator())
725 addPreLegalizeMachineIR();
727 if (addLegalizeMachineIR())
730 // Before running the register bank selector, ask the target if it
731 // wants to run some passes.
732 addPreRegBankSelect();
734 if (addRegBankSelect())
737 addPreGlobalInstructionSelect();
739 if (addGlobalInstructionSelect())
742 // Pass to reset the MachineFunction if the ISel failed.
743 addPass(createResetMachineFunctionPass(
744 reportDiagnosticWhenGlobalISelFallback(), isGlobalISelAbortEnabled()));
746 // Provide a fallback path when we do not want to abort on
747 // not-yet-supported input.
748 if (!isGlobalISelAbortEnabled() && addInstSelector())
751 } else if (addInstSelector())
757 bool TargetPassConfig::addISelPasses() {
758 if (TM->Options.EmulatedTLS)
759 addPass(createLowerEmuTLSPass());
761 addPass(createPreISelIntrinsicLoweringPass());
762 addPass(createTargetTransformInfoWrapperPass(TM->getTargetIRAnalysis()));
765 addPassesToHandleExceptions();
768 return addCoreISelPasses();
771 /// -regalloc=... command line option.
772 static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
773 static cl::opt<RegisterRegAlloc::FunctionPassCtor, false,
774 RegisterPassParser<RegisterRegAlloc>>
775 RegAlloc("regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator),
776 cl::desc("Register allocator to use"));
778 /// Add the complete set of target-independent postISel code generator passes.
780 /// This can be read as the standard order of major LLVM CodeGen stages. Stages
781 /// with nontrivial configuration or multiple passes are broken out below in
782 /// add%Stage routines.
784 /// Any TargetPassConfig::addXX routine may be overriden by the Target. The
785 /// addPre/Post methods with empty header implementations allow injecting
786 /// target-specific fixups just before or after major stages. Additionally,
787 /// targets have the flexibility to change pass order within a stage by
788 /// overriding default implementation of add%Stage routines below. Each
789 /// technique has maintainability tradeoffs because alternate pass orders are
790 /// not well supported. addPre/Post works better if the target pass is easily
791 /// tied to a common pass. But if it has subtle dependencies on multiple passes,
792 /// the target should override the stage instead.
794 /// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
795 /// before/after any target-independent pass. But it's currently overkill.
796 void TargetPassConfig::addMachinePasses() {
797 AddingMachinePasses = true;
799 // Insert a machine instr printer pass after the specified pass.
800 if (!StringRef(PrintMachineInstrs.getValue()).equals("") &&
801 !StringRef(PrintMachineInstrs.getValue()).equals("option-unspecified")) {
802 const PassRegistry *PR = PassRegistry::getPassRegistry();
803 const PassInfo *TPI = PR->getPassInfo(PrintMachineInstrs.getValue());
804 const PassInfo *IPI = PR->getPassInfo(StringRef("machineinstr-printer"));
805 assert (TPI && IPI && "Pass ID not registered!");
806 const char *TID = (const char *)(TPI->getTypeInfo());
807 const char *IID = (const char *)(IPI->getTypeInfo());
808 insertPass(TID, IID);
811 // Print the instruction selected machine code...
812 printAndVerify("After Instruction Selection");
814 // Expand pseudo-instructions emitted by ISel.
815 addPass(&ExpandISelPseudosID);
817 // Add passes that optimize machine instructions in SSA form.
818 if (getOptLevel() != CodeGenOpt::None) {
819 addMachineSSAOptimization();
821 // If the target requests it, assign local variables to stack slots relative
822 // to one another and simplify frame index references where possible.
823 addPass(&LocalStackSlotAllocationID, false);
826 if (TM->Options.EnableIPRA)
827 addPass(createRegUsageInfoPropPass());
829 // Run pre-ra passes.
832 // Run register allocation and passes that are tightly coupled with it,
833 // including phi elimination and scheduling.
834 if (getOptimizeRegAlloc())
835 addOptimizedRegAlloc(createRegAllocPass(true));
837 if (RegAlloc != &useDefaultRegisterAllocator &&
838 RegAlloc != &createFastRegisterAllocator)
839 report_fatal_error("Must use fast (default) register allocator for unoptimized regalloc.");
840 addFastRegAlloc(createRegAllocPass(false));
843 // Run post-ra passes.
846 // Insert prolog/epilog code. Eliminate abstract frame index references...
847 if (getOptLevel() != CodeGenOpt::None)
848 addPass(&ShrinkWrapID);
850 // Prolog/Epilog inserter needs a TargetMachine to instantiate. But only
851 // do so if it hasn't been disabled, substituted, or overridden.
852 if (!isPassSubstitutedOrOverridden(&PrologEpilogCodeInserterID))
853 addPass(createPrologEpilogInserterPass());
855 /// Add passes that optimize machine instructions after register allocation.
856 if (getOptLevel() != CodeGenOpt::None)
857 addMachineLateOptimization();
859 // Expand pseudo instructions before second scheduling pass.
860 addPass(&ExpandPostRAPseudosID);
862 // Run pre-sched2 passes.
865 if (EnableImplicitNullChecks)
866 addPass(&ImplicitNullChecksID);
868 // Second pass scheduler.
869 // Let Target optionally insert this pass by itself at some other
871 if (getOptLevel() != CodeGenOpt::None &&
872 !TM->targetSchedulesPostRAScheduling()) {
874 addPass(&PostMachineSchedulerID);
876 addPass(&PostRASchedulerID);
882 addPass(createGCInfoPrinter(dbgs()), false, false);
885 // Basic block placement.
886 if (getOptLevel() != CodeGenOpt::None)
891 if (TM->Options.EnableIPRA)
892 // Collect register usage information and produce a register mask of
893 // clobbered registers, to be used to optimize call sites.
894 addPass(createRegUsageInfoCollector());
896 addPass(&FuncletLayoutID, false);
898 addPass(&StackMapLivenessID, false);
899 addPass(&LiveDebugValuesID, false);
901 // Insert before XRay Instrumentation.
902 addPass(&FEntryInserterID, false);
904 addPass(&XRayInstrumentationID, false);
905 addPass(&PatchableFunctionID, false);
907 if (EnableMachineOutliner)
908 PM->add(createMachineOutlinerPass(EnableLinkOnceODROutlining));
910 // Add passes that directly emit MI after all other MI passes.
913 AddingMachinePasses = false;
916 /// Add passes that optimize machine instructions in SSA form.
917 void TargetPassConfig::addMachineSSAOptimization() {
918 // Pre-ra tail duplication.
919 addPass(&EarlyTailDuplicateID);
921 // Optimize PHIs before DCE: removing dead PHI cycles may make more
922 // instructions dead.
923 addPass(&OptimizePHIsID, false);
925 // This pass merges large allocas. StackSlotColoring is a different pass
926 // which merges spill slots.
927 addPass(&StackColoringID, false);
929 // If the target requests it, assign local variables to stack slots relative
930 // to one another and simplify frame index references where possible.
931 addPass(&LocalStackSlotAllocationID, false);
933 // With optimization, dead code should already be eliminated. However
934 // there is one known exception: lowered code for arguments that are only
935 // used by tail calls, where the tail calls reuse the incoming stack
936 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
937 addPass(&DeadMachineInstructionElimID);
939 // Allow targets to insert passes that improve instruction level parallelism,
940 // like if-conversion. Such passes will typically need dominator trees and
941 // loop info, just like LICM and CSE below.
944 addPass(&MachineLICMID, false);
945 addPass(&MachineCSEID, false);
947 addPass(&MachineSinkingID);
949 addPass(&PeepholeOptimizerID);
950 // Clean-up the dead code that may have been generated by peephole
952 addPass(&DeadMachineInstructionElimID);
955 //===---------------------------------------------------------------------===//
956 /// Register Allocation Pass Configuration
957 //===---------------------------------------------------------------------===//
959 bool TargetPassConfig::getOptimizeRegAlloc() const {
960 switch (OptimizeRegAlloc) {
961 case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
962 case cl::BOU_TRUE: return true;
963 case cl::BOU_FALSE: return false;
965 llvm_unreachable("Invalid optimize-regalloc state");
968 /// RegisterRegAlloc's global Registry tracks allocator registration.
969 MachinePassRegistry RegisterRegAlloc::Registry;
971 /// A dummy default pass factory indicates whether the register allocator is
972 /// overridden on the command line.
973 static llvm::once_flag InitializeDefaultRegisterAllocatorFlag;
975 static RegisterRegAlloc
976 defaultRegAlloc("default",
977 "pick register allocator based on -O option",
978 useDefaultRegisterAllocator);
980 static void initializeDefaultRegisterAllocatorOnce() {
981 RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
985 RegisterRegAlloc::setDefault(RegAlloc);
989 /// Instantiate the default register allocator pass for this target for either
990 /// the optimized or unoptimized allocation path. This will be added to the pass
991 /// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
992 /// in the optimized case.
994 /// A target that uses the standard regalloc pass order for fast or optimized
995 /// allocation may still override this for per-target regalloc
996 /// selection. But -regalloc=... always takes precedence.
997 FunctionPass *TargetPassConfig::createTargetRegisterAllocator(bool Optimized) {
999 return createGreedyRegisterAllocator();
1001 return createFastRegisterAllocator();
1004 /// Find and instantiate the register allocation pass requested by this target
1005 /// at the current optimization level. Different register allocators are
1006 /// defined as separate passes because they may require different analysis.
1008 /// This helper ensures that the regalloc= option is always available,
1009 /// even for targets that override the default allocator.
1011 /// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs,
1012 /// this can be folded into addPass.
1013 FunctionPass *TargetPassConfig::createRegAllocPass(bool Optimized) {
1014 // Initialize the global default.
1015 llvm::call_once(InitializeDefaultRegisterAllocatorFlag,
1016 initializeDefaultRegisterAllocatorOnce);
1018 RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
1019 if (Ctor != useDefaultRegisterAllocator)
1022 // With no -regalloc= override, ask the target for a regalloc pass.
1023 return createTargetRegisterAllocator(Optimized);
1026 /// Return true if the default global register allocator is in use and
1027 /// has not be overriden on the command line with '-regalloc=...'
1028 bool TargetPassConfig::usingDefaultRegAlloc() const {
1029 return RegAlloc.getNumOccurrences() == 0;
1032 /// Add the minimum set of target-independent passes that are required for
1033 /// register allocation. No coalescing or scheduling.
1034 void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
1035 addPass(&PHIEliminationID, false);
1036 addPass(&TwoAddressInstructionPassID, false);
1039 addPass(RegAllocPass);
1042 /// Add standard target-independent passes that are tightly coupled with
1043 /// optimized register allocation, including coalescing, machine instruction
1044 /// scheduling, and register allocation itself.
1045 void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
1046 addPass(&DetectDeadLanesID, false);
1048 addPass(&ProcessImplicitDefsID, false);
1050 // LiveVariables currently requires pure SSA form.
1052 // FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
1053 // LiveVariables can be removed completely, and LiveIntervals can be directly
1054 // computed. (We still either need to regenerate kill flags after regalloc, or
1055 // preferably fix the scavenger to not depend on them).
1056 addPass(&LiveVariablesID, false);
1058 // Edge splitting is smarter with machine loop info.
1059 addPass(&MachineLoopInfoID, false);
1060 addPass(&PHIEliminationID, false);
1062 // Eventually, we want to run LiveIntervals before PHI elimination.
1063 if (EarlyLiveIntervals)
1064 addPass(&LiveIntervalsID, false);
1066 addPass(&TwoAddressInstructionPassID, false);
1067 addPass(&RegisterCoalescerID);
1069 // The machine scheduler may accidentally create disconnected components
1070 // when moving subregister definitions around, avoid this by splitting them to
1071 // separate vregs before. Splitting can also improve reg. allocation quality.
1072 addPass(&RenameIndependentSubregsID);
1074 // PreRA instruction scheduling.
1075 addPass(&MachineSchedulerID);
1078 // Add the selected register allocation pass.
1079 addPass(RegAllocPass);
1081 // Allow targets to change the register assignments before rewriting.
1084 // Finally rewrite virtual registers.
1085 addPass(&VirtRegRewriterID);
1087 // Perform stack slot coloring and post-ra machine LICM.
1089 // FIXME: Re-enable coloring with register when it's capable of adding
1091 addPass(&StackSlotColoringID);
1093 // Run post-ra machine LICM to hoist reloads / remats.
1095 // FIXME: can this move into MachineLateOptimization?
1096 addPass(&PostRAMachineLICMID);
1100 //===---------------------------------------------------------------------===//
1101 /// Post RegAlloc Pass Configuration
1102 //===---------------------------------------------------------------------===//
1104 /// Add passes that optimize machine instructions after register allocation.
1105 void TargetPassConfig::addMachineLateOptimization() {
1106 // Branch folding must be run after regalloc and prolog/epilog insertion.
1107 addPass(&BranchFolderPassID);
1109 // Tail duplication.
1110 // Note that duplicating tail just increases code size and degrades
1111 // performance for targets that require Structured Control Flow.
1112 // In addition it can also make CFG irreducible. Thus we disable it.
1113 if (!TM->requiresStructuredCFG())
1114 addPass(&TailDuplicateID);
1116 // Copy propagation.
1117 addPass(&MachineCopyPropagationID);
1120 /// Add standard GC passes.
1121 bool TargetPassConfig::addGCPasses() {
1122 addPass(&GCMachineCodeAnalysisID, false);
1126 /// Add standard basic block placement passes.
1127 void TargetPassConfig::addBlockPlacement() {
1128 if (addPass(&MachineBlockPlacementID)) {
1129 // Run a separate pass to collect block placement statistics.
1130 if (EnableBlockPlacementStats)
1131 addPass(&MachineBlockPlacementStatsID);
1135 //===---------------------------------------------------------------------===//
1136 /// GlobalISel Configuration
1137 //===---------------------------------------------------------------------===//
1139 bool TargetPassConfig::isGlobalISelEnabled() const {
1143 bool TargetPassConfig::isGlobalISelAbortEnabled() const {
1144 if (EnableGlobalISelAbort.getNumOccurrences() > 0)
1145 return EnableGlobalISelAbort == 1;
1147 // When no abort behaviour is specified, we don't abort if the target says
1148 // that GISel is enabled.
1149 return !isGlobalISelEnabled();
1152 bool TargetPassConfig::reportDiagnosticWhenGlobalISelFallback() const {
1153 return EnableGlobalISelAbort == 2;