1 //===- llvm/Target/TargetSchedule.cpp - Sched Machine Model ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a wrapper around MCSchedModel that allows the interface
11 // to benefit from information currently only available in TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
15 #include "llvm/CodeGen/TargetSchedule.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/MachineInstr.h"
18 #include "llvm/CodeGen/MachineOperand.h"
19 #include "llvm/CodeGen/TargetInstrInfo.h"
20 #include "llvm/CodeGen/TargetRegisterInfo.h"
21 #include "llvm/CodeGen/TargetSubtargetInfo.h"
22 #include "llvm/MC/MCInstrDesc.h"
23 #include "llvm/MC/MCInstrItineraries.h"
24 #include "llvm/MC/MCSchedule.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/raw_ostream.h"
34 static cl::opt<bool> EnableSchedModel("schedmodel", cl::Hidden, cl::init(true),
35 cl::desc("Use TargetSchedModel for latency lookup"));
37 static cl::opt<bool> EnableSchedItins("scheditins", cl::Hidden, cl::init(true),
38 cl::desc("Use InstrItineraryData for latency lookup"));
40 bool TargetSchedModel::hasInstrSchedModel() const {
41 return EnableSchedModel && SchedModel.hasInstrSchedModel();
44 bool TargetSchedModel::hasInstrItineraries() const {
45 return EnableSchedItins && !InstrItins.isEmpty();
48 static unsigned gcd(unsigned Dividend, unsigned Divisor) {
49 // Dividend and Divisor will be naturally swapped as needed.
51 unsigned Rem = Dividend % Divisor;
58 static unsigned lcm(unsigned A, unsigned B) {
59 unsigned LCM = (uint64_t(A) * B) / gcd(A, B);
60 assert((LCM >= A && LCM >= B) && "LCM overflow");
64 void TargetSchedModel::init(const TargetSubtargetInfo *TSInfo) {
66 SchedModel = TSInfo->getSchedModel();
67 TII = TSInfo->getInstrInfo();
68 STI->initInstrItins(InstrItins);
70 unsigned NumRes = SchedModel.getNumProcResourceKinds();
71 ResourceFactors.resize(NumRes);
72 ResourceLCM = SchedModel.IssueWidth;
73 for (unsigned Idx = 0; Idx < NumRes; ++Idx) {
74 unsigned NumUnits = SchedModel.getProcResource(Idx)->NumUnits;
76 ResourceLCM = lcm(ResourceLCM, NumUnits);
78 MicroOpFactor = ResourceLCM / SchedModel.IssueWidth;
79 for (unsigned Idx = 0; Idx < NumRes; ++Idx) {
80 unsigned NumUnits = SchedModel.getProcResource(Idx)->NumUnits;
81 ResourceFactors[Idx] = NumUnits ? (ResourceLCM / NumUnits) : 0;
85 /// Returns true only if instruction is specified as single issue.
86 bool TargetSchedModel::mustBeginGroup(const MachineInstr *MI,
87 const MCSchedClassDesc *SC) const {
88 if (hasInstrSchedModel()) {
90 SC = resolveSchedClass(MI);
92 return SC->BeginGroup;
97 bool TargetSchedModel::mustEndGroup(const MachineInstr *MI,
98 const MCSchedClassDesc *SC) const {
99 if (hasInstrSchedModel()) {
101 SC = resolveSchedClass(MI);
108 unsigned TargetSchedModel::getNumMicroOps(const MachineInstr *MI,
109 const MCSchedClassDesc *SC) const {
110 if (hasInstrItineraries()) {
111 int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass());
112 return (UOps >= 0) ? UOps : TII->getNumMicroOps(&InstrItins, *MI);
114 if (hasInstrSchedModel()) {
116 SC = resolveSchedClass(MI);
118 return SC->NumMicroOps;
120 return MI->isTransient() ? 0 : 1;
123 // The machine model may explicitly specify an invalid latency, which
124 // effectively means infinite latency. Since users of the TargetSchedule API
125 // don't know how to handle this, we convert it to a very large latency that is
126 // easy to distinguish when debugging the DAG but won't induce overflow.
127 static unsigned capLatency(int Cycles) {
128 return Cycles >= 0 ? Cycles : 1000;
131 /// Return the MCSchedClassDesc for this instruction. Some SchedClasses require
132 /// evaluation of predicates that depend on instruction operands or flags.
133 const MCSchedClassDesc *TargetSchedModel::
134 resolveSchedClass(const MachineInstr *MI) const {
135 // Get the definition's scheduling class descriptor from this machine model.
136 unsigned SchedClass = MI->getDesc().getSchedClass();
137 const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass);
138 if (!SCDesc->isValid())
144 while (SCDesc->isVariant()) {
145 assert(++NIter < 6 && "Variants are nested deeper than the magic number");
147 SchedClass = STI->resolveSchedClass(SchedClass, MI, this);
148 SCDesc = SchedModel.getSchedClassDesc(SchedClass);
153 /// Find the def index of this operand. This index maps to the machine model and
154 /// is independent of use operands. Def operands may be reordered with uses or
155 /// merged with uses without affecting the def index (e.g. before/after
156 /// regalloc). However, an instruction's def operands must never be reordered
157 /// with respect to each other.
158 static unsigned findDefIdx(const MachineInstr *MI, unsigned DefOperIdx) {
160 for (unsigned i = 0; i != DefOperIdx; ++i) {
161 const MachineOperand &MO = MI->getOperand(i);
162 if (MO.isReg() && MO.isDef())
168 /// Find the use index of this operand. This is independent of the instruction's
171 /// Note that uses are not determined by the operand's isUse property, which
172 /// is simply the inverse of isDef. Here we consider any readsReg operand to be
173 /// a "use". The machine model allows an operand to be both a Def and Use.
174 static unsigned findUseIdx(const MachineInstr *MI, unsigned UseOperIdx) {
176 for (unsigned i = 0; i != UseOperIdx; ++i) {
177 const MachineOperand &MO = MI->getOperand(i);
178 if (MO.isReg() && MO.readsReg() && !MO.isDef())
184 // Top-level API for clients that know the operand indices.
185 unsigned TargetSchedModel::computeOperandLatency(
186 const MachineInstr *DefMI, unsigned DefOperIdx,
187 const MachineInstr *UseMI, unsigned UseOperIdx) const {
189 if (!hasInstrSchedModel() && !hasInstrItineraries())
190 return TII->defaultDefLatency(SchedModel, *DefMI);
192 if (hasInstrItineraries()) {
195 OperLatency = TII->getOperandLatency(&InstrItins, *DefMI, DefOperIdx,
199 unsigned DefClass = DefMI->getDesc().getSchedClass();
200 OperLatency = InstrItins.getOperandCycle(DefClass, DefOperIdx);
202 if (OperLatency >= 0)
205 // No operand latency was found.
206 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, *DefMI);
208 // Expected latency is the max of the stage latency and itinerary props.
209 // Rather than directly querying InstrItins stage latency, we call a TII
210 // hook to allow subtargets to specialize latency. This hook is only
211 // applicable to the InstrItins model. InstrSchedModel should model all
212 // special cases without TII hooks.
214 std::max(InstrLatency, TII->defaultDefLatency(SchedModel, *DefMI));
217 // hasInstrSchedModel()
218 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
219 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx);
220 if (DefIdx < SCDesc->NumWriteLatencyEntries) {
221 // Lookup the definition's write latency in SubtargetInfo.
222 const MCWriteLatencyEntry *WLEntry =
223 STI->getWriteLatencyEntry(SCDesc, DefIdx);
224 unsigned WriteID = WLEntry->WriteResourceID;
225 unsigned Latency = capLatency(WLEntry->Cycles);
229 // Lookup the use's latency adjustment in SubtargetInfo.
230 const MCSchedClassDesc *UseDesc = resolveSchedClass(UseMI);
231 if (UseDesc->NumReadAdvanceEntries == 0)
233 unsigned UseIdx = findUseIdx(UseMI, UseOperIdx);
234 int Advance = STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID);
235 if (Advance > 0 && (unsigned)Advance > Latency) // unsigned wrap
237 return Latency - Advance;
239 // If DefIdx does not exist in the model (e.g. implicit defs), then return
240 // unit latency (defaultDefLatency may be too conservative).
242 if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit()
243 && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef()
244 && SchedModel.isComplete()) {
245 errs() << "DefIdx " << DefIdx << " exceeds machine model writes for "
246 << *DefMI << " (Try with MCSchedModel.CompleteModel set to false)";
247 llvm_unreachable("incomplete machine model");
250 // FIXME: Automatically giving all implicit defs defaultDefLatency is
251 // undesirable. We should only do it for defs that are known to the MC
252 // desc like flags. Truly implicit defs should get 1 cycle latency.
253 return DefMI->isTransient() ? 0 : TII->defaultDefLatency(SchedModel, *DefMI);
257 TargetSchedModel::computeInstrLatency(const MCSchedClassDesc &SCDesc) const {
258 return capLatency(MCSchedModel::computeInstrLatency(*STI, SCDesc));
261 unsigned TargetSchedModel::computeInstrLatency(unsigned Opcode) const {
262 assert(hasInstrSchedModel() && "Only call this function with a SchedModel");
263 unsigned SCIdx = TII->get(Opcode).getSchedClass();
264 return capLatency(SchedModel.computeInstrLatency(*STI, SCIdx));
267 unsigned TargetSchedModel::computeInstrLatency(const MCInst &Inst) const {
268 if (hasInstrSchedModel())
269 return capLatency(SchedModel.computeInstrLatency(*STI, *TII, Inst));
270 return computeInstrLatency(Inst.getOpcode());
274 TargetSchedModel::computeInstrLatency(const MachineInstr *MI,
275 bool UseDefaultDefLatency) const {
276 // For the itinerary model, fall back to the old subtarget hook.
277 // Allow subtargets to compute Bundle latencies outside the machine model.
278 if (hasInstrItineraries() || MI->isBundle() ||
279 (!hasInstrSchedModel() && !UseDefaultDefLatency))
280 return TII->getInstrLatency(&InstrItins, *MI);
282 if (hasInstrSchedModel()) {
283 const MCSchedClassDesc *SCDesc = resolveSchedClass(MI);
284 if (SCDesc->isValid())
285 return computeInstrLatency(*SCDesc);
287 return TII->defaultDefLatency(SchedModel, *MI);
290 unsigned TargetSchedModel::
291 computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
292 const MachineInstr *DepMI) const {
293 if (!SchedModel.isOutOfOrder())
296 // Out-of-order processor can dispatch WAW dependencies in the same cycle.
298 // Treat predication as a data dependency for out-of-order cpus. In-order
299 // cpus do not need to treat predicated writes specially.
301 // TODO: The following hack exists because predication passes do not
302 // correctly append imp-use operands, and readsReg() strangely returns false
303 // for predicated defs.
304 unsigned Reg = DefMI->getOperand(DefOperIdx).getReg();
305 const MachineFunction &MF = *DefMI->getMF();
306 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
307 if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(*DepMI))
308 return computeInstrLatency(DefMI);
310 // If we have a per operand scheduling model, check if this def is writing
311 // an unbuffered resource. If so, it treated like an in-order cpu.
312 if (hasInstrSchedModel()) {
313 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
314 if (SCDesc->isValid()) {
315 for (const MCWriteProcResEntry *PRI = STI->getWriteProcResBegin(SCDesc),
316 *PRE = STI->getWriteProcResEnd(SCDesc); PRI != PRE; ++PRI) {
317 if (!SchedModel.getProcResource(PRI->ProcResourceIdx)->BufferSize)
326 TargetSchedModel::computeReciprocalThroughput(const MachineInstr *MI) const {
327 if (hasInstrItineraries()) {
328 unsigned SchedClass = MI->getDesc().getSchedClass();
329 return MCSchedModel::getReciprocalThroughput(SchedClass,
330 *getInstrItineraries());
333 if (hasInstrSchedModel())
334 return MCSchedModel::getReciprocalThroughput(*STI, *resolveSchedClass(MI));
340 TargetSchedModel::computeReciprocalThroughput(unsigned Opcode) const {
341 unsigned SchedClass = TII->get(Opcode).getSchedClass();
342 if (hasInstrItineraries())
343 return MCSchedModel::getReciprocalThroughput(SchedClass,
344 *getInstrItineraries());
345 if (hasInstrSchedModel()) {
346 const MCSchedClassDesc &SCDesc = *SchedModel.getSchedClassDesc(SchedClass);
347 if (SCDesc.isValid() && !SCDesc.isVariant())
348 return MCSchedModel::getReciprocalThroughput(*STI, SCDesc);
355 TargetSchedModel::computeReciprocalThroughput(const MCInst &MI) const {
356 if (hasInstrSchedModel())
357 return SchedModel.getReciprocalThroughput(*STI, *TII, MI);
358 return computeReciprocalThroughput(MI.getOpcode());