1 //===-- TargetSubtargetInfo.cpp - General Target Information ---------------==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// \file This file describes the general parts of a Subtarget.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/CodeGen/TargetSchedule.h"
16 #include "llvm/Support/raw_ostream.h"
17 #include "llvm/Target/TargetSubtargetInfo.h"
20 //---------------------------------------------------------------------------
21 // TargetSubtargetInfo Class
23 TargetSubtargetInfo::TargetSubtargetInfo(
24 const Triple &TT, StringRef CPU, StringRef FS,
25 ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD,
26 const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR,
27 const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
28 const InstrStage *IS, const unsigned *OC, const unsigned *FP)
29 : MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched, WPR, WL, RA, IS, OC, FP) {
32 TargetSubtargetInfo::~TargetSubtargetInfo() {}
34 bool TargetSubtargetInfo::enableAtomicExpand() const {
38 bool TargetSubtargetInfo::enableMachineScheduler() const {
42 bool TargetSubtargetInfo::enableJoinGlobalCopies() const {
43 return enableMachineScheduler();
46 bool TargetSubtargetInfo::enableRALocalReassignment(
47 CodeGenOpt::Level OptLevel) const {
51 bool TargetSubtargetInfo::enablePostRAScheduler() const {
52 return getSchedModel().PostRAScheduler;
55 bool TargetSubtargetInfo::useAA() const {
59 static std::string createSchedInfoStr(unsigned Latency,
60 Optional<double> RThroughput) {
61 static const char *SchedPrefix = " sched: [";
63 raw_string_ostream CS(Comment);
64 if (Latency > 0 && RThroughput.hasValue())
65 CS << SchedPrefix << Latency << format(":%2.2f", RThroughput.getValue())
68 CS << SchedPrefix << Latency << ":?]";
69 else if (RThroughput.hasValue())
70 CS << SchedPrefix << "?:" << RThroughput.getValue() << "]";
75 /// Returns string representation of scheduler comment
76 std::string TargetSubtargetInfo::getSchedInfoStr(const MachineInstr &MI) const {
77 if (MI.isPseudo() || MI.isTerminator())
79 // We don't cache TSchedModel because it depends on TargetInstrInfo
80 // that could be changed during the compilation
81 TargetSchedModel TSchedModel;
82 TSchedModel.init(getSchedModel(), this, getInstrInfo());
83 unsigned Latency = TSchedModel.computeInstrLatency(&MI);
84 Optional<double> RThroughput = TSchedModel.computeInstrRThroughput(&MI);
85 return createSchedInfoStr(Latency, RThroughput);
88 /// Returns string representation of scheduler comment
89 std::string TargetSubtargetInfo::getSchedInfoStr(MCInst const &MCI) const {
90 // We don't cache TSchedModel because it depends on TargetInstrInfo
91 // that could be changed during the compilation
92 TargetSchedModel TSchedModel;
93 TSchedModel.init(getSchedModel(), this, getInstrInfo());
94 if (!TSchedModel.hasInstrSchedModel())
96 unsigned Latency = TSchedModel.computeInstrLatency(MCI.getOpcode());
97 Optional<double> RThroughput =
98 TSchedModel.computeInstrRThroughput(MCI.getOpcode());
99 return createSchedInfoStr(Latency, RThroughput);