1 //===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TwoAddress instruction pass which is used
11 // by most register allocators. Two-Address instructions are rewritten
21 // Note that if a register allocator chooses to use this pass, that it
22 // has to be capable of handling the non-SSA nature of these rewritten
25 // It is also worth noting that the duplicate operand of the two
26 // address instruction is removed.
28 //===----------------------------------------------------------------------===//
30 #include "llvm/ADT/DenseMap.h"
31 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/Analysis/AliasAnalysis.h"
35 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
36 #include "llvm/CodeGen/LiveVariables.h"
37 #include "llvm/CodeGen/MachineFunctionPass.h"
38 #include "llvm/CodeGen/MachineInstr.h"
39 #include "llvm/CodeGen/MachineInstrBuilder.h"
40 #include "llvm/CodeGen/MachineRegisterInfo.h"
41 #include "llvm/CodeGen/Passes.h"
42 #include "llvm/IR/Function.h"
43 #include "llvm/MC/MCInstrItineraries.h"
44 #include "llvm/Support/CommandLine.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/ErrorHandling.h"
47 #include "llvm/Support/raw_ostream.h"
48 #include "llvm/Target/TargetInstrInfo.h"
49 #include "llvm/Target/TargetMachine.h"
50 #include "llvm/Target/TargetRegisterInfo.h"
51 #include "llvm/Target/TargetSubtargetInfo.h"
55 #define DEBUG_TYPE "twoaddrinstr"
57 STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions");
58 STATISTIC(NumCommuted , "Number of instructions commuted to coalesce");
59 STATISTIC(NumAggrCommuted , "Number of instructions aggressively commuted");
60 STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");
61 STATISTIC(Num3AddrSunk, "Number of 3-address instructions sunk");
62 STATISTIC(NumReSchedUps, "Number of instructions re-scheduled up");
63 STATISTIC(NumReSchedDowns, "Number of instructions re-scheduled down");
65 // Temporary flag to disable rescheduling.
67 EnableRescheduling("twoaddr-reschedule",
68 cl::desc("Coalesce copies by rescheduling (default=true)"),
69 cl::init(true), cl::Hidden);
72 class TwoAddressInstructionPass : public MachineFunctionPass {
74 const TargetInstrInfo *TII;
75 const TargetRegisterInfo *TRI;
76 const InstrItineraryData *InstrItins;
77 MachineRegisterInfo *MRI;
81 CodeGenOpt::Level OptLevel;
83 // The current basic block being processed.
84 MachineBasicBlock *MBB;
86 // Keep track the distance of a MI from the start of the current basic block.
87 DenseMap<MachineInstr*, unsigned> DistanceMap;
89 // Set of already processed instructions in the current block.
90 SmallPtrSet<MachineInstr*, 8> Processed;
92 // A map from virtual registers to physical registers which are likely targets
93 // to be coalesced to due to copies from physical registers to virtual
94 // registers. e.g. v1024 = move r0.
95 DenseMap<unsigned, unsigned> SrcRegMap;
97 // A map from virtual registers to physical registers which are likely targets
98 // to be coalesced to due to copies to physical registers from virtual
99 // registers. e.g. r1 = move v1024.
100 DenseMap<unsigned, unsigned> DstRegMap;
102 bool sink3AddrInstruction(MachineInstr *MI, unsigned Reg,
103 MachineBasicBlock::iterator OldPos);
105 bool isRevCopyChain(unsigned FromReg, unsigned ToReg, int Maxlen);
107 bool noUseAfterLastDef(unsigned Reg, unsigned Dist, unsigned &LastDef);
109 bool isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC,
110 MachineInstr *MI, unsigned Dist);
112 bool commuteInstruction(MachineInstr *MI, unsigned DstIdx,
113 unsigned RegBIdx, unsigned RegCIdx, unsigned Dist);
115 bool isProfitableToConv3Addr(unsigned RegA, unsigned RegB);
117 bool convertInstTo3Addr(MachineBasicBlock::iterator &mi,
118 MachineBasicBlock::iterator &nmi,
119 unsigned RegA, unsigned RegB, unsigned Dist);
121 bool isDefTooClose(unsigned Reg, unsigned Dist, MachineInstr *MI);
123 bool rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
124 MachineBasicBlock::iterator &nmi,
126 bool rescheduleKillAboveMI(MachineBasicBlock::iterator &mi,
127 MachineBasicBlock::iterator &nmi,
130 bool tryInstructionTransform(MachineBasicBlock::iterator &mi,
131 MachineBasicBlock::iterator &nmi,
132 unsigned SrcIdx, unsigned DstIdx,
133 unsigned Dist, bool shouldOnlyCommute);
135 bool tryInstructionCommute(MachineInstr *MI,
140 void scanUses(unsigned DstReg);
142 void processCopy(MachineInstr *MI);
144 typedef SmallVector<std::pair<unsigned, unsigned>, 4> TiedPairList;
145 typedef SmallDenseMap<unsigned, TiedPairList> TiedOperandMap;
146 bool collectTiedOperands(MachineInstr *MI, TiedOperandMap&);
147 void processTiedPairs(MachineInstr *MI, TiedPairList&, unsigned &Dist);
148 void eliminateRegSequence(MachineBasicBlock::iterator&);
151 static char ID; // Pass identification, replacement for typeid
152 TwoAddressInstructionPass() : MachineFunctionPass(ID) {
153 initializeTwoAddressInstructionPassPass(*PassRegistry::getPassRegistry());
156 void getAnalysisUsage(AnalysisUsage &AU) const override {
157 AU.setPreservesCFG();
158 AU.addRequired<AAResultsWrapperPass>();
159 AU.addUsedIfAvailable<LiveVariables>();
160 AU.addPreserved<LiveVariables>();
161 AU.addPreserved<SlotIndexes>();
162 AU.addPreserved<LiveIntervals>();
163 AU.addPreservedID(MachineLoopInfoID);
164 AU.addPreservedID(MachineDominatorsID);
165 MachineFunctionPass::getAnalysisUsage(AU);
168 /// Pass entry point.
169 bool runOnMachineFunction(MachineFunction&) override;
171 } // end anonymous namespace
173 char TwoAddressInstructionPass::ID = 0;
174 INITIALIZE_PASS_BEGIN(TwoAddressInstructionPass, "twoaddressinstruction",
175 "Two-Address instruction pass", false, false)
176 INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
177 INITIALIZE_PASS_END(TwoAddressInstructionPass, "twoaddressinstruction",
178 "Two-Address instruction pass", false, false)
180 char &llvm::TwoAddressInstructionPassID = TwoAddressInstructionPass::ID;
182 static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg, LiveIntervals *LIS);
184 /// A two-address instruction has been converted to a three-address instruction
185 /// to avoid clobbering a register. Try to sink it past the instruction that
186 /// would kill the above mentioned register to reduce register pressure.
187 bool TwoAddressInstructionPass::
188 sink3AddrInstruction(MachineInstr *MI, unsigned SavedReg,
189 MachineBasicBlock::iterator OldPos) {
190 // FIXME: Shouldn't we be trying to do this before we three-addressify the
191 // instruction? After this transformation is done, we no longer need
192 // the instruction to be in three-address form.
194 // Check if it's safe to move this instruction.
195 bool SeenStore = true; // Be conservative.
196 if (!MI->isSafeToMove(AA, SeenStore))
200 SmallSet<unsigned, 4> UseRegs;
202 for (const MachineOperand &MO : MI->operands()) {
205 unsigned MOReg = MO.getReg();
208 if (MO.isUse() && MOReg != SavedReg)
209 UseRegs.insert(MO.getReg());
213 // Don't try to move it if it implicitly defines a register.
216 // For now, don't move any instructions that define multiple registers.
218 DefReg = MO.getReg();
221 // Find the instruction that kills SavedReg.
222 MachineInstr *KillMI = nullptr;
224 LiveInterval &LI = LIS->getInterval(SavedReg);
225 assert(LI.end() != LI.begin() &&
226 "Reg should not have empty live interval.");
228 SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot();
229 LiveInterval::const_iterator I = LI.find(MBBEndIdx);
230 if (I != LI.end() && I->start < MBBEndIdx)
234 KillMI = LIS->getInstructionFromIndex(I->end);
237 for (MachineOperand &UseMO : MRI->use_nodbg_operands(SavedReg)) {
240 KillMI = UseMO.getParent();
245 // If we find the instruction that kills SavedReg, and it is in an
246 // appropriate location, we can try to sink the current instruction
248 if (!KillMI || KillMI->getParent() != MBB || KillMI == MI ||
249 MachineBasicBlock::iterator(KillMI) == OldPos || KillMI->isTerminator())
252 // If any of the definitions are used by another instruction between the
253 // position and the kill use, then it's not safe to sink it.
255 // FIXME: This can be sped up if there is an easy way to query whether an
256 // instruction is before or after another instruction. Then we can use
257 // MachineRegisterInfo def / use instead.
258 MachineOperand *KillMO = nullptr;
259 MachineBasicBlock::iterator KillPos = KillMI;
262 unsigned NumVisited = 0;
263 for (MachineInstr &OtherMI : llvm::make_range(std::next(OldPos), KillPos)) {
264 // DBG_VALUE cannot be counted against the limit.
265 if (OtherMI.isDebugValue())
267 if (NumVisited > 30) // FIXME: Arbitrary limit to reduce compile time cost.
270 for (unsigned i = 0, e = OtherMI.getNumOperands(); i != e; ++i) {
271 MachineOperand &MO = OtherMI.getOperand(i);
274 unsigned MOReg = MO.getReg();
280 if (MO.isKill() || (LIS && isPlainlyKilled(&OtherMI, MOReg, LIS))) {
281 if (&OtherMI == KillMI && MOReg == SavedReg)
282 // Save the operand that kills the register. We want to unset the kill
283 // marker if we can sink MI past it.
285 else if (UseRegs.count(MOReg))
286 // One of the uses is killed before the destination.
291 assert(KillMO && "Didn't find kill");
294 // Update kill and LV information.
295 KillMO->setIsKill(false);
296 KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI);
297 KillMO->setIsKill(true);
300 LV->replaceKillInstruction(SavedReg, *KillMI, *MI);
303 // Move instruction to its destination.
305 MBB->insert(KillPos, MI);
308 LIS->handleMove(*MI);
314 /// Return the MachineInstr* if it is the single def of the Reg in current BB.
315 static MachineInstr *getSingleDef(unsigned Reg, MachineBasicBlock *BB,
316 const MachineRegisterInfo *MRI) {
317 MachineInstr *Ret = nullptr;
318 for (MachineInstr &DefMI : MRI->def_instructions(Reg)) {
319 if (DefMI.getParent() != BB || DefMI.isDebugValue())
323 else if (Ret != &DefMI)
329 /// Check if there is a reversed copy chain from FromReg to ToReg:
330 /// %Tmp1 = copy %Tmp2;
331 /// %FromReg = copy %Tmp1;
332 /// %ToReg = add %FromReg ...
333 /// %Tmp2 = copy %ToReg;
334 /// MaxLen specifies the maximum length of the copy chain the func
335 /// can walk through.
336 bool TwoAddressInstructionPass::isRevCopyChain(unsigned FromReg, unsigned ToReg,
338 unsigned TmpReg = FromReg;
339 for (int i = 0; i < Maxlen; i++) {
340 MachineInstr *Def = getSingleDef(TmpReg, MBB, MRI);
341 if (!Def || !Def->isCopy())
344 TmpReg = Def->getOperand(1).getReg();
352 /// Return true if there are no intervening uses between the last instruction
353 /// in the MBB that defines the specified register and the two-address
354 /// instruction which is being processed. It also returns the last def location
356 bool TwoAddressInstructionPass::noUseAfterLastDef(unsigned Reg, unsigned Dist,
359 unsigned LastUse = Dist;
360 for (MachineOperand &MO : MRI->reg_operands(Reg)) {
361 MachineInstr *MI = MO.getParent();
362 if (MI->getParent() != MBB || MI->isDebugValue())
364 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
365 if (DI == DistanceMap.end())
367 if (MO.isUse() && DI->second < LastUse)
368 LastUse = DI->second;
369 if (MO.isDef() && DI->second > LastDef)
370 LastDef = DI->second;
373 return !(LastUse > LastDef && LastUse < Dist);
376 /// Return true if the specified MI is a copy instruction or an extract_subreg
377 /// instruction. It also returns the source and destination registers and
378 /// whether they are physical registers by reference.
379 static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII,
380 unsigned &SrcReg, unsigned &DstReg,
381 bool &IsSrcPhys, bool &IsDstPhys) {
385 DstReg = MI.getOperand(0).getReg();
386 SrcReg = MI.getOperand(1).getReg();
387 } else if (MI.isInsertSubreg() || MI.isSubregToReg()) {
388 DstReg = MI.getOperand(0).getReg();
389 SrcReg = MI.getOperand(2).getReg();
393 IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
394 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
398 /// Test if the given register value, which is used by the
399 /// given instruction, is killed by the given instruction.
400 static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg,
401 LiveIntervals *LIS) {
402 if (LIS && TargetRegisterInfo::isVirtualRegister(Reg) &&
403 !LIS->isNotInMIMap(*MI)) {
404 // FIXME: Sometimes tryInstructionTransform() will add instructions and
405 // test whether they can be folded before keeping them. In this case it
406 // sets a kill before recursively calling tryInstructionTransform() again.
407 // If there is no interval available, we assume that this instruction is
408 // one of those. A kill flag is manually inserted on the operand so the
409 // check below will handle it.
410 LiveInterval &LI = LIS->getInterval(Reg);
411 // This is to match the kill flag version where undefs don't have kill
413 if (!LI.hasAtLeastOneValue())
416 SlotIndex useIdx = LIS->getInstructionIndex(*MI);
417 LiveInterval::const_iterator I = LI.find(useIdx);
418 assert(I != LI.end() && "Reg must be live-in to use.");
419 return !I->end.isBlock() && SlotIndex::isSameInstr(I->end, useIdx);
422 return MI->killsRegister(Reg);
425 /// Test if the given register value, which is used by the given
426 /// instruction, is killed by the given instruction. This looks through
427 /// coalescable copies to see if the original value is potentially not killed.
429 /// For example, in this code:
431 /// %reg1034 = copy %reg1024
432 /// %reg1035 = copy %reg1025<kill>
433 /// %reg1036 = add %reg1034<kill>, %reg1035<kill>
435 /// %reg1034 is not considered to be killed, since it is copied from a
436 /// register which is not killed. Treating it as not killed lets the
437 /// normal heuristics commute the (two-address) add, which lets
438 /// coalescing eliminate the extra copy.
440 /// If allowFalsePositives is true then likely kills are treated as kills even
441 /// if it can't be proven that they are kills.
442 static bool isKilled(MachineInstr &MI, unsigned Reg,
443 const MachineRegisterInfo *MRI,
444 const TargetInstrInfo *TII,
446 bool allowFalsePositives) {
447 MachineInstr *DefMI = &MI;
449 // All uses of physical registers are likely to be kills.
450 if (TargetRegisterInfo::isPhysicalRegister(Reg) &&
451 (allowFalsePositives || MRI->hasOneUse(Reg)))
453 if (!isPlainlyKilled(DefMI, Reg, LIS))
455 if (TargetRegisterInfo::isPhysicalRegister(Reg))
457 MachineRegisterInfo::def_iterator Begin = MRI->def_begin(Reg);
458 // If there are multiple defs, we can't do a simple analysis, so just
459 // go with what the kill flag says.
460 if (std::next(Begin) != MRI->def_end())
462 DefMI = Begin->getParent();
463 bool IsSrcPhys, IsDstPhys;
464 unsigned SrcReg, DstReg;
465 // If the def is something other than a copy, then it isn't going to
466 // be coalesced, so follow the kill flag.
467 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
473 /// Return true if the specified MI uses the specified register as a two-address
474 /// use. If so, return the destination register by reference.
475 static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) {
476 for (unsigned i = 0, NumOps = MI.getNumOperands(); i != NumOps; ++i) {
477 const MachineOperand &MO = MI.getOperand(i);
478 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
481 if (MI.isRegTiedToDefOperand(i, &ti)) {
482 DstReg = MI.getOperand(ti).getReg();
489 /// Given a register, if has a single in-basic block use, return the use
490 /// instruction if it's a copy or a two-address use.
492 MachineInstr *findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB,
493 MachineRegisterInfo *MRI,
494 const TargetInstrInfo *TII,
496 unsigned &DstReg, bool &IsDstPhys) {
497 if (!MRI->hasOneNonDBGUse(Reg))
498 // None or more than one use.
500 MachineInstr &UseMI = *MRI->use_instr_nodbg_begin(Reg);
501 if (UseMI.getParent() != MBB)
505 if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) {
510 if (isTwoAddrUse(UseMI, Reg, DstReg)) {
511 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
517 /// Return the physical register the specified virtual register might be mapped
520 getMappedReg(unsigned Reg, DenseMap<unsigned, unsigned> &RegMap) {
521 while (TargetRegisterInfo::isVirtualRegister(Reg)) {
522 DenseMap<unsigned, unsigned>::iterator SI = RegMap.find(Reg);
523 if (SI == RegMap.end())
527 if (TargetRegisterInfo::isPhysicalRegister(Reg))
532 /// Return true if the two registers are equal or aliased.
534 regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) {
539 return TRI->regsOverlap(RegA, RegB);
542 // Returns true if Reg is equal or aliased to at least one register in Set.
543 static bool regOverlapsSet(const SmallVectorImpl<unsigned> &Set, unsigned Reg,
544 const TargetRegisterInfo *TRI) {
545 for (unsigned R : Set)
546 if (TRI->regsOverlap(R, Reg))
552 /// Return true if it's potentially profitable to commute the two-address
553 /// instruction that's being processed.
555 TwoAddressInstructionPass::
556 isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC,
557 MachineInstr *MI, unsigned Dist) {
558 if (OptLevel == CodeGenOpt::None)
561 // Determine if it's profitable to commute this two address instruction. In
562 // general, we want no uses between this instruction and the definition of
563 // the two-address register.
565 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
566 // %reg1029<def> = MOV8rr %reg1028
567 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
568 // insert => %reg1030<def> = MOV8rr %reg1028
569 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
570 // In this case, it might not be possible to coalesce the second MOV8rr
571 // instruction if the first one is coalesced. So it would be profitable to
573 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
574 // %reg1029<def> = MOV8rr %reg1028
575 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
576 // insert => %reg1030<def> = MOV8rr %reg1029
577 // %reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>
579 if (!isPlainlyKilled(MI, regC, LIS))
582 // Ok, we have something like:
583 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
584 // let's see if it's worth commuting it.
586 // Look for situations like this:
587 // %reg1024<def> = MOV r1
588 // %reg1025<def> = MOV r0
589 // %reg1026<def> = ADD %reg1024, %reg1025
591 // Commute the ADD to hopefully eliminate an otherwise unavoidable copy.
592 unsigned ToRegA = getMappedReg(regA, DstRegMap);
594 unsigned FromRegB = getMappedReg(regB, SrcRegMap);
595 unsigned FromRegC = getMappedReg(regC, SrcRegMap);
596 bool CompB = FromRegB && regsAreCompatible(FromRegB, ToRegA, TRI);
597 bool CompC = FromRegC && regsAreCompatible(FromRegC, ToRegA, TRI);
599 // Compute if any of the following are true:
600 // -RegB is not tied to a register and RegC is compatible with RegA.
601 // -RegB is tied to the wrong physical register, but RegC is.
602 // -RegB is tied to the wrong physical register, and RegC isn't tied.
603 if ((!FromRegB && CompC) || (FromRegB && !CompB && (!FromRegC || CompC)))
605 // Don't compute if any of the following are true:
606 // -RegC is not tied to a register and RegB is compatible with RegA.
607 // -RegC is tied to the wrong physical register, but RegB is.
608 // -RegC is tied to the wrong physical register, and RegB isn't tied.
609 if ((!FromRegC && CompB) || (FromRegC && !CompC && (!FromRegB || CompB)))
613 // If there is a use of regC between its last def (could be livein) and this
614 // instruction, then bail.
615 unsigned LastDefC = 0;
616 if (!noUseAfterLastDef(regC, Dist, LastDefC))
619 // If there is a use of regB between its last def (could be livein) and this
620 // instruction, then go ahead and make this transformation.
621 unsigned LastDefB = 0;
622 if (!noUseAfterLastDef(regB, Dist, LastDefB))
625 // Look for situation like this:
626 // %reg101 = MOV %reg100
628 // %reg103 = ADD %reg102, %reg101
630 // %reg100 = MOV %reg103
631 // If there is a reversed copy chain from reg101 to reg103, commute the ADD
632 // to eliminate an otherwise unavoidable copy.
634 // We can extend the logic further: If an pair of operands in an insn has
635 // been merged, the insn could be regarded as a virtual copy, and the virtual
636 // copy could also be used to construct a copy chain.
637 // To more generally minimize register copies, ideally the logic of two addr
638 // instruction pass should be integrated with register allocation pass where
639 // interference graph is available.
640 if (isRevCopyChain(regC, regA, 3))
643 if (isRevCopyChain(regB, regA, 3))
646 // Since there are no intervening uses for both registers, then commute
647 // if the def of regC is closer. Its live interval is shorter.
648 return LastDefB && LastDefC && LastDefC > LastDefB;
651 /// Commute a two-address instruction and update the basic block, distance map,
652 /// and live variables if needed. Return true if it is successful.
653 bool TwoAddressInstructionPass::commuteInstruction(MachineInstr *MI,
658 unsigned RegC = MI->getOperand(RegCIdx).getReg();
659 DEBUG(dbgs() << "2addr: COMMUTING : " << *MI);
660 MachineInstr *NewMI = TII->commuteInstruction(*MI, false, RegBIdx, RegCIdx);
662 if (NewMI == nullptr) {
663 DEBUG(dbgs() << "2addr: COMMUTING FAILED!\n");
667 DEBUG(dbgs() << "2addr: COMMUTED TO: " << *NewMI);
668 assert(NewMI == MI &&
669 "TargetInstrInfo::commuteInstruction() should not return a new "
670 "instruction unless it was requested.");
672 // Update source register map.
673 unsigned FromRegC = getMappedReg(RegC, SrcRegMap);
675 unsigned RegA = MI->getOperand(DstIdx).getReg();
676 SrcRegMap[RegA] = FromRegC;
682 /// Return true if it is profitable to convert the given 2-address instruction
683 /// to a 3-address one.
685 TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA,unsigned RegB){
686 // Look for situations like this:
687 // %reg1024<def> = MOV r1
688 // %reg1025<def> = MOV r0
689 // %reg1026<def> = ADD %reg1024, %reg1025
691 // Turn ADD into a 3-address instruction to avoid a copy.
692 unsigned FromRegB = getMappedReg(RegB, SrcRegMap);
695 unsigned ToRegA = getMappedReg(RegA, DstRegMap);
696 return (ToRegA && !regsAreCompatible(FromRegB, ToRegA, TRI));
699 /// Convert the specified two-address instruction into a three address one.
700 /// Return true if this transformation was successful.
702 TwoAddressInstructionPass::convertInstTo3Addr(MachineBasicBlock::iterator &mi,
703 MachineBasicBlock::iterator &nmi,
704 unsigned RegA, unsigned RegB,
706 // FIXME: Why does convertToThreeAddress() need an iterator reference?
707 MachineFunction::iterator MFI = MBB->getIterator();
708 MachineInstr *NewMI = TII->convertToThreeAddress(MFI, *mi, LV);
709 assert(MBB->getIterator() == MFI &&
710 "convertToThreeAddress changed iterator reference");
714 DEBUG(dbgs() << "2addr: CONVERTING 2-ADDR: " << *mi);
715 DEBUG(dbgs() << "2addr: TO 3-ADDR: " << *NewMI);
719 LIS->ReplaceMachineInstrInMaps(*mi, *NewMI);
721 if (NewMI->findRegisterUseOperand(RegB, false, TRI))
722 // FIXME: Temporary workaround. If the new instruction doesn't
723 // uses RegB, convertToThreeAddress must have created more
724 // then one instruction.
725 Sunk = sink3AddrInstruction(NewMI, RegB, mi);
727 MBB->erase(mi); // Nuke the old inst.
730 DistanceMap.insert(std::make_pair(NewMI, Dist));
735 // Update source and destination register maps.
736 SrcRegMap.erase(RegA);
737 DstRegMap.erase(RegB);
741 /// Scan forward recursively for only uses, update maps if the use is a copy or
742 /// a two-address instruction.
744 TwoAddressInstructionPass::scanUses(unsigned DstReg) {
745 SmallVector<unsigned, 4> VirtRegPairs;
749 unsigned Reg = DstReg;
750 while (MachineInstr *UseMI = findOnlyInterestingUse(Reg, MBB, MRI, TII,IsCopy,
751 NewReg, IsDstPhys)) {
752 if (IsCopy && !Processed.insert(UseMI).second)
755 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
756 if (DI != DistanceMap.end())
757 // Earlier in the same MBB.Reached via a back edge.
761 VirtRegPairs.push_back(NewReg);
764 bool isNew = SrcRegMap.insert(std::make_pair(NewReg, Reg)).second;
766 assert(SrcRegMap[NewReg] == Reg && "Can't map to two src registers!");
767 VirtRegPairs.push_back(NewReg);
771 if (!VirtRegPairs.empty()) {
772 unsigned ToReg = VirtRegPairs.back();
773 VirtRegPairs.pop_back();
774 while (!VirtRegPairs.empty()) {
775 unsigned FromReg = VirtRegPairs.back();
776 VirtRegPairs.pop_back();
777 bool isNew = DstRegMap.insert(std::make_pair(FromReg, ToReg)).second;
779 assert(DstRegMap[FromReg] == ToReg &&"Can't map to two dst registers!");
782 bool isNew = DstRegMap.insert(std::make_pair(DstReg, ToReg)).second;
784 assert(DstRegMap[DstReg] == ToReg && "Can't map to two dst registers!");
788 /// If the specified instruction is not yet processed, process it if it's a
789 /// copy. For a copy instruction, we find the physical registers the
790 /// source and destination registers might be mapped to. These are kept in
791 /// point-to maps used to determine future optimizations. e.g.
794 /// v1026 = add v1024, v1025
796 /// If 'add' is a two-address instruction, v1024, v1026 are both potentially
797 /// coalesced to r0 (from the input side). v1025 is mapped to r1. v1026 is
798 /// potentially joined with r1 on the output side. It's worthwhile to commute
799 /// 'add' to eliminate a copy.
800 void TwoAddressInstructionPass::processCopy(MachineInstr *MI) {
801 if (Processed.count(MI))
804 bool IsSrcPhys, IsDstPhys;
805 unsigned SrcReg, DstReg;
806 if (!isCopyToReg(*MI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
809 if (IsDstPhys && !IsSrcPhys)
810 DstRegMap.insert(std::make_pair(SrcReg, DstReg));
811 else if (!IsDstPhys && IsSrcPhys) {
812 bool isNew = SrcRegMap.insert(std::make_pair(DstReg, SrcReg)).second;
814 assert(SrcRegMap[DstReg] == SrcReg &&
815 "Can't map to two src physical registers!");
820 Processed.insert(MI);
823 /// If there is one more local instruction that reads 'Reg' and it kills 'Reg,
824 /// consider moving the instruction below the kill instruction in order to
825 /// eliminate the need for the copy.
826 bool TwoAddressInstructionPass::
827 rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
828 MachineBasicBlock::iterator &nmi,
830 // Bail immediately if we don't have LV or LIS available. We use them to find
831 // kills efficiently.
835 MachineInstr *MI = &*mi;
836 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
837 if (DI == DistanceMap.end())
838 // Must be created from unfolded load. Don't waste time trying this.
841 MachineInstr *KillMI = nullptr;
843 LiveInterval &LI = LIS->getInterval(Reg);
844 assert(LI.end() != LI.begin() &&
845 "Reg should not have empty live interval.");
847 SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot();
848 LiveInterval::const_iterator I = LI.find(MBBEndIdx);
849 if (I != LI.end() && I->start < MBBEndIdx)
853 KillMI = LIS->getInstructionFromIndex(I->end);
855 KillMI = LV->getVarInfo(Reg).findKill(MBB);
857 if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike())
858 // Don't mess with copies, they may be coalesced later.
861 if (KillMI->hasUnmodeledSideEffects() || KillMI->isCall() ||
862 KillMI->isBranch() || KillMI->isTerminator())
863 // Don't move pass calls, etc.
867 if (isTwoAddrUse(*KillMI, Reg, DstReg))
870 bool SeenStore = true;
871 if (!MI->isSafeToMove(AA, SeenStore))
874 if (TII->getInstrLatency(InstrItins, *MI) > 1)
875 // FIXME: Needs more sophisticated heuristics.
878 SmallVector<unsigned, 2> Uses;
879 SmallVector<unsigned, 2> Kills;
880 SmallVector<unsigned, 2> Defs;
881 for (const MachineOperand &MO : MI->operands()) {
884 unsigned MOReg = MO.getReg();
888 Defs.push_back(MOReg);
890 Uses.push_back(MOReg);
891 if (MOReg != Reg && (MO.isKill() ||
892 (LIS && isPlainlyKilled(MI, MOReg, LIS))))
893 Kills.push_back(MOReg);
897 // Move the copies connected to MI down as well.
898 MachineBasicBlock::iterator Begin = MI;
899 MachineBasicBlock::iterator AfterMI = std::next(Begin);
901 MachineBasicBlock::iterator End = AfterMI;
902 while (End->isCopy() &&
903 regOverlapsSet(Defs, End->getOperand(1).getReg(), TRI)) {
904 Defs.push_back(End->getOperand(0).getReg());
908 // Check if the reschedule will not break depedencies.
909 unsigned NumVisited = 0;
910 MachineBasicBlock::iterator KillPos = KillMI;
912 for (MachineInstr &OtherMI : llvm::make_range(End, KillPos)) {
913 // DBG_VALUE cannot be counted against the limit.
914 if (OtherMI.isDebugValue())
916 if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
919 if (OtherMI.hasUnmodeledSideEffects() || OtherMI.isCall() ||
920 OtherMI.isBranch() || OtherMI.isTerminator())
921 // Don't move pass calls, etc.
923 for (const MachineOperand &MO : OtherMI.operands()) {
926 unsigned MOReg = MO.getReg();
930 if (regOverlapsSet(Uses, MOReg, TRI))
931 // Physical register use would be clobbered.
933 if (!MO.isDead() && regOverlapsSet(Defs, MOReg, TRI))
934 // May clobber a physical register def.
935 // FIXME: This may be too conservative. It's ok if the instruction
936 // is sunken completely below the use.
939 if (regOverlapsSet(Defs, MOReg, TRI))
942 MO.isKill() || (LIS && isPlainlyKilled(&OtherMI, MOReg, LIS));
943 if (MOReg != Reg && ((isKill && regOverlapsSet(Uses, MOReg, TRI)) ||
944 regOverlapsSet(Kills, MOReg, TRI)))
945 // Don't want to extend other live ranges and update kills.
947 if (MOReg == Reg && !isKill)
948 // We can't schedule across a use of the register in question.
950 // Ensure that if this is register in question, its the kill we expect.
951 assert((MOReg != Reg || &OtherMI == KillMI) &&
952 "Found multiple kills of a register in a basic block");
957 // Move debug info as well.
958 while (Begin != MBB->begin() && std::prev(Begin)->isDebugValue())
962 MachineBasicBlock::iterator InsertPos = KillPos;
964 // We have to move the copies first so that the MBB is still well-formed
965 // when calling handleMove().
966 for (MachineBasicBlock::iterator MBBI = AfterMI; MBBI != End;) {
967 auto CopyMI = MBBI++;
968 MBB->splice(InsertPos, MBB, CopyMI);
969 LIS->handleMove(*CopyMI);
972 End = std::next(MachineBasicBlock::iterator(MI));
975 // Copies following MI may have been moved as well.
976 MBB->splice(InsertPos, MBB, Begin, End);
977 DistanceMap.erase(DI);
979 // Update live variables
981 LIS->handleMove(*MI);
983 LV->removeVirtualRegisterKilled(Reg, *KillMI);
984 LV->addVirtualRegisterKilled(Reg, *MI);
987 DEBUG(dbgs() << "\trescheduled below kill: " << *KillMI);
991 /// Return true if the re-scheduling will put the given instruction too close
992 /// to the defs of its register dependencies.
993 bool TwoAddressInstructionPass::isDefTooClose(unsigned Reg, unsigned Dist,
995 for (MachineInstr &DefMI : MRI->def_instructions(Reg)) {
996 if (DefMI.getParent() != MBB || DefMI.isCopy() || DefMI.isCopyLike())
999 return true; // MI is defining something KillMI uses
1000 DenseMap<MachineInstr*, unsigned>::iterator DDI = DistanceMap.find(&DefMI);
1001 if (DDI == DistanceMap.end())
1002 return true; // Below MI
1003 unsigned DefDist = DDI->second;
1004 assert(Dist > DefDist && "Visited def already?");
1005 if (TII->getInstrLatency(InstrItins, DefMI) > (Dist - DefDist))
1011 /// If there is one more local instruction that reads 'Reg' and it kills 'Reg,
1012 /// consider moving the kill instruction above the current two-address
1013 /// instruction in order to eliminate the need for the copy.
1014 bool TwoAddressInstructionPass::
1015 rescheduleKillAboveMI(MachineBasicBlock::iterator &mi,
1016 MachineBasicBlock::iterator &nmi,
1018 // Bail immediately if we don't have LV or LIS available. We use them to find
1019 // kills efficiently.
1023 MachineInstr *MI = &*mi;
1024 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
1025 if (DI == DistanceMap.end())
1026 // Must be created from unfolded load. Don't waste time trying this.
1029 MachineInstr *KillMI = nullptr;
1031 LiveInterval &LI = LIS->getInterval(Reg);
1032 assert(LI.end() != LI.begin() &&
1033 "Reg should not have empty live interval.");
1035 SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot();
1036 LiveInterval::const_iterator I = LI.find(MBBEndIdx);
1037 if (I != LI.end() && I->start < MBBEndIdx)
1041 KillMI = LIS->getInstructionFromIndex(I->end);
1043 KillMI = LV->getVarInfo(Reg).findKill(MBB);
1045 if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike())
1046 // Don't mess with copies, they may be coalesced later.
1050 if (isTwoAddrUse(*KillMI, Reg, DstReg))
1053 bool SeenStore = true;
1054 if (!KillMI->isSafeToMove(AA, SeenStore))
1057 SmallSet<unsigned, 2> Uses;
1058 SmallSet<unsigned, 2> Kills;
1059 SmallSet<unsigned, 2> Defs;
1060 SmallSet<unsigned, 2> LiveDefs;
1061 for (const MachineOperand &MO : KillMI->operands()) {
1064 unsigned MOReg = MO.getReg();
1068 if (isDefTooClose(MOReg, DI->second, MI))
1070 bool isKill = MO.isKill() || (LIS && isPlainlyKilled(KillMI, MOReg, LIS));
1071 if (MOReg == Reg && !isKill)
1074 if (isKill && MOReg != Reg)
1075 Kills.insert(MOReg);
1076 } else if (TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1079 LiveDefs.insert(MOReg);
1083 // Check if the reschedule will not break depedencies.
1084 unsigned NumVisited = 0;
1085 for (MachineInstr &OtherMI :
1086 llvm::make_range(mi, MachineBasicBlock::iterator(KillMI))) {
1087 // DBG_VALUE cannot be counted against the limit.
1088 if (OtherMI.isDebugValue())
1090 if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
1093 if (OtherMI.hasUnmodeledSideEffects() || OtherMI.isCall() ||
1094 OtherMI.isBranch() || OtherMI.isTerminator())
1095 // Don't move pass calls, etc.
1097 SmallVector<unsigned, 2> OtherDefs;
1098 for (const MachineOperand &MO : OtherMI.operands()) {
1101 unsigned MOReg = MO.getReg();
1105 if (Defs.count(MOReg))
1106 // Moving KillMI can clobber the physical register if the def has
1109 if (Kills.count(MOReg))
1110 // Don't want to extend other live ranges and update kills.
1112 if (&OtherMI != MI && MOReg == Reg &&
1113 !(MO.isKill() || (LIS && isPlainlyKilled(&OtherMI, MOReg, LIS))))
1114 // We can't schedule across a use of the register in question.
1117 OtherDefs.push_back(MOReg);
1121 for (unsigned i = 0, e = OtherDefs.size(); i != e; ++i) {
1122 unsigned MOReg = OtherDefs[i];
1123 if (Uses.count(MOReg))
1125 if (TargetRegisterInfo::isPhysicalRegister(MOReg) &&
1126 LiveDefs.count(MOReg))
1128 // Physical register def is seen.
1133 // Move the old kill above MI, don't forget to move debug info as well.
1134 MachineBasicBlock::iterator InsertPos = mi;
1135 while (InsertPos != MBB->begin() && std::prev(InsertPos)->isDebugValue())
1137 MachineBasicBlock::iterator From = KillMI;
1138 MachineBasicBlock::iterator To = std::next(From);
1139 while (std::prev(From)->isDebugValue())
1141 MBB->splice(InsertPos, MBB, From, To);
1143 nmi = std::prev(InsertPos); // Backtrack so we process the moved instr.
1144 DistanceMap.erase(DI);
1146 // Update live variables
1148 LIS->handleMove(*KillMI);
1150 LV->removeVirtualRegisterKilled(Reg, *KillMI);
1151 LV->addVirtualRegisterKilled(Reg, *MI);
1154 DEBUG(dbgs() << "\trescheduled kill: " << *KillMI);
1158 /// Tries to commute the operand 'BaseOpIdx' and some other operand in the
1159 /// given machine instruction to improve opportunities for coalescing and
1160 /// elimination of a register to register copy.
1162 /// 'DstOpIdx' specifies the index of MI def operand.
1163 /// 'BaseOpKilled' specifies if the register associated with 'BaseOpIdx'
1164 /// operand is killed by the given instruction.
1165 /// The 'Dist' arguments provides the distance of MI from the start of the
1166 /// current basic block and it is used to determine if it is profitable
1167 /// to commute operands in the instruction.
1169 /// Returns true if the transformation happened. Otherwise, returns false.
1170 bool TwoAddressInstructionPass::tryInstructionCommute(MachineInstr *MI,
1175 if (!MI->isCommutable())
1178 unsigned DstOpReg = MI->getOperand(DstOpIdx).getReg();
1179 unsigned BaseOpReg = MI->getOperand(BaseOpIdx).getReg();
1180 unsigned OpsNum = MI->getDesc().getNumOperands();
1181 unsigned OtherOpIdx = MI->getDesc().getNumDefs();
1182 for (; OtherOpIdx < OpsNum; OtherOpIdx++) {
1183 // The call of findCommutedOpIndices below only checks if BaseOpIdx
1184 // and OtherOpIdx are commutable, it does not really search for
1185 // other commutable operands and does not change the values of passed
1187 if (OtherOpIdx == BaseOpIdx || !MI->getOperand(OtherOpIdx).isReg() ||
1188 !TII->findCommutedOpIndices(*MI, BaseOpIdx, OtherOpIdx))
1191 unsigned OtherOpReg = MI->getOperand(OtherOpIdx).getReg();
1192 bool AggressiveCommute = false;
1194 // If OtherOp dies but BaseOp does not, swap the OtherOp and BaseOp
1195 // operands. This makes the live ranges of DstOp and OtherOp joinable.
1197 !BaseOpKilled && isKilled(*MI, OtherOpReg, MRI, TII, LIS, false);
1200 isProfitableToCommute(DstOpReg, BaseOpReg, OtherOpReg, MI, Dist)) {
1202 AggressiveCommute = true;
1205 // If it's profitable to commute, try to do so.
1206 if (DoCommute && commuteInstruction(MI, DstOpIdx, BaseOpIdx, OtherOpIdx,
1209 if (AggressiveCommute)
1217 /// For the case where an instruction has a single pair of tied register
1218 /// operands, attempt some transformations that may either eliminate the tied
1219 /// operands or improve the opportunities for coalescing away the register copy.
1220 /// Returns true if no copy needs to be inserted to untie mi's operands
1221 /// (either because they were untied, or because mi was rescheduled, and will
1222 /// be visited again later). If the shouldOnlyCommute flag is true, only
1223 /// instruction commutation is attempted.
1224 bool TwoAddressInstructionPass::
1225 tryInstructionTransform(MachineBasicBlock::iterator &mi,
1226 MachineBasicBlock::iterator &nmi,
1227 unsigned SrcIdx, unsigned DstIdx,
1228 unsigned Dist, bool shouldOnlyCommute) {
1229 if (OptLevel == CodeGenOpt::None)
1232 MachineInstr &MI = *mi;
1233 unsigned regA = MI.getOperand(DstIdx).getReg();
1234 unsigned regB = MI.getOperand(SrcIdx).getReg();
1236 assert(TargetRegisterInfo::isVirtualRegister(regB) &&
1237 "cannot make instruction into two-address form");
1238 bool regBKilled = isKilled(MI, regB, MRI, TII, LIS, true);
1240 if (TargetRegisterInfo::isVirtualRegister(regA))
1243 bool Commuted = tryInstructionCommute(&MI, DstIdx, SrcIdx, regBKilled, Dist);
1245 // If the instruction is convertible to 3 Addr, instead
1246 // of returning try 3 Addr transformation aggresively and
1247 // use this variable to check later. Because it might be better.
1248 // For example, we can just use `leal (%rsi,%rdi), %eax` and `ret`
1249 // instead of the following code.
1253 if (Commuted && !MI.isConvertibleTo3Addr())
1256 if (shouldOnlyCommute)
1259 // If there is one more use of regB later in the same MBB, consider
1260 // re-schedule this MI below it.
1261 if (!Commuted && EnableRescheduling && rescheduleMIBelowKill(mi, nmi, regB)) {
1266 // If we commuted, regB may have changed so we should re-sample it to avoid
1267 // confusing the three address conversion below.
1269 regB = MI.getOperand(SrcIdx).getReg();
1270 regBKilled = isKilled(MI, regB, MRI, TII, LIS, true);
1273 if (MI.isConvertibleTo3Addr()) {
1274 // This instruction is potentially convertible to a true
1275 // three-address instruction. Check if it is profitable.
1276 if (!regBKilled || isProfitableToConv3Addr(regA, regB)) {
1277 // Try to convert it.
1278 if (convertInstTo3Addr(mi, nmi, regA, regB, Dist)) {
1279 ++NumConvertedTo3Addr;
1280 return true; // Done with this instruction.
1285 // Return if it is commuted but 3 addr conversion is failed.
1289 // If there is one more use of regB later in the same MBB, consider
1290 // re-schedule it before this MI if it's legal.
1291 if (EnableRescheduling && rescheduleKillAboveMI(mi, nmi, regB)) {
1296 // If this is an instruction with a load folded into it, try unfolding
1297 // the load, e.g. avoid this:
1299 // addq (%rax), %rcx
1300 // in favor of this:
1301 // movq (%rax), %rcx
1303 // because it's preferable to schedule a load than a register copy.
1304 if (MI.mayLoad() && !regBKilled) {
1305 // Determine if a load can be unfolded.
1306 unsigned LoadRegIndex;
1308 TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(),
1309 /*UnfoldLoad=*/true,
1310 /*UnfoldStore=*/false,
1313 const MCInstrDesc &UnfoldMCID = TII->get(NewOpc);
1314 if (UnfoldMCID.getNumDefs() == 1) {
1316 DEBUG(dbgs() << "2addr: UNFOLDING: " << MI);
1317 const TargetRegisterClass *RC =
1318 TRI->getAllocatableClass(
1319 TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI, *MF));
1320 unsigned Reg = MRI->createVirtualRegister(RC);
1321 SmallVector<MachineInstr *, 2> NewMIs;
1322 if (!TII->unfoldMemoryOperand(*MF, MI, Reg,
1323 /*UnfoldLoad=*/true,
1324 /*UnfoldStore=*/false, NewMIs)) {
1325 DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
1328 assert(NewMIs.size() == 2 &&
1329 "Unfolded a load into multiple instructions!");
1330 // The load was previously folded, so this is the only use.
1331 NewMIs[1]->addRegisterKilled(Reg, TRI);
1333 // Tentatively insert the instructions into the block so that they
1334 // look "normal" to the transformation logic.
1335 MBB->insert(mi, NewMIs[0]);
1336 MBB->insert(mi, NewMIs[1]);
1338 DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0]
1339 << "2addr: NEW INST: " << *NewMIs[1]);
1341 // Transform the instruction, now that it no longer has a load.
1342 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA);
1343 unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB);
1344 MachineBasicBlock::iterator NewMI = NewMIs[1];
1345 bool TransformResult =
1346 tryInstructionTransform(NewMI, mi, NewSrcIdx, NewDstIdx, Dist, true);
1347 (void)TransformResult;
1348 assert(!TransformResult &&
1349 "tryInstructionTransform() should return false.");
1350 if (NewMIs[1]->getOperand(NewSrcIdx).isKill()) {
1351 // Success, or at least we made an improvement. Keep the unfolded
1352 // instructions and discard the original.
1354 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1355 MachineOperand &MO = MI.getOperand(i);
1357 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
1360 if (NewMIs[0]->killsRegister(MO.getReg()))
1361 LV->replaceKillInstruction(MO.getReg(), MI, *NewMIs[0]);
1363 assert(NewMIs[1]->killsRegister(MO.getReg()) &&
1364 "Kill missing after load unfold!");
1365 LV->replaceKillInstruction(MO.getReg(), MI, *NewMIs[1]);
1368 } else if (LV->removeVirtualRegisterDead(MO.getReg(), MI)) {
1369 if (NewMIs[1]->registerDefIsDead(MO.getReg()))
1370 LV->addVirtualRegisterDead(MO.getReg(), *NewMIs[1]);
1372 assert(NewMIs[0]->registerDefIsDead(MO.getReg()) &&
1373 "Dead flag missing after load unfold!");
1374 LV->addVirtualRegisterDead(MO.getReg(), *NewMIs[0]);
1379 LV->addVirtualRegisterKilled(Reg, *NewMIs[1]);
1382 SmallVector<unsigned, 4> OrigRegs;
1384 for (const MachineOperand &MO : MI.operands()) {
1386 OrigRegs.push_back(MO.getReg());
1390 MI.eraseFromParent();
1392 // Update LiveIntervals.
1394 MachineBasicBlock::iterator Begin(NewMIs[0]);
1395 MachineBasicBlock::iterator End(NewMIs[1]);
1396 LIS->repairIntervalsInRange(MBB, Begin, End, OrigRegs);
1401 // Transforming didn't eliminate the tie and didn't lead to an
1402 // improvement. Clean up the unfolded instructions and keep the
1404 DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
1405 NewMIs[0]->eraseFromParent();
1406 NewMIs[1]->eraseFromParent();
1415 // Collect tied operands of MI that need to be handled.
1416 // Rewrite trivial cases immediately.
1417 // Return true if any tied operands where found, including the trivial ones.
1418 bool TwoAddressInstructionPass::
1419 collectTiedOperands(MachineInstr *MI, TiedOperandMap &TiedOperands) {
1420 const MCInstrDesc &MCID = MI->getDesc();
1421 bool AnyOps = false;
1422 unsigned NumOps = MI->getNumOperands();
1424 for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) {
1425 unsigned DstIdx = 0;
1426 if (!MI->isRegTiedToDefOperand(SrcIdx, &DstIdx))
1429 MachineOperand &SrcMO = MI->getOperand(SrcIdx);
1430 MachineOperand &DstMO = MI->getOperand(DstIdx);
1431 unsigned SrcReg = SrcMO.getReg();
1432 unsigned DstReg = DstMO.getReg();
1433 // Tied constraint already satisfied?
1434 if (SrcReg == DstReg)
1437 assert(SrcReg && SrcMO.isUse() && "two address instruction invalid");
1439 // Deal with <undef> uses immediately - simply rewrite the src operand.
1440 if (SrcMO.isUndef() && !DstMO.getSubReg()) {
1441 // Constrain the DstReg register class if required.
1442 if (TargetRegisterInfo::isVirtualRegister(DstReg))
1443 if (const TargetRegisterClass *RC = TII->getRegClass(MCID, SrcIdx,
1445 MRI->constrainRegClass(DstReg, RC);
1446 SrcMO.setReg(DstReg);
1448 DEBUG(dbgs() << "\t\trewrite undef:\t" << *MI);
1451 TiedOperands[SrcReg].push_back(std::make_pair(SrcIdx, DstIdx));
1456 // Process a list of tied MI operands that all use the same source register.
1457 // The tied pairs are of the form (SrcIdx, DstIdx).
1459 TwoAddressInstructionPass::processTiedPairs(MachineInstr *MI,
1460 TiedPairList &TiedPairs,
1462 bool IsEarlyClobber = false;
1463 for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
1464 const MachineOperand &DstMO = MI->getOperand(TiedPairs[tpi].second);
1465 IsEarlyClobber |= DstMO.isEarlyClobber();
1468 bool RemovedKillFlag = false;
1469 bool AllUsesCopied = true;
1470 unsigned LastCopiedReg = 0;
1471 SlotIndex LastCopyIdx;
1473 unsigned SubRegB = 0;
1474 for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
1475 unsigned SrcIdx = TiedPairs[tpi].first;
1476 unsigned DstIdx = TiedPairs[tpi].second;
1478 const MachineOperand &DstMO = MI->getOperand(DstIdx);
1479 unsigned RegA = DstMO.getReg();
1481 // Grab RegB from the instruction because it may have changed if the
1482 // instruction was commuted.
1483 RegB = MI->getOperand(SrcIdx).getReg();
1484 SubRegB = MI->getOperand(SrcIdx).getSubReg();
1487 // The register is tied to multiple destinations (or else we would
1488 // not have continued this far), but this use of the register
1489 // already matches the tied destination. Leave it.
1490 AllUsesCopied = false;
1493 LastCopiedReg = RegA;
1495 assert(TargetRegisterInfo::isVirtualRegister(RegB) &&
1496 "cannot make instruction into two-address form");
1499 // First, verify that we don't have a use of "a" in the instruction
1500 // (a = b + a for example) because our transformation will not
1501 // work. This should never occur because we are in SSA form.
1502 for (unsigned i = 0; i != MI->getNumOperands(); ++i)
1503 assert(i == DstIdx ||
1504 !MI->getOperand(i).isReg() ||
1505 MI->getOperand(i).getReg() != RegA);
1509 MachineInstrBuilder MIB = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1510 TII->get(TargetOpcode::COPY), RegA);
1511 // If this operand is folding a truncation, the truncation now moves to the
1512 // copy so that the register classes remain valid for the operands.
1513 MIB.addReg(RegB, 0, SubRegB);
1514 const TargetRegisterClass *RC = MRI->getRegClass(RegB);
1516 if (TargetRegisterInfo::isVirtualRegister(RegA)) {
1517 assert(TRI->getMatchingSuperRegClass(RC, MRI->getRegClass(RegA),
1519 "tied subregister must be a truncation");
1520 // The superreg class will not be used to constrain the subreg class.
1524 assert(TRI->getMatchingSuperReg(RegA, SubRegB, MRI->getRegClass(RegB))
1525 && "tied subregister must be a truncation");
1529 // Update DistanceMap.
1530 MachineBasicBlock::iterator PrevMI = MI;
1532 DistanceMap.insert(std::make_pair(&*PrevMI, Dist));
1533 DistanceMap[MI] = ++Dist;
1536 LastCopyIdx = LIS->InsertMachineInstrInMaps(*PrevMI).getRegSlot();
1538 if (TargetRegisterInfo::isVirtualRegister(RegA)) {
1539 LiveInterval &LI = LIS->getInterval(RegA);
1540 VNInfo *VNI = LI.getNextValue(LastCopyIdx, LIS->getVNInfoAllocator());
1542 LIS->getInstructionIndex(*MI).getRegSlot(IsEarlyClobber);
1543 LI.addSegment(LiveInterval::Segment(LastCopyIdx, endIdx, VNI));
1547 DEBUG(dbgs() << "\t\tprepend:\t" << *MIB);
1549 MachineOperand &MO = MI->getOperand(SrcIdx);
1550 assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() &&
1551 "inconsistent operand info for 2-reg pass");
1553 MO.setIsKill(false);
1554 RemovedKillFlag = true;
1557 // Make sure regA is a legal regclass for the SrcIdx operand.
1558 if (TargetRegisterInfo::isVirtualRegister(RegA) &&
1559 TargetRegisterInfo::isVirtualRegister(RegB))
1560 MRI->constrainRegClass(RegA, RC);
1562 // The getMatchingSuper asserts guarantee that the register class projected
1563 // by SubRegB is compatible with RegA with no subregister. So regardless of
1564 // whether the dest oper writes a subreg, the source oper should not.
1567 // Propagate SrcRegMap.
1568 SrcRegMap[RegA] = RegB;
1571 if (AllUsesCopied) {
1572 if (!IsEarlyClobber) {
1573 // Replace other (un-tied) uses of regB with LastCopiedReg.
1574 for (MachineOperand &MO : MI->operands()) {
1575 if (MO.isReg() && MO.getReg() == RegB &&
1578 MO.setIsKill(false);
1579 RemovedKillFlag = true;
1581 MO.setReg(LastCopiedReg);
1582 MO.setSubReg(MO.getSubReg());
1587 // Update live variables for regB.
1588 if (RemovedKillFlag && LV && LV->getVarInfo(RegB).removeKill(*MI)) {
1589 MachineBasicBlock::iterator PrevMI = MI;
1591 LV->addVirtualRegisterKilled(RegB, *PrevMI);
1594 // Update LiveIntervals.
1596 LiveInterval &LI = LIS->getInterval(RegB);
1597 SlotIndex MIIdx = LIS->getInstructionIndex(*MI);
1598 LiveInterval::const_iterator I = LI.find(MIIdx);
1599 assert(I != LI.end() && "RegB must be live-in to use.");
1601 SlotIndex UseIdx = MIIdx.getRegSlot(IsEarlyClobber);
1602 if (I->end == UseIdx)
1603 LI.removeSegment(LastCopyIdx, UseIdx);
1606 } else if (RemovedKillFlag) {
1607 // Some tied uses of regB matched their destination registers, so
1608 // regB is still used in this instruction, but a kill flag was
1609 // removed from a different tied use of regB, so now we need to add
1610 // a kill flag to one of the remaining uses of regB.
1611 for (MachineOperand &MO : MI->operands()) {
1612 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {
1620 /// Reduce two-address instructions to two operands.
1621 bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) {
1623 const TargetMachine &TM = MF->getTarget();
1624 MRI = &MF->getRegInfo();
1625 TII = MF->getSubtarget().getInstrInfo();
1626 TRI = MF->getSubtarget().getRegisterInfo();
1627 InstrItins = MF->getSubtarget().getInstrItineraryData();
1628 LV = getAnalysisIfAvailable<LiveVariables>();
1629 LIS = getAnalysisIfAvailable<LiveIntervals>();
1630 AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
1631 OptLevel = TM.getOptLevel();
1633 bool MadeChange = false;
1635 DEBUG(dbgs() << "********** REWRITING TWO-ADDR INSTRS **********\n");
1636 DEBUG(dbgs() << "********** Function: "
1637 << MF->getName() << '\n');
1639 // This pass takes the function out of SSA form.
1642 TiedOperandMap TiedOperands;
1643 for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
1644 MBBI != MBBE; ++MBBI) {
1647 DistanceMap.clear();
1651 for (MachineBasicBlock::iterator mi = MBB->begin(), me = MBB->end();
1653 MachineBasicBlock::iterator nmi = std::next(mi);
1654 if (mi->isDebugValue()) {
1659 // Expand REG_SEQUENCE instructions. This will position mi at the first
1660 // expanded instruction.
1661 if (mi->isRegSequence())
1662 eliminateRegSequence(mi);
1664 DistanceMap.insert(std::make_pair(&*mi, ++Dist));
1668 // First scan through all the tied register uses in this instruction
1669 // and record a list of pairs of tied operands for each register.
1670 if (!collectTiedOperands(&*mi, TiedOperands)) {
1675 ++NumTwoAddressInstrs;
1677 DEBUG(dbgs() << '\t' << *mi);
1679 // If the instruction has a single pair of tied operands, try some
1680 // transformations that may either eliminate the tied operands or
1681 // improve the opportunities for coalescing away the register copy.
1682 if (TiedOperands.size() == 1) {
1683 SmallVectorImpl<std::pair<unsigned, unsigned> > &TiedPairs
1684 = TiedOperands.begin()->second;
1685 if (TiedPairs.size() == 1) {
1686 unsigned SrcIdx = TiedPairs[0].first;
1687 unsigned DstIdx = TiedPairs[0].second;
1688 unsigned SrcReg = mi->getOperand(SrcIdx).getReg();
1689 unsigned DstReg = mi->getOperand(DstIdx).getReg();
1690 if (SrcReg != DstReg &&
1691 tryInstructionTransform(mi, nmi, SrcIdx, DstIdx, Dist, false)) {
1692 // The tied operands have been eliminated or shifted further down
1693 // the block to ease elimination. Continue processing with 'nmi'.
1694 TiedOperands.clear();
1701 // Now iterate over the information collected above.
1702 for (auto &TO : TiedOperands) {
1703 processTiedPairs(&*mi, TO.second, Dist);
1704 DEBUG(dbgs() << "\t\trewrite to:\t" << *mi);
1707 // Rewrite INSERT_SUBREG as COPY now that we no longer need SSA form.
1708 if (mi->isInsertSubreg()) {
1709 // From %reg = INSERT_SUBREG %reg, %subreg, subidx
1710 // To %reg:subidx = COPY %subreg
1711 unsigned SubIdx = mi->getOperand(3).getImm();
1712 mi->RemoveOperand(3);
1713 assert(mi->getOperand(0).getSubReg() == 0 && "Unexpected subreg idx");
1714 mi->getOperand(0).setSubReg(SubIdx);
1715 mi->getOperand(0).setIsUndef(mi->getOperand(1).isUndef());
1716 mi->RemoveOperand(1);
1717 mi->setDesc(TII->get(TargetOpcode::COPY));
1718 DEBUG(dbgs() << "\t\tconvert to:\t" << *mi);
1721 // Clear TiedOperands here instead of at the top of the loop
1722 // since most instructions do not have tied operands.
1723 TiedOperands.clear();
1729 MF->verify(this, "After two-address instruction pass");
1734 /// Eliminate a REG_SEQUENCE instruction as part of the de-ssa process.
1736 /// The instruction is turned into a sequence of sub-register copies:
1738 /// %dst = REG_SEQUENCE %v1, ssub0, %v2, ssub1
1742 /// %dst:ssub0<def,undef> = COPY %v1
1743 /// %dst:ssub1<def> = COPY %v2
1745 void TwoAddressInstructionPass::
1746 eliminateRegSequence(MachineBasicBlock::iterator &MBBI) {
1747 MachineInstr &MI = *MBBI;
1748 unsigned DstReg = MI.getOperand(0).getReg();
1749 if (MI.getOperand(0).getSubReg() ||
1750 TargetRegisterInfo::isPhysicalRegister(DstReg) ||
1751 !(MI.getNumOperands() & 1)) {
1752 DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << MI);
1753 llvm_unreachable(nullptr);
1756 SmallVector<unsigned, 4> OrigRegs;
1758 OrigRegs.push_back(MI.getOperand(0).getReg());
1759 for (unsigned i = 1, e = MI.getNumOperands(); i < e; i += 2)
1760 OrigRegs.push_back(MI.getOperand(i).getReg());
1763 bool DefEmitted = false;
1764 for (unsigned i = 1, e = MI.getNumOperands(); i < e; i += 2) {
1765 MachineOperand &UseMO = MI.getOperand(i);
1766 unsigned SrcReg = UseMO.getReg();
1767 unsigned SubIdx = MI.getOperand(i+1).getImm();
1768 // Nothing needs to be inserted for <undef> operands.
1769 if (UseMO.isUndef())
1772 // Defer any kill flag to the last operand using SrcReg. Otherwise, we
1773 // might insert a COPY that uses SrcReg after is was killed.
1774 bool isKill = UseMO.isKill();
1776 for (unsigned j = i + 2; j < e; j += 2)
1777 if (MI.getOperand(j).getReg() == SrcReg) {
1778 MI.getOperand(j).setIsKill();
1779 UseMO.setIsKill(false);
1784 // Insert the sub-register copy.
1785 MachineInstr *CopyMI = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
1786 TII->get(TargetOpcode::COPY))
1787 .addReg(DstReg, RegState::Define, SubIdx)
1790 // The first def needs an <undef> flag because there is no live register
1793 CopyMI->getOperand(0).setIsUndef(true);
1794 // Return an iterator pointing to the first inserted instr.
1799 // Update LiveVariables' kill info.
1800 if (LV && isKill && !TargetRegisterInfo::isPhysicalRegister(SrcReg))
1801 LV->replaceKillInstruction(SrcReg, MI, *CopyMI);
1803 DEBUG(dbgs() << "Inserted: " << *CopyMI);
1806 MachineBasicBlock::iterator EndMBBI =
1807 std::next(MachineBasicBlock::iterator(MI));
1810 DEBUG(dbgs() << "Turned: " << MI << " into an IMPLICIT_DEF");
1811 MI.setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
1812 for (int j = MI.getNumOperands() - 1, ee = 0; j > ee; --j)
1813 MI.RemoveOperand(j);
1815 DEBUG(dbgs() << "Eliminated: " << MI);
1816 MI.eraseFromParent();
1819 // Udpate LiveIntervals.
1821 LIS->repairIntervalsInRange(MBB, MBBI, EndMBBI, OrigRegs);