1 //===- TwoAddressInstructionPass.cpp - Two-Address instruction pass -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TwoAddress instruction pass which is used
11 // by most register allocators. Two-Address instructions are rewritten
21 // Note that if a register allocator chooses to use this pass, that it
22 // has to be capable of handling the non-SSA nature of these rewritten
25 // It is also worth noting that the duplicate operand of the two
26 // address instruction is removed.
28 //===----------------------------------------------------------------------===//
30 #include "llvm/ADT/DenseMap.h"
31 #include "llvm/ADT/SmallPtrSet.h"
32 #include "llvm/ADT/SmallSet.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/ADT/iterator_range.h"
36 #include "llvm/Analysis/AliasAnalysis.h"
37 #include "llvm/CodeGen/LiveInterval.h"
38 #include "llvm/CodeGen/LiveIntervals.h"
39 #include "llvm/CodeGen/LiveVariables.h"
40 #include "llvm/CodeGen/MachineBasicBlock.h"
41 #include "llvm/CodeGen/MachineFunction.h"
42 #include "llvm/CodeGen/MachineFunctionPass.h"
43 #include "llvm/CodeGen/MachineInstr.h"
44 #include "llvm/CodeGen/MachineInstrBuilder.h"
45 #include "llvm/CodeGen/MachineOperand.h"
46 #include "llvm/CodeGen/MachineRegisterInfo.h"
47 #include "llvm/CodeGen/Passes.h"
48 #include "llvm/CodeGen/SlotIndexes.h"
49 #include "llvm/CodeGen/TargetInstrInfo.h"
50 #include "llvm/CodeGen/TargetOpcodes.h"
51 #include "llvm/CodeGen/TargetRegisterInfo.h"
52 #include "llvm/CodeGen/TargetSubtargetInfo.h"
53 #include "llvm/MC/MCInstrDesc.h"
54 #include "llvm/MC/MCInstrItineraries.h"
55 #include "llvm/Pass.h"
56 #include "llvm/Support/CodeGen.h"
57 #include "llvm/Support/CommandLine.h"
58 #include "llvm/Support/Debug.h"
59 #include "llvm/Support/ErrorHandling.h"
60 #include "llvm/Support/raw_ostream.h"
61 #include "llvm/Target/TargetMachine.h"
68 #define DEBUG_TYPE "twoaddressinstruction"
70 STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions");
71 STATISTIC(NumCommuted , "Number of instructions commuted to coalesce");
72 STATISTIC(NumAggrCommuted , "Number of instructions aggressively commuted");
73 STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");
74 STATISTIC(Num3AddrSunk, "Number of 3-address instructions sunk");
75 STATISTIC(NumReSchedUps, "Number of instructions re-scheduled up");
76 STATISTIC(NumReSchedDowns, "Number of instructions re-scheduled down");
78 // Temporary flag to disable rescheduling.
80 EnableRescheduling("twoaddr-reschedule",
81 cl::desc("Coalesce copies by rescheduling (default=true)"),
82 cl::init(true), cl::Hidden);
84 // Limit the number of dataflow edges to traverse when evaluating the benefit
85 // of commuting operands.
86 static cl::opt<unsigned> MaxDataFlowEdge(
87 "dataflow-edge-limit", cl::Hidden, cl::init(3),
88 cl::desc("Maximum number of dataflow edges to traverse when evaluating "
89 "the benefit of commuting operands"));
93 class TwoAddressInstructionPass : public MachineFunctionPass {
95 const TargetInstrInfo *TII;
96 const TargetRegisterInfo *TRI;
97 const InstrItineraryData *InstrItins;
98 MachineRegisterInfo *MRI;
102 CodeGenOpt::Level OptLevel;
104 // The current basic block being processed.
105 MachineBasicBlock *MBB;
107 // Keep track the distance of a MI from the start of the current basic block.
108 DenseMap<MachineInstr*, unsigned> DistanceMap;
110 // Set of already processed instructions in the current block.
111 SmallPtrSet<MachineInstr*, 8> Processed;
113 // Set of instructions converted to three-address by target and then sunk
114 // down current basic block.
115 SmallPtrSet<MachineInstr*, 8> SunkInstrs;
117 // A map from virtual registers to physical registers which are likely targets
118 // to be coalesced to due to copies from physical registers to virtual
119 // registers. e.g. v1024 = move r0.
120 DenseMap<unsigned, unsigned> SrcRegMap;
122 // A map from virtual registers to physical registers which are likely targets
123 // to be coalesced to due to copies to physical registers from virtual
124 // registers. e.g. r1 = move v1024.
125 DenseMap<unsigned, unsigned> DstRegMap;
127 bool sink3AddrInstruction(MachineInstr *MI, unsigned Reg,
128 MachineBasicBlock::iterator OldPos);
130 bool isRevCopyChain(unsigned FromReg, unsigned ToReg, int Maxlen);
132 bool noUseAfterLastDef(unsigned Reg, unsigned Dist, unsigned &LastDef);
134 bool isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC,
135 MachineInstr *MI, unsigned Dist);
137 bool commuteInstruction(MachineInstr *MI, unsigned DstIdx,
138 unsigned RegBIdx, unsigned RegCIdx, unsigned Dist);
140 bool isProfitableToConv3Addr(unsigned RegA, unsigned RegB);
142 bool convertInstTo3Addr(MachineBasicBlock::iterator &mi,
143 MachineBasicBlock::iterator &nmi,
144 unsigned RegA, unsigned RegB, unsigned Dist);
146 bool isDefTooClose(unsigned Reg, unsigned Dist, MachineInstr *MI);
148 bool rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
149 MachineBasicBlock::iterator &nmi,
151 bool rescheduleKillAboveMI(MachineBasicBlock::iterator &mi,
152 MachineBasicBlock::iterator &nmi,
155 bool tryInstructionTransform(MachineBasicBlock::iterator &mi,
156 MachineBasicBlock::iterator &nmi,
157 unsigned SrcIdx, unsigned DstIdx,
158 unsigned Dist, bool shouldOnlyCommute);
160 bool tryInstructionCommute(MachineInstr *MI,
165 void scanUses(unsigned DstReg);
167 void processCopy(MachineInstr *MI);
169 using TiedPairList = SmallVector<std::pair<unsigned, unsigned>, 4>;
170 using TiedOperandMap = SmallDenseMap<unsigned, TiedPairList>;
172 bool collectTiedOperands(MachineInstr *MI, TiedOperandMap&);
173 void processTiedPairs(MachineInstr *MI, TiedPairList&, unsigned &Dist);
174 void eliminateRegSequence(MachineBasicBlock::iterator&);
177 static char ID; // Pass identification, replacement for typeid
179 TwoAddressInstructionPass() : MachineFunctionPass(ID) {
180 initializeTwoAddressInstructionPassPass(*PassRegistry::getPassRegistry());
183 void getAnalysisUsage(AnalysisUsage &AU) const override {
184 AU.setPreservesCFG();
185 AU.addUsedIfAvailable<AAResultsWrapperPass>();
186 AU.addUsedIfAvailable<LiveVariables>();
187 AU.addPreserved<LiveVariables>();
188 AU.addPreserved<SlotIndexes>();
189 AU.addPreserved<LiveIntervals>();
190 AU.addPreservedID(MachineLoopInfoID);
191 AU.addPreservedID(MachineDominatorsID);
192 MachineFunctionPass::getAnalysisUsage(AU);
195 /// Pass entry point.
196 bool runOnMachineFunction(MachineFunction&) override;
199 } // end anonymous namespace
201 char TwoAddressInstructionPass::ID = 0;
203 char &llvm::TwoAddressInstructionPassID = TwoAddressInstructionPass::ID;
205 INITIALIZE_PASS_BEGIN(TwoAddressInstructionPass, DEBUG_TYPE,
206 "Two-Address instruction pass", false, false)
207 INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
208 INITIALIZE_PASS_END(TwoAddressInstructionPass, DEBUG_TYPE,
209 "Two-Address instruction pass", false, false)
211 static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg, LiveIntervals *LIS);
213 /// A two-address instruction has been converted to a three-address instruction
214 /// to avoid clobbering a register. Try to sink it past the instruction that
215 /// would kill the above mentioned register to reduce register pressure.
216 bool TwoAddressInstructionPass::
217 sink3AddrInstruction(MachineInstr *MI, unsigned SavedReg,
218 MachineBasicBlock::iterator OldPos) {
219 // FIXME: Shouldn't we be trying to do this before we three-addressify the
220 // instruction? After this transformation is done, we no longer need
221 // the instruction to be in three-address form.
223 // Check if it's safe to move this instruction.
224 bool SeenStore = true; // Be conservative.
225 if (!MI->isSafeToMove(AA, SeenStore))
229 SmallSet<unsigned, 4> UseRegs;
231 for (const MachineOperand &MO : MI->operands()) {
234 unsigned MOReg = MO.getReg();
237 if (MO.isUse() && MOReg != SavedReg)
238 UseRegs.insert(MO.getReg());
242 // Don't try to move it if it implicitly defines a register.
245 // For now, don't move any instructions that define multiple registers.
247 DefReg = MO.getReg();
250 // Find the instruction that kills SavedReg.
251 MachineInstr *KillMI = nullptr;
253 LiveInterval &LI = LIS->getInterval(SavedReg);
254 assert(LI.end() != LI.begin() &&
255 "Reg should not have empty live interval.");
257 SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot();
258 LiveInterval::const_iterator I = LI.find(MBBEndIdx);
259 if (I != LI.end() && I->start < MBBEndIdx)
263 KillMI = LIS->getInstructionFromIndex(I->end);
266 for (MachineOperand &UseMO : MRI->use_nodbg_operands(SavedReg)) {
269 KillMI = UseMO.getParent();
274 // If we find the instruction that kills SavedReg, and it is in an
275 // appropriate location, we can try to sink the current instruction
277 if (!KillMI || KillMI->getParent() != MBB || KillMI == MI ||
278 MachineBasicBlock::iterator(KillMI) == OldPos || KillMI->isTerminator())
281 // If any of the definitions are used by another instruction between the
282 // position and the kill use, then it's not safe to sink it.
284 // FIXME: This can be sped up if there is an easy way to query whether an
285 // instruction is before or after another instruction. Then we can use
286 // MachineRegisterInfo def / use instead.
287 MachineOperand *KillMO = nullptr;
288 MachineBasicBlock::iterator KillPos = KillMI;
291 unsigned NumVisited = 0;
292 for (MachineInstr &OtherMI : make_range(std::next(OldPos), KillPos)) {
293 // DBG_VALUE cannot be counted against the limit.
294 if (OtherMI.isDebugValue())
296 if (NumVisited > 30) // FIXME: Arbitrary limit to reduce compile time cost.
299 for (unsigned i = 0, e = OtherMI.getNumOperands(); i != e; ++i) {
300 MachineOperand &MO = OtherMI.getOperand(i);
303 unsigned MOReg = MO.getReg();
309 if (MO.isKill() || (LIS && isPlainlyKilled(&OtherMI, MOReg, LIS))) {
310 if (&OtherMI == KillMI && MOReg == SavedReg)
311 // Save the operand that kills the register. We want to unset the kill
312 // marker if we can sink MI past it.
314 else if (UseRegs.count(MOReg))
315 // One of the uses is killed before the destination.
320 assert(KillMO && "Didn't find kill");
323 // Update kill and LV information.
324 KillMO->setIsKill(false);
325 KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI);
326 KillMO->setIsKill(true);
329 LV->replaceKillInstruction(SavedReg, *KillMI, *MI);
332 // Move instruction to its destination.
334 MBB->insert(KillPos, MI);
337 LIS->handleMove(*MI);
343 /// Return the MachineInstr* if it is the single def of the Reg in current BB.
344 static MachineInstr *getSingleDef(unsigned Reg, MachineBasicBlock *BB,
345 const MachineRegisterInfo *MRI) {
346 MachineInstr *Ret = nullptr;
347 for (MachineInstr &DefMI : MRI->def_instructions(Reg)) {
348 if (DefMI.getParent() != BB || DefMI.isDebugValue())
352 else if (Ret != &DefMI)
358 /// Check if there is a reversed copy chain from FromReg to ToReg:
359 /// %Tmp1 = copy %Tmp2;
360 /// %FromReg = copy %Tmp1;
361 /// %ToReg = add %FromReg ...
362 /// %Tmp2 = copy %ToReg;
363 /// MaxLen specifies the maximum length of the copy chain the func
364 /// can walk through.
365 bool TwoAddressInstructionPass::isRevCopyChain(unsigned FromReg, unsigned ToReg,
367 unsigned TmpReg = FromReg;
368 for (int i = 0; i < Maxlen; i++) {
369 MachineInstr *Def = getSingleDef(TmpReg, MBB, MRI);
370 if (!Def || !Def->isCopy())
373 TmpReg = Def->getOperand(1).getReg();
381 /// Return true if there are no intervening uses between the last instruction
382 /// in the MBB that defines the specified register and the two-address
383 /// instruction which is being processed. It also returns the last def location
385 bool TwoAddressInstructionPass::noUseAfterLastDef(unsigned Reg, unsigned Dist,
388 unsigned LastUse = Dist;
389 for (MachineOperand &MO : MRI->reg_operands(Reg)) {
390 MachineInstr *MI = MO.getParent();
391 if (MI->getParent() != MBB || MI->isDebugValue())
393 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
394 if (DI == DistanceMap.end())
396 if (MO.isUse() && DI->second < LastUse)
397 LastUse = DI->second;
398 if (MO.isDef() && DI->second > LastDef)
399 LastDef = DI->second;
402 return !(LastUse > LastDef && LastUse < Dist);
405 /// Return true if the specified MI is a copy instruction or an extract_subreg
406 /// instruction. It also returns the source and destination registers and
407 /// whether they are physical registers by reference.
408 static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII,
409 unsigned &SrcReg, unsigned &DstReg,
410 bool &IsSrcPhys, bool &IsDstPhys) {
414 DstReg = MI.getOperand(0).getReg();
415 SrcReg = MI.getOperand(1).getReg();
416 } else if (MI.isInsertSubreg() || MI.isSubregToReg()) {
417 DstReg = MI.getOperand(0).getReg();
418 SrcReg = MI.getOperand(2).getReg();
422 IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
423 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
427 /// Test if the given register value, which is used by the
428 /// given instruction, is killed by the given instruction.
429 static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg,
430 LiveIntervals *LIS) {
431 if (LIS && TargetRegisterInfo::isVirtualRegister(Reg) &&
432 !LIS->isNotInMIMap(*MI)) {
433 // FIXME: Sometimes tryInstructionTransform() will add instructions and
434 // test whether they can be folded before keeping them. In this case it
435 // sets a kill before recursively calling tryInstructionTransform() again.
436 // If there is no interval available, we assume that this instruction is
437 // one of those. A kill flag is manually inserted on the operand so the
438 // check below will handle it.
439 LiveInterval &LI = LIS->getInterval(Reg);
440 // This is to match the kill flag version where undefs don't have kill
442 if (!LI.hasAtLeastOneValue())
445 SlotIndex useIdx = LIS->getInstructionIndex(*MI);
446 LiveInterval::const_iterator I = LI.find(useIdx);
447 assert(I != LI.end() && "Reg must be live-in to use.");
448 return !I->end.isBlock() && SlotIndex::isSameInstr(I->end, useIdx);
451 return MI->killsRegister(Reg);
454 /// Test if the given register value, which is used by the given
455 /// instruction, is killed by the given instruction. This looks through
456 /// coalescable copies to see if the original value is potentially not killed.
458 /// For example, in this code:
460 /// %reg1034 = copy %reg1024
461 /// %reg1035 = copy killed %reg1025
462 /// %reg1036 = add killed %reg1034, killed %reg1035
464 /// %reg1034 is not considered to be killed, since it is copied from a
465 /// register which is not killed. Treating it as not killed lets the
466 /// normal heuristics commute the (two-address) add, which lets
467 /// coalescing eliminate the extra copy.
469 /// If allowFalsePositives is true then likely kills are treated as kills even
470 /// if it can't be proven that they are kills.
471 static bool isKilled(MachineInstr &MI, unsigned Reg,
472 const MachineRegisterInfo *MRI,
473 const TargetInstrInfo *TII,
475 bool allowFalsePositives) {
476 MachineInstr *DefMI = &MI;
478 // All uses of physical registers are likely to be kills.
479 if (TargetRegisterInfo::isPhysicalRegister(Reg) &&
480 (allowFalsePositives || MRI->hasOneUse(Reg)))
482 if (!isPlainlyKilled(DefMI, Reg, LIS))
484 if (TargetRegisterInfo::isPhysicalRegister(Reg))
486 MachineRegisterInfo::def_iterator Begin = MRI->def_begin(Reg);
487 // If there are multiple defs, we can't do a simple analysis, so just
488 // go with what the kill flag says.
489 if (std::next(Begin) != MRI->def_end())
491 DefMI = Begin->getParent();
492 bool IsSrcPhys, IsDstPhys;
493 unsigned SrcReg, DstReg;
494 // If the def is something other than a copy, then it isn't going to
495 // be coalesced, so follow the kill flag.
496 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
502 /// Return true if the specified MI uses the specified register as a two-address
503 /// use. If so, return the destination register by reference.
504 static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) {
505 for (unsigned i = 0, NumOps = MI.getNumOperands(); i != NumOps; ++i) {
506 const MachineOperand &MO = MI.getOperand(i);
507 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
510 if (MI.isRegTiedToDefOperand(i, &ti)) {
511 DstReg = MI.getOperand(ti).getReg();
518 /// Given a register, if has a single in-basic block use, return the use
519 /// instruction if it's a copy or a two-address use.
521 MachineInstr *findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB,
522 MachineRegisterInfo *MRI,
523 const TargetInstrInfo *TII,
525 unsigned &DstReg, bool &IsDstPhys) {
526 if (!MRI->hasOneNonDBGUse(Reg))
527 // None or more than one use.
529 MachineInstr &UseMI = *MRI->use_instr_nodbg_begin(Reg);
530 if (UseMI.getParent() != MBB)
534 if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) {
539 if (isTwoAddrUse(UseMI, Reg, DstReg)) {
540 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
546 /// Return the physical register the specified virtual register might be mapped
549 getMappedReg(unsigned Reg, DenseMap<unsigned, unsigned> &RegMap) {
550 while (TargetRegisterInfo::isVirtualRegister(Reg)) {
551 DenseMap<unsigned, unsigned>::iterator SI = RegMap.find(Reg);
552 if (SI == RegMap.end())
556 if (TargetRegisterInfo::isPhysicalRegister(Reg))
561 /// Return true if the two registers are equal or aliased.
563 regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) {
568 return TRI->regsOverlap(RegA, RegB);
571 // Returns true if Reg is equal or aliased to at least one register in Set.
572 static bool regOverlapsSet(const SmallVectorImpl<unsigned> &Set, unsigned Reg,
573 const TargetRegisterInfo *TRI) {
574 for (unsigned R : Set)
575 if (TRI->regsOverlap(R, Reg))
581 /// Return true if it's potentially profitable to commute the two-address
582 /// instruction that's being processed.
584 TwoAddressInstructionPass::
585 isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC,
586 MachineInstr *MI, unsigned Dist) {
587 if (OptLevel == CodeGenOpt::None)
590 // Determine if it's profitable to commute this two address instruction. In
591 // general, we want no uses between this instruction and the definition of
592 // the two-address register.
594 // %reg1028 = EXTRACT_SUBREG killed %reg1027, 1
595 // %reg1029 = MOV8rr %reg1028
596 // %reg1029 = SHR8ri %reg1029, 7, implicit dead %eflags
597 // insert => %reg1030 = MOV8rr %reg1028
598 // %reg1030 = ADD8rr killed %reg1028, killed %reg1029, implicit dead %eflags
599 // In this case, it might not be possible to coalesce the second MOV8rr
600 // instruction if the first one is coalesced. So it would be profitable to
602 // %reg1028 = EXTRACT_SUBREG killed %reg1027, 1
603 // %reg1029 = MOV8rr %reg1028
604 // %reg1029 = SHR8ri %reg1029, 7, implicit dead %eflags
605 // insert => %reg1030 = MOV8rr %reg1029
606 // %reg1030 = ADD8rr killed %reg1029, killed %reg1028, implicit dead %eflags
608 if (!isPlainlyKilled(MI, regC, LIS))
611 // Ok, we have something like:
612 // %reg1030 = ADD8rr killed %reg1028, killed %reg1029, implicit dead %eflags
613 // let's see if it's worth commuting it.
615 // Look for situations like this:
618 // %reg1026 = ADD %reg1024, %reg1025
620 // Commute the ADD to hopefully eliminate an otherwise unavoidable copy.
621 unsigned ToRegA = getMappedReg(regA, DstRegMap);
623 unsigned FromRegB = getMappedReg(regB, SrcRegMap);
624 unsigned FromRegC = getMappedReg(regC, SrcRegMap);
625 bool CompB = FromRegB && regsAreCompatible(FromRegB, ToRegA, TRI);
626 bool CompC = FromRegC && regsAreCompatible(FromRegC, ToRegA, TRI);
628 // Compute if any of the following are true:
629 // -RegB is not tied to a register and RegC is compatible with RegA.
630 // -RegB is tied to the wrong physical register, but RegC is.
631 // -RegB is tied to the wrong physical register, and RegC isn't tied.
632 if ((!FromRegB && CompC) || (FromRegB && !CompB && (!FromRegC || CompC)))
634 // Don't compute if any of the following are true:
635 // -RegC is not tied to a register and RegB is compatible with RegA.
636 // -RegC is tied to the wrong physical register, but RegB is.
637 // -RegC is tied to the wrong physical register, and RegB isn't tied.
638 if ((!FromRegC && CompB) || (FromRegC && !CompC && (!FromRegB || CompB)))
642 // If there is a use of regC between its last def (could be livein) and this
643 // instruction, then bail.
644 unsigned LastDefC = 0;
645 if (!noUseAfterLastDef(regC, Dist, LastDefC))
648 // If there is a use of regB between its last def (could be livein) and this
649 // instruction, then go ahead and make this transformation.
650 unsigned LastDefB = 0;
651 if (!noUseAfterLastDef(regB, Dist, LastDefB))
654 // Look for situation like this:
655 // %reg101 = MOV %reg100
657 // %reg103 = ADD %reg102, %reg101
659 // %reg100 = MOV %reg103
660 // If there is a reversed copy chain from reg101 to reg103, commute the ADD
661 // to eliminate an otherwise unavoidable copy.
663 // We can extend the logic further: If an pair of operands in an insn has
664 // been merged, the insn could be regarded as a virtual copy, and the virtual
665 // copy could also be used to construct a copy chain.
666 // To more generally minimize register copies, ideally the logic of two addr
667 // instruction pass should be integrated with register allocation pass where
668 // interference graph is available.
669 if (isRevCopyChain(regC, regA, MaxDataFlowEdge))
672 if (isRevCopyChain(regB, regA, MaxDataFlowEdge))
675 // Since there are no intervening uses for both registers, then commute
676 // if the def of regC is closer. Its live interval is shorter.
677 return LastDefB && LastDefC && LastDefC > LastDefB;
680 /// Commute a two-address instruction and update the basic block, distance map,
681 /// and live variables if needed. Return true if it is successful.
682 bool TwoAddressInstructionPass::commuteInstruction(MachineInstr *MI,
687 unsigned RegC = MI->getOperand(RegCIdx).getReg();
688 DEBUG(dbgs() << "2addr: COMMUTING : " << *MI);
689 MachineInstr *NewMI = TII->commuteInstruction(*MI, false, RegBIdx, RegCIdx);
691 if (NewMI == nullptr) {
692 DEBUG(dbgs() << "2addr: COMMUTING FAILED!\n");
696 DEBUG(dbgs() << "2addr: COMMUTED TO: " << *NewMI);
697 assert(NewMI == MI &&
698 "TargetInstrInfo::commuteInstruction() should not return a new "
699 "instruction unless it was requested.");
701 // Update source register map.
702 unsigned FromRegC = getMappedReg(RegC, SrcRegMap);
704 unsigned RegA = MI->getOperand(DstIdx).getReg();
705 SrcRegMap[RegA] = FromRegC;
711 /// Return true if it is profitable to convert the given 2-address instruction
712 /// to a 3-address one.
714 TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA,unsigned RegB){
715 // Look for situations like this:
718 // %reg1026 = ADD %reg1024, %reg1025
720 // Turn ADD into a 3-address instruction to avoid a copy.
721 unsigned FromRegB = getMappedReg(RegB, SrcRegMap);
724 unsigned ToRegA = getMappedReg(RegA, DstRegMap);
725 return (ToRegA && !regsAreCompatible(FromRegB, ToRegA, TRI));
728 /// Convert the specified two-address instruction into a three address one.
729 /// Return true if this transformation was successful.
731 TwoAddressInstructionPass::convertInstTo3Addr(MachineBasicBlock::iterator &mi,
732 MachineBasicBlock::iterator &nmi,
733 unsigned RegA, unsigned RegB,
735 // FIXME: Why does convertToThreeAddress() need an iterator reference?
736 MachineFunction::iterator MFI = MBB->getIterator();
737 MachineInstr *NewMI = TII->convertToThreeAddress(MFI, *mi, LV);
738 assert(MBB->getIterator() == MFI &&
739 "convertToThreeAddress changed iterator reference");
743 DEBUG(dbgs() << "2addr: CONVERTING 2-ADDR: " << *mi);
744 DEBUG(dbgs() << "2addr: TO 3-ADDR: " << *NewMI);
748 LIS->ReplaceMachineInstrInMaps(*mi, *NewMI);
750 if (NewMI->findRegisterUseOperand(RegB, false, TRI))
751 // FIXME: Temporary workaround. If the new instruction doesn't
752 // uses RegB, convertToThreeAddress must have created more
753 // then one instruction.
754 Sunk = sink3AddrInstruction(NewMI, RegB, mi);
756 MBB->erase(mi); // Nuke the old inst.
759 DistanceMap.insert(std::make_pair(NewMI, Dist));
764 SunkInstrs.insert(NewMI);
766 // Update source and destination register maps.
767 SrcRegMap.erase(RegA);
768 DstRegMap.erase(RegB);
772 /// Scan forward recursively for only uses, update maps if the use is a copy or
773 /// a two-address instruction.
775 TwoAddressInstructionPass::scanUses(unsigned DstReg) {
776 SmallVector<unsigned, 4> VirtRegPairs;
780 unsigned Reg = DstReg;
781 while (MachineInstr *UseMI = findOnlyInterestingUse(Reg, MBB, MRI, TII,IsCopy,
782 NewReg, IsDstPhys)) {
783 if (IsCopy && !Processed.insert(UseMI).second)
786 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
787 if (DI != DistanceMap.end())
788 // Earlier in the same MBB.Reached via a back edge.
792 VirtRegPairs.push_back(NewReg);
795 bool isNew = SrcRegMap.insert(std::make_pair(NewReg, Reg)).second;
797 assert(SrcRegMap[NewReg] == Reg && "Can't map to two src registers!");
798 VirtRegPairs.push_back(NewReg);
802 if (!VirtRegPairs.empty()) {
803 unsigned ToReg = VirtRegPairs.back();
804 VirtRegPairs.pop_back();
805 while (!VirtRegPairs.empty()) {
806 unsigned FromReg = VirtRegPairs.back();
807 VirtRegPairs.pop_back();
808 bool isNew = DstRegMap.insert(std::make_pair(FromReg, ToReg)).second;
810 assert(DstRegMap[FromReg] == ToReg &&"Can't map to two dst registers!");
813 bool isNew = DstRegMap.insert(std::make_pair(DstReg, ToReg)).second;
815 assert(DstRegMap[DstReg] == ToReg && "Can't map to two dst registers!");
819 /// If the specified instruction is not yet processed, process it if it's a
820 /// copy. For a copy instruction, we find the physical registers the
821 /// source and destination registers might be mapped to. These are kept in
822 /// point-to maps used to determine future optimizations. e.g.
825 /// v1026 = add v1024, v1025
827 /// If 'add' is a two-address instruction, v1024, v1026 are both potentially
828 /// coalesced to r0 (from the input side). v1025 is mapped to r1. v1026 is
829 /// potentially joined with r1 on the output side. It's worthwhile to commute
830 /// 'add' to eliminate a copy.
831 void TwoAddressInstructionPass::processCopy(MachineInstr *MI) {
832 if (Processed.count(MI))
835 bool IsSrcPhys, IsDstPhys;
836 unsigned SrcReg, DstReg;
837 if (!isCopyToReg(*MI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
840 if (IsDstPhys && !IsSrcPhys)
841 DstRegMap.insert(std::make_pair(SrcReg, DstReg));
842 else if (!IsDstPhys && IsSrcPhys) {
843 bool isNew = SrcRegMap.insert(std::make_pair(DstReg, SrcReg)).second;
845 assert(SrcRegMap[DstReg] == SrcReg &&
846 "Can't map to two src physical registers!");
851 Processed.insert(MI);
854 /// If there is one more local instruction that reads 'Reg' and it kills 'Reg,
855 /// consider moving the instruction below the kill instruction in order to
856 /// eliminate the need for the copy.
857 bool TwoAddressInstructionPass::
858 rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
859 MachineBasicBlock::iterator &nmi,
861 // Bail immediately if we don't have LV or LIS available. We use them to find
862 // kills efficiently.
866 MachineInstr *MI = &*mi;
867 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
868 if (DI == DistanceMap.end())
869 // Must be created from unfolded load. Don't waste time trying this.
872 MachineInstr *KillMI = nullptr;
874 LiveInterval &LI = LIS->getInterval(Reg);
875 assert(LI.end() != LI.begin() &&
876 "Reg should not have empty live interval.");
878 SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot();
879 LiveInterval::const_iterator I = LI.find(MBBEndIdx);
880 if (I != LI.end() && I->start < MBBEndIdx)
884 KillMI = LIS->getInstructionFromIndex(I->end);
886 KillMI = LV->getVarInfo(Reg).findKill(MBB);
888 if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike())
889 // Don't mess with copies, they may be coalesced later.
892 if (KillMI->hasUnmodeledSideEffects() || KillMI->isCall() ||
893 KillMI->isBranch() || KillMI->isTerminator())
894 // Don't move pass calls, etc.
898 if (isTwoAddrUse(*KillMI, Reg, DstReg))
901 bool SeenStore = true;
902 if (!MI->isSafeToMove(AA, SeenStore))
905 if (TII->getInstrLatency(InstrItins, *MI) > 1)
906 // FIXME: Needs more sophisticated heuristics.
909 SmallVector<unsigned, 2> Uses;
910 SmallVector<unsigned, 2> Kills;
911 SmallVector<unsigned, 2> Defs;
912 for (const MachineOperand &MO : MI->operands()) {
915 unsigned MOReg = MO.getReg();
919 Defs.push_back(MOReg);
921 Uses.push_back(MOReg);
922 if (MOReg != Reg && (MO.isKill() ||
923 (LIS && isPlainlyKilled(MI, MOReg, LIS))))
924 Kills.push_back(MOReg);
928 // Move the copies connected to MI down as well.
929 MachineBasicBlock::iterator Begin = MI;
930 MachineBasicBlock::iterator AfterMI = std::next(Begin);
931 MachineBasicBlock::iterator End = AfterMI;
932 while (End->isCopy() &&
933 regOverlapsSet(Defs, End->getOperand(1).getReg(), TRI)) {
934 Defs.push_back(End->getOperand(0).getReg());
938 // Check if the reschedule will not break dependencies.
939 unsigned NumVisited = 0;
940 MachineBasicBlock::iterator KillPos = KillMI;
942 for (MachineInstr &OtherMI : make_range(End, KillPos)) {
943 // DBG_VALUE cannot be counted against the limit.
944 if (OtherMI.isDebugValue())
946 if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
949 if (OtherMI.hasUnmodeledSideEffects() || OtherMI.isCall() ||
950 OtherMI.isBranch() || OtherMI.isTerminator())
951 // Don't move pass calls, etc.
953 for (const MachineOperand &MO : OtherMI.operands()) {
956 unsigned MOReg = MO.getReg();
960 if (regOverlapsSet(Uses, MOReg, TRI))
961 // Physical register use would be clobbered.
963 if (!MO.isDead() && regOverlapsSet(Defs, MOReg, TRI))
964 // May clobber a physical register def.
965 // FIXME: This may be too conservative. It's ok if the instruction
966 // is sunken completely below the use.
969 if (regOverlapsSet(Defs, MOReg, TRI))
972 MO.isKill() || (LIS && isPlainlyKilled(&OtherMI, MOReg, LIS));
973 if (MOReg != Reg && ((isKill && regOverlapsSet(Uses, MOReg, TRI)) ||
974 regOverlapsSet(Kills, MOReg, TRI)))
975 // Don't want to extend other live ranges and update kills.
977 if (MOReg == Reg && !isKill)
978 // We can't schedule across a use of the register in question.
980 // Ensure that if this is register in question, its the kill we expect.
981 assert((MOReg != Reg || &OtherMI == KillMI) &&
982 "Found multiple kills of a register in a basic block");
987 // Move debug info as well.
988 while (Begin != MBB->begin() && std::prev(Begin)->isDebugValue())
992 MachineBasicBlock::iterator InsertPos = KillPos;
994 // We have to move the copies first so that the MBB is still well-formed
995 // when calling handleMove().
996 for (MachineBasicBlock::iterator MBBI = AfterMI; MBBI != End;) {
997 auto CopyMI = MBBI++;
998 MBB->splice(InsertPos, MBB, CopyMI);
999 LIS->handleMove(*CopyMI);
1002 End = std::next(MachineBasicBlock::iterator(MI));
1005 // Copies following MI may have been moved as well.
1006 MBB->splice(InsertPos, MBB, Begin, End);
1007 DistanceMap.erase(DI);
1009 // Update live variables
1011 LIS->handleMove(*MI);
1013 LV->removeVirtualRegisterKilled(Reg, *KillMI);
1014 LV->addVirtualRegisterKilled(Reg, *MI);
1017 DEBUG(dbgs() << "\trescheduled below kill: " << *KillMI);
1021 /// Return true if the re-scheduling will put the given instruction too close
1022 /// to the defs of its register dependencies.
1023 bool TwoAddressInstructionPass::isDefTooClose(unsigned Reg, unsigned Dist,
1025 for (MachineInstr &DefMI : MRI->def_instructions(Reg)) {
1026 if (DefMI.getParent() != MBB || DefMI.isCopy() || DefMI.isCopyLike())
1029 return true; // MI is defining something KillMI uses
1030 DenseMap<MachineInstr*, unsigned>::iterator DDI = DistanceMap.find(&DefMI);
1031 if (DDI == DistanceMap.end())
1032 return true; // Below MI
1033 unsigned DefDist = DDI->second;
1034 assert(Dist > DefDist && "Visited def already?");
1035 if (TII->getInstrLatency(InstrItins, DefMI) > (Dist - DefDist))
1041 /// If there is one more local instruction that reads 'Reg' and it kills 'Reg,
1042 /// consider moving the kill instruction above the current two-address
1043 /// instruction in order to eliminate the need for the copy.
1044 bool TwoAddressInstructionPass::
1045 rescheduleKillAboveMI(MachineBasicBlock::iterator &mi,
1046 MachineBasicBlock::iterator &nmi,
1048 // Bail immediately if we don't have LV or LIS available. We use them to find
1049 // kills efficiently.
1053 MachineInstr *MI = &*mi;
1054 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
1055 if (DI == DistanceMap.end())
1056 // Must be created from unfolded load. Don't waste time trying this.
1059 MachineInstr *KillMI = nullptr;
1061 LiveInterval &LI = LIS->getInterval(Reg);
1062 assert(LI.end() != LI.begin() &&
1063 "Reg should not have empty live interval.");
1065 SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot();
1066 LiveInterval::const_iterator I = LI.find(MBBEndIdx);
1067 if (I != LI.end() && I->start < MBBEndIdx)
1071 KillMI = LIS->getInstructionFromIndex(I->end);
1073 KillMI = LV->getVarInfo(Reg).findKill(MBB);
1075 if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike())
1076 // Don't mess with copies, they may be coalesced later.
1080 if (isTwoAddrUse(*KillMI, Reg, DstReg))
1083 bool SeenStore = true;
1084 if (!KillMI->isSafeToMove(AA, SeenStore))
1087 SmallSet<unsigned, 2> Uses;
1088 SmallSet<unsigned, 2> Kills;
1089 SmallSet<unsigned, 2> Defs;
1090 SmallSet<unsigned, 2> LiveDefs;
1091 for (const MachineOperand &MO : KillMI->operands()) {
1094 unsigned MOReg = MO.getReg();
1098 if (isDefTooClose(MOReg, DI->second, MI))
1100 bool isKill = MO.isKill() || (LIS && isPlainlyKilled(KillMI, MOReg, LIS));
1101 if (MOReg == Reg && !isKill)
1104 if (isKill && MOReg != Reg)
1105 Kills.insert(MOReg);
1106 } else if (TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1109 LiveDefs.insert(MOReg);
1113 // Check if the reschedule will not break depedencies.
1114 unsigned NumVisited = 0;
1115 for (MachineInstr &OtherMI :
1116 make_range(mi, MachineBasicBlock::iterator(KillMI))) {
1117 // DBG_VALUE cannot be counted against the limit.
1118 if (OtherMI.isDebugValue())
1120 if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
1123 if (OtherMI.hasUnmodeledSideEffects() || OtherMI.isCall() ||
1124 OtherMI.isBranch() || OtherMI.isTerminator())
1125 // Don't move pass calls, etc.
1127 SmallVector<unsigned, 2> OtherDefs;
1128 for (const MachineOperand &MO : OtherMI.operands()) {
1131 unsigned MOReg = MO.getReg();
1135 if (Defs.count(MOReg))
1136 // Moving KillMI can clobber the physical register if the def has
1139 if (Kills.count(MOReg))
1140 // Don't want to extend other live ranges and update kills.
1142 if (&OtherMI != MI && MOReg == Reg &&
1143 !(MO.isKill() || (LIS && isPlainlyKilled(&OtherMI, MOReg, LIS))))
1144 // We can't schedule across a use of the register in question.
1147 OtherDefs.push_back(MOReg);
1151 for (unsigned i = 0, e = OtherDefs.size(); i != e; ++i) {
1152 unsigned MOReg = OtherDefs[i];
1153 if (Uses.count(MOReg))
1155 if (TargetRegisterInfo::isPhysicalRegister(MOReg) &&
1156 LiveDefs.count(MOReg))
1158 // Physical register def is seen.
1163 // Move the old kill above MI, don't forget to move debug info as well.
1164 MachineBasicBlock::iterator InsertPos = mi;
1165 while (InsertPos != MBB->begin() && std::prev(InsertPos)->isDebugValue())
1167 MachineBasicBlock::iterator From = KillMI;
1168 MachineBasicBlock::iterator To = std::next(From);
1169 while (std::prev(From)->isDebugValue())
1171 MBB->splice(InsertPos, MBB, From, To);
1173 nmi = std::prev(InsertPos); // Backtrack so we process the moved instr.
1174 DistanceMap.erase(DI);
1176 // Update live variables
1178 LIS->handleMove(*KillMI);
1180 LV->removeVirtualRegisterKilled(Reg, *KillMI);
1181 LV->addVirtualRegisterKilled(Reg, *MI);
1184 DEBUG(dbgs() << "\trescheduled kill: " << *KillMI);
1188 /// Tries to commute the operand 'BaseOpIdx' and some other operand in the
1189 /// given machine instruction to improve opportunities for coalescing and
1190 /// elimination of a register to register copy.
1192 /// 'DstOpIdx' specifies the index of MI def operand.
1193 /// 'BaseOpKilled' specifies if the register associated with 'BaseOpIdx'
1194 /// operand is killed by the given instruction.
1195 /// The 'Dist' arguments provides the distance of MI from the start of the
1196 /// current basic block and it is used to determine if it is profitable
1197 /// to commute operands in the instruction.
1199 /// Returns true if the transformation happened. Otherwise, returns false.
1200 bool TwoAddressInstructionPass::tryInstructionCommute(MachineInstr *MI,
1205 if (!MI->isCommutable())
1208 unsigned DstOpReg = MI->getOperand(DstOpIdx).getReg();
1209 unsigned BaseOpReg = MI->getOperand(BaseOpIdx).getReg();
1210 unsigned OpsNum = MI->getDesc().getNumOperands();
1211 unsigned OtherOpIdx = MI->getDesc().getNumDefs();
1212 for (; OtherOpIdx < OpsNum; OtherOpIdx++) {
1213 // The call of findCommutedOpIndices below only checks if BaseOpIdx
1214 // and OtherOpIdx are commutable, it does not really search for
1215 // other commutable operands and does not change the values of passed
1217 if (OtherOpIdx == BaseOpIdx || !MI->getOperand(OtherOpIdx).isReg() ||
1218 !TII->findCommutedOpIndices(*MI, BaseOpIdx, OtherOpIdx))
1221 unsigned OtherOpReg = MI->getOperand(OtherOpIdx).getReg();
1222 bool AggressiveCommute = false;
1224 // If OtherOp dies but BaseOp does not, swap the OtherOp and BaseOp
1225 // operands. This makes the live ranges of DstOp and OtherOp joinable.
1227 !BaseOpKilled && isKilled(*MI, OtherOpReg, MRI, TII, LIS, false);
1230 isProfitableToCommute(DstOpReg, BaseOpReg, OtherOpReg, MI, Dist)) {
1232 AggressiveCommute = true;
1235 // If it's profitable to commute, try to do so.
1236 if (DoCommute && commuteInstruction(MI, DstOpIdx, BaseOpIdx, OtherOpIdx,
1239 if (AggressiveCommute)
1247 /// For the case where an instruction has a single pair of tied register
1248 /// operands, attempt some transformations that may either eliminate the tied
1249 /// operands or improve the opportunities for coalescing away the register copy.
1250 /// Returns true if no copy needs to be inserted to untie mi's operands
1251 /// (either because they were untied, or because mi was rescheduled, and will
1252 /// be visited again later). If the shouldOnlyCommute flag is true, only
1253 /// instruction commutation is attempted.
1254 bool TwoAddressInstructionPass::
1255 tryInstructionTransform(MachineBasicBlock::iterator &mi,
1256 MachineBasicBlock::iterator &nmi,
1257 unsigned SrcIdx, unsigned DstIdx,
1258 unsigned Dist, bool shouldOnlyCommute) {
1259 if (OptLevel == CodeGenOpt::None)
1262 MachineInstr &MI = *mi;
1263 unsigned regA = MI.getOperand(DstIdx).getReg();
1264 unsigned regB = MI.getOperand(SrcIdx).getReg();
1266 assert(TargetRegisterInfo::isVirtualRegister(regB) &&
1267 "cannot make instruction into two-address form");
1268 bool regBKilled = isKilled(MI, regB, MRI, TII, LIS, true);
1270 if (TargetRegisterInfo::isVirtualRegister(regA))
1273 bool Commuted = tryInstructionCommute(&MI, DstIdx, SrcIdx, regBKilled, Dist);
1275 // If the instruction is convertible to 3 Addr, instead
1276 // of returning try 3 Addr transformation aggresively and
1277 // use this variable to check later. Because it might be better.
1278 // For example, we can just use `leal (%rsi,%rdi), %eax` and `ret`
1279 // instead of the following code.
1283 if (Commuted && !MI.isConvertibleTo3Addr())
1286 if (shouldOnlyCommute)
1289 // If there is one more use of regB later in the same MBB, consider
1290 // re-schedule this MI below it.
1291 if (!Commuted && EnableRescheduling && rescheduleMIBelowKill(mi, nmi, regB)) {
1296 // If we commuted, regB may have changed so we should re-sample it to avoid
1297 // confusing the three address conversion below.
1299 regB = MI.getOperand(SrcIdx).getReg();
1300 regBKilled = isKilled(MI, regB, MRI, TII, LIS, true);
1303 if (MI.isConvertibleTo3Addr()) {
1304 // This instruction is potentially convertible to a true
1305 // three-address instruction. Check if it is profitable.
1306 if (!regBKilled || isProfitableToConv3Addr(regA, regB)) {
1307 // Try to convert it.
1308 if (convertInstTo3Addr(mi, nmi, regA, regB, Dist)) {
1309 ++NumConvertedTo3Addr;
1310 return true; // Done with this instruction.
1315 // Return if it is commuted but 3 addr conversion is failed.
1319 // If there is one more use of regB later in the same MBB, consider
1320 // re-schedule it before this MI if it's legal.
1321 if (EnableRescheduling && rescheduleKillAboveMI(mi, nmi, regB)) {
1326 // If this is an instruction with a load folded into it, try unfolding
1327 // the load, e.g. avoid this:
1329 // addq (%rax), %rcx
1330 // in favor of this:
1331 // movq (%rax), %rcx
1333 // because it's preferable to schedule a load than a register copy.
1334 if (MI.mayLoad() && !regBKilled) {
1335 // Determine if a load can be unfolded.
1336 unsigned LoadRegIndex;
1338 TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(),
1339 /*UnfoldLoad=*/true,
1340 /*UnfoldStore=*/false,
1343 const MCInstrDesc &UnfoldMCID = TII->get(NewOpc);
1344 if (UnfoldMCID.getNumDefs() == 1) {
1346 DEBUG(dbgs() << "2addr: UNFOLDING: " << MI);
1347 const TargetRegisterClass *RC =
1348 TRI->getAllocatableClass(
1349 TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI, *MF));
1350 unsigned Reg = MRI->createVirtualRegister(RC);
1351 SmallVector<MachineInstr *, 2> NewMIs;
1352 if (!TII->unfoldMemoryOperand(*MF, MI, Reg,
1353 /*UnfoldLoad=*/true,
1354 /*UnfoldStore=*/false, NewMIs)) {
1355 DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
1358 assert(NewMIs.size() == 2 &&
1359 "Unfolded a load into multiple instructions!");
1360 // The load was previously folded, so this is the only use.
1361 NewMIs[1]->addRegisterKilled(Reg, TRI);
1363 // Tentatively insert the instructions into the block so that they
1364 // look "normal" to the transformation logic.
1365 MBB->insert(mi, NewMIs[0]);
1366 MBB->insert(mi, NewMIs[1]);
1368 DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0]
1369 << "2addr: NEW INST: " << *NewMIs[1]);
1371 // Transform the instruction, now that it no longer has a load.
1372 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA);
1373 unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB);
1374 MachineBasicBlock::iterator NewMI = NewMIs[1];
1375 bool TransformResult =
1376 tryInstructionTransform(NewMI, mi, NewSrcIdx, NewDstIdx, Dist, true);
1377 (void)TransformResult;
1378 assert(!TransformResult &&
1379 "tryInstructionTransform() should return false.");
1380 if (NewMIs[1]->getOperand(NewSrcIdx).isKill()) {
1381 // Success, or at least we made an improvement. Keep the unfolded
1382 // instructions and discard the original.
1384 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1385 MachineOperand &MO = MI.getOperand(i);
1387 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
1390 if (NewMIs[0]->killsRegister(MO.getReg()))
1391 LV->replaceKillInstruction(MO.getReg(), MI, *NewMIs[0]);
1393 assert(NewMIs[1]->killsRegister(MO.getReg()) &&
1394 "Kill missing after load unfold!");
1395 LV->replaceKillInstruction(MO.getReg(), MI, *NewMIs[1]);
1398 } else if (LV->removeVirtualRegisterDead(MO.getReg(), MI)) {
1399 if (NewMIs[1]->registerDefIsDead(MO.getReg()))
1400 LV->addVirtualRegisterDead(MO.getReg(), *NewMIs[1]);
1402 assert(NewMIs[0]->registerDefIsDead(MO.getReg()) &&
1403 "Dead flag missing after load unfold!");
1404 LV->addVirtualRegisterDead(MO.getReg(), *NewMIs[0]);
1409 LV->addVirtualRegisterKilled(Reg, *NewMIs[1]);
1412 SmallVector<unsigned, 4> OrigRegs;
1414 for (const MachineOperand &MO : MI.operands()) {
1416 OrigRegs.push_back(MO.getReg());
1420 MI.eraseFromParent();
1422 // Update LiveIntervals.
1424 MachineBasicBlock::iterator Begin(NewMIs[0]);
1425 MachineBasicBlock::iterator End(NewMIs[1]);
1426 LIS->repairIntervalsInRange(MBB, Begin, End, OrigRegs);
1431 // Transforming didn't eliminate the tie and didn't lead to an
1432 // improvement. Clean up the unfolded instructions and keep the
1434 DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
1435 NewMIs[0]->eraseFromParent();
1436 NewMIs[1]->eraseFromParent();
1445 // Collect tied operands of MI that need to be handled.
1446 // Rewrite trivial cases immediately.
1447 // Return true if any tied operands where found, including the trivial ones.
1448 bool TwoAddressInstructionPass::
1449 collectTiedOperands(MachineInstr *MI, TiedOperandMap &TiedOperands) {
1450 const MCInstrDesc &MCID = MI->getDesc();
1451 bool AnyOps = false;
1452 unsigned NumOps = MI->getNumOperands();
1454 for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) {
1455 unsigned DstIdx = 0;
1456 if (!MI->isRegTiedToDefOperand(SrcIdx, &DstIdx))
1459 MachineOperand &SrcMO = MI->getOperand(SrcIdx);
1460 MachineOperand &DstMO = MI->getOperand(DstIdx);
1461 unsigned SrcReg = SrcMO.getReg();
1462 unsigned DstReg = DstMO.getReg();
1463 // Tied constraint already satisfied?
1464 if (SrcReg == DstReg)
1467 assert(SrcReg && SrcMO.isUse() && "two address instruction invalid");
1469 // Deal with undef uses immediately - simply rewrite the src operand.
1470 if (SrcMO.isUndef() && !DstMO.getSubReg()) {
1471 // Constrain the DstReg register class if required.
1472 if (TargetRegisterInfo::isVirtualRegister(DstReg))
1473 if (const TargetRegisterClass *RC = TII->getRegClass(MCID, SrcIdx,
1475 MRI->constrainRegClass(DstReg, RC);
1476 SrcMO.setReg(DstReg);
1478 DEBUG(dbgs() << "\t\trewrite undef:\t" << *MI);
1481 TiedOperands[SrcReg].push_back(std::make_pair(SrcIdx, DstIdx));
1486 // Process a list of tied MI operands that all use the same source register.
1487 // The tied pairs are of the form (SrcIdx, DstIdx).
1489 TwoAddressInstructionPass::processTiedPairs(MachineInstr *MI,
1490 TiedPairList &TiedPairs,
1492 bool IsEarlyClobber = false;
1493 for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
1494 const MachineOperand &DstMO = MI->getOperand(TiedPairs[tpi].second);
1495 IsEarlyClobber |= DstMO.isEarlyClobber();
1498 bool RemovedKillFlag = false;
1499 bool AllUsesCopied = true;
1500 unsigned LastCopiedReg = 0;
1501 SlotIndex LastCopyIdx;
1503 unsigned SubRegB = 0;
1504 for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
1505 unsigned SrcIdx = TiedPairs[tpi].first;
1506 unsigned DstIdx = TiedPairs[tpi].second;
1508 const MachineOperand &DstMO = MI->getOperand(DstIdx);
1509 unsigned RegA = DstMO.getReg();
1511 // Grab RegB from the instruction because it may have changed if the
1512 // instruction was commuted.
1513 RegB = MI->getOperand(SrcIdx).getReg();
1514 SubRegB = MI->getOperand(SrcIdx).getSubReg();
1517 // The register is tied to multiple destinations (or else we would
1518 // not have continued this far), but this use of the register
1519 // already matches the tied destination. Leave it.
1520 AllUsesCopied = false;
1523 LastCopiedReg = RegA;
1525 assert(TargetRegisterInfo::isVirtualRegister(RegB) &&
1526 "cannot make instruction into two-address form");
1529 // First, verify that we don't have a use of "a" in the instruction
1530 // (a = b + a for example) because our transformation will not
1531 // work. This should never occur because we are in SSA form.
1532 for (unsigned i = 0; i != MI->getNumOperands(); ++i)
1533 assert(i == DstIdx ||
1534 !MI->getOperand(i).isReg() ||
1535 MI->getOperand(i).getReg() != RegA);
1539 MachineInstrBuilder MIB = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1540 TII->get(TargetOpcode::COPY), RegA);
1541 // If this operand is folding a truncation, the truncation now moves to the
1542 // copy so that the register classes remain valid for the operands.
1543 MIB.addReg(RegB, 0, SubRegB);
1544 const TargetRegisterClass *RC = MRI->getRegClass(RegB);
1546 if (TargetRegisterInfo::isVirtualRegister(RegA)) {
1547 assert(TRI->getMatchingSuperRegClass(RC, MRI->getRegClass(RegA),
1549 "tied subregister must be a truncation");
1550 // The superreg class will not be used to constrain the subreg class.
1554 assert(TRI->getMatchingSuperReg(RegA, SubRegB, MRI->getRegClass(RegB))
1555 && "tied subregister must be a truncation");
1559 // Update DistanceMap.
1560 MachineBasicBlock::iterator PrevMI = MI;
1562 DistanceMap.insert(std::make_pair(&*PrevMI, Dist));
1563 DistanceMap[MI] = ++Dist;
1566 LastCopyIdx = LIS->InsertMachineInstrInMaps(*PrevMI).getRegSlot();
1568 if (TargetRegisterInfo::isVirtualRegister(RegA)) {
1569 LiveInterval &LI = LIS->getInterval(RegA);
1570 VNInfo *VNI = LI.getNextValue(LastCopyIdx, LIS->getVNInfoAllocator());
1572 LIS->getInstructionIndex(*MI).getRegSlot(IsEarlyClobber);
1573 LI.addSegment(LiveInterval::Segment(LastCopyIdx, endIdx, VNI));
1577 DEBUG(dbgs() << "\t\tprepend:\t" << *MIB);
1579 MachineOperand &MO = MI->getOperand(SrcIdx);
1580 assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() &&
1581 "inconsistent operand info for 2-reg pass");
1583 MO.setIsKill(false);
1584 RemovedKillFlag = true;
1587 // Make sure regA is a legal regclass for the SrcIdx operand.
1588 if (TargetRegisterInfo::isVirtualRegister(RegA) &&
1589 TargetRegisterInfo::isVirtualRegister(RegB))
1590 MRI->constrainRegClass(RegA, RC);
1592 // The getMatchingSuper asserts guarantee that the register class projected
1593 // by SubRegB is compatible with RegA with no subregister. So regardless of
1594 // whether the dest oper writes a subreg, the source oper should not.
1597 // Propagate SrcRegMap.
1598 SrcRegMap[RegA] = RegB;
1601 if (AllUsesCopied) {
1602 if (!IsEarlyClobber) {
1603 // Replace other (un-tied) uses of regB with LastCopiedReg.
1604 for (MachineOperand &MO : MI->operands()) {
1605 if (MO.isReg() && MO.getReg() == RegB &&
1608 MO.setIsKill(false);
1609 RemovedKillFlag = true;
1611 MO.setReg(LastCopiedReg);
1612 MO.setSubReg(MO.getSubReg());
1617 // Update live variables for regB.
1618 if (RemovedKillFlag && LV && LV->getVarInfo(RegB).removeKill(*MI)) {
1619 MachineBasicBlock::iterator PrevMI = MI;
1621 LV->addVirtualRegisterKilled(RegB, *PrevMI);
1624 // Update LiveIntervals.
1626 LiveInterval &LI = LIS->getInterval(RegB);
1627 SlotIndex MIIdx = LIS->getInstructionIndex(*MI);
1628 LiveInterval::const_iterator I = LI.find(MIIdx);
1629 assert(I != LI.end() && "RegB must be live-in to use.");
1631 SlotIndex UseIdx = MIIdx.getRegSlot(IsEarlyClobber);
1632 if (I->end == UseIdx)
1633 LI.removeSegment(LastCopyIdx, UseIdx);
1635 } else if (RemovedKillFlag) {
1636 // Some tied uses of regB matched their destination registers, so
1637 // regB is still used in this instruction, but a kill flag was
1638 // removed from a different tied use of regB, so now we need to add
1639 // a kill flag to one of the remaining uses of regB.
1640 for (MachineOperand &MO : MI->operands()) {
1641 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {
1649 /// Reduce two-address instructions to two operands.
1650 bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) {
1652 const TargetMachine &TM = MF->getTarget();
1653 MRI = &MF->getRegInfo();
1654 TII = MF->getSubtarget().getInstrInfo();
1655 TRI = MF->getSubtarget().getRegisterInfo();
1656 InstrItins = MF->getSubtarget().getInstrItineraryData();
1657 LV = getAnalysisIfAvailable<LiveVariables>();
1658 LIS = getAnalysisIfAvailable<LiveIntervals>();
1659 if (auto *AAPass = getAnalysisIfAvailable<AAResultsWrapperPass>())
1660 AA = &AAPass->getAAResults();
1663 OptLevel = TM.getOptLevel();
1664 // Disable optimizations if requested. We cannot skip the whole pass as some
1665 // fixups are necessary for correctness.
1666 if (skipFunction(Func.getFunction()))
1667 OptLevel = CodeGenOpt::None;
1669 bool MadeChange = false;
1671 DEBUG(dbgs() << "********** REWRITING TWO-ADDR INSTRS **********\n");
1672 DEBUG(dbgs() << "********** Function: "
1673 << MF->getName() << '\n');
1675 // This pass takes the function out of SSA form.
1678 TiedOperandMap TiedOperands;
1679 for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
1680 MBBI != MBBE; ++MBBI) {
1683 DistanceMap.clear();
1688 for (MachineBasicBlock::iterator mi = MBB->begin(), me = MBB->end();
1690 MachineBasicBlock::iterator nmi = std::next(mi);
1691 // Don't revisit an instruction previously converted by target. It may
1692 // contain undef register operands (%noreg), which are not handled.
1693 if (mi->isDebugValue() || SunkInstrs.count(&*mi)) {
1698 // Expand REG_SEQUENCE instructions. This will position mi at the first
1699 // expanded instruction.
1700 if (mi->isRegSequence())
1701 eliminateRegSequence(mi);
1703 DistanceMap.insert(std::make_pair(&*mi, ++Dist));
1707 // First scan through all the tied register uses in this instruction
1708 // and record a list of pairs of tied operands for each register.
1709 if (!collectTiedOperands(&*mi, TiedOperands)) {
1714 ++NumTwoAddressInstrs;
1716 DEBUG(dbgs() << '\t' << *mi);
1718 // If the instruction has a single pair of tied operands, try some
1719 // transformations that may either eliminate the tied operands or
1720 // improve the opportunities for coalescing away the register copy.
1721 if (TiedOperands.size() == 1) {
1722 SmallVectorImpl<std::pair<unsigned, unsigned>> &TiedPairs
1723 = TiedOperands.begin()->second;
1724 if (TiedPairs.size() == 1) {
1725 unsigned SrcIdx = TiedPairs[0].first;
1726 unsigned DstIdx = TiedPairs[0].second;
1727 unsigned SrcReg = mi->getOperand(SrcIdx).getReg();
1728 unsigned DstReg = mi->getOperand(DstIdx).getReg();
1729 if (SrcReg != DstReg &&
1730 tryInstructionTransform(mi, nmi, SrcIdx, DstIdx, Dist, false)) {
1731 // The tied operands have been eliminated or shifted further down
1732 // the block to ease elimination. Continue processing with 'nmi'.
1733 TiedOperands.clear();
1740 // Now iterate over the information collected above.
1741 for (auto &TO : TiedOperands) {
1742 processTiedPairs(&*mi, TO.second, Dist);
1743 DEBUG(dbgs() << "\t\trewrite to:\t" << *mi);
1746 // Rewrite INSERT_SUBREG as COPY now that we no longer need SSA form.
1747 if (mi->isInsertSubreg()) {
1748 // From %reg = INSERT_SUBREG %reg, %subreg, subidx
1749 // To %reg:subidx = COPY %subreg
1750 unsigned SubIdx = mi->getOperand(3).getImm();
1751 mi->RemoveOperand(3);
1752 assert(mi->getOperand(0).getSubReg() == 0 && "Unexpected subreg idx");
1753 mi->getOperand(0).setSubReg(SubIdx);
1754 mi->getOperand(0).setIsUndef(mi->getOperand(1).isUndef());
1755 mi->RemoveOperand(1);
1756 mi->setDesc(TII->get(TargetOpcode::COPY));
1757 DEBUG(dbgs() << "\t\tconvert to:\t" << *mi);
1760 // Clear TiedOperands here instead of at the top of the loop
1761 // since most instructions do not have tied operands.
1762 TiedOperands.clear();
1768 MF->verify(this, "After two-address instruction pass");
1773 /// Eliminate a REG_SEQUENCE instruction as part of the de-ssa process.
1775 /// The instruction is turned into a sequence of sub-register copies:
1777 /// %dst = REG_SEQUENCE %v1, ssub0, %v2, ssub1
1781 /// undef %dst:ssub0 = COPY %v1
1782 /// %dst:ssub1 = COPY %v2
1783 void TwoAddressInstructionPass::
1784 eliminateRegSequence(MachineBasicBlock::iterator &MBBI) {
1785 MachineInstr &MI = *MBBI;
1786 unsigned DstReg = MI.getOperand(0).getReg();
1787 if (MI.getOperand(0).getSubReg() ||
1788 TargetRegisterInfo::isPhysicalRegister(DstReg) ||
1789 !(MI.getNumOperands() & 1)) {
1790 DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << MI);
1791 llvm_unreachable(nullptr);
1794 SmallVector<unsigned, 4> OrigRegs;
1796 OrigRegs.push_back(MI.getOperand(0).getReg());
1797 for (unsigned i = 1, e = MI.getNumOperands(); i < e; i += 2)
1798 OrigRegs.push_back(MI.getOperand(i).getReg());
1801 bool DefEmitted = false;
1802 for (unsigned i = 1, e = MI.getNumOperands(); i < e; i += 2) {
1803 MachineOperand &UseMO = MI.getOperand(i);
1804 unsigned SrcReg = UseMO.getReg();
1805 unsigned SubIdx = MI.getOperand(i+1).getImm();
1806 // Nothing needs to be inserted for undef operands.
1807 if (UseMO.isUndef())
1810 // Defer any kill flag to the last operand using SrcReg. Otherwise, we
1811 // might insert a COPY that uses SrcReg after is was killed.
1812 bool isKill = UseMO.isKill();
1814 for (unsigned j = i + 2; j < e; j += 2)
1815 if (MI.getOperand(j).getReg() == SrcReg) {
1816 MI.getOperand(j).setIsKill();
1817 UseMO.setIsKill(false);
1822 // Insert the sub-register copy.
1823 MachineInstr *CopyMI = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
1824 TII->get(TargetOpcode::COPY))
1825 .addReg(DstReg, RegState::Define, SubIdx)
1828 // The first def needs an undef flag because there is no live register
1831 CopyMI->getOperand(0).setIsUndef(true);
1832 // Return an iterator pointing to the first inserted instr.
1837 // Update LiveVariables' kill info.
1838 if (LV && isKill && !TargetRegisterInfo::isPhysicalRegister(SrcReg))
1839 LV->replaceKillInstruction(SrcReg, MI, *CopyMI);
1841 DEBUG(dbgs() << "Inserted: " << *CopyMI);
1844 MachineBasicBlock::iterator EndMBBI =
1845 std::next(MachineBasicBlock::iterator(MI));
1848 DEBUG(dbgs() << "Turned: " << MI << " into an IMPLICIT_DEF");
1849 MI.setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
1850 for (int j = MI.getNumOperands() - 1, ee = 0; j > ee; --j)
1851 MI.RemoveOperand(j);
1853 DEBUG(dbgs() << "Eliminated: " << MI);
1854 MI.eraseFromParent();
1857 // Udpate LiveIntervals.
1859 LIS->repairIntervalsInRange(MBB, MBBI, EndMBBI, OrigRegs);