1 //===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the VirtRegMap class.
12 // It also contains implementations of the Spiller interface, which, given a
13 // virtual register map and a machine function, eliminates all virtual
14 // references by replacing them with physical register references - adding spill
17 //===----------------------------------------------------------------------===//
19 #include "llvm/CodeGen/VirtRegMap.h"
20 #include "LiveDebugVariables.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
24 #include "llvm/CodeGen/LiveStackAnalysis.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/Passes.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/Support/Compiler.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetRegisterInfo.h"
37 #include "llvm/Target/TargetSubtargetInfo.h"
41 #define DEBUG_TYPE "regalloc"
43 STATISTIC(NumSpillSlots, "Number of spill slots allocated");
44 STATISTIC(NumIdCopies, "Number of identity moves eliminated after rewriting");
46 //===----------------------------------------------------------------------===//
47 // VirtRegMap implementation
48 //===----------------------------------------------------------------------===//
50 char VirtRegMap::ID = 0;
52 INITIALIZE_PASS(VirtRegMap, "virtregmap", "Virtual Register Map", false, false)
54 bool VirtRegMap::runOnMachineFunction(MachineFunction &mf) {
55 MRI = &mf.getRegInfo();
56 TII = mf.getSubtarget().getInstrInfo();
57 TRI = mf.getSubtarget().getRegisterInfo();
61 Virt2StackSlotMap.clear();
62 Virt2SplitMap.clear();
68 void VirtRegMap::grow() {
69 unsigned NumRegs = MF->getRegInfo().getNumVirtRegs();
70 Virt2PhysMap.resize(NumRegs);
71 Virt2StackSlotMap.resize(NumRegs);
72 Virt2SplitMap.resize(NumRegs);
75 void VirtRegMap::assignVirt2Phys(unsigned virtReg, MCPhysReg physReg) {
76 assert(TargetRegisterInfo::isVirtualRegister(virtReg) &&
77 TargetRegisterInfo::isPhysicalRegister(physReg));
78 assert(Virt2PhysMap[virtReg] == NO_PHYS_REG &&
79 "attempt to assign physical register to already mapped "
81 assert(!getRegInfo().isReserved(physReg) &&
82 "Attempt to map virtReg to a reserved physReg");
83 Virt2PhysMap[virtReg] = physReg;
86 unsigned VirtRegMap::createSpillSlot(const TargetRegisterClass *RC) {
87 unsigned Size = TRI->getSpillSize(*RC);
88 unsigned Align = TRI->getSpillAlignment(*RC);
89 int SS = MF->getFrameInfo().CreateSpillStackObject(Size, Align);
94 bool VirtRegMap::hasPreferredPhys(unsigned VirtReg) {
95 unsigned Hint = MRI->getSimpleHint(VirtReg);
98 if (TargetRegisterInfo::isVirtualRegister(Hint))
100 return getPhys(VirtReg) == Hint;
103 bool VirtRegMap::hasKnownPreference(unsigned VirtReg) {
104 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(VirtReg);
105 if (TargetRegisterInfo::isPhysicalRegister(Hint.second))
107 if (TargetRegisterInfo::isVirtualRegister(Hint.second))
108 return hasPhys(Hint.second);
112 int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
113 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
114 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
115 "attempt to assign stack slot to already spilled register");
116 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
117 return Virt2StackSlotMap[virtReg] = createSpillSlot(RC);
120 void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) {
121 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
122 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
123 "attempt to assign stack slot to already spilled register");
125 (SS >= MF->getFrameInfo().getObjectIndexBegin())) &&
126 "illegal fixed frame index");
127 Virt2StackSlotMap[virtReg] = SS;
130 void VirtRegMap::print(raw_ostream &OS, const Module*) const {
131 OS << "********** REGISTER MAP **********\n";
132 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
133 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
134 if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG) {
135 OS << '[' << PrintReg(Reg, TRI) << " -> "
136 << PrintReg(Virt2PhysMap[Reg], TRI) << "] "
137 << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n";
141 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
142 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
143 if (Virt2StackSlotMap[Reg] != VirtRegMap::NO_STACK_SLOT) {
144 OS << '[' << PrintReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg]
145 << "] " << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n";
151 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
152 LLVM_DUMP_METHOD void VirtRegMap::dump() const {
157 //===----------------------------------------------------------------------===//
159 //===----------------------------------------------------------------------===//
161 // The VirtRegRewriter is the last of the register allocator passes.
162 // It rewrites virtual registers to physical registers as specified in the
163 // VirtRegMap analysis. It also updates live-in information on basic blocks
164 // according to LiveIntervals.
167 class VirtRegRewriter : public MachineFunctionPass {
169 const TargetMachine *TM;
170 const TargetRegisterInfo *TRI;
171 const TargetInstrInfo *TII;
172 MachineRegisterInfo *MRI;
173 SlotIndexes *Indexes;
178 void addMBBLiveIns();
179 bool readsUndefSubreg(const MachineOperand &MO) const;
180 void addLiveInsForSubRanges(const LiveInterval &LI, unsigned PhysReg) const;
181 void handleIdentityCopy(MachineInstr &MI) const;
182 void expandCopyBundle(MachineInstr &MI) const;
183 bool subRegLiveThrough(const MachineInstr &MI, unsigned SuperPhysReg) const;
187 VirtRegRewriter() : MachineFunctionPass(ID) {}
189 void getAnalysisUsage(AnalysisUsage &AU) const override;
191 bool runOnMachineFunction(MachineFunction&) override;
192 MachineFunctionProperties getSetProperties() const override {
193 return MachineFunctionProperties().set(
194 MachineFunctionProperties::Property::NoVRegs);
197 } // end anonymous namespace
199 char &llvm::VirtRegRewriterID = VirtRegRewriter::ID;
201 INITIALIZE_PASS_BEGIN(VirtRegRewriter, "virtregrewriter",
202 "Virtual Register Rewriter", false, false)
203 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
204 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
205 INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
206 INITIALIZE_PASS_DEPENDENCY(LiveStacks)
207 INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
208 INITIALIZE_PASS_END(VirtRegRewriter, "virtregrewriter",
209 "Virtual Register Rewriter", false, false)
211 char VirtRegRewriter::ID = 0;
213 void VirtRegRewriter::getAnalysisUsage(AnalysisUsage &AU) const {
214 AU.setPreservesCFG();
215 AU.addRequired<LiveIntervals>();
216 AU.addRequired<SlotIndexes>();
217 AU.addPreserved<SlotIndexes>();
218 AU.addRequired<LiveDebugVariables>();
219 AU.addRequired<LiveStacks>();
220 AU.addPreserved<LiveStacks>();
221 AU.addRequired<VirtRegMap>();
222 MachineFunctionPass::getAnalysisUsage(AU);
225 bool VirtRegRewriter::runOnMachineFunction(MachineFunction &fn) {
227 TM = &MF->getTarget();
228 TRI = MF->getSubtarget().getRegisterInfo();
229 TII = MF->getSubtarget().getInstrInfo();
230 MRI = &MF->getRegInfo();
231 Indexes = &getAnalysis<SlotIndexes>();
232 LIS = &getAnalysis<LiveIntervals>();
233 VRM = &getAnalysis<VirtRegMap>();
234 DEBUG(dbgs() << "********** REWRITE VIRTUAL REGISTERS **********\n"
235 << "********** Function: "
236 << MF->getName() << '\n');
239 // Add kill flags while we still have virtual registers.
240 LIS->addKillFlags(VRM);
242 // Live-in lists on basic blocks are required for physregs.
245 // Rewrite virtual registers.
248 // Write out new DBG_VALUE instructions.
249 getAnalysis<LiveDebugVariables>().emitDebugValues(VRM);
251 // All machine operands and other references to virtual registers have been
252 // replaced. Remove the virtual registers and release all the transient data.
254 MRI->clearVirtRegs();
258 void VirtRegRewriter::addLiveInsForSubRanges(const LiveInterval &LI,
259 unsigned PhysReg) const {
261 assert(LI.hasSubRanges());
263 typedef std::pair<const LiveInterval::SubRange *,
264 LiveInterval::const_iterator> SubRangeIteratorPair;
265 SmallVector<SubRangeIteratorPair, 4> SubRanges;
268 for (const LiveInterval::SubRange &SR : LI.subranges()) {
269 SubRanges.push_back(std::make_pair(&SR, SR.begin()));
270 if (!First.isValid() || SR.segments.front().start < First)
271 First = SR.segments.front().start;
272 if (!Last.isValid() || SR.segments.back().end > Last)
273 Last = SR.segments.back().end;
276 // Check all mbb start positions between First and Last while
277 // simulatenously advancing an iterator for each subrange.
278 for (SlotIndexes::MBBIndexIterator MBBI = Indexes->findMBBIndex(First);
279 MBBI != Indexes->MBBIndexEnd() && MBBI->first <= Last; ++MBBI) {
280 SlotIndex MBBBegin = MBBI->first;
281 // Advance all subrange iterators so that their end position is just
282 // behind MBBBegin (or the iterator is at the end).
283 LaneBitmask LaneMask;
284 for (auto &RangeIterPair : SubRanges) {
285 const LiveInterval::SubRange *SR = RangeIterPair.first;
286 LiveInterval::const_iterator &SRI = RangeIterPair.second;
287 while (SRI != SR->end() && SRI->end <= MBBBegin)
289 if (SRI == SR->end())
291 if (SRI->start <= MBBBegin)
292 LaneMask |= SR->LaneMask;
296 MachineBasicBlock *MBB = MBBI->second;
297 MBB->addLiveIn(PhysReg, LaneMask);
301 // Compute MBB live-in lists from virtual register live ranges and their
303 void VirtRegRewriter::addMBBLiveIns() {
304 for (unsigned Idx = 0, IdxE = MRI->getNumVirtRegs(); Idx != IdxE; ++Idx) {
305 unsigned VirtReg = TargetRegisterInfo::index2VirtReg(Idx);
306 if (MRI->reg_nodbg_empty(VirtReg))
308 LiveInterval &LI = LIS->getInterval(VirtReg);
309 if (LI.empty() || LIS->intervalIsInOneMBB(LI))
311 // This is a virtual register that is live across basic blocks. Its
312 // assigned PhysReg must be marked as live-in to those blocks.
313 unsigned PhysReg = VRM->getPhys(VirtReg);
314 assert(PhysReg != VirtRegMap::NO_PHYS_REG && "Unmapped virtual register.");
316 if (LI.hasSubRanges()) {
317 addLiveInsForSubRanges(LI, PhysReg);
319 // Go over MBB begin positions and see if we have segments covering them.
320 // The following works because segments and the MBBIndex list are both
321 // sorted by slot indexes.
322 SlotIndexes::MBBIndexIterator I = Indexes->MBBIndexBegin();
323 for (const auto &Seg : LI) {
324 I = Indexes->advanceMBBIndex(I, Seg.start);
325 for (; I != Indexes->MBBIndexEnd() && I->first < Seg.end; ++I) {
326 MachineBasicBlock *MBB = I->second;
327 MBB->addLiveIn(PhysReg);
333 // Sort and unique MBB LiveIns as we've not checked if SubReg/PhysReg were in
334 // each MBB's LiveIns set before calling addLiveIn on them.
335 for (MachineBasicBlock &MBB : *MF)
336 MBB.sortUniqueLiveIns();
339 /// Returns true if the given machine operand \p MO only reads undefined lanes.
340 /// The function only works for use operands with a subregister set.
341 bool VirtRegRewriter::readsUndefSubreg(const MachineOperand &MO) const {
342 // Shortcut if the operand is already marked undef.
346 unsigned Reg = MO.getReg();
347 const LiveInterval &LI = LIS->getInterval(Reg);
348 const MachineInstr &MI = *MO.getParent();
349 SlotIndex BaseIndex = LIS->getInstructionIndex(MI);
350 // This code is only meant to handle reading undefined subregisters which
351 // we couldn't properly detect before.
352 assert(LI.liveAt(BaseIndex) &&
353 "Reads of completely dead register should be marked undef already");
354 unsigned SubRegIdx = MO.getSubReg();
355 assert(SubRegIdx != 0 && LI.hasSubRanges());
356 LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(SubRegIdx);
357 // See if any of the relevant subregister liveranges is defined at this point.
358 for (const LiveInterval::SubRange &SR : LI.subranges()) {
359 if ((SR.LaneMask & UseMask).any() && SR.liveAt(BaseIndex))
365 void VirtRegRewriter::handleIdentityCopy(MachineInstr &MI) const {
366 if (!MI.isIdentityCopy())
368 DEBUG(dbgs() << "Identity copy: " << MI);
372 // %R0 = COPY %R0<undef>
373 // %AL = COPY %AL, %EAX<imp-def>
374 // give us additional liveness information: The target (super-)register
375 // must not be valid before this point. Replace the COPY with a KILL
376 // instruction to maintain this information.
377 if (MI.getOperand(0).isUndef() || MI.getNumOperands() > 2) {
378 MI.setDesc(TII->get(TargetOpcode::KILL));
379 DEBUG(dbgs() << " replace by: " << MI);
384 Indexes->removeSingleMachineInstrFromMaps(MI);
385 MI.eraseFromBundle();
386 DEBUG(dbgs() << " deleted.\n");
389 /// The liverange splitting logic sometimes produces bundles of copies when
390 /// subregisters are involved. Expand these into a sequence of copy instructions
391 /// after processing the last in the bundle. Does not update LiveIntervals
392 /// which we shouldn't need for this instruction anymore.
393 void VirtRegRewriter::expandCopyBundle(MachineInstr &MI) const {
397 if (MI.isBundledWithPred() && !MI.isBundledWithSucc()) {
398 // Only do this when the complete bundle is made out of COPYs.
399 MachineBasicBlock &MBB = *MI.getParent();
400 for (MachineBasicBlock::reverse_instr_iterator I =
401 std::next(MI.getReverseIterator()), E = MBB.instr_rend();
402 I != E && I->isBundledWithSucc(); ++I) {
407 for (MachineBasicBlock::reverse_instr_iterator I = MI.getReverseIterator();
408 I->isBundledWithPred(); ) {
409 MachineInstr &MI = *I;
412 MI.unbundleFromPred();
414 Indexes->insertMachineInstrInMaps(MI);
419 /// Check whether (part of) \p SuperPhysReg is live through \p MI.
420 /// \pre \p MI defines a subregister of a virtual register that
421 /// has been assigned to \p SuperPhysReg.
422 bool VirtRegRewriter::subRegLiveThrough(const MachineInstr &MI,
423 unsigned SuperPhysReg) const {
424 SlotIndex MIIndex = LIS->getInstructionIndex(MI);
425 SlotIndex BeforeMIUses = MIIndex.getBaseIndex();
426 SlotIndex AfterMIDefs = MIIndex.getBoundaryIndex();
427 for (MCRegUnitIterator Unit(SuperPhysReg, TRI); Unit.isValid(); ++Unit) {
428 const LiveRange &UnitRange = LIS->getRegUnit(*Unit);
429 // If the regunit is live both before and after MI,
430 // we assume it is live through.
431 // Generally speaking, this is not true, because something like
432 // "RU = op RU" would match that description.
433 // However, we know that we are trying to assess whether
434 // a def of a virtual reg, vreg, is live at the same time of RU.
435 // If we are in the "RU = op RU" situation, that means that vreg
436 // is defined at the same time as RU (i.e., "vreg, RU = op RU").
437 // Thus, vreg and RU interferes and vreg cannot be assigned to
438 // SuperPhysReg. Therefore, this situation cannot happen.
439 if (UnitRange.liveAt(AfterMIDefs) && UnitRange.liveAt(BeforeMIUses))
445 void VirtRegRewriter::rewrite() {
446 bool NoSubRegLiveness = !MRI->subRegLivenessEnabled();
447 SmallVector<unsigned, 8> SuperDeads;
448 SmallVector<unsigned, 8> SuperDefs;
449 SmallVector<unsigned, 8> SuperKills;
451 for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
452 MBBI != MBBE; ++MBBI) {
453 DEBUG(MBBI->print(dbgs(), Indexes));
454 for (MachineBasicBlock::instr_iterator
455 MII = MBBI->instr_begin(), MIE = MBBI->instr_end(); MII != MIE;) {
456 MachineInstr *MI = &*MII;
459 for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
460 MOE = MI->operands_end(); MOI != MOE; ++MOI) {
461 MachineOperand &MO = *MOI;
463 // Make sure MRI knows about registers clobbered by regmasks.
465 MRI->addPhysRegsUsedFromRegMask(MO.getRegMask());
467 if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
469 unsigned VirtReg = MO.getReg();
470 unsigned PhysReg = VRM->getPhys(VirtReg);
471 assert(PhysReg != VirtRegMap::NO_PHYS_REG &&
472 "Instruction uses unmapped VirtReg");
473 assert(!MRI->isReserved(PhysReg) && "Reserved register assignment");
475 // Preserve semantics of sub-register operands.
476 unsigned SubReg = MO.getSubReg();
478 if (NoSubRegLiveness) {
479 // A virtual register kill refers to the whole register, so we may
480 // have to add <imp-use,kill> operands for the super-register. A
481 // partial redef always kills and redefines the super-register.
482 if ((MO.readsReg() && (MO.isDef() || MO.isKill())) ||
483 (MO.isDef() && subRegLiveThrough(*MI, PhysReg)))
484 SuperKills.push_back(PhysReg);
487 // Also add implicit defs for the super-register.
489 SuperDeads.push_back(PhysReg);
491 SuperDefs.push_back(PhysReg);
495 if (readsUndefSubreg(MO))
496 // We need to add an <undef> flag if the subregister is
497 // completely undefined (and we are not adding super-register
500 } else if (!MO.isDead()) {
505 // The <def,undef> and <def,internal> flags only make sense for
506 // sub-register defs, and we are substituting a full physreg. An
507 // <imp-use,kill> operand from the SuperKills list will represent the
508 // partial read of the super-register.
510 MO.setIsUndef(false);
511 MO.setIsInternalRead(false);
514 // PhysReg operands cannot have subregister indexes.
515 PhysReg = TRI->getSubReg(PhysReg, SubReg);
516 assert(PhysReg && "Invalid SubReg for physical register");
519 // Rewrite. Note we could have used MachineOperand::substPhysReg(), but
520 // we need the inlining here.
524 // Add any missing super-register kills after rewriting the whole
526 while (!SuperKills.empty())
527 MI->addRegisterKilled(SuperKills.pop_back_val(), TRI, true);
529 while (!SuperDeads.empty())
530 MI->addRegisterDead(SuperDeads.pop_back_val(), TRI, true);
532 while (!SuperDefs.empty())
533 MI->addRegisterDefined(SuperDefs.pop_back_val(), TRI);
535 DEBUG(dbgs() << "> " << *MI);
537 expandCopyBundle(*MI);
539 // We can remove identity copies right now.
540 handleIdentityCopy(*MI);