contrib/llvm/lib/MC/MCSubtargetInfo.cpp

   1 //===- MCSubtargetInfo.cpp - Subtarget Information ------------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 #include "llvm/MC/MCSubtargetInfo.h"
  11 #include "llvm/ADT/ArrayRef.h"
  12 #include "llvm/ADT/StringRef.h"
  13 #include "llvm/MC/MCInstrItineraries.h"
  14 #include "llvm/MC/MCSchedule.h"
  15 #include "llvm/MC/SubtargetFeature.h"
  16 #include "llvm/Support/raw_ostream.h"
  17 #include <algorithm>
  18 #include <cassert>
  19 #include <cstring>
  20
  21 using namespace llvm;
  22
  23 static FeatureBitset getFeatures(StringRef CPU, StringRef FS,
  24                                  ArrayRef<SubtargetFeatureKV> ProcDesc,
  25                                  ArrayRef<SubtargetFeatureKV> ProcFeatures) {
  26   SubtargetFeatures Features(FS);
  27   return Features.getFeatureBits(CPU, ProcDesc, ProcFeatures);
  28 }
  29
  30 void MCSubtargetInfo::InitMCProcessorInfo(StringRef CPU, StringRef FS) {
  31   FeatureBits = getFeatures(CPU, FS, ProcDesc, ProcFeatures);
  32   if (!CPU.empty())
  33     CPUSchedModel = &getSchedModelForCPU(CPU);
  34   else
  35     CPUSchedModel = &MCSchedModel::GetDefaultSchedModel();
  36 }
  37
  38 void MCSubtargetInfo::setDefaultFeatures(StringRef CPU, StringRef FS) {
  39   FeatureBits = getFeatures(CPU, FS, ProcDesc, ProcFeatures);
  40 }
  41
  42 MCSubtargetInfo::MCSubtargetInfo(
  43     const Triple &TT, StringRef C, StringRef FS,
  44     ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD,
  45     const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR,
  46     const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
  47     const InstrStage *IS, const unsigned *OC, const unsigned *FP)
  48     : TargetTriple(TT), CPU(C), ProcFeatures(PF), ProcDesc(PD),
  49       ProcSchedModels(ProcSched), WriteProcResTable(WPR), WriteLatencyTable(WL),
  50       ReadAdvanceTable(RA), Stages(IS), OperandCycles(OC), ForwardingPaths(FP) {
  51   InitMCProcessorInfo(CPU, FS);
  52 }
  53
  54 /// ToggleFeature - Toggle a feature and returns the re-computed feature
  55 /// bits. This version does not change the implied bits.
  56 FeatureBitset MCSubtargetInfo::ToggleFeature(uint64_t FB) {
  57   FeatureBits.flip(FB);
  58   return FeatureBits;
  59 }
  60
  61 FeatureBitset MCSubtargetInfo::ToggleFeature(const FeatureBitset &FB) {
  62   FeatureBits ^= FB;
  63   return FeatureBits;
  64 }
  65
  66 /// ToggleFeature - Toggle a feature and returns the re-computed feature
  67 /// bits. This version will also change all implied bits.
  68 FeatureBitset MCSubtargetInfo::ToggleFeature(StringRef FS) {
  69   SubtargetFeatures::ToggleFeature(FeatureBits, FS, ProcFeatures);
  70   return FeatureBits;
  71 }
  72
  73 FeatureBitset MCSubtargetInfo::ApplyFeatureFlag(StringRef FS) {
  74   SubtargetFeatures::ApplyFeatureFlag(FeatureBits, FS, ProcFeatures);
  75   return FeatureBits;
  76 }
  77
  78 const MCSchedModel &MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const {
  79   assert(ProcSchedModels && "Processor machine model not available!");
  80
  81   ArrayRef<SubtargetInfoKV> SchedModels(ProcSchedModels, ProcDesc.size());
  82
  83   assert(std::is_sorted(SchedModels.begin(), SchedModels.end(),
  84                     [](const SubtargetInfoKV &LHS, const SubtargetInfoKV &RHS) {
  85                       return strcmp(LHS.Key, RHS.Key) < 0;
  86                     }) &&
  87          "Processor machine model table is not sorted");
  88
  89   // Find entry
  90   auto Found =
  91     std::lower_bound(SchedModels.begin(), SchedModels.end(), CPU);
  92   if (Found == SchedModels.end() || StringRef(Found->Key) != CPU) {
  93     if (CPU != "help") // Don't error if the user asked for help.
  94       errs() << "'" << CPU
  95              << "' is not a recognized processor for this target"
  96              << " (ignoring processor)\n";
  97     return MCSchedModel::GetDefaultSchedModel();
  98   }
  99   assert(Found->Value && "Missing processor SchedModel value");
 100   return *(const MCSchedModel *)Found->Value;
 101 }
 102
 103 InstrItineraryData
 104 MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const {
 105   const MCSchedModel SchedModel = getSchedModelForCPU(CPU);
 106   return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths);
 107 }
 108
 109 /// Initialize an InstrItineraryData instance.
 110 void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const {
 111   InstrItins = InstrItineraryData(getSchedModel(), Stages, OperandCycles,
 112                                   ForwardingPaths);
 113 }