1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the operating system Host concept.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Support/Host.h"
15 #include "llvm/ADT/SmallSet.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/ADT/StringSwitch.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/Config/config.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/FileSystem.h"
23 #include "llvm/Support/MemoryBuffer.h"
24 #include "llvm/Support/raw_ostream.h"
28 // Include the platform-specific parts of this class.
30 #include "Unix/Host.inc"
33 #include "Windows/Host.inc"
38 #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
39 #include <mach/host_info.h>
40 #include <mach/mach.h>
41 #include <mach/mach_host.h>
42 #include <mach/machine.h>
45 #define DEBUG_TYPE "host-detection"
47 //===----------------------------------------------------------------------===//
49 // Implementations of the CPU detection routines
51 //===----------------------------------------------------------------------===//
55 static std::unique_ptr<llvm::MemoryBuffer>
56 LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent() {
57 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text =
58 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo");
59 if (std::error_code EC = Text.getError()) {
60 llvm::errs() << "Can't read "
61 << "/proc/cpuinfo: " << EC.message() << "\n";
64 return std::move(*Text);
67 StringRef sys::detail::getHostCPUNameForPowerPC(
68 const StringRef &ProcCpuinfoContent) {
69 // Access to the Processor Version Register (PVR) on PowerPC is privileged,
70 // and so we must use an operating-system interface to determine the current
71 // processor type. On Linux, this is exposed through the /proc/cpuinfo file.
72 const char *generic = "generic";
74 // The cpu line is second (after the 'processor: 0' line), so if this
75 // buffer is too small then something has changed (or is wrong).
76 StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin();
77 StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end();
79 StringRef::const_iterator CIP = CPUInfoStart;
81 StringRef::const_iterator CPUStart = 0;
84 // We need to find the first line which starts with cpu, spaces, and a colon.
85 // After the colon, there may be some additional spaces and then the cpu type.
86 while (CIP < CPUInfoEnd && CPUStart == 0) {
87 if (CIP < CPUInfoEnd && *CIP == '\n')
90 if (CIP < CPUInfoEnd && *CIP == 'c') {
92 if (CIP < CPUInfoEnd && *CIP == 'p') {
94 if (CIP < CPUInfoEnd && *CIP == 'u') {
96 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
99 if (CIP < CPUInfoEnd && *CIP == ':') {
101 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
104 if (CIP < CPUInfoEnd) {
106 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' &&
107 *CIP != ',' && *CIP != '\n'))
109 CPULen = CIP - CPUStart;
117 while (CIP < CPUInfoEnd && *CIP != '\n')
124 return StringSwitch<const char *>(StringRef(CPUStart, CPULen))
125 .Case("604e", "604e")
127 .Case("7400", "7400")
128 .Case("7410", "7400")
129 .Case("7447", "7400")
130 .Case("7455", "7450")
132 .Case("POWER4", "970")
133 .Case("PPC970FX", "970")
134 .Case("PPC970MP", "970")
136 .Case("POWER5", "g5")
138 .Case("POWER6", "pwr6")
139 .Case("POWER7", "pwr7")
140 .Case("POWER8", "pwr8")
141 .Case("POWER8E", "pwr8")
142 .Case("POWER8NVL", "pwr8")
143 .Case("POWER9", "pwr9")
147 StringRef sys::detail::getHostCPUNameForARM(
148 const StringRef &ProcCpuinfoContent) {
149 // The cpuid register on arm is not accessible from user space. On Linux,
150 // it is exposed through the /proc/cpuinfo file.
152 // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line
154 SmallVector<StringRef, 32> Lines;
155 ProcCpuinfoContent.split(Lines, "\n");
157 // Look for the CPU implementer line.
158 StringRef Implementer;
160 for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
161 if (Lines[I].startswith("CPU implementer"))
162 Implementer = Lines[I].substr(15).ltrim("\t :");
163 if (Lines[I].startswith("Hardware"))
164 Hardware = Lines[I].substr(8).ltrim("\t :");
167 if (Implementer == "0x41") { // ARM Ltd.
168 // MSM8992/8994 may give cpu part for the core that the kernel is running on,
169 // which is undeterministic and wrong. Always return cortex-a53 for these SoC.
170 if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996"))
174 // Look for the CPU part line.
175 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
176 if (Lines[I].startswith("CPU part"))
177 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
178 // values correspond to the "Part number" in the CP15/c0 register. The
179 // contents are specified in the various processor manuals.
180 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
181 .Case("0x926", "arm926ej-s")
182 .Case("0xb02", "mpcore")
183 .Case("0xb36", "arm1136j-s")
184 .Case("0xb56", "arm1156t2-s")
185 .Case("0xb76", "arm1176jz-s")
186 .Case("0xc08", "cortex-a8")
187 .Case("0xc09", "cortex-a9")
188 .Case("0xc0f", "cortex-a15")
189 .Case("0xc20", "cortex-m0")
190 .Case("0xc23", "cortex-m3")
191 .Case("0xc24", "cortex-m4")
192 .Case("0xd04", "cortex-a35")
193 .Case("0xd03", "cortex-a53")
194 .Case("0xd07", "cortex-a57")
195 .Case("0xd08", "cortex-a72")
196 .Case("0xd09", "cortex-a73")
200 if (Implementer == "0x51") // Qualcomm Technologies, Inc.
201 // Look for the CPU part line.
202 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
203 if (Lines[I].startswith("CPU part"))
204 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
205 // values correspond to the "Part number" in the CP15/c0 register. The
206 // contents are specified in the various processor manuals.
207 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
208 .Case("0x06f", "krait") // APQ8064
209 .Case("0x201", "kryo")
210 .Case("0x205", "kryo")
216 StringRef sys::detail::getHostCPUNameForS390x(
217 const StringRef &ProcCpuinfoContent) {
218 // STIDP is a privileged operation, so use /proc/cpuinfo instead.
220 // The "processor 0:" line comes after a fair amount of other information,
221 // including a cache breakdown, but this should be plenty.
222 SmallVector<StringRef, 32> Lines;
223 ProcCpuinfoContent.split(Lines, "\n");
225 // Look for the CPU features.
226 SmallVector<StringRef, 32> CPUFeatures;
227 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
228 if (Lines[I].startswith("features")) {
229 size_t Pos = Lines[I].find(":");
230 if (Pos != StringRef::npos) {
231 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' ');
236 // We need to check for the presence of vector support independently of
237 // the machine type, since we may only use the vector register set when
238 // supported by the kernel (and hypervisor).
239 bool HaveVectorSupport = false;
240 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
241 if (CPUFeatures[I] == "vx")
242 HaveVectorSupport = true;
245 // Now check the processor machine type.
246 for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
247 if (Lines[I].startswith("processor ")) {
248 size_t Pos = Lines[I].find("machine = ");
249 if (Pos != StringRef::npos) {
250 Pos += sizeof("machine = ") - 1;
252 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) {
253 if (Id >= 3906 && HaveVectorSupport)
255 if (Id >= 2964 && HaveVectorSupport)
270 #if defined(__i386__) || defined(_M_IX86) || \
271 defined(__x86_64__) || defined(_M_X64)
273 enum VendorSignatures {
274 SIG_INTEL = 0x756e6547 /* Genu */,
275 SIG_AMD = 0x68747541 /* Auth */
278 enum ProcessorVendors {
285 enum ProcessorTypes {
296 // Entries below this are not in libgcc/compiler-rt.
316 enum ProcessorSubtypes {
317 INTEL_COREI7_NEHALEM = 1,
318 INTEL_COREI7_WESTMERE,
319 INTEL_COREI7_SANDYBRIDGE,
328 INTEL_COREI7_IVYBRIDGE,
329 INTEL_COREI7_HASWELL,
330 INTEL_COREI7_BROADWELL,
331 INTEL_COREI7_SKYLAKE,
332 INTEL_COREI7_SKYLAKE_AVX512,
333 // Entries below this are not in libgcc/compiler-rt.
348 enum ProcessorFeatures {
377 FEATURE_AVX5124VNNIW,
378 FEATURE_AVX5124FMAPS,
379 FEATURE_AVX512VPOPCNTDQ,
380 // Only one bit free left in the first 32 features.
386 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max).
387 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID
388 // support. Consequently, for i386, the presence of CPUID is checked first
389 // via the corresponding eflags bit.
390 // Removal of cpuid.h header motivated by PR30384
391 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp
392 // or test-suite, but are used in external projects e.g. libstdcxx
393 static bool isCpuIdSupported() {
394 #if defined(__GNUC__) || defined(__clang__)
395 #if defined(__i386__)
396 int __cpuid_supported;
399 " movl %%eax,%%ecx\n"
400 " xorl $0x00200000,%%eax\n"
406 " cmpl %%eax,%%ecx\n"
410 : "=r"(__cpuid_supported)
413 if (!__cpuid_supported)
421 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in
422 /// the specified arguments. If we can't run cpuid on the host, return true.
423 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
424 unsigned *rECX, unsigned *rEDX) {
425 #if defined(__GNUC__) || defined(__clang__)
426 #if defined(__x86_64__)
427 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually.
428 // FIXME: should we save this for Clang?
429 __asm__("movq\t%%rbx, %%rsi\n\t"
431 "xchgq\t%%rbx, %%rsi\n\t"
432 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
435 #elif defined(__i386__)
436 __asm__("movl\t%%ebx, %%esi\n\t"
438 "xchgl\t%%ebx, %%esi\n\t"
439 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
445 #elif defined(_MSC_VER)
446 // The MSVC intrinsic is portable across x86 and x64.
448 __cpuid(registers, value);
449 *rEAX = registers[0];
450 *rEBX = registers[1];
451 *rECX = registers[2];
452 *rEDX = registers[3];
459 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return
460 /// the 4 values in the specified arguments. If we can't run cpuid on the host,
462 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf,
463 unsigned *rEAX, unsigned *rEBX, unsigned *rECX,
465 #if defined(__GNUC__) || defined(__clang__)
466 #if defined(__x86_64__)
467 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually.
468 // FIXME: should we save this for Clang?
469 __asm__("movq\t%%rbx, %%rsi\n\t"
471 "xchgq\t%%rbx, %%rsi\n\t"
472 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
473 : "a"(value), "c"(subleaf));
475 #elif defined(__i386__)
476 __asm__("movl\t%%ebx, %%esi\n\t"
478 "xchgl\t%%ebx, %%esi\n\t"
479 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
480 : "a"(value), "c"(subleaf));
485 #elif defined(_MSC_VER)
487 __cpuidex(registers, value, subleaf);
488 *rEAX = registers[0];
489 *rEBX = registers[1];
490 *rECX = registers[2];
491 *rEDX = registers[3];
498 // Read control register 0 (XCR0). Used to detect features such as AVX.
499 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) {
500 #if defined(__GNUC__) || defined(__clang__)
501 // Check xgetbv; this uses a .byte sequence instead of the instruction
502 // directly because older assemblers do not include support for xgetbv and
503 // there is no easy way to conditionally compile based on the assembler used.
504 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0));
506 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
507 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
509 *rEDX = Result >> 32;
516 static void detectX86FamilyModel(unsigned EAX, unsigned *Family,
518 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11
519 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7
520 if (*Family == 6 || *Family == 0xf) {
522 // Examine extended family ID if family ID is F.
523 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27
524 // Examine extended model ID if family ID is 6 or F.
525 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
530 getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model,
531 unsigned Brand_id, unsigned Features,
532 unsigned Features2, unsigned *Type,
542 case 0: // Intel486 DX processors
543 case 1: // Intel486 DX processors
544 case 2: // Intel486 SX processors
545 case 3: // Intel487 processors, IntelDX2 OverDrive processors,
546 // IntelDX2 processors
547 case 4: // Intel486 SL processor
548 case 5: // IntelSX2 processors
549 case 7: // Write-Back Enhanced IntelDX2 processors
550 case 8: // IntelDX4 OverDrive processors, IntelDX4 processors
558 case 1: // Pentium OverDrive processor for Pentium processor (60, 66),
559 // Pentium processors (60, 66)
560 case 2: // Pentium OverDrive processor for Pentium processor (75, 90,
561 // 100, 120, 133), Pentium processors (75, 90, 100, 120, 133,
563 case 3: // Pentium OverDrive processors for Intel486 processor-based
565 *Type = INTEL_PENTIUM;
567 case 4: // Pentium OverDrive processor with MMX technology for Pentium
568 // processor (75, 90, 100, 120, 133), Pentium processor with
569 // MMX technology (166, 200)
570 *Type = INTEL_PENTIUM;
571 *Subtype = INTEL_PENTIUM_MMX;
574 *Type = INTEL_PENTIUM;
580 case 0x01: // Pentium Pro processor
581 *Type = INTEL_PENTIUM_PRO;
583 case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor,
585 case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor,
586 // model 05, and Intel Celeron processor, model 05
587 case 0x06: // Celeron processor, model 06
588 *Type = INTEL_PENTIUM_II;
590 case 0x07: // Pentium III processor, model 07, and Pentium III Xeon
591 // processor, model 07
592 case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor,
593 // model 08, and Celeron processor, model 08
594 case 0x0a: // Pentium III Xeon processor, model 0Ah
595 case 0x0b: // Pentium III processor, model 0Bh
596 *Type = INTEL_PENTIUM_III;
598 case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09.
599 case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model
600 // 0Dh. All processors are manufactured using the 90 nm process.
601 case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579
602 // Integrated Processor with Intel QuickAssist Technology
603 *Type = INTEL_PENTIUM_M;
605 case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model
606 // 0Eh. All processors are manufactured using the 65 nm process.
607 *Type = INTEL_CORE_DUO;
609 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile
610 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad
611 // mobile processor, Intel Core 2 Extreme processor, Intel
612 // Pentium Dual-Core processor, Intel Xeon processor, model
613 // 0Fh. All processors are manufactured using the 65 nm process.
614 case 0x16: // Intel Celeron processor model 16h. All processors are
615 // manufactured using the 65 nm process
616 *Type = INTEL_CORE2; // "core2"
617 *Subtype = INTEL_CORE2_65;
619 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model
620 // 17h. All processors are manufactured using the 45 nm process.
622 // 45nm: Penryn , Wolfdale, Yorkfield (XE)
623 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using
624 // the 45 nm process.
625 *Type = INTEL_CORE2; // "penryn"
626 *Subtype = INTEL_CORE2_45;
628 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All
629 // processors are manufactured using the 45 nm process.
630 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz.
631 // As found in a Summer 2010 model iMac.
633 case 0x2e: // Nehalem EX
634 *Type = INTEL_COREI7; // "nehalem"
635 *Subtype = INTEL_COREI7_NEHALEM;
637 case 0x25: // Intel Core i7, laptop version.
638 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All
639 // processors are manufactured using the 32 nm process.
640 case 0x2f: // Westmere EX
641 *Type = INTEL_COREI7; // "westmere"
642 *Subtype = INTEL_COREI7_WESTMERE;
644 case 0x2a: // Intel Core i7 processor. All processors are manufactured
645 // using the 32 nm process.
647 *Type = INTEL_COREI7; //"sandybridge"
648 *Subtype = INTEL_COREI7_SANDYBRIDGE;
651 case 0x3e: // Ivy Bridge EP
652 *Type = INTEL_COREI7; // "ivybridge"
653 *Subtype = INTEL_COREI7_IVYBRIDGE;
661 *Type = INTEL_COREI7; // "haswell"
662 *Subtype = INTEL_COREI7_HASWELL;
670 *Type = INTEL_COREI7; // "broadwell"
671 *Subtype = INTEL_COREI7_BROADWELL;
675 case 0x4e: // Skylake mobile
676 case 0x5e: // Skylake desktop
677 case 0x8e: // Kaby Lake mobile
678 case 0x9e: // Kaby Lake desktop
679 *Type = INTEL_COREI7; // "skylake"
680 *Subtype = INTEL_COREI7_SKYLAKE;
685 *Type = INTEL_COREI7;
686 *Subtype = INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512"
689 case 0x1c: // Most 45 nm Intel Atom processors
690 case 0x26: // 45 nm Atom Lincroft
691 case 0x27: // 32 nm Atom Medfield
692 case 0x35: // 32 nm Atom Midview
693 case 0x36: // 32 nm Atom Midview
694 *Type = INTEL_BONNELL;
697 // Atom Silvermont codes from the Intel software optimization guide.
703 case 0x4c: // really airmont
704 *Type = INTEL_SILVERMONT;
705 break; // "silvermont"
709 *Type = INTEL_GOLDMONT;
712 *Type = INTEL_KNL; // knl
715 default: // Unknown family 6 CPU, try to guess.
716 if (Features & (1 << FEATURE_AVX512F)) {
717 *Type = INTEL_KNL; // knl
720 if (Features2 & (1 << (FEATURE_ADX - 32))) {
721 *Type = INTEL_COREI7;
722 *Subtype = INTEL_COREI7_BROADWELL;
725 if (Features & (1 << FEATURE_AVX2)) {
726 *Type = INTEL_COREI7;
727 *Subtype = INTEL_COREI7_HASWELL;
730 if (Features & (1 << FEATURE_AVX)) {
731 *Type = INTEL_COREI7;
732 *Subtype = INTEL_COREI7_SANDYBRIDGE;
735 if (Features & (1 << FEATURE_SSE4_2)) {
736 if (Features2 & (1 << (FEATURE_MOVBE - 32))) {
737 *Type = INTEL_SILVERMONT;
739 *Type = INTEL_COREI7;
740 *Subtype = INTEL_COREI7_NEHALEM;
744 if (Features & (1 << FEATURE_SSE4_1)) {
745 *Type = INTEL_CORE2; // "penryn"
746 *Subtype = INTEL_CORE2_45;
749 if (Features & (1 << FEATURE_SSSE3)) {
750 if (Features2 & (1 << (FEATURE_MOVBE - 32))) {
751 *Type = INTEL_BONNELL; // "bonnell"
753 *Type = INTEL_CORE2; // "core2"
754 *Subtype = INTEL_CORE2_65;
758 if (Features2 & (1 << (FEATURE_EM64T - 32))) {
759 *Type = INTEL_X86_64;
762 if (Features & (1 << FEATURE_SSE2)) {
763 *Type = INTEL_PENTIUM_M;
766 if (Features & (1 << FEATURE_SSE)) {
767 *Type = INTEL_PENTIUM_III;
770 if (Features & (1 << FEATURE_MMX)) {
771 *Type = INTEL_PENTIUM_II;
774 *Type = INTEL_PENTIUM_PRO;
780 case 0: // Pentium 4 processor, Intel Xeon processor. All processors are
781 // model 00h and manufactured using the 0.18 micron process.
782 case 1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon
783 // processor MP, and Intel Celeron processor. All processors are
784 // model 01h and manufactured using the 0.18 micron process.
785 case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M,
786 // Intel Xeon processor, Intel Xeon processor MP, Intel Celeron
787 // processor, and Mobile Intel Celeron processor. All processors
788 // are model 02h and manufactured using the 0.13 micron process.
789 *Type = ((Features2 & (1 << (FEATURE_EM64T - 32))) ? INTEL_X86_64
793 case 3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D
794 // processor. All processors are model 03h and manufactured using
795 // the 90 nm process.
796 case 4: // Pentium 4 processor, Pentium 4 processor Extreme Edition,
797 // Pentium D processor, Intel Xeon processor, Intel Xeon
798 // processor MP, Intel Celeron D processor. All processors are
799 // model 04h and manufactured using the 90 nm process.
800 case 6: // Pentium 4 processor, Pentium D processor, Pentium processor
801 // Extreme Edition, Intel Xeon processor, Intel Xeon processor
802 // MP, Intel Celeron D processor. All processors are model 06h
803 // and manufactured using the 65 nm process.
804 *Type = ((Features2 & (1 << (FEATURE_EM64T - 32))) ? INTEL_NOCONA
809 *Type = ((Features2 & (1 << (FEATURE_EM64T - 32))) ? INTEL_X86_64
820 static void getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model,
821 unsigned Features, unsigned *Type,
823 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There
824 // appears to be no way to generate the wide variety of AMD-specific targets
825 // from the information returned from CPUID.
835 *Subtype = AMDPENTIUM_K6;
838 *Subtype = AMDPENTIUM_K62;
842 *Subtype = AMDPENTIUM_K63;
845 *Subtype = AMDPENTIUM_GEODE;
851 if (Features & (1 << FEATURE_SSE)) {
852 *Subtype = AMDATHLON_XP;
853 break; // "athlon-xp"
855 *Subtype = AMDATHLON_CLASSIC;
859 if (Features & (1 << FEATURE_SSE3)) {
860 *Subtype = AMDATHLON_K8SSE3;
863 *Subtype = AMDATHLON_K8;
866 *Type = AMDFAM10H; // "amdfam10"
869 *Subtype = AMDFAM10H_BARCELONA;
872 *Subtype = AMDFAM10H_SHANGHAI;
875 *Subtype = AMDFAM10H_ISTANBUL;
884 if (Model >= 0x60 && Model <= 0x7f) {
885 *Subtype = AMDFAM15H_BDVER4;
886 break; // "bdver4"; 60h-7Fh: Excavator
888 if (Model >= 0x30 && Model <= 0x3f) {
889 *Subtype = AMDFAM15H_BDVER3;
890 break; // "bdver3"; 30h-3Fh: Steamroller
892 if (Model >= 0x10 && Model <= 0x1f) {
893 *Subtype = AMDFAM15H_BDVER2;
894 break; // "bdver2"; 10h-1Fh: Piledriver
897 *Subtype = AMDFAM15H_BDVER1;
898 break; // "bdver1"; 00h-0Fh: Bulldozer
906 *Subtype = AMDFAM17H_ZNVER1;
913 static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf,
914 unsigned *FeaturesOut,
915 unsigned *Features2Out) {
916 unsigned Features = 0;
917 unsigned Features2 = 0;
921 Features |= 1 << FEATURE_CMOV;
923 Features |= 1 << FEATURE_MMX;
925 Features |= 1 << FEATURE_SSE;
927 Features |= 1 << FEATURE_SSE2;
930 Features |= 1 << FEATURE_SSE3;
932 Features |= 1 << FEATURE_PCLMUL;
934 Features |= 1 << FEATURE_SSSE3;
936 Features |= 1 << FEATURE_FMA;
938 Features |= 1 << FEATURE_SSE4_1;
940 Features |= 1 << FEATURE_SSE4_2;
942 Features |= 1 << FEATURE_POPCNT;
944 Features |= 1 << FEATURE_AES;
947 Features2 |= 1 << (FEATURE_MOVBE - 32);
949 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
950 // indicates that the AVX registers will be saved and restored on context
951 // switch, then we have full AVX support.
952 const unsigned AVXBits = (1 << 27) | (1 << 28);
953 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) &&
954 ((EAX & 0x6) == 0x6);
955 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0);
958 Features |= 1 << FEATURE_AVX;
961 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
963 if (HasLeaf7 && ((EBX >> 3) & 1))
964 Features |= 1 << FEATURE_BMI;
965 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX)
966 Features |= 1 << FEATURE_AVX2;
967 if (HasLeaf7 && ((EBX >> 9) & 1))
968 Features |= 1 << FEATURE_BMI2;
969 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save)
970 Features |= 1 << FEATURE_AVX512F;
971 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save)
972 Features |= 1 << FEATURE_AVX512DQ;
973 if (HasLeaf7 && ((EBX >> 19) & 1))
974 Features2 |= 1 << (FEATURE_ADX - 32);
975 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save)
976 Features |= 1 << FEATURE_AVX512IFMA;
977 if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save)
978 Features |= 1 << FEATURE_AVX512PF;
979 if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save)
980 Features |= 1 << FEATURE_AVX512ER;
981 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save)
982 Features |= 1 << FEATURE_AVX512CD;
983 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save)
984 Features |= 1 << FEATURE_AVX512BW;
985 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save)
986 Features |= 1 << FEATURE_AVX512VL;
988 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save)
989 Features |= 1 << FEATURE_AVX512VBMI;
990 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save)
991 Features |= 1 << FEATURE_AVX512VPOPCNTDQ;
993 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save)
994 Features |= 1 << FEATURE_AVX5124VNNIW;
995 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save)
996 Features |= 1 << FEATURE_AVX5124FMAPS;
998 unsigned MaxExtLevel;
999 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1001 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1002 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1003 if (HasExtLeaf1 && ((ECX >> 6) & 1))
1004 Features |= 1 << FEATURE_SSE4_A;
1005 if (HasExtLeaf1 && ((ECX >> 11) & 1))
1006 Features |= 1 << FEATURE_XOP;
1007 if (HasExtLeaf1 && ((ECX >> 16) & 1))
1008 Features |= 1 << FEATURE_FMA4;
1010 if (HasExtLeaf1 && ((EDX >> 29) & 1))
1011 Features2 |= 1 << (FEATURE_EM64T - 32);
1013 *FeaturesOut = Features;
1014 *Features2Out = Features2;
1017 StringRef sys::getHostCPUName() {
1018 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
1019 unsigned MaxLeaf, Vendor;
1021 #if defined(__GNUC__) || defined(__clang__)
1022 //FIXME: include cpuid.h from clang or copy __get_cpuid_max here
1023 // and simplify it to not invoke __cpuid (like cpu_model.c in
1024 // compiler-rt/lib/builtins/cpu_model.c?
1025 // Opting for the second option.
1026 if(!isCpuIdSupported())
1029 if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX) || MaxLeaf < 1)
1031 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
1033 unsigned Brand_id = EBX & 0xff;
1034 unsigned Family = 0, Model = 0;
1035 unsigned Features = 0, Features2 = 0;
1036 detectX86FamilyModel(EAX, &Family, &Model);
1037 getAvailableFeatures(ECX, EDX, MaxLeaf, &Features, &Features2);
1042 if (Vendor == SIG_INTEL) {
1043 getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features,
1044 Features2, &Type, &Subtype);
1051 if (Subtype == INTEL_PENTIUM_MMX)
1052 return "pentium-mmx";
1054 case INTEL_PENTIUM_PRO:
1055 return "pentiumpro";
1056 case INTEL_PENTIUM_II:
1058 case INTEL_PENTIUM_III:
1060 case INTEL_PENTIUM_IV:
1062 case INTEL_PENTIUM_M:
1064 case INTEL_CORE_DUO:
1068 case INTEL_CORE2_65:
1070 case INTEL_CORE2_45:
1073 llvm_unreachable("Unexpected subtype!");
1077 case INTEL_COREI7_NEHALEM:
1079 case INTEL_COREI7_WESTMERE:
1081 case INTEL_COREI7_SANDYBRIDGE:
1082 return "sandybridge";
1083 case INTEL_COREI7_IVYBRIDGE:
1085 case INTEL_COREI7_HASWELL:
1087 case INTEL_COREI7_BROADWELL:
1089 case INTEL_COREI7_SKYLAKE:
1091 case INTEL_COREI7_SKYLAKE_AVX512:
1092 return "skylake-avx512";
1094 llvm_unreachable("Unexpected subtype!");
1098 case INTEL_SILVERMONT:
1099 return "silvermont";
1100 case INTEL_GOLDMONT:
1108 case INTEL_PRESCOTT:
1113 } else if (Vendor == SIG_AMD) {
1114 getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype);
1122 case AMDPENTIUM_K62:
1124 case AMDPENTIUM_K63:
1126 case AMDPENTIUM_GEODE:
1133 case AMDATHLON_CLASSIC:
1139 case AMDATHLON_K8SSE3:
1142 llvm_unreachable("Unexpected subtype!");
1150 default: // There are gaps in the subtype detection.
1151 case AMDFAM15H_BDVER1:
1153 case AMDFAM15H_BDVER2:
1155 case AMDFAM15H_BDVER3:
1157 case AMDFAM15H_BDVER4:
1171 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
1172 StringRef sys::getHostCPUName() {
1173 host_basic_info_data_t hostInfo;
1174 mach_msg_type_number_t infoCount;
1176 infoCount = HOST_BASIC_INFO_COUNT;
1177 host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo,
1180 if (hostInfo.cpu_type != CPU_TYPE_POWERPC)
1183 switch (hostInfo.cpu_subtype) {
1184 case CPU_SUBTYPE_POWERPC_601:
1186 case CPU_SUBTYPE_POWERPC_602:
1188 case CPU_SUBTYPE_POWERPC_603:
1190 case CPU_SUBTYPE_POWERPC_603e:
1192 case CPU_SUBTYPE_POWERPC_603ev:
1194 case CPU_SUBTYPE_POWERPC_604:
1196 case CPU_SUBTYPE_POWERPC_604e:
1198 case CPU_SUBTYPE_POWERPC_620:
1200 case CPU_SUBTYPE_POWERPC_750:
1202 case CPU_SUBTYPE_POWERPC_7400:
1204 case CPU_SUBTYPE_POWERPC_7450:
1206 case CPU_SUBTYPE_POWERPC_970:
1213 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__))
1214 StringRef sys::getHostCPUName() {
1215 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1216 const StringRef& Content = P ? P->getBuffer() : "";
1217 return detail::getHostCPUNameForPowerPC(Content);
1219 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1220 StringRef sys::getHostCPUName() {
1221 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1222 const StringRef& Content = P ? P->getBuffer() : "";
1223 return detail::getHostCPUNameForARM(Content);
1225 #elif defined(__linux__) && defined(__s390x__)
1226 StringRef sys::getHostCPUName() {
1227 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1228 const StringRef& Content = P ? P->getBuffer() : "";
1229 return detail::getHostCPUNameForS390x(Content);
1232 StringRef sys::getHostCPUName() { return "generic"; }
1235 #if defined(__linux__) && defined(__x86_64__)
1236 // On Linux, the number of physical cores can be computed from /proc/cpuinfo,
1237 // using the number of unique physical/core id pairs. The following
1238 // implementation reads the /proc/cpuinfo format on an x86_64 system.
1239 static int computeHostNumPhysicalCores() {
1240 // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be
1241 // mmapped because it appears to have 0 size.
1242 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text =
1243 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo");
1244 if (std::error_code EC = Text.getError()) {
1245 llvm::errs() << "Can't read "
1246 << "/proc/cpuinfo: " << EC.message() << "\n";
1249 SmallVector<StringRef, 8> strs;
1250 (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1,
1251 /*KeepEmpty=*/false);
1252 int CurPhysicalId = -1;
1254 SmallSet<std::pair<int, int>, 32> UniqueItems;
1255 for (auto &Line : strs) {
1257 if (!Line.startswith("physical id") && !Line.startswith("core id"))
1259 std::pair<StringRef, StringRef> Data = Line.split(':');
1260 auto Name = Data.first.trim();
1261 auto Val = Data.second.trim();
1262 if (Name == "physical id") {
1263 assert(CurPhysicalId == -1 &&
1264 "Expected a core id before seeing another physical id");
1265 Val.getAsInteger(10, CurPhysicalId);
1267 if (Name == "core id") {
1268 assert(CurCoreId == -1 &&
1269 "Expected a physical id before seeing another core id");
1270 Val.getAsInteger(10, CurCoreId);
1272 if (CurPhysicalId != -1 && CurCoreId != -1) {
1273 UniqueItems.insert(std::make_pair(CurPhysicalId, CurCoreId));
1278 return UniqueItems.size();
1280 #elif defined(__APPLE__) && defined(__x86_64__)
1281 #include <sys/param.h>
1282 #include <sys/sysctl.h>
1284 // Gets the number of *physical cores* on the machine.
1285 static int computeHostNumPhysicalCores() {
1287 size_t len = sizeof(count);
1288 sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0);
1292 nm[1] = HW_AVAILCPU;
1293 sysctl(nm, 2, &count, &len, NULL, 0);
1300 // On other systems, return -1 to indicate unknown.
1301 static int computeHostNumPhysicalCores() { return -1; }
1304 int sys::getHostNumPhysicalCores() {
1305 static int NumCores = computeHostNumPhysicalCores();
1309 #if defined(__i386__) || defined(_M_IX86) || \
1310 defined(__x86_64__) || defined(_M_X64)
1311 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
1312 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
1319 if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) ||
1323 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX);
1325 Features["cmov"] = (EDX >> 15) & 1;
1326 Features["mmx"] = (EDX >> 23) & 1;
1327 Features["sse"] = (EDX >> 25) & 1;
1328 Features["sse2"] = (EDX >> 26) & 1;
1329 Features["sse3"] = (ECX >> 0) & 1;
1330 Features["ssse3"] = (ECX >> 9) & 1;
1331 Features["sse4.1"] = (ECX >> 19) & 1;
1332 Features["sse4.2"] = (ECX >> 20) & 1;
1334 Features["pclmul"] = (ECX >> 1) & 1;
1335 Features["cx16"] = (ECX >> 13) & 1;
1336 Features["movbe"] = (ECX >> 22) & 1;
1337 Features["popcnt"] = (ECX >> 23) & 1;
1338 Features["aes"] = (ECX >> 25) & 1;
1339 Features["rdrnd"] = (ECX >> 30) & 1;
1341 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
1342 // indicates that the AVX registers will be saved and restored on context
1343 // switch, then we have full AVX support.
1344 bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) &&
1345 !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6);
1346 Features["avx"] = HasAVXSave;
1347 Features["fma"] = HasAVXSave && (ECX >> 12) & 1;
1348 Features["f16c"] = HasAVXSave && (ECX >> 29) & 1;
1350 // Only enable XSAVE if OS has enabled support for saving YMM state.
1351 Features["xsave"] = HasAVXSave && (ECX >> 26) & 1;
1353 // AVX512 requires additional context to be saved by the OS.
1354 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0);
1356 unsigned MaxExtLevel;
1357 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1359 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1360 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1361 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1);
1362 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1);
1363 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1);
1364 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave;
1365 Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1);
1366 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave;
1367 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1);
1368 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1);
1370 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 &&
1371 !getX86CpuIDAndInfoEx(0x80000008,0x0, &EAX, &EBX, &ECX, &EDX);
1372 Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1);
1375 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1377 // AVX2 is only supported if we have the OS save support from AVX.
1378 Features["avx2"] = HasAVXSave && HasLeaf7 && ((EBX >> 5) & 1);
1380 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1);
1381 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1);
1382 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1);
1383 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1);
1384 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1);
1385 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1);
1386 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1);
1387 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1);
1388 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1);
1389 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1);
1391 // AVX512 is only supported if the OS supports the context save for it.
1392 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save;
1393 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save;
1394 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save;
1395 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save;
1396 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save;
1397 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save;
1398 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save;
1399 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save;
1401 Features["prefetchwt1"] = HasLeaf7 && (ECX & 1);
1402 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save;
1403 Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save;
1404 // Enable protection keys
1405 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1);
1407 bool HasLeafD = MaxLevel >= 0xd &&
1408 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
1410 // Only enable XSAVE if OS has enabled support for saving YMM state.
1411 Features["xsaveopt"] = HasAVXSave && HasLeafD && ((EAX >> 0) & 1);
1412 Features["xsavec"] = HasAVXSave && HasLeafD && ((EAX >> 1) & 1);
1413 Features["xsaves"] = HasAVXSave && HasLeafD && ((EAX >> 3) & 1);
1417 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1418 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
1419 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1423 SmallVector<StringRef, 32> Lines;
1424 P->getBuffer().split(Lines, "\n");
1426 SmallVector<StringRef, 32> CPUFeatures;
1428 // Look for the CPU features.
1429 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
1430 if (Lines[I].startswith("Features")) {
1431 Lines[I].split(CPUFeatures, ' ');
1435 #if defined(__aarch64__)
1436 // Keep track of which crypto features we have seen
1437 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 };
1438 uint32_t crypto = 0;
1441 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
1442 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I])
1443 #if defined(__aarch64__)
1444 .Case("asimd", "neon")
1445 .Case("fp", "fp-armv8")
1446 .Case("crc32", "crc")
1448 .Case("half", "fp16")
1449 .Case("neon", "neon")
1450 .Case("vfpv3", "vfp3")
1451 .Case("vfpv3d16", "d16")
1452 .Case("vfpv4", "vfp4")
1453 .Case("idiva", "hwdiv-arm")
1454 .Case("idivt", "hwdiv")
1458 #if defined(__aarch64__)
1459 // We need to check crypto separately since we need all of the crypto
1460 // extensions to enable the subtarget feature
1461 if (CPUFeatures[I] == "aes")
1463 else if (CPUFeatures[I] == "pmull")
1464 crypto |= CAP_PMULL;
1465 else if (CPUFeatures[I] == "sha1")
1467 else if (CPUFeatures[I] == "sha2")
1471 if (LLVMFeatureStr != "")
1472 Features[LLVMFeatureStr] = true;
1475 #if defined(__aarch64__)
1476 // If we have all crypto bits we can add the feature
1477 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2))
1478 Features["crypto"] = true;
1484 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; }
1487 std::string sys::getProcessTriple() {
1488 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE);
1489 Triple PT(Triple::normalize(TargetTripleString));
1491 if (sizeof(void *) == 8 && PT.isArch32Bit())
1492 PT = PT.get64BitArchVariant();
1493 if (sizeof(void *) == 4 && PT.isArch64Bit())
1494 PT = PT.get32BitArchVariant();