1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the operating system Host concept.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Support/Host.h"
15 #include "llvm/ADT/SmallSet.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/ADT/StringSwitch.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/Config/config.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/FileSystem.h"
23 #include "llvm/Support/MemoryBuffer.h"
24 #include "llvm/Support/raw_ostream.h"
28 // Include the platform-specific parts of this class.
30 #include "Unix/Host.inc"
33 #include "Windows/Host.inc"
38 #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
39 #include <mach/host_info.h>
40 #include <mach/mach.h>
41 #include <mach/mach_host.h>
42 #include <mach/machine.h>
45 #define DEBUG_TYPE "host-detection"
47 //===----------------------------------------------------------------------===//
49 // Implementations of the CPU detection routines
51 //===----------------------------------------------------------------------===//
55 static std::unique_ptr<llvm::MemoryBuffer>
56 LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent() {
57 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text =
58 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo");
59 if (std::error_code EC = Text.getError()) {
60 llvm::errs() << "Can't read "
61 << "/proc/cpuinfo: " << EC.message() << "\n";
64 return std::move(*Text);
67 StringRef sys::detail::getHostCPUNameForPowerPC(
68 const StringRef &ProcCpuinfoContent) {
69 // Access to the Processor Version Register (PVR) on PowerPC is privileged,
70 // and so we must use an operating-system interface to determine the current
71 // processor type. On Linux, this is exposed through the /proc/cpuinfo file.
72 const char *generic = "generic";
74 // The cpu line is second (after the 'processor: 0' line), so if this
75 // buffer is too small then something has changed (or is wrong).
76 StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin();
77 StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end();
79 StringRef::const_iterator CIP = CPUInfoStart;
81 StringRef::const_iterator CPUStart = 0;
84 // We need to find the first line which starts with cpu, spaces, and a colon.
85 // After the colon, there may be some additional spaces and then the cpu type.
86 while (CIP < CPUInfoEnd && CPUStart == 0) {
87 if (CIP < CPUInfoEnd && *CIP == '\n')
90 if (CIP < CPUInfoEnd && *CIP == 'c') {
92 if (CIP < CPUInfoEnd && *CIP == 'p') {
94 if (CIP < CPUInfoEnd && *CIP == 'u') {
96 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
99 if (CIP < CPUInfoEnd && *CIP == ':') {
101 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
104 if (CIP < CPUInfoEnd) {
106 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' &&
107 *CIP != ',' && *CIP != '\n'))
109 CPULen = CIP - CPUStart;
117 while (CIP < CPUInfoEnd && *CIP != '\n')
124 return StringSwitch<const char *>(StringRef(CPUStart, CPULen))
125 .Case("604e", "604e")
127 .Case("7400", "7400")
128 .Case("7410", "7400")
129 .Case("7447", "7400")
130 .Case("7455", "7450")
132 .Case("POWER4", "970")
133 .Case("PPC970FX", "970")
134 .Case("PPC970MP", "970")
136 .Case("POWER5", "g5")
138 .Case("POWER6", "pwr6")
139 .Case("POWER7", "pwr7")
140 .Case("POWER8", "pwr8")
141 .Case("POWER8E", "pwr8")
142 .Case("POWER8NVL", "pwr8")
143 .Case("POWER9", "pwr9")
147 StringRef sys::detail::getHostCPUNameForARM(
148 const StringRef &ProcCpuinfoContent) {
149 // The cpuid register on arm is not accessible from user space. On Linux,
150 // it is exposed through the /proc/cpuinfo file.
152 // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line
154 SmallVector<StringRef, 32> Lines;
155 ProcCpuinfoContent.split(Lines, "\n");
157 // Look for the CPU implementer line.
158 StringRef Implementer;
160 for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
161 if (Lines[I].startswith("CPU implementer"))
162 Implementer = Lines[I].substr(15).ltrim("\t :");
163 if (Lines[I].startswith("Hardware"))
164 Hardware = Lines[I].substr(8).ltrim("\t :");
167 if (Implementer == "0x41") { // ARM Ltd.
168 // MSM8992/8994 may give cpu part for the core that the kernel is running on,
169 // which is undeterministic and wrong. Always return cortex-a53 for these SoC.
170 if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996"))
174 // Look for the CPU part line.
175 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
176 if (Lines[I].startswith("CPU part"))
177 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
178 // values correspond to the "Part number" in the CP15/c0 register. The
179 // contents are specified in the various processor manuals.
180 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
181 .Case("0x926", "arm926ej-s")
182 .Case("0xb02", "mpcore")
183 .Case("0xb36", "arm1136j-s")
184 .Case("0xb56", "arm1156t2-s")
185 .Case("0xb76", "arm1176jz-s")
186 .Case("0xc08", "cortex-a8")
187 .Case("0xc09", "cortex-a9")
188 .Case("0xc0f", "cortex-a15")
189 .Case("0xc20", "cortex-m0")
190 .Case("0xc23", "cortex-m3")
191 .Case("0xc24", "cortex-m4")
192 .Case("0xd04", "cortex-a35")
193 .Case("0xd03", "cortex-a53")
194 .Case("0xd07", "cortex-a57")
195 .Case("0xd08", "cortex-a72")
196 .Case("0xd09", "cortex-a73")
200 if (Implementer == "0x51") // Qualcomm Technologies, Inc.
201 // Look for the CPU part line.
202 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
203 if (Lines[I].startswith("CPU part"))
204 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
205 // values correspond to the "Part number" in the CP15/c0 register. The
206 // contents are specified in the various processor manuals.
207 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
208 .Case("0x06f", "krait") // APQ8064
209 .Case("0x201", "kryo")
210 .Case("0x205", "kryo")
216 StringRef sys::detail::getHostCPUNameForS390x(
217 const StringRef &ProcCpuinfoContent) {
218 // STIDP is a privileged operation, so use /proc/cpuinfo instead.
220 // The "processor 0:" line comes after a fair amount of other information,
221 // including a cache breakdown, but this should be plenty.
222 SmallVector<StringRef, 32> Lines;
223 ProcCpuinfoContent.split(Lines, "\n");
225 // Look for the CPU features.
226 SmallVector<StringRef, 32> CPUFeatures;
227 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
228 if (Lines[I].startswith("features")) {
229 size_t Pos = Lines[I].find(":");
230 if (Pos != StringRef::npos) {
231 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' ');
236 // We need to check for the presence of vector support independently of
237 // the machine type, since we may only use the vector register set when
238 // supported by the kernel (and hypervisor).
239 bool HaveVectorSupport = false;
240 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
241 if (CPUFeatures[I] == "vx")
242 HaveVectorSupport = true;
245 // Now check the processor machine type.
246 for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
247 if (Lines[I].startswith("processor ")) {
248 size_t Pos = Lines[I].find("machine = ");
249 if (Pos != StringRef::npos) {
250 Pos += sizeof("machine = ") - 1;
252 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) {
253 if (Id >= 2964 && HaveVectorSupport)
268 #if defined(__i386__) || defined(_M_IX86) || \
269 defined(__x86_64__) || defined(_M_X64)
271 enum VendorSignatures {
272 SIG_INTEL = 0x756e6547 /* Genu */,
273 SIG_AMD = 0x68747541 /* Auth */
276 enum ProcessorVendors {
283 enum ProcessorTypes {
311 enum ProcessorSubtypes {
312 INTEL_COREI7_NEHALEM = 1,
313 INTEL_COREI7_WESTMERE,
314 INTEL_COREI7_SANDYBRIDGE,
323 INTEL_COREI7_IVYBRIDGE,
324 INTEL_COREI7_HASWELL,
325 INTEL_COREI7_BROADWELL,
326 INTEL_COREI7_SKYLAKE,
327 INTEL_COREI7_SKYLAKE_AVX512,
329 INTEL_ATOM_SILVERMONT,
330 INTEL_KNIGHTS_LANDING,
350 enum ProcessorFeatures {
369 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max).
370 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID
371 // support. Consequently, for i386, the presence of CPUID is checked first
372 // via the corresponding eflags bit.
373 // Removal of cpuid.h header motivated by PR30384
374 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp
375 // or test-suite, but are used in external projects e.g. libstdcxx
376 static bool isCpuIdSupported() {
377 #if defined(__GNUC__) || defined(__clang__)
378 #if defined(__i386__)
379 int __cpuid_supported;
382 " movl %%eax,%%ecx\n"
383 " xorl $0x00200000,%%eax\n"
389 " cmpl %%eax,%%ecx\n"
393 : "=r"(__cpuid_supported)
396 if (!__cpuid_supported)
404 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in
405 /// the specified arguments. If we can't run cpuid on the host, return true.
406 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
407 unsigned *rECX, unsigned *rEDX) {
408 #if defined(__GNUC__) || defined(__clang__) || defined(_MSC_VER)
409 #if defined(__GNUC__) || defined(__clang__)
410 #if defined(__x86_64__)
411 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually.
412 // FIXME: should we save this for Clang?
413 __asm__("movq\t%%rbx, %%rsi\n\t"
415 "xchgq\t%%rbx, %%rsi\n\t"
416 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
418 #elif defined(__i386__)
419 __asm__("movl\t%%ebx, %%esi\n\t"
421 "xchgl\t%%ebx, %%esi\n\t"
422 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
425 assert(0 && "This method is defined only for x86.");
427 #elif defined(_MSC_VER)
428 // The MSVC intrinsic is portable across x86 and x64.
430 __cpuid(registers, value);
431 *rEAX = registers[0];
432 *rEBX = registers[1];
433 *rECX = registers[2];
434 *rEDX = registers[3];
442 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return
443 /// the 4 values in the specified arguments. If we can't run cpuid on the host,
445 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf,
446 unsigned *rEAX, unsigned *rEBX, unsigned *rECX,
448 #if defined(__GNUC__) || defined(__clang__) || defined(_MSC_VER)
449 #if defined(__x86_64__) || defined(_M_X64)
450 #if defined(__GNUC__) || defined(__clang__)
451 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
452 // FIXME: should we save this for Clang?
453 __asm__("movq\t%%rbx, %%rsi\n\t"
455 "xchgq\t%%rbx, %%rsi\n\t"
456 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
457 : "a"(value), "c"(subleaf));
458 #elif defined(_MSC_VER)
460 __cpuidex(registers, value, subleaf);
461 *rEAX = registers[0];
462 *rEBX = registers[1];
463 *rECX = registers[2];
464 *rEDX = registers[3];
466 #elif defined(__i386__) || defined(_M_IX86)
467 #if defined(__GNUC__) || defined(__clang__)
468 __asm__("movl\t%%ebx, %%esi\n\t"
470 "xchgl\t%%ebx, %%esi\n\t"
471 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
472 : "a"(value), "c"(subleaf));
473 #elif defined(_MSC_VER)
479 mov dword ptr [esi],eax
481 mov dword ptr [esi],ebx
483 mov dword ptr [esi],ecx
485 mov dword ptr [esi],edx
489 assert(0 && "This method is defined only for x86.");
497 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) {
498 #if defined(__GNUC__) || defined(__clang__)
499 // Check xgetbv; this uses a .byte sequence instead of the instruction
500 // directly because older assemblers do not include support for xgetbv and
501 // there is no easy way to conditionally compile based on the assembler used.
502 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0));
504 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
505 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
507 *rEDX = Result >> 32;
514 static void detectX86FamilyModel(unsigned EAX, unsigned *Family,
516 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11
517 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7
518 if (*Family == 6 || *Family == 0xf) {
520 // Examine extended family ID if family ID is F.
521 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27
522 // Examine extended model ID if family ID is 6 or F.
523 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
528 getIntelProcessorTypeAndSubtype(unsigned int Family, unsigned int Model,
529 unsigned int Brand_id, unsigned int Features,
530 unsigned *Type, unsigned *Subtype) {
539 case 0: // Intel486 DX processors
540 case 1: // Intel486 DX processors
541 case 2: // Intel486 SX processors
542 case 3: // Intel487 processors, IntelDX2 OverDrive processors,
543 // IntelDX2 processors
544 case 4: // Intel486 SL processor
545 case 5: // IntelSX2 processors
546 case 7: // Write-Back Enhanced IntelDX2 processors
547 case 8: // IntelDX4 OverDrive processors, IntelDX4 processors
555 case 1: // Pentium OverDrive processor for Pentium processor (60, 66),
556 // Pentium processors (60, 66)
557 case 2: // Pentium OverDrive processor for Pentium processor (75, 90,
558 // 100, 120, 133), Pentium processors (75, 90, 100, 120, 133,
560 case 3: // Pentium OverDrive processors for Intel486 processor-based
562 *Type = INTEL_PENTIUM;
564 case 4: // Pentium OverDrive processor with MMX technology for Pentium
565 // processor (75, 90, 100, 120, 133), Pentium processor with
566 // MMX technology (166, 200)
567 *Type = INTEL_PENTIUM;
568 *Subtype = INTEL_PENTIUM_MMX;
571 *Type = INTEL_PENTIUM;
577 case 0x01: // Pentium Pro processor
578 *Type = INTEL_PENTIUM_PRO;
580 case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor,
582 case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor,
583 // model 05, and Intel Celeron processor, model 05
584 case 0x06: // Celeron processor, model 06
585 *Type = INTEL_PENTIUM_II;
587 case 0x07: // Pentium III processor, model 07, and Pentium III Xeon
588 // processor, model 07
589 case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor,
590 // model 08, and Celeron processor, model 08
591 case 0x0a: // Pentium III Xeon processor, model 0Ah
592 case 0x0b: // Pentium III processor, model 0Bh
593 *Type = INTEL_PENTIUM_III;
595 case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09.
596 case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model
597 // 0Dh. All processors are manufactured using the 90 nm process.
598 case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579
599 // Integrated Processor with Intel QuickAssist Technology
600 *Type = INTEL_PENTIUM_M;
602 case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model
603 // 0Eh. All processors are manufactured using the 65 nm process.
604 *Type = INTEL_CORE_DUO;
606 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile
607 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad
608 // mobile processor, Intel Core 2 Extreme processor, Intel
609 // Pentium Dual-Core processor, Intel Xeon processor, model
610 // 0Fh. All processors are manufactured using the 65 nm process.
611 case 0x16: // Intel Celeron processor model 16h. All processors are
612 // manufactured using the 65 nm process
613 *Type = INTEL_CORE2; // "core2"
614 *Subtype = INTEL_CORE2_65;
616 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model
617 // 17h. All processors are manufactured using the 45 nm process.
619 // 45nm: Penryn , Wolfdale, Yorkfield (XE)
620 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using
621 // the 45 nm process.
622 *Type = INTEL_CORE2; // "penryn"
623 *Subtype = INTEL_CORE2_45;
625 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All
626 // processors are manufactured using the 45 nm process.
627 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz.
628 // As found in a Summer 2010 model iMac.
630 case 0x2e: // Nehalem EX
631 *Type = INTEL_COREI7; // "nehalem"
632 *Subtype = INTEL_COREI7_NEHALEM;
634 case 0x25: // Intel Core i7, laptop version.
635 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All
636 // processors are manufactured using the 32 nm process.
637 case 0x2f: // Westmere EX
638 *Type = INTEL_COREI7; // "westmere"
639 *Subtype = INTEL_COREI7_WESTMERE;
641 case 0x2a: // Intel Core i7 processor. All processors are manufactured
642 // using the 32 nm process.
644 *Type = INTEL_COREI7; //"sandybridge"
645 *Subtype = INTEL_COREI7_SANDYBRIDGE;
648 case 0x3e: // Ivy Bridge EP
649 *Type = INTEL_COREI7; // "ivybridge"
650 *Subtype = INTEL_COREI7_IVYBRIDGE;
658 *Type = INTEL_COREI7; // "haswell"
659 *Subtype = INTEL_COREI7_HASWELL;
667 *Type = INTEL_COREI7; // "broadwell"
668 *Subtype = INTEL_COREI7_BROADWELL;
672 case 0x4e: // Skylake mobile
673 case 0x5e: // Skylake desktop
674 case 0x8e: // Kaby Lake mobile
675 case 0x9e: // Kaby Lake desktop
676 *Type = INTEL_COREI7; // "skylake"
677 *Subtype = INTEL_COREI7_SKYLAKE;
682 *Type = INTEL_COREI7;
683 // Check that we really have AVX512
684 if (Features & (1 << FEATURE_AVX512)) {
685 *Subtype = INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512"
687 *Subtype = INTEL_COREI7_SKYLAKE; // "skylake"
691 case 0x1c: // Most 45 nm Intel Atom processors
692 case 0x26: // 45 nm Atom Lincroft
693 case 0x27: // 32 nm Atom Medfield
694 case 0x35: // 32 nm Atom Midview
695 case 0x36: // 32 nm Atom Midview
697 *Subtype = INTEL_ATOM_BONNELL;
700 // Atom Silvermont codes from the Intel software optimization guide.
706 case 0x4c: // really airmont
708 *Subtype = INTEL_ATOM_SILVERMONT;
709 break; // "silvermont"
712 *Type = INTEL_XEONPHI; // knl
713 *Subtype = INTEL_KNIGHTS_LANDING;
716 default: // Unknown family 6 CPU, try to guess.
717 if (Features & (1 << FEATURE_AVX512)) {
718 *Type = INTEL_XEONPHI; // knl
719 *Subtype = INTEL_KNIGHTS_LANDING;
722 if (Features & (1 << FEATURE_ADX)) {
723 *Type = INTEL_COREI7;
724 *Subtype = INTEL_COREI7_BROADWELL;
727 if (Features & (1 << FEATURE_AVX2)) {
728 *Type = INTEL_COREI7;
729 *Subtype = INTEL_COREI7_HASWELL;
732 if (Features & (1 << FEATURE_AVX)) {
733 *Type = INTEL_COREI7;
734 *Subtype = INTEL_COREI7_SANDYBRIDGE;
737 if (Features & (1 << FEATURE_SSE4_2)) {
738 if (Features & (1 << FEATURE_MOVBE)) {
740 *Subtype = INTEL_ATOM_SILVERMONT;
742 *Type = INTEL_COREI7;
743 *Subtype = INTEL_COREI7_NEHALEM;
747 if (Features & (1 << FEATURE_SSE4_1)) {
748 *Type = INTEL_CORE2; // "penryn"
749 *Subtype = INTEL_CORE2_45;
752 if (Features & (1 << FEATURE_SSSE3)) {
753 if (Features & (1 << FEATURE_MOVBE)) {
755 *Subtype = INTEL_ATOM_BONNELL; // "bonnell"
757 *Type = INTEL_CORE2; // "core2"
758 *Subtype = INTEL_CORE2_65;
762 if (Features & (1 << FEATURE_EM64T)) {
763 *Type = INTEL_X86_64;
766 if (Features & (1 << FEATURE_SSE2)) {
767 *Type = INTEL_PENTIUM_M;
770 if (Features & (1 << FEATURE_SSE)) {
771 *Type = INTEL_PENTIUM_III;
774 if (Features & (1 << FEATURE_MMX)) {
775 *Type = INTEL_PENTIUM_II;
778 *Type = INTEL_PENTIUM_PRO;
784 case 0: // Pentium 4 processor, Intel Xeon processor. All processors are
785 // model 00h and manufactured using the 0.18 micron process.
786 case 1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon
787 // processor MP, and Intel Celeron processor. All processors are
788 // model 01h and manufactured using the 0.18 micron process.
789 case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M,
790 // Intel Xeon processor, Intel Xeon processor MP, Intel Celeron
791 // processor, and Mobile Intel Celeron processor. All processors
792 // are model 02h and manufactured using the 0.13 micron process.
794 ((Features & (1 << FEATURE_EM64T)) ? INTEL_X86_64 : INTEL_PENTIUM_IV);
797 case 3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D
798 // processor. All processors are model 03h and manufactured using
799 // the 90 nm process.
800 case 4: // Pentium 4 processor, Pentium 4 processor Extreme Edition,
801 // Pentium D processor, Intel Xeon processor, Intel Xeon
802 // processor MP, Intel Celeron D processor. All processors are
803 // model 04h and manufactured using the 90 nm process.
804 case 6: // Pentium 4 processor, Pentium D processor, Pentium processor
805 // Extreme Edition, Intel Xeon processor, Intel Xeon processor
806 // MP, Intel Celeron D processor. All processors are model 06h
807 // and manufactured using the 65 nm process.
809 ((Features & (1 << FEATURE_EM64T)) ? INTEL_NOCONA : INTEL_PRESCOTT);
814 ((Features & (1 << FEATURE_EM64T)) ? INTEL_X86_64 : INTEL_PENTIUM_IV);
824 static void getAMDProcessorTypeAndSubtype(unsigned int Family,
826 unsigned int Features,
829 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There
830 // appears to be no way to generate the wide variety of AMD-specific targets
831 // from the information returned from CPUID.
841 *Subtype = AMDPENTIUM_K6;
844 *Subtype = AMDPENTIUM_K62;
848 *Subtype = AMDPENTIUM_K63;
851 *Subtype = AMDPENTIUM_GEODE;
859 *Subtype = AMDATHLON_TBIRD;
860 break; // "athlon-tbird"
864 *Subtype = AMDATHLON_MP;
865 break; // "athlon-mp"
867 *Subtype = AMDATHLON_XP;
868 break; // "athlon-xp"
873 if (Features & (1 << FEATURE_SSE3)) {
874 *Subtype = AMDATHLON_K8SSE3;
879 *Subtype = AMDATHLON_OPTERON;
882 *Subtype = AMDATHLON_FX;
883 break; // "athlon-fx"; also opteron
885 *Subtype = AMDATHLON_64;
890 *Type = AMDFAM10H; // "amdfam10"
893 *Subtype = AMDFAM10H_BARCELONA;
896 *Subtype = AMDFAM10H_SHANGHAI;
899 *Subtype = AMDFAM10H_ISTANBUL;
905 *Subtype = AMD_BTVER1;
910 (1 << FEATURE_AVX))) { // If no AVX support, provide a sane fallback.
911 *Subtype = AMD_BTVER1;
914 if (Model >= 0x50 && Model <= 0x6f) {
915 *Subtype = AMDFAM15H_BDVER4;
916 break; // "bdver4"; 50h-6Fh: Excavator
918 if (Model >= 0x30 && Model <= 0x3f) {
919 *Subtype = AMDFAM15H_BDVER3;
920 break; // "bdver3"; 30h-3Fh: Steamroller
922 if (Model >= 0x10 && Model <= 0x1f) {
923 *Subtype = AMDFAM15H_BDVER2;
924 break; // "bdver2"; 10h-1Fh: Piledriver
927 *Subtype = AMDFAM15H_BDVER1;
928 break; // "bdver1"; 00h-0Fh: Bulldozer
934 (1 << FEATURE_AVX))) { // If no AVX support provide a sane fallback.
935 *Subtype = AMD_BTVER1;
938 *Subtype = AMD_BTVER2;
942 if (Features & (1 << FEATURE_ADX)) {
943 *Subtype = AMDFAM17H_ZNVER1;
946 *Subtype = AMD_BTVER1;
953 static unsigned getAvailableFeatures(unsigned int ECX, unsigned int EDX,
955 unsigned Features = 0;
956 unsigned int EAX, EBX;
957 Features |= (((EDX >> 23) & 1) << FEATURE_MMX);
958 Features |= (((EDX >> 25) & 1) << FEATURE_SSE);
959 Features |= (((EDX >> 26) & 1) << FEATURE_SSE2);
960 Features |= (((ECX >> 0) & 1) << FEATURE_SSE3);
961 Features |= (((ECX >> 9) & 1) << FEATURE_SSSE3);
962 Features |= (((ECX >> 19) & 1) << FEATURE_SSE4_1);
963 Features |= (((ECX >> 20) & 1) << FEATURE_SSE4_2);
964 Features |= (((ECX >> 22) & 1) << FEATURE_MOVBE);
966 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
967 // indicates that the AVX registers will be saved and restored on context
968 // switch, then we have full AVX support.
969 const unsigned AVXBits = (1 << 27) | (1 << 28);
970 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) &&
971 ((EAX & 0x6) == 0x6);
972 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0);
974 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
975 bool HasADX = HasLeaf7 && ((EBX >> 19) & 1);
976 bool HasAVX2 = HasAVX && HasLeaf7 && (EBX & 0x20);
977 bool HasAVX512 = HasLeaf7 && HasAVX512Save && ((EBX >> 16) & 1);
978 Features |= (HasAVX << FEATURE_AVX);
979 Features |= (HasAVX2 << FEATURE_AVX2);
980 Features |= (HasAVX512 << FEATURE_AVX512);
981 Features |= (HasAVX512Save << FEATURE_AVX512SAVE);
982 Features |= (HasADX << FEATURE_ADX);
984 getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
985 Features |= (((EDX >> 29) & 0x1) << FEATURE_EM64T);
989 StringRef sys::getHostCPUName() {
990 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
991 unsigned MaxLeaf, Vendor;
993 #if defined(__GNUC__) || defined(__clang__)
994 //FIXME: include cpuid.h from clang or copy __get_cpuid_max here
995 // and simplify it to not invoke __cpuid (like cpu_model.c in
996 // compiler-rt/lib/builtins/cpu_model.c?
997 // Opting for the second option.
998 if(!isCpuIdSupported())
1001 if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX))
1003 if (getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
1006 unsigned Brand_id = EBX & 0xff;
1007 unsigned Family = 0, Model = 0;
1008 unsigned Features = 0;
1009 detectX86FamilyModel(EAX, &Family, &Model);
1010 Features = getAvailableFeatures(ECX, EDX, MaxLeaf);
1015 if (Vendor == SIG_INTEL) {
1016 getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features, &Type,
1024 if (Subtype == INTEL_PENTIUM_MMX)
1025 return "pentium-mmx";
1027 case INTEL_PENTIUM_PRO:
1028 return "pentiumpro";
1029 case INTEL_PENTIUM_II:
1031 case INTEL_PENTIUM_III:
1033 case INTEL_PENTIUM_IV:
1035 case INTEL_PENTIUM_M:
1037 case INTEL_CORE_DUO:
1041 case INTEL_CORE2_65:
1043 case INTEL_CORE2_45:
1050 case INTEL_COREI7_NEHALEM:
1052 case INTEL_COREI7_WESTMERE:
1054 case INTEL_COREI7_SANDYBRIDGE:
1055 return "sandybridge";
1056 case INTEL_COREI7_IVYBRIDGE:
1058 case INTEL_COREI7_HASWELL:
1060 case INTEL_COREI7_BROADWELL:
1062 case INTEL_COREI7_SKYLAKE:
1064 case INTEL_COREI7_SKYLAKE_AVX512:
1065 return "skylake-avx512";
1071 case INTEL_ATOM_BONNELL:
1073 case INTEL_ATOM_SILVERMONT:
1074 return "silvermont";
1079 return "knl"; /*update for more variants added*/
1084 case INTEL_PRESCOTT:
1089 } else if (Vendor == SIG_AMD) {
1090 getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype);
1098 case AMDPENTIUM_K62:
1100 case AMDPENTIUM_K63:
1102 case AMDPENTIUM_GEODE:
1109 case AMDATHLON_TBIRD:
1110 return "athlon-tbird";
1115 case AMDATHLON_K8SSE3:
1117 case AMDATHLON_OPTERON:
1127 if(Subtype == AMDFAM10H_BARCELONA)
1134 case AMDFAM15H_BDVER1:
1136 case AMDFAM15H_BDVER2:
1138 case AMDFAM15H_BDVER3:
1140 case AMDFAM15H_BDVER4:
1160 case AMDFAM17H_ZNVER1:
1172 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
1173 StringRef sys::getHostCPUName() {
1174 host_basic_info_data_t hostInfo;
1175 mach_msg_type_number_t infoCount;
1177 infoCount = HOST_BASIC_INFO_COUNT;
1178 host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo,
1181 if (hostInfo.cpu_type != CPU_TYPE_POWERPC)
1184 switch (hostInfo.cpu_subtype) {
1185 case CPU_SUBTYPE_POWERPC_601:
1187 case CPU_SUBTYPE_POWERPC_602:
1189 case CPU_SUBTYPE_POWERPC_603:
1191 case CPU_SUBTYPE_POWERPC_603e:
1193 case CPU_SUBTYPE_POWERPC_603ev:
1195 case CPU_SUBTYPE_POWERPC_604:
1197 case CPU_SUBTYPE_POWERPC_604e:
1199 case CPU_SUBTYPE_POWERPC_620:
1201 case CPU_SUBTYPE_POWERPC_750:
1203 case CPU_SUBTYPE_POWERPC_7400:
1205 case CPU_SUBTYPE_POWERPC_7450:
1207 case CPU_SUBTYPE_POWERPC_970:
1214 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__))
1215 StringRef sys::getHostCPUName() {
1216 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1217 const StringRef& Content = P ? P->getBuffer() : "";
1218 return detail::getHostCPUNameForPowerPC(Content);
1220 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1221 StringRef sys::getHostCPUName() {
1222 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1223 const StringRef& Content = P ? P->getBuffer() : "";
1224 return detail::getHostCPUNameForARM(Content);
1226 #elif defined(__linux__) && defined(__s390x__)
1227 StringRef sys::getHostCPUName() {
1228 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1229 const StringRef& Content = P ? P->getBuffer() : "";
1230 return detail::getHostCPUNameForS390x(Content);
1233 StringRef sys::getHostCPUName() { return "generic"; }
1236 #if defined(__linux__) && defined(__x86_64__)
1237 // On Linux, the number of physical cores can be computed from /proc/cpuinfo,
1238 // using the number of unique physical/core id pairs. The following
1239 // implementation reads the /proc/cpuinfo format on an x86_64 system.
1240 static int computeHostNumPhysicalCores() {
1241 // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be
1242 // mmapped because it appears to have 0 size.
1243 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text =
1244 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo");
1245 if (std::error_code EC = Text.getError()) {
1246 llvm::errs() << "Can't read "
1247 << "/proc/cpuinfo: " << EC.message() << "\n";
1250 SmallVector<StringRef, 8> strs;
1251 (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1,
1252 /*KeepEmpty=*/false);
1253 int CurPhysicalId = -1;
1255 SmallSet<std::pair<int, int>, 32> UniqueItems;
1256 for (auto &Line : strs) {
1258 if (!Line.startswith("physical id") && !Line.startswith("core id"))
1260 std::pair<StringRef, StringRef> Data = Line.split(':');
1261 auto Name = Data.first.trim();
1262 auto Val = Data.second.trim();
1263 if (Name == "physical id") {
1264 assert(CurPhysicalId == -1 &&
1265 "Expected a core id before seeing another physical id");
1266 Val.getAsInteger(10, CurPhysicalId);
1268 if (Name == "core id") {
1269 assert(CurCoreId == -1 &&
1270 "Expected a physical id before seeing another core id");
1271 Val.getAsInteger(10, CurCoreId);
1273 if (CurPhysicalId != -1 && CurCoreId != -1) {
1274 UniqueItems.insert(std::make_pair(CurPhysicalId, CurCoreId));
1279 return UniqueItems.size();
1281 #elif defined(__APPLE__) && defined(__x86_64__)
1282 #include <sys/param.h>
1283 #include <sys/sysctl.h>
1285 // Gets the number of *physical cores* on the machine.
1286 static int computeHostNumPhysicalCores() {
1288 size_t len = sizeof(count);
1289 sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0);
1293 nm[1] = HW_AVAILCPU;
1294 sysctl(nm, 2, &count, &len, NULL, 0);
1301 // On other systems, return -1 to indicate unknown.
1302 static int computeHostNumPhysicalCores() { return -1; }
1305 int sys::getHostNumPhysicalCores() {
1306 static int NumCores = computeHostNumPhysicalCores();
1310 #if defined(__i386__) || defined(_M_IX86) || \
1311 defined(__x86_64__) || defined(_M_X64)
1312 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
1313 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
1320 if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) ||
1324 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX);
1326 Features["cmov"] = (EDX >> 15) & 1;
1327 Features["mmx"] = (EDX >> 23) & 1;
1328 Features["sse"] = (EDX >> 25) & 1;
1329 Features["sse2"] = (EDX >> 26) & 1;
1330 Features["sse3"] = (ECX >> 0) & 1;
1331 Features["ssse3"] = (ECX >> 9) & 1;
1332 Features["sse4.1"] = (ECX >> 19) & 1;
1333 Features["sse4.2"] = (ECX >> 20) & 1;
1335 Features["pclmul"] = (ECX >> 1) & 1;
1336 Features["cx16"] = (ECX >> 13) & 1;
1337 Features["movbe"] = (ECX >> 22) & 1;
1338 Features["popcnt"] = (ECX >> 23) & 1;
1339 Features["aes"] = (ECX >> 25) & 1;
1340 Features["rdrnd"] = (ECX >> 30) & 1;
1342 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
1343 // indicates that the AVX registers will be saved and restored on context
1344 // switch, then we have full AVX support.
1345 bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) &&
1346 !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6);
1347 Features["avx"] = HasAVXSave;
1348 Features["fma"] = HasAVXSave && (ECX >> 12) & 1;
1349 Features["f16c"] = HasAVXSave && (ECX >> 29) & 1;
1351 // Only enable XSAVE if OS has enabled support for saving YMM state.
1352 Features["xsave"] = HasAVXSave && (ECX >> 26) & 1;
1354 // AVX512 requires additional context to be saved by the OS.
1355 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0);
1357 unsigned MaxExtLevel;
1358 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1360 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1361 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1362 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1);
1363 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1);
1364 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1);
1365 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave;
1366 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave;
1367 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1);
1368 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1);
1370 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 &&
1371 !getX86CpuIDAndInfoEx(0x80000008,0x0, &EAX, &EBX, &ECX, &EDX);
1372 Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1);
1375 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1377 // AVX2 is only supported if we have the OS save support from AVX.
1378 Features["avx2"] = HasAVXSave && HasLeaf7 && ((EBX >> 5) & 1);
1380 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1);
1381 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1);
1382 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1);
1383 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1);
1384 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1);
1385 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1);
1386 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1);
1387 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1);
1388 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1);
1389 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1);
1391 // AVX512 is only supported if the OS supports the context save for it.
1392 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save;
1393 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save;
1394 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save;
1395 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save;
1396 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save;
1397 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save;
1398 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save;
1399 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save;
1401 Features["prefetchwt1"] = HasLeaf7 && (ECX & 1);
1402 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save;
1403 // Enable protection keys
1404 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1);
1406 bool HasLeafD = MaxLevel >= 0xd &&
1407 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
1409 // Only enable XSAVE if OS has enabled support for saving YMM state.
1410 Features["xsaveopt"] = HasAVXSave && HasLeafD && ((EAX >> 0) & 1);
1411 Features["xsavec"] = HasAVXSave && HasLeafD && ((EAX >> 1) & 1);
1412 Features["xsaves"] = HasAVXSave && HasLeafD && ((EAX >> 3) & 1);
1416 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1417 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
1418 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1422 SmallVector<StringRef, 32> Lines;
1423 P->getBuffer().split(Lines, "\n");
1425 SmallVector<StringRef, 32> CPUFeatures;
1427 // Look for the CPU features.
1428 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
1429 if (Lines[I].startswith("Features")) {
1430 Lines[I].split(CPUFeatures, ' ');
1434 #if defined(__aarch64__)
1435 // Keep track of which crypto features we have seen
1436 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 };
1437 uint32_t crypto = 0;
1440 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
1441 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I])
1442 #if defined(__aarch64__)
1443 .Case("asimd", "neon")
1444 .Case("fp", "fp-armv8")
1445 .Case("crc32", "crc")
1447 .Case("half", "fp16")
1448 .Case("neon", "neon")
1449 .Case("vfpv3", "vfp3")
1450 .Case("vfpv3d16", "d16")
1451 .Case("vfpv4", "vfp4")
1452 .Case("idiva", "hwdiv-arm")
1453 .Case("idivt", "hwdiv")
1457 #if defined(__aarch64__)
1458 // We need to check crypto separately since we need all of the crypto
1459 // extensions to enable the subtarget feature
1460 if (CPUFeatures[I] == "aes")
1462 else if (CPUFeatures[I] == "pmull")
1463 crypto |= CAP_PMULL;
1464 else if (CPUFeatures[I] == "sha1")
1466 else if (CPUFeatures[I] == "sha2")
1470 if (LLVMFeatureStr != "")
1471 Features[LLVMFeatureStr] = true;
1474 #if defined(__aarch64__)
1475 // If we have all crypto bits we can add the feature
1476 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2))
1477 Features["crypto"] = true;
1483 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; }
1486 std::string sys::getProcessTriple() {
1487 Triple PT(Triple::normalize(LLVM_HOST_TRIPLE));
1489 if (sizeof(void *) == 8 && PT.isArch32Bit())
1490 PT = PT.get64BitArchVariant();
1491 if (sizeof(void *) == 4 && PT.isArch64Bit())
1492 PT = PT.get32BitArchVariant();