1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the operating system Host concept.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Support/Host.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringRef.h"
17 #include "llvm/ADT/StringSwitch.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/Config/config.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/FileSystem.h"
22 #include "llvm/Support/raw_ostream.h"
25 // Include the platform-specific parts of this class.
27 #include "Unix/Host.inc"
30 #include "Windows/Host.inc"
35 #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
36 #include <mach/host_info.h>
37 #include <mach/mach.h>
38 #include <mach/mach_host.h>
39 #include <mach/machine.h>
42 #define DEBUG_TYPE "host-detection"
44 //===----------------------------------------------------------------------===//
46 // Implementations of the CPU detection routines
48 //===----------------------------------------------------------------------===//
52 #if defined(__linux__)
53 static ssize_t LLVM_ATTRIBUTE_UNUSED readCpuInfo(void *Buf, size_t Size) {
54 // Note: We cannot mmap /proc/cpuinfo here and then process the resulting
55 // memory buffer because the 'file' has 0 size (it can be read from only
59 std::error_code EC = sys::fs::openFileForRead("/proc/cpuinfo", FD);
61 DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << EC.message() << "\n");
64 int Ret = read(FD, Buf, Size);
65 int CloseStatus = close(FD);
72 #if defined(i386) || defined(__i386__) || defined(__x86__) || \
73 defined(_M_IX86) || defined(__x86_64__) || defined(_M_AMD64) || \
76 enum VendorSignatures {
77 SIG_INTEL = 0x756e6547 /* Genu */,
78 SIG_AMD = 0x68747541 /* Auth */
81 enum ProcessorVendors {
115 enum ProcessorSubtypes {
116 INTEL_COREI7_NEHALEM = 1,
117 INTEL_COREI7_WESTMERE,
118 INTEL_COREI7_SANDYBRIDGE,
127 INTEL_COREI7_IVYBRIDGE,
128 INTEL_COREI7_HASWELL,
129 INTEL_COREI7_BROADWELL,
130 INTEL_COREI7_SKYLAKE,
131 INTEL_COREI7_SKYLAKE_AVX512,
133 INTEL_ATOM_SILVERMONT,
134 INTEL_KNIGHTS_LANDING,
153 enum ProcessorFeatures {
172 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in
173 /// the specified arguments. If we can't run cpuid on the host, return true.
174 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
175 unsigned *rECX, unsigned *rEDX) {
176 #if defined(__GNUC__) || defined(__clang__)
177 #if defined(__x86_64__) || defined(_M_AMD64) || defined(_M_X64)
178 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
179 asm("movq\t%%rbx, %%rsi\n\t"
181 "xchgq\t%%rbx, %%rsi\n\t"
182 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
185 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
186 asm("movl\t%%ebx, %%esi\n\t"
188 "xchgl\t%%ebx, %%esi\n\t"
189 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
192 // pedantic #else returns to appease -Wunreachable-code (so we don't generate
193 // postprocessed code that looks like "return true; return false;")
197 #elif defined(_MSC_VER)
198 // The MSVC intrinsic is portable across x86 and x64.
200 __cpuid(registers, value);
201 *rEAX = registers[0];
202 *rEBX = registers[1];
203 *rECX = registers[2];
204 *rEDX = registers[3];
211 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return
212 /// the 4 values in the specified arguments. If we can't run cpuid on the host,
214 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf,
215 unsigned *rEAX, unsigned *rEBX, unsigned *rECX,
217 #if defined(__x86_64__) || defined(_M_AMD64) || defined(_M_X64)
218 #if defined(__GNUC__)
219 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
220 asm("movq\t%%rbx, %%rsi\n\t"
222 "xchgq\t%%rbx, %%rsi\n\t"
223 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
224 : "a"(value), "c"(subleaf));
226 #elif defined(_MSC_VER)
228 __cpuidex(registers, value, subleaf);
229 *rEAX = registers[0];
230 *rEBX = registers[1];
231 *rECX = registers[2];
232 *rEDX = registers[3];
237 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
238 #if defined(__GNUC__)
239 asm("movl\t%%ebx, %%esi\n\t"
241 "xchgl\t%%ebx, %%esi\n\t"
242 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
243 : "a"(value), "c"(subleaf));
245 #elif defined(_MSC_VER)
251 mov dword ptr [esi],eax
253 mov dword ptr [esi],ebx
255 mov dword ptr [esi],ecx
257 mov dword ptr [esi],edx
268 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) {
269 #if defined(__GNUC__)
270 // Check xgetbv; this uses a .byte sequence instead of the instruction
271 // directly because older assemblers do not include support for xgetbv and
272 // there is no easy way to conditionally compile based on the assembler used.
273 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0));
275 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
276 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
278 *rEDX = Result >> 32;
285 static void detectX86FamilyModel(unsigned EAX, unsigned *Family,
287 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11
288 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7
289 if (*Family == 6 || *Family == 0xf) {
291 // Examine extended family ID if family ID is F.
292 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27
293 // Examine extended model ID if family ID is 6 or F.
294 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
299 getIntelProcessorTypeAndSubtype(unsigned int Family, unsigned int Model,
300 unsigned int Brand_id, unsigned int Features,
301 unsigned *Type, unsigned *Subtype) {
310 case 0: // Intel486 DX processors
311 case 1: // Intel486 DX processors
312 case 2: // Intel486 SX processors
313 case 3: // Intel487 processors, IntelDX2 OverDrive processors,
314 // IntelDX2 processors
315 case 4: // Intel486 SL processor
316 case 5: // IntelSX2 processors
317 case 7: // Write-Back Enhanced IntelDX2 processors
318 case 8: // IntelDX4 OverDrive processors, IntelDX4 processors
326 case 1: // Pentium OverDrive processor for Pentium processor (60, 66),
327 // Pentium processors (60, 66)
328 case 2: // Pentium OverDrive processor for Pentium processor (75, 90,
329 // 100, 120, 133), Pentium processors (75, 90, 100, 120, 133,
331 case 3: // Pentium OverDrive processors for Intel486 processor-based
333 *Type = INTEL_PENTIUM;
335 case 4: // Pentium OverDrive processor with MMX technology for Pentium
336 // processor (75, 90, 100, 120, 133), Pentium processor with
337 // MMX technology (166, 200)
338 *Type = INTEL_PENTIUM;
339 *Subtype = INTEL_PENTIUM_MMX;
342 *Type = INTEL_PENTIUM;
348 case 0x01: // Pentium Pro processor
349 *Type = INTEL_PENTIUM_PRO;
351 case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor,
353 case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor,
354 // model 05, and Intel Celeron processor, model 05
355 case 0x06: // Celeron processor, model 06
356 *Type = INTEL_PENTIUM_II;
358 case 0x07: // Pentium III processor, model 07, and Pentium III Xeon
359 // processor, model 07
360 case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor,
361 // model 08, and Celeron processor, model 08
362 case 0x0a: // Pentium III Xeon processor, model 0Ah
363 case 0x0b: // Pentium III processor, model 0Bh
364 *Type = INTEL_PENTIUM_III;
366 case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09.
367 case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model
368 // 0Dh. All processors are manufactured using the 90 nm process.
369 case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579
370 // Integrated Processor with Intel QuickAssist Technology
371 *Type = INTEL_PENTIUM_M;
373 case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model
374 // 0Eh. All processors are manufactured using the 65 nm process.
375 *Type = INTEL_CORE_DUO;
377 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile
378 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad
379 // mobile processor, Intel Core 2 Extreme processor, Intel
380 // Pentium Dual-Core processor, Intel Xeon processor, model
381 // 0Fh. All processors are manufactured using the 65 nm process.
382 case 0x16: // Intel Celeron processor model 16h. All processors are
383 // manufactured using the 65 nm process
384 *Type = INTEL_CORE2; // "core2"
385 *Subtype = INTEL_CORE2_65;
387 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model
388 // 17h. All processors are manufactured using the 45 nm process.
390 // 45nm: Penryn , Wolfdale, Yorkfield (XE)
391 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using
392 // the 45 nm process.
393 *Type = INTEL_CORE2; // "penryn"
394 *Subtype = INTEL_CORE2_45;
396 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All
397 // processors are manufactured using the 45 nm process.
398 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz.
399 // As found in a Summer 2010 model iMac.
401 case 0x2e: // Nehalem EX
402 *Type = INTEL_COREI7; // "nehalem"
403 *Subtype = INTEL_COREI7_NEHALEM;
405 case 0x25: // Intel Core i7, laptop version.
406 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All
407 // processors are manufactured using the 32 nm process.
408 case 0x2f: // Westmere EX
409 *Type = INTEL_COREI7; // "westmere"
410 *Subtype = INTEL_COREI7_WESTMERE;
412 case 0x2a: // Intel Core i7 processor. All processors are manufactured
413 // using the 32 nm process.
415 *Type = INTEL_COREI7; //"sandybridge"
416 *Subtype = INTEL_COREI7_SANDYBRIDGE;
419 case 0x3e: // Ivy Bridge EP
420 *Type = INTEL_COREI7; // "ivybridge"
421 *Subtype = INTEL_COREI7_IVYBRIDGE;
429 *Type = INTEL_COREI7; // "haswell"
430 *Subtype = INTEL_COREI7_HASWELL;
438 *Type = INTEL_COREI7; // "broadwell"
439 *Subtype = INTEL_COREI7_BROADWELL;
444 *Type = INTEL_COREI7; // "skylake-avx512"
445 *Subtype = INTEL_COREI7_SKYLAKE_AVX512;
448 *Type = INTEL_COREI7; // "skylake"
449 *Subtype = INTEL_COREI7_SKYLAKE;
452 case 0x1c: // Most 45 nm Intel Atom processors
453 case 0x26: // 45 nm Atom Lincroft
454 case 0x27: // 32 nm Atom Medfield
455 case 0x35: // 32 nm Atom Midview
456 case 0x36: // 32 nm Atom Midview
458 *Subtype = INTEL_ATOM_BONNELL;
461 // Atom Silvermont codes from the Intel software optimization guide.
467 case 0x4c: // really airmont
469 *Subtype = INTEL_ATOM_SILVERMONT;
470 break; // "silvermont"
473 *Type = INTEL_XEONPHI; // knl
474 *Subtype = INTEL_KNIGHTS_LANDING;
477 default: // Unknown family 6 CPU, try to guess.
478 if (Features & (1 << FEATURE_AVX512)) {
479 *Type = INTEL_XEONPHI; // knl
480 *Subtype = INTEL_KNIGHTS_LANDING;
483 if (Features & (1 << FEATURE_ADX)) {
484 *Type = INTEL_COREI7;
485 *Subtype = INTEL_COREI7_BROADWELL;
488 if (Features & (1 << FEATURE_AVX2)) {
489 *Type = INTEL_COREI7;
490 *Subtype = INTEL_COREI7_HASWELL;
493 if (Features & (1 << FEATURE_AVX)) {
494 *Type = INTEL_COREI7;
495 *Subtype = INTEL_COREI7_SANDYBRIDGE;
498 if (Features & (1 << FEATURE_SSE4_2)) {
499 if (Features & (1 << FEATURE_MOVBE)) {
501 *Subtype = INTEL_ATOM_SILVERMONT;
503 *Type = INTEL_COREI7;
504 *Subtype = INTEL_COREI7_NEHALEM;
508 if (Features & (1 << FEATURE_SSE4_1)) {
509 *Type = INTEL_CORE2; // "penryn"
510 *Subtype = INTEL_CORE2_45;
513 if (Features & (1 << FEATURE_SSSE3)) {
514 if (Features & (1 << FEATURE_MOVBE)) {
516 *Subtype = INTEL_ATOM_BONNELL; // "bonnell"
518 *Type = INTEL_CORE2; // "core2"
519 *Subtype = INTEL_CORE2_65;
523 if (Features & (1 << FEATURE_EM64T)) {
524 *Type = INTEL_X86_64;
527 if (Features & (1 << FEATURE_SSE2)) {
528 *Type = INTEL_PENTIUM_M;
531 if (Features & (1 << FEATURE_SSE)) {
532 *Type = INTEL_PENTIUM_III;
535 if (Features & (1 << FEATURE_MMX)) {
536 *Type = INTEL_PENTIUM_II;
539 *Type = INTEL_PENTIUM_PRO;
545 case 0: // Pentium 4 processor, Intel Xeon processor. All processors are
546 // model 00h and manufactured using the 0.18 micron process.
547 case 1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon
548 // processor MP, and Intel Celeron processor. All processors are
549 // model 01h and manufactured using the 0.18 micron process.
550 case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M,
551 // Intel Xeon processor, Intel Xeon processor MP, Intel Celeron
552 // processor, and Mobile Intel Celeron processor. All processors
553 // are model 02h and manufactured using the 0.13 micron process.
555 ((Features & (1 << FEATURE_EM64T)) ? INTEL_X86_64 : INTEL_PENTIUM_IV);
558 case 3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D
559 // processor. All processors are model 03h and manufactured using
560 // the 90 nm process.
561 case 4: // Pentium 4 processor, Pentium 4 processor Extreme Edition,
562 // Pentium D processor, Intel Xeon processor, Intel Xeon
563 // processor MP, Intel Celeron D processor. All processors are
564 // model 04h and manufactured using the 90 nm process.
565 case 6: // Pentium 4 processor, Pentium D processor, Pentium processor
566 // Extreme Edition, Intel Xeon processor, Intel Xeon processor
567 // MP, Intel Celeron D processor. All processors are model 06h
568 // and manufactured using the 65 nm process.
570 ((Features & (1 << FEATURE_EM64T)) ? INTEL_NOCONA : INTEL_PRESCOTT);
575 ((Features & (1 << FEATURE_EM64T)) ? INTEL_X86_64 : INTEL_PENTIUM_IV);
585 static void getAMDProcessorTypeAndSubtype(unsigned int Family,
587 unsigned int Features,
590 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There
591 // appears to be no way to generate the wide variety of AMD-specific targets
592 // from the information returned from CPUID.
602 *Subtype = AMDPENTIUM_K6;
605 *Subtype = AMDPENTIUM_K62;
609 *Subtype = AMDPENTIUM_K63;
612 *Subtype = AMDPENTIUM_GEODE;
620 *Subtype = AMDATHLON_TBIRD;
621 break; // "athlon-tbird"
625 *Subtype = AMDATHLON_MP;
626 break; // "athlon-mp"
628 *Subtype = AMDATHLON_XP;
629 break; // "athlon-xp"
634 if (Features & (1 << FEATURE_SSE3)) {
635 *Subtype = AMDATHLON_K8SSE3;
640 *Subtype = AMDATHLON_OPTERON;
643 *Subtype = AMDATHLON_FX;
644 break; // "athlon-fx"; also opteron
646 *Subtype = AMDATHLON_64;
651 *Type = AMDFAM10H; // "amdfam10"
654 *Subtype = AMDFAM10H_BARCELONA;
657 *Subtype = AMDFAM10H_SHANGHAI;
660 *Subtype = AMDFAM10H_ISTANBUL;
666 *Subtype = AMD_BTVER1;
671 (1 << FEATURE_AVX))) { // If no AVX support, provide a sane fallback.
672 *Subtype = AMD_BTVER1;
675 if (Model >= 0x50 && Model <= 0x6f) {
676 *Subtype = AMDFAM15H_BDVER4;
677 break; // "bdver4"; 50h-6Fh: Excavator
679 if (Model >= 0x30 && Model <= 0x3f) {
680 *Subtype = AMDFAM15H_BDVER3;
681 break; // "bdver3"; 30h-3Fh: Steamroller
683 if (Model >= 0x10 && Model <= 0x1f) {
684 *Subtype = AMDFAM15H_BDVER2;
685 break; // "bdver2"; 10h-1Fh: Piledriver
688 *Subtype = AMDFAM15H_BDVER1;
689 break; // "bdver1"; 00h-0Fh: Bulldozer
695 (1 << FEATURE_AVX))) { // If no AVX support provide a sane fallback.
696 *Subtype = AMD_BTVER1;
699 *Subtype = AMD_BTVER2;
706 static unsigned getAvailableFeatures(unsigned int ECX, unsigned int EDX,
708 unsigned Features = 0;
709 unsigned int EAX, EBX;
710 Features |= (((EDX >> 23) & 1) << FEATURE_MMX);
711 Features |= (((EDX >> 25) & 1) << FEATURE_SSE);
712 Features |= (((EDX >> 26) & 1) << FEATURE_SSE2);
713 Features |= (((ECX >> 0) & 1) << FEATURE_SSE3);
714 Features |= (((ECX >> 9) & 1) << FEATURE_SSSE3);
715 Features |= (((ECX >> 19) & 1) << FEATURE_SSE4_1);
716 Features |= (((ECX >> 20) & 1) << FEATURE_SSE4_2);
717 Features |= (((ECX >> 22) & 1) << FEATURE_MOVBE);
719 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
720 // indicates that the AVX registers will be saved and restored on context
721 // switch, then we have full AVX support.
722 const unsigned AVXBits = (1 << 27) | (1 << 28);
723 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) &&
724 ((EAX & 0x6) == 0x6);
725 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0);
727 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
728 bool HasADX = HasLeaf7 && ((EBX >> 19) & 1);
729 bool HasAVX2 = HasAVX && HasLeaf7 && (EBX & 0x20);
730 bool HasAVX512 = HasLeaf7 && HasAVX512Save && ((EBX >> 16) & 1);
731 Features |= (HasAVX << FEATURE_AVX);
732 Features |= (HasAVX2 << FEATURE_AVX2);
733 Features |= (HasAVX512 << FEATURE_AVX512);
734 Features |= (HasAVX512Save << FEATURE_AVX512SAVE);
735 Features |= (HasADX << FEATURE_ADX);
737 getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
738 Features |= (((EDX >> 29) & 0x1) << FEATURE_EM64T);
742 StringRef sys::getHostCPUName() {
743 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
744 unsigned MaxLeaf, Vendor;
746 if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX))
748 if (getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
751 unsigned Brand_id = EBX & 0xff;
752 unsigned Family = 0, Model = 0;
753 unsigned Features = 0;
754 detectX86FamilyModel(EAX, &Family, &Model);
755 Features = getAvailableFeatures(ECX, EDX, MaxLeaf);
760 if (Vendor == SIG_INTEL) {
761 getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features, &Type,
769 if (Subtype == INTEL_PENTIUM_MMX)
770 return "pentium-mmx";
772 case INTEL_PENTIUM_PRO:
774 case INTEL_PENTIUM_II:
776 case INTEL_PENTIUM_III:
778 case INTEL_PENTIUM_IV:
780 case INTEL_PENTIUM_M:
795 case INTEL_COREI7_NEHALEM:
797 case INTEL_COREI7_WESTMERE:
799 case INTEL_COREI7_SANDYBRIDGE:
800 return "sandybridge";
801 case INTEL_COREI7_IVYBRIDGE:
803 case INTEL_COREI7_HASWELL:
805 case INTEL_COREI7_BROADWELL:
807 case INTEL_COREI7_SKYLAKE:
809 case INTEL_COREI7_SKYLAKE_AVX512:
810 return "skylake-avx512";
816 case INTEL_ATOM_BONNELL:
818 case INTEL_ATOM_SILVERMONT:
824 return "knl"; /*update for more variants added*/
834 } else if (Vendor == SIG_AMD) {
835 getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype);
847 case AMDPENTIUM_GEODE:
854 case AMDATHLON_TBIRD:
855 return "athlon-tbird";
860 case AMDATHLON_K8SSE3:
862 case AMDATHLON_OPTERON:
872 if(Subtype == AMDFAM10H_BARCELONA)
879 case AMDFAM15H_BDVER1:
881 case AMDFAM15H_BDVER2:
883 case AMDFAM15H_BDVER3:
885 case AMDFAM15H_BDVER4:
908 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
909 StringRef sys::getHostCPUName() {
910 host_basic_info_data_t hostInfo;
911 mach_msg_type_number_t infoCount;
913 infoCount = HOST_BASIC_INFO_COUNT;
914 host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo,
917 if (hostInfo.cpu_type != CPU_TYPE_POWERPC)
920 switch (hostInfo.cpu_subtype) {
921 case CPU_SUBTYPE_POWERPC_601:
923 case CPU_SUBTYPE_POWERPC_602:
925 case CPU_SUBTYPE_POWERPC_603:
927 case CPU_SUBTYPE_POWERPC_603e:
929 case CPU_SUBTYPE_POWERPC_603ev:
931 case CPU_SUBTYPE_POWERPC_604:
933 case CPU_SUBTYPE_POWERPC_604e:
935 case CPU_SUBTYPE_POWERPC_620:
937 case CPU_SUBTYPE_POWERPC_750:
939 case CPU_SUBTYPE_POWERPC_7400:
941 case CPU_SUBTYPE_POWERPC_7450:
943 case CPU_SUBTYPE_POWERPC_970:
950 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__))
951 StringRef sys::getHostCPUName() {
952 // Access to the Processor Version Register (PVR) on PowerPC is privileged,
953 // and so we must use an operating-system interface to determine the current
954 // processor type. On Linux, this is exposed through the /proc/cpuinfo file.
955 const char *generic = "generic";
957 // The cpu line is second (after the 'processor: 0' line), so if this
958 // buffer is too small then something has changed (or is wrong).
960 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer));
961 if (CPUInfoSize == -1)
964 const char *CPUInfoStart = buffer;
965 const char *CPUInfoEnd = buffer + CPUInfoSize;
967 const char *CIP = CPUInfoStart;
969 const char *CPUStart = 0;
972 // We need to find the first line which starts with cpu, spaces, and a colon.
973 // After the colon, there may be some additional spaces and then the cpu type.
974 while (CIP < CPUInfoEnd && CPUStart == 0) {
975 if (CIP < CPUInfoEnd && *CIP == '\n')
978 if (CIP < CPUInfoEnd && *CIP == 'c') {
980 if (CIP < CPUInfoEnd && *CIP == 'p') {
982 if (CIP < CPUInfoEnd && *CIP == 'u') {
984 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
987 if (CIP < CPUInfoEnd && *CIP == ':') {
989 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
992 if (CIP < CPUInfoEnd) {
994 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' &&
995 *CIP != ',' && *CIP != '\n'))
997 CPULen = CIP - CPUStart;
1005 while (CIP < CPUInfoEnd && *CIP != '\n')
1012 return StringSwitch<const char *>(StringRef(CPUStart, CPULen))
1013 .Case("604e", "604e")
1015 .Case("7400", "7400")
1016 .Case("7410", "7400")
1017 .Case("7447", "7400")
1018 .Case("7455", "7450")
1020 .Case("POWER4", "970")
1021 .Case("PPC970FX", "970")
1022 .Case("PPC970MP", "970")
1024 .Case("POWER5", "g5")
1026 .Case("POWER6", "pwr6")
1027 .Case("POWER7", "pwr7")
1028 .Case("POWER8", "pwr8")
1029 .Case("POWER8E", "pwr8")
1030 .Case("POWER9", "pwr9")
1033 #elif defined(__linux__) && defined(__arm__)
1034 StringRef sys::getHostCPUName() {
1035 // The cpuid register on arm is not accessible from user space. On Linux,
1036 // it is exposed through the /proc/cpuinfo file.
1038 // Read 1024 bytes from /proc/cpuinfo, which should contain the CPU part line
1041 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer));
1042 if (CPUInfoSize == -1)
1045 StringRef Str(buffer, CPUInfoSize);
1047 SmallVector<StringRef, 32> Lines;
1048 Str.split(Lines, "\n");
1050 // Look for the CPU implementer line.
1051 StringRef Implementer;
1052 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
1053 if (Lines[I].startswith("CPU implementer"))
1054 Implementer = Lines[I].substr(15).ltrim("\t :");
1056 if (Implementer == "0x41") // ARM Ltd.
1057 // Look for the CPU part line.
1058 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
1059 if (Lines[I].startswith("CPU part"))
1060 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
1061 // values correspond to the "Part number" in the CP15/c0 register. The
1062 // contents are specified in the various processor manuals.
1063 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
1064 .Case("0x926", "arm926ej-s")
1065 .Case("0xb02", "mpcore")
1066 .Case("0xb36", "arm1136j-s")
1067 .Case("0xb56", "arm1156t2-s")
1068 .Case("0xb76", "arm1176jz-s")
1069 .Case("0xc08", "cortex-a8")
1070 .Case("0xc09", "cortex-a9")
1071 .Case("0xc0f", "cortex-a15")
1072 .Case("0xc20", "cortex-m0")
1073 .Case("0xc23", "cortex-m3")
1074 .Case("0xc24", "cortex-m4")
1075 .Default("generic");
1077 if (Implementer == "0x51") // Qualcomm Technologies, Inc.
1078 // Look for the CPU part line.
1079 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
1080 if (Lines[I].startswith("CPU part"))
1081 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
1082 // values correspond to the "Part number" in the CP15/c0 register. The
1083 // contents are specified in the various processor manuals.
1084 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
1085 .Case("0x06f", "krait") // APQ8064
1086 .Default("generic");
1090 #elif defined(__linux__) && defined(__s390x__)
1091 StringRef sys::getHostCPUName() {
1092 // STIDP is a privileged operation, so use /proc/cpuinfo instead.
1094 // The "processor 0:" line comes after a fair amount of other information,
1095 // including a cache breakdown, but this should be plenty.
1097 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer));
1098 if (CPUInfoSize == -1)
1101 StringRef Str(buffer, CPUInfoSize);
1102 SmallVector<StringRef, 32> Lines;
1103 Str.split(Lines, "\n");
1105 // Look for the CPU features.
1106 SmallVector<StringRef, 32> CPUFeatures;
1107 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
1108 if (Lines[I].startswith("features")) {
1109 size_t Pos = Lines[I].find(":");
1110 if (Pos != StringRef::npos) {
1111 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' ');
1116 // We need to check for the presence of vector support independently of
1117 // the machine type, since we may only use the vector register set when
1118 // supported by the kernel (and hypervisor).
1119 bool HaveVectorSupport = false;
1120 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
1121 if (CPUFeatures[I] == "vx")
1122 HaveVectorSupport = true;
1125 // Now check the processor machine type.
1126 for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
1127 if (Lines[I].startswith("processor ")) {
1128 size_t Pos = Lines[I].find("machine = ");
1129 if (Pos != StringRef::npos) {
1130 Pos += sizeof("machine = ") - 1;
1132 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) {
1133 if (Id >= 2964 && HaveVectorSupport)
1148 StringRef sys::getHostCPUName() { return "generic"; }
1151 #if defined(i386) || defined(__i386__) || defined(__x86__) || \
1152 defined(_M_IX86) || defined(__x86_64__) || defined(_M_AMD64) || \
1154 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
1155 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
1162 if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) ||
1166 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX);
1168 Features["cmov"] = (EDX >> 15) & 1;
1169 Features["mmx"] = (EDX >> 23) & 1;
1170 Features["sse"] = (EDX >> 25) & 1;
1171 Features["sse2"] = (EDX >> 26) & 1;
1172 Features["sse3"] = (ECX >> 0) & 1;
1173 Features["ssse3"] = (ECX >> 9) & 1;
1174 Features["sse4.1"] = (ECX >> 19) & 1;
1175 Features["sse4.2"] = (ECX >> 20) & 1;
1177 Features["pclmul"] = (ECX >> 1) & 1;
1178 Features["cx16"] = (ECX >> 13) & 1;
1179 Features["movbe"] = (ECX >> 22) & 1;
1180 Features["popcnt"] = (ECX >> 23) & 1;
1181 Features["aes"] = (ECX >> 25) & 1;
1182 Features["rdrnd"] = (ECX >> 30) & 1;
1184 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
1185 // indicates that the AVX registers will be saved and restored on context
1186 // switch, then we have full AVX support.
1187 bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) &&
1188 !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6);
1189 Features["avx"] = HasAVXSave;
1190 Features["fma"] = HasAVXSave && (ECX >> 12) & 1;
1191 Features["f16c"] = HasAVXSave && (ECX >> 29) & 1;
1193 // Only enable XSAVE if OS has enabled support for saving YMM state.
1194 Features["xsave"] = HasAVXSave && (ECX >> 26) & 1;
1196 // AVX512 requires additional context to be saved by the OS.
1197 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0);
1199 unsigned MaxExtLevel;
1200 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1202 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1203 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1204 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1);
1205 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1);
1206 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1);
1207 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave;
1208 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave;
1209 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1);
1210 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1);
1213 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1215 // AVX2 is only supported if we have the OS save support from AVX.
1216 Features["avx2"] = HasAVXSave && HasLeaf7 && ((EBX >> 5) & 1);
1218 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1);
1219 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1);
1220 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1);
1221 Features["hle"] = HasLeaf7 && ((EBX >> 4) & 1);
1222 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1);
1223 Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1);
1224 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1);
1225 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1);
1226 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1);
1227 Features["smap"] = HasLeaf7 && ((EBX >> 20) & 1);
1228 Features["pcommit"] = HasLeaf7 && ((EBX >> 22) & 1);
1229 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1);
1230 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1);
1231 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1);
1233 // AVX512 is only supported if the OS supports the context save for it.
1234 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save;
1235 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save;
1236 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save;
1237 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save;
1238 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save;
1239 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save;
1240 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save;
1241 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save;
1243 Features["prefetchwt1"] = HasLeaf7 && (ECX & 1);
1244 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save;
1245 // Enable protection keys
1246 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1);
1248 bool HasLeafD = MaxLevel >= 0xd &&
1249 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
1251 // Only enable XSAVE if OS has enabled support for saving YMM state.
1252 Features["xsaveopt"] = HasAVXSave && HasLeafD && ((EAX >> 0) & 1);
1253 Features["xsavec"] = HasAVXSave && HasLeafD && ((EAX >> 1) & 1);
1254 Features["xsaves"] = HasAVXSave && HasLeafD && ((EAX >> 3) & 1);
1258 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1259 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
1260 // Read 1024 bytes from /proc/cpuinfo, which should contain the Features line
1263 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer));
1264 if (CPUInfoSize == -1)
1267 StringRef Str(buffer, CPUInfoSize);
1269 SmallVector<StringRef, 32> Lines;
1270 Str.split(Lines, "\n");
1272 SmallVector<StringRef, 32> CPUFeatures;
1274 // Look for the CPU features.
1275 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
1276 if (Lines[I].startswith("Features")) {
1277 Lines[I].split(CPUFeatures, ' ');
1281 #if defined(__aarch64__)
1282 // Keep track of which crypto features we have seen
1283 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 };
1284 uint32_t crypto = 0;
1287 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
1288 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I])
1289 #if defined(__aarch64__)
1290 .Case("asimd", "neon")
1291 .Case("fp", "fp-armv8")
1292 .Case("crc32", "crc")
1294 .Case("half", "fp16")
1295 .Case("neon", "neon")
1296 .Case("vfpv3", "vfp3")
1297 .Case("vfpv3d16", "d16")
1298 .Case("vfpv4", "vfp4")
1299 .Case("idiva", "hwdiv-arm")
1300 .Case("idivt", "hwdiv")
1304 #if defined(__aarch64__)
1305 // We need to check crypto separately since we need all of the crypto
1306 // extensions to enable the subtarget feature
1307 if (CPUFeatures[I] == "aes")
1309 else if (CPUFeatures[I] == "pmull")
1310 crypto |= CAP_PMULL;
1311 else if (CPUFeatures[I] == "sha1")
1313 else if (CPUFeatures[I] == "sha2")
1317 if (LLVMFeatureStr != "")
1318 Features[LLVMFeatureStr] = true;
1321 #if defined(__aarch64__)
1322 // If we have all crypto bits we can add the feature
1323 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2))
1324 Features["crypto"] = true;
1330 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; }
1333 std::string sys::getProcessTriple() {
1334 Triple PT(Triple::normalize(LLVM_HOST_TRIPLE));
1336 if (sizeof(void *) == 8 && PT.isArch32Bit())
1337 PT = PT.get64BitArchVariant();
1338 if (sizeof(void *) == 4 && PT.isArch64Bit())
1339 PT = PT.get32BitArchVariant();