contrib/llvm/lib/Target/AArch64/AArch64.td

   1 //=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 //===----------------------------------------------------------------------===//
  14 // Target-independent interfaces which we are implementing.
  15 //===----------------------------------------------------------------------===//
  16
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // AArch64 Subtarget features.
  21 //
  22
  23 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
  24                                        "Enable ARMv8 FP">;
  25
  26 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
  27   "Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
  28
  29 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
  30   "Enable cryptographic instructions">;
  31
  32 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
  33   "Enable ARMv8 CRC-32 checksum instructions">;
  34
  35 def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
  36   "Enable ARMv8 Reliability, Availability and Serviceability Extensions">;
  37
  38 def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true",
  39   "Enable ARMv8.1 Large System Extension (LSE) atomic instructions">;
  40
  41 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
  42   "Enable ARMv8 PMUv3 Performance Monitors extension">;
  43
  44 def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
  45   "Full FP16", [FeatureFPARMv8]>;
  46
  47 def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true",
  48   "Enable Statistical Profiling extension">;
  49
  50 /// Cyclone has register move instructions which are "free".
  51 def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
  52                                         "Has zero-cycle register moves">;
  53
  54 /// Cyclone has instructions which zero registers for "free".
  55 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
  56                                         "Has zero-cycle zeroing instructions">;
  57
  58 def FeatureStrictAlign : SubtargetFeature<"strict-align",
  59                                           "StrictAlign", "true",
  60                                           "Disallow all unaligned memory "
  61                                           "access">;
  62
  63 def FeatureReserveX18 : SubtargetFeature<"reserve-x18", "ReserveX18", "true",
  64                                          "Reserve X18, making it unavailable "
  65                                          "as a GPR">;
  66
  67 def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",
  68                                     "Use alias analysis during codegen">;
  69
  70 def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps",
  71     "true",
  72     "balance mix of odd and even D-registers for fp multiply(-accumulate) ops">;
  73
  74 def FeaturePredictableSelectIsExpensive : SubtargetFeature<
  75     "predictable-select-expensive", "PredictableSelectIsExpensive", "true",
  76     "Prefer likely predicted branches over selects">;
  77
  78 def FeatureCustomCheapAsMoveHandling : SubtargetFeature<"custom-cheap-as-move",
  79     "CustomAsCheapAsMove", "true",
  80     "Use custom code for TargetInstrInfo::isAsCheapAsAMove()">;
  81
  82 def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
  83     "UsePostRAScheduler", "true", "Schedule again after register allocation">;
  84
  85 def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store",
  86     "Misaligned128StoreIsSlow", "true", "Misaligned 128 bit stores are slow">;
  87
  88 def FeatureAvoidQuadLdStPairs : SubtargetFeature<"no-quad-ldst-pairs",
  89     "AvoidQuadLdStPairs", "true",
  90     "Do not form quad load/store pair operations">;
  91
  92 def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature<
  93     "alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern",
  94     "true", "Use alternative pattern for sextload convert to f32">;
  95
  96 def FeatureArithmeticBccFusion : SubtargetFeature<
  97     "arith-bcc-fusion", "HasArithmeticBccFusion", "true",
  98     "CPU fuses arithmetic+bcc operations">;
  99
 100 def FeatureArithmeticCbzFusion : SubtargetFeature<
 101     "arith-cbz-fusion", "HasArithmeticCbzFusion", "true",
 102     "CPU fuses arithmetic + cbz/cbnz operations">;
 103
 104 def FeatureDisableLatencySchedHeuristic : SubtargetFeature<
 105     "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",
 106     "Disable latency scheduling heuristic">;
 107
 108 def FeatureUseRSqrt : SubtargetFeature<
 109     "use-reciprocal-square-root", "UseRSqrt", "true",
 110     "Use the reciprocal square root approximation">;
 111
 112 //===----------------------------------------------------------------------===//
 113 // Architectures.
 114 //
 115
 116 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
 117   "Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE]>;
 118
 119 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
 120   "Support ARM v8.2a instructions", [HasV8_1aOps, FeatureRAS]>;
 121
 122 //===----------------------------------------------------------------------===//
 123 // Register File Description
 124 //===----------------------------------------------------------------------===//
 125
 126 include "AArch64RegisterInfo.td"
 127 include "AArch64CallingConvention.td"
 128
 129 //===----------------------------------------------------------------------===//
 130 // Instruction Descriptions
 131 //===----------------------------------------------------------------------===//
 132
 133 include "AArch64Schedule.td"
 134 include "AArch64InstrInfo.td"
 135
 136 def AArch64InstrInfo : InstrInfo;
 137
 138 //===----------------------------------------------------------------------===//
 139 // Named operands for MRS/MSR/TLBI/...
 140 //===----------------------------------------------------------------------===//
 141
 142 include "AArch64SystemOperands.td"
 143
 144 //===----------------------------------------------------------------------===//
 145 // AArch64 Processors supported.
 146 //
 147 include "AArch64SchedA53.td"
 148 include "AArch64SchedA57.td"
 149 include "AArch64SchedCyclone.td"
 150 include "AArch64SchedFalkor.td"
 151 include "AArch64SchedKryo.td"
 152 include "AArch64SchedM1.td"
 153 include "AArch64SchedVulcan.td"
 154
 155 def ProcA35     : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
 156                                    "Cortex-A35 ARM processors", [
 157                                    FeatureCRC,
 158                                    FeatureCrypto,
 159                                    FeatureFPARMv8,
 160                                    FeatureNEON,
 161                                    FeaturePerfMon
 162                                    ]>;
 163
 164 def ProcA53     : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
 165                                    "Cortex-A53 ARM processors", [
 166                                    FeatureBalanceFPOps,
 167                                    FeatureCRC,
 168                                    FeatureCrypto,
 169                                    FeatureCustomCheapAsMoveHandling,
 170                                    FeatureFPARMv8,
 171                                    FeatureNEON,
 172                                    FeaturePerfMon,
 173                                    FeaturePostRAScheduler,
 174                                    FeatureUseAA
 175                                    ]>;
 176
 177 def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
 178                                    "Cortex-A57 ARM processors", [
 179                                    FeatureBalanceFPOps,
 180                                    FeatureCRC,
 181                                    FeatureCrypto,
 182                                    FeatureCustomCheapAsMoveHandling,
 183                                    FeatureFPARMv8,
 184                                    FeatureNEON,
 185                                    FeaturePerfMon,
 186                                    FeaturePostRAScheduler,
 187                                    FeaturePredictableSelectIsExpensive
 188                                    ]>;
 189
 190 def ProcA72     : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
 191                                    "Cortex-A72 ARM processors", [
 192                                    FeatureCRC,
 193                                    FeatureCrypto,
 194                                    FeatureFPARMv8,
 195                                    FeatureNEON,
 196                                    FeaturePerfMon
 197                                    ]>;
 198
 199 def ProcA73     : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
 200                                    "Cortex-A73 ARM processors", [
 201                                    FeatureCRC,
 202                                    FeatureCrypto,
 203                                    FeatureFPARMv8,
 204                                    FeatureNEON,
 205                                    FeaturePerfMon
 206                                    ]>;
 207
 208 def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
 209                                    "Cyclone", [
 210                                    FeatureAlternateSExtLoadCVTF32Pattern,
 211                                    FeatureCrypto,
 212                                    FeatureDisableLatencySchedHeuristic,
 213                                    FeatureFPARMv8,
 214                                    FeatureArithmeticBccFusion,
 215                                    FeatureArithmeticCbzFusion,
 216                                    FeatureNEON,
 217                                    FeaturePerfMon,
 218                                    FeatureSlowMisaligned128Store,
 219                                    FeatureZCRegMove,
 220                                    FeatureZCZeroing
 221                                    ]>;
 222
 223 def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1",
 224                                     "Samsung Exynos-M1 processors",
 225                                     [FeatureAvoidQuadLdStPairs,
 226                                      FeatureCRC,
 227                                      FeatureCrypto,
 228                                      FeatureCustomCheapAsMoveHandling,
 229                                      FeatureFPARMv8,
 230                                      FeatureNEON,
 231                                      FeaturePerfMon,
 232                                      FeaturePostRAScheduler,
 233                                      FeatureSlowMisaligned128Store,
 234                                      FeatureUseRSqrt,
 235                                      FeatureZCZeroing]>;
 236
 237 def ProcExynosM2 : SubtargetFeature<"exynosm2", "ARMProcFamily", "ExynosM1",
 238                                     "Samsung Exynos-M2/M3 processors",
 239                                     [FeatureAvoidQuadLdStPairs,
 240                                      FeatureCRC,
 241                                      FeatureCrypto,
 242                                      FeatureCustomCheapAsMoveHandling,
 243                                      FeatureFPARMv8,
 244                                      FeatureNEON,
 245                                      FeaturePerfMon,
 246                                      FeaturePostRAScheduler,
 247                                      FeatureSlowMisaligned128Store,
 248                                      FeatureZCZeroing]>;
 249
 250 def ProcKryo    : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",
 251                                    "Qualcomm Kryo processors", [
 252                                    FeatureCRC,
 253                                    FeatureCrypto,
 254                                    FeatureCustomCheapAsMoveHandling,
 255                                    FeatureFPARMv8,
 256                                    FeatureNEON,
 257                                    FeaturePerfMon,
 258                                    FeaturePostRAScheduler,
 259                                    FeaturePredictableSelectIsExpensive,
 260                                    FeatureZCZeroing
 261                                    ]>;
 262
 263 def ProcFalkor  : SubtargetFeature<"falkor", "ARMProcFamily", "Falkor",
 264                                    "Qualcomm Falkor processors", [
 265                                    FeatureCRC,
 266                                    FeatureCrypto,
 267                                    FeatureCustomCheapAsMoveHandling,
 268                                    FeatureFPARMv8,
 269                                    FeatureNEON,
 270                                    FeaturePerfMon,
 271                                    FeaturePostRAScheduler,
 272                                    FeaturePredictableSelectIsExpensive,
 273                                    FeatureZCZeroing
 274                                    ]>;
 275
 276 def ProcVulcan  : SubtargetFeature<"vulcan", "ARMProcFamily", "Vulcan",
 277                                    "Broadcom Vulcan processors", [
 278                                    FeatureCRC,
 279                                    FeatureCrypto,
 280                                    FeatureFPARMv8,
 281                                    FeatureArithmeticBccFusion,
 282                                    FeatureNEON,
 283                                    FeaturePostRAScheduler,
 284                                    FeaturePredictableSelectIsExpensive,
 285                                    HasV8_1aOps]>;
 286
 287 def : ProcessorModel<"generic", NoSchedModel, [
 288                      FeatureCRC,
 289                      FeatureFPARMv8,
 290                      FeatureNEON,
 291                      FeaturePerfMon,
 292                      FeaturePostRAScheduler
 293                      ]>;
 294
 295 // FIXME: Cortex-A35 is currently modelled as a Cortex-A53
 296 def : ProcessorModel<"cortex-a35", CortexA53Model, [ProcA35]>;
 297 def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
 298 def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
 299 // FIXME: Cortex-A72 and Cortex-A73 are currently modelled as an Cortex-A57.
 300 def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA72]>;
 301 def : ProcessorModel<"cortex-a73", CortexA57Model, [ProcA73]>;
 302 def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
 303 def : ProcessorModel<"exynos-m1", ExynosM1Model, [ProcExynosM1]>;
 304 def : ProcessorModel<"exynos-m2", ExynosM1Model, [ProcExynosM2]>;
 305 def : ProcessorModel<"exynos-m3", ExynosM1Model, [ProcExynosM2]>;
 306 def : ProcessorModel<"falkor", FalkorModel, [ProcFalkor]>;
 307 def : ProcessorModel<"kryo", KryoModel, [ProcKryo]>;
 308 def : ProcessorModel<"vulcan", VulcanModel, [ProcVulcan]>;
 309
 310 //===----------------------------------------------------------------------===//
 311 // Assembly parser
 312 //===----------------------------------------------------------------------===//
 313
 314 def GenericAsmParserVariant : AsmParserVariant {
 315   int Variant = 0;
 316   string Name = "generic";
 317   string BreakCharacters = ".";
 318 }
 319
 320 def AppleAsmParserVariant : AsmParserVariant {
 321   int Variant = 1;
 322   string Name = "apple-neon";
 323   string BreakCharacters = ".";
 324 }
 325
 326 //===----------------------------------------------------------------------===//
 327 // Assembly printer
 328 //===----------------------------------------------------------------------===//
 329 // AArch64 Uses the MC printer for asm output, so make sure the TableGen
 330 // AsmWriter bits get associated with the correct class.
 331 def GenericAsmWriter : AsmWriter {
 332   string AsmWriterClassName  = "InstPrinter";
 333   int PassSubtarget = 1;
 334   int Variant = 0;
 335   bit isMCAsmWriter = 1;
 336 }
 337
 338 def AppleAsmWriter : AsmWriter {
 339   let AsmWriterClassName = "AppleInstPrinter";
 340   int PassSubtarget = 1;
 341   int Variant = 1;
 342   int isMCAsmWriter = 1;
 343 }
 344
 345 //===----------------------------------------------------------------------===//
 346 // Target Declaration
 347 //===----------------------------------------------------------------------===//
 348
 349 def AArch64 : Target {
 350   let InstructionSet = AArch64InstrInfo;
 351   let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
 352   let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];
 353 }