contrib/llvm/lib/Target/AArch64/AArch64.td

   1 //=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 //===----------------------------------------------------------------------===//
  14 // Target-independent interfaces which we are implementing.
  15 //===----------------------------------------------------------------------===//
  16
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // AArch64 Subtarget features.
  21 //
  22
  23 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
  24                                        "Enable ARMv8 FP">;
  25
  26 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
  27   "Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
  28
  29 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
  30   "Enable cryptographic instructions", [FeatureNEON]>;
  31
  32 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
  33   "Enable ARMv8 CRC-32 checksum instructions">;
  34
  35 def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
  36   "Enable ARMv8 Reliability, Availability and Serviceability Extensions">;
  37
  38 def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true",
  39   "Enable ARMv8.1 Large System Extension (LSE) atomic instructions">;
  40
  41 def FeatureRDM : SubtargetFeature<"rdm", "HasRDM", "true",
  42   "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions">;
  43
  44 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
  45   "Enable ARMv8 PMUv3 Performance Monitors extension">;
  46
  47 def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
  48   "Full FP16", [FeatureFPARMv8]>;
  49
  50 def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true",
  51   "Enable Statistical Profiling extension">;
  52
  53 def FeatureSVE : SubtargetFeature<"sve", "HasSVE", "true",
  54   "Enable Scalable Vector Extension (SVE) instructions">;
  55
  56 /// Cyclone has register move instructions which are "free".
  57 def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
  58                                         "Has zero-cycle register moves">;
  59
  60 /// Cyclone has instructions which zero registers for "free".
  61 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
  62                                         "Has zero-cycle zeroing instructions">;
  63
  64 /// ... but the floating-point version doesn't quite work in rare cases on older
  65 /// CPUs.
  66 def FeatureZCZeroingFPWorkaround : SubtargetFeature<"zcz-fp-workaround",
  67     "HasZeroCycleZeroingFPWorkaround", "true",
  68     "The zero-cycle floating-point zeroing instruction has a bug">;
  69
  70 def FeatureStrictAlign : SubtargetFeature<"strict-align",
  71                                           "StrictAlign", "true",
  72                                           "Disallow all unaligned memory "
  73                                           "access">;
  74
  75 def FeatureReserveX18 : SubtargetFeature<"reserve-x18", "ReserveX18", "true",
  76                                          "Reserve X18, making it unavailable "
  77                                          "as a GPR">;
  78
  79 def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",
  80                                     "Use alias analysis during codegen">;
  81
  82 def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps",
  83     "true",
  84     "balance mix of odd and even D-registers for fp multiply(-accumulate) ops">;
  85
  86 def FeaturePredictableSelectIsExpensive : SubtargetFeature<
  87     "predictable-select-expensive", "PredictableSelectIsExpensive", "true",
  88     "Prefer likely predicted branches over selects">;
  89
  90 def FeatureCustomCheapAsMoveHandling : SubtargetFeature<"custom-cheap-as-move",
  91     "CustomAsCheapAsMove", "true",
  92     "Use custom code for TargetInstrInfo::isAsCheapAsAMove()">;
  93
  94 def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
  95     "UsePostRAScheduler", "true", "Schedule again after register allocation">;
  96
  97 def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store",
  98     "Misaligned128StoreIsSlow", "true", "Misaligned 128 bit stores are slow">;
  99
 100 def FeatureSlowPaired128 : SubtargetFeature<"slow-paired-128",
 101     "Paired128IsSlow", "true", "Paired 128 bit loads and stores are slow">;
 102
 103 def FeatureSlowSTRQro : SubtargetFeature<"slow-strqro-store", "STRQroIsSlow",
 104     "true", "STR of Q register with register offset is slow">;
 105
 106 def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature<
 107     "alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern",
 108     "true", "Use alternative pattern for sextload convert to f32">;
 109
 110 def FeatureArithmeticBccFusion : SubtargetFeature<
 111     "arith-bcc-fusion", "HasArithmeticBccFusion", "true",
 112     "CPU fuses arithmetic+bcc operations">;
 113
 114 def FeatureArithmeticCbzFusion : SubtargetFeature<
 115     "arith-cbz-fusion", "HasArithmeticCbzFusion", "true",
 116     "CPU fuses arithmetic + cbz/cbnz operations">;
 117
 118 def FeatureFuseAES : SubtargetFeature<
 119     "fuse-aes", "HasFuseAES", "true",
 120     "CPU fuses AES crypto operations">;
 121
 122 def FeatureFuseLiterals : SubtargetFeature<
 123     "fuse-literals", "HasFuseLiterals", "true",
 124     "CPU fuses literal generation operations">;
 125
 126 def FeatureDisableLatencySchedHeuristic : SubtargetFeature<
 127     "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",
 128     "Disable latency scheduling heuristic">;
 129
 130 def FeatureRCPC : SubtargetFeature<"rcpc", "HasRCPC", "true",
 131                                    "Enable support for RCPC extension">;
 132
 133 def FeatureUseRSqrt : SubtargetFeature<
 134     "use-reciprocal-square-root", "UseRSqrt", "true",
 135     "Use the reciprocal square root approximation">;
 136
 137 def FeatureDotProd : SubtargetFeature<
 138     "dotprod", "HasDotProd", "true",
 139     "Enable dot product support">;
 140
 141 def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates",
 142                                         "NegativeImmediates", "false",
 143                                         "Convert immediates and instructions "
 144                                         "to their negated or complemented "
 145                                         "equivalent when the immediate does "
 146                                         "not fit in the encoding.">;
 147
 148 def FeatureLSLFast : SubtargetFeature<
 149     "lsl-fast", "HasLSLFast", "true",
 150     "CPU has a fastpath logical shift of up to 3 places">;
 151
 152 //===----------------------------------------------------------------------===//
 153 // Architectures.
 154 //
 155
 156 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
 157   "Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE, FeatureRDM]>;
 158
 159 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
 160   "Support ARM v8.2a instructions", [HasV8_1aOps, FeatureRAS]>;
 161
 162 def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",
 163   "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC]>;
 164
 165 //===----------------------------------------------------------------------===//
 166 // Register File Description
 167 //===----------------------------------------------------------------------===//
 168
 169 include "AArch64RegisterInfo.td"
 170 include "AArch64RegisterBanks.td"
 171 include "AArch64CallingConvention.td"
 172
 173 //===----------------------------------------------------------------------===//
 174 // Instruction Descriptions
 175 //===----------------------------------------------------------------------===//
 176
 177 include "AArch64Schedule.td"
 178 include "AArch64InstrInfo.td"
 179
 180 def AArch64InstrInfo : InstrInfo;
 181
 182 //===----------------------------------------------------------------------===//
 183 // Named operands for MRS/MSR/TLBI/...
 184 //===----------------------------------------------------------------------===//
 185
 186 include "AArch64SystemOperands.td"
 187
 188 //===----------------------------------------------------------------------===//
 189 // AArch64 Processors supported.
 190 //
 191 include "AArch64SchedA53.td"
 192 include "AArch64SchedA57.td"
 193 include "AArch64SchedCyclone.td"
 194 include "AArch64SchedFalkor.td"
 195 include "AArch64SchedKryo.td"
 196 include "AArch64SchedM1.td"
 197 include "AArch64SchedThunderX.td"
 198 include "AArch64SchedThunderX2T99.td"
 199
 200 def ProcA35     : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
 201                                    "Cortex-A35 ARM processors", [
 202                                    FeatureCRC,
 203                                    FeatureCrypto,
 204                                    FeatureFPARMv8,
 205                                    FeatureNEON,
 206                                    FeaturePerfMon
 207                                    ]>;
 208
 209 def ProcA53     : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
 210                                    "Cortex-A53 ARM processors", [
 211                                    FeatureBalanceFPOps,
 212                                    FeatureCRC,
 213                                    FeatureCrypto,
 214                                    FeatureCustomCheapAsMoveHandling,
 215                                    FeatureFPARMv8,
 216                                    FeatureFuseAES,
 217                                    FeatureNEON,
 218                                    FeaturePerfMon,
 219                                    FeaturePostRAScheduler,
 220                                    FeatureUseAA
 221                                    ]>;
 222
 223 def ProcA55     : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55",
 224                                    "Cortex-A55 ARM processors", [
 225                                    HasV8_2aOps,
 226                                    FeatureCrypto,
 227                                    FeatureFPARMv8,
 228                                    FeatureFuseAES,
 229                                    FeatureNEON,
 230                                    FeatureFullFP16,
 231                                    FeatureDotProd,
 232                                    FeatureRCPC,
 233                                    FeaturePerfMon
 234                                    ]>;
 235
 236 def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
 237                                    "Cortex-A57 ARM processors", [
 238                                    FeatureBalanceFPOps,
 239                                    FeatureCRC,
 240                                    FeatureCrypto,
 241                                    FeatureCustomCheapAsMoveHandling,
 242                                    FeatureFPARMv8,
 243                                    FeatureFuseAES,
 244                                    FeatureFuseLiterals,
 245                                    FeatureNEON,
 246                                    FeaturePerfMon,
 247                                    FeaturePostRAScheduler,
 248                                    FeaturePredictableSelectIsExpensive
 249                                    ]>;
 250
 251 def ProcA72     : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
 252                                    "Cortex-A72 ARM processors", [
 253                                    FeatureCRC,
 254                                    FeatureCrypto,
 255                                    FeatureFPARMv8,
 256                                    FeatureFuseAES,
 257                                    FeatureNEON,
 258                                    FeaturePerfMon
 259                                    ]>;
 260
 261 def ProcA73     : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
 262                                    "Cortex-A73 ARM processors", [
 263                                    FeatureCRC,
 264                                    FeatureCrypto,
 265                                    FeatureFPARMv8,
 266                                    FeatureFuseAES,
 267                                    FeatureNEON,
 268                                    FeaturePerfMon
 269                                    ]>;
 270
 271 def ProcA75     : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75",
 272                                    "Cortex-A75 ARM processors", [
 273                                    HasV8_2aOps,
 274                                    FeatureCrypto,
 275                                    FeatureFPARMv8,
 276                                    FeatureFuseAES,
 277                                    FeatureNEON,
 278                                    FeatureFullFP16,
 279                                    FeatureDotProd,
 280                                    FeatureRCPC,
 281                                    FeaturePerfMon
 282                                    ]>;
 283
 284 // Note that cyclone does not fuse AES instructions, but newer apple chips do
 285 // perform the fusion and cyclone is used by default when targetting apple OSes.
 286 def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
 287                                    "Cyclone", [
 288                                    FeatureAlternateSExtLoadCVTF32Pattern,
 289                                    FeatureArithmeticBccFusion,
 290                                    FeatureArithmeticCbzFusion,
 291                                    FeatureCrypto,
 292                                    FeatureDisableLatencySchedHeuristic,
 293                                    FeatureFPARMv8,
 294                                    FeatureFuseAES,
 295                                    FeatureNEON,
 296                                    FeaturePerfMon,
 297                                    FeatureSlowMisaligned128Store,
 298                                    FeatureZCRegMove,
 299                                    FeatureZCZeroing,
 300                                    FeatureZCZeroingFPWorkaround
 301                                    ]>;
 302
 303 def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1",
 304                                     "Samsung Exynos-M1 processors",
 305                                     [FeatureSlowPaired128,
 306                                      FeatureCRC,
 307                                      FeatureCrypto,
 308                                      FeatureCustomCheapAsMoveHandling,
 309                                      FeatureFPARMv8,
 310                                      FeatureFuseAES,
 311                                      FeatureNEON,
 312                                      FeaturePerfMon,
 313                                      FeaturePostRAScheduler,
 314                                      FeatureSlowMisaligned128Store,
 315                                      FeatureUseRSqrt,
 316                                      FeatureZCZeroing]>;
 317
 318 def ProcExynosM2 : SubtargetFeature<"exynosm2", "ARMProcFamily", "ExynosM1",
 319                                     "Samsung Exynos-M2/M3 processors",
 320                                     [FeatureSlowPaired128,
 321                                      FeatureCRC,
 322                                      FeatureCrypto,
 323                                      FeatureCustomCheapAsMoveHandling,
 324                                      FeatureFPARMv8,
 325                                      FeatureFuseAES,
 326                                      FeatureNEON,
 327                                      FeaturePerfMon,
 328                                      FeaturePostRAScheduler,
 329                                      FeatureSlowMisaligned128Store,
 330                                      FeatureZCZeroing]>;
 331
 332 def ProcKryo    : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",
 333                                    "Qualcomm Kryo processors", [
 334                                    FeatureCRC,
 335                                    FeatureCrypto,
 336                                    FeatureCustomCheapAsMoveHandling,
 337                                    FeatureFPARMv8,
 338                                    FeatureNEON,
 339                                    FeaturePerfMon,
 340                                    FeaturePostRAScheduler,
 341                                    FeaturePredictableSelectIsExpensive,
 342                                    FeatureZCZeroing,
 343                                    FeatureLSLFast
 344                                    ]>;
 345
 346 def ProcFalkor  : SubtargetFeature<"falkor", "ARMProcFamily", "Falkor",
 347                                    "Qualcomm Falkor processors", [
 348                                    FeatureCRC,
 349                                    FeatureCrypto,
 350                                    FeatureCustomCheapAsMoveHandling,
 351                                    FeatureFPARMv8,
 352                                    FeatureNEON,
 353                                    FeaturePerfMon,
 354                                    FeaturePostRAScheduler,
 355                                    FeaturePredictableSelectIsExpensive,
 356                                    FeatureRDM,
 357                                    FeatureZCZeroing,
 358                                    FeatureLSLFast,
 359                                    FeatureSlowSTRQro
 360                                    ]>;
 361
 362 def ProcSaphira  : SubtargetFeature<"saphira", "ARMProcFamily", "Saphira",
 363                                    "Qualcomm Saphira processors", [
 364                                    FeatureCrypto,
 365                                    FeatureCustomCheapAsMoveHandling,
 366                                    FeatureFPARMv8,
 367                                    FeatureNEON,
 368                                    FeatureSPE,
 369                                    FeaturePerfMon,
 370                                    FeaturePostRAScheduler,
 371                                    FeaturePredictableSelectIsExpensive,
 372                                    FeatureZCZeroing,
 373                                    FeatureLSLFast,
 374                                    HasV8_3aOps]>;
 375
 376 def ProcThunderX2T99  : SubtargetFeature<"thunderx2t99", "ARMProcFamily",
 377                                          "ThunderX2T99",
 378                                          "Cavium ThunderX2 processors", [
 379                                           FeatureCRC,
 380                                           FeatureCrypto,
 381                                           FeatureFPARMv8,
 382                                           FeatureArithmeticBccFusion,
 383                                           FeatureNEON,
 384                                           FeaturePostRAScheduler,
 385                                           FeaturePredictableSelectIsExpensive,
 386                                           FeatureLSE,
 387                                           HasV8_1aOps]>;
 388
 389 def ProcThunderX : SubtargetFeature<"thunderx", "ARMProcFamily", "ThunderX",
 390                                     "Cavium ThunderX processors", [
 391                                     FeatureCRC,
 392                                     FeatureCrypto,
 393                                     FeatureFPARMv8,
 394                                     FeaturePerfMon,
 395                                     FeaturePostRAScheduler,
 396                                     FeaturePredictableSelectIsExpensive,
 397                                     FeatureNEON]>;
 398
 399 def ProcThunderXT88 : SubtargetFeature<"thunderxt88", "ARMProcFamily",
 400                                        "ThunderXT88",
 401                                        "Cavium ThunderX processors", [
 402                                        FeatureCRC,
 403                                        FeatureCrypto,
 404                                        FeatureFPARMv8,
 405                                        FeaturePerfMon,
 406                                        FeaturePostRAScheduler,
 407                                        FeaturePredictableSelectIsExpensive,
 408                                        FeatureNEON]>;
 409
 410 def ProcThunderXT81 : SubtargetFeature<"thunderxt81", "ARMProcFamily",
 411                                        "ThunderXT81",
 412                                        "Cavium ThunderX processors", [
 413                                        FeatureCRC,
 414                                        FeatureCrypto,
 415                                        FeatureFPARMv8,
 416                                        FeaturePerfMon,
 417                                        FeaturePostRAScheduler,
 418                                        FeaturePredictableSelectIsExpensive,
 419                                        FeatureNEON]>;
 420
 421 def ProcThunderXT83 : SubtargetFeature<"thunderxt83", "ARMProcFamily",
 422                                        "ThunderXT83",
 423                                        "Cavium ThunderX processors", [
 424                                        FeatureCRC,
 425                                        FeatureCrypto,
 426                                        FeatureFPARMv8,
 427                                        FeaturePerfMon,
 428                                        FeaturePostRAScheduler,
 429                                        FeaturePredictableSelectIsExpensive,
 430                                        FeatureNEON]>;
 431
 432 def : ProcessorModel<"generic", NoSchedModel, [
 433                      FeatureFPARMv8,
 434                      FeatureFuseAES,
 435                      FeatureNEON,
 436                      FeaturePerfMon,
 437                      FeaturePostRAScheduler
 438                      ]>;
 439
 440 // FIXME: Cortex-A35 and Cortex-A55 are currently modeled as a Cortex-A53.
 441 def : ProcessorModel<"cortex-a35", CortexA53Model, [ProcA35]>;
 442 def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
 443 def : ProcessorModel<"cortex-a55", CortexA53Model, [ProcA55]>;
 444 def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
 445 // FIXME: Cortex-A72, Cortex-A73 and Cortex-A75 are currently modeled as a Cortex-A57.
 446 def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA72]>;
 447 def : ProcessorModel<"cortex-a73", CortexA57Model, [ProcA73]>;
 448 def : ProcessorModel<"cortex-a75", CortexA57Model, [ProcA75]>;
 449 def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
 450 def : ProcessorModel<"exynos-m1", ExynosM1Model, [ProcExynosM1]>;
 451 def : ProcessorModel<"exynos-m2", ExynosM1Model, [ProcExynosM2]>;
 452 def : ProcessorModel<"exynos-m3", ExynosM1Model, [ProcExynosM2]>;
 453 def : ProcessorModel<"falkor", FalkorModel, [ProcFalkor]>;
 454 def : ProcessorModel<"saphira", FalkorModel, [ProcSaphira]>;
 455 def : ProcessorModel<"kryo", KryoModel, [ProcKryo]>;
 456 // Cavium ThunderX/ThunderX T8X  Processors
 457 def : ProcessorModel<"thunderx", ThunderXT8XModel,  [ProcThunderX]>;
 458 def : ProcessorModel<"thunderxt88", ThunderXT8XModel,  [ProcThunderXT88]>;
 459 def : ProcessorModel<"thunderxt81", ThunderXT8XModel,  [ProcThunderXT81]>;
 460 def : ProcessorModel<"thunderxt83", ThunderXT8XModel,  [ProcThunderXT83]>;
 461 // Cavium ThunderX2T9X  Processors. Formerly Broadcom Vulcan.
 462 def : ProcessorModel<"thunderx2t99", ThunderX2T99Model, [ProcThunderX2T99]>;
 463
 464 //===----------------------------------------------------------------------===//
 465 // Assembly parser
 466 //===----------------------------------------------------------------------===//
 467
 468 def GenericAsmParserVariant : AsmParserVariant {
 469   int Variant = 0;
 470   string Name = "generic";
 471   string BreakCharacters = ".";
 472 }
 473
 474 def AppleAsmParserVariant : AsmParserVariant {
 475   int Variant = 1;
 476   string Name = "apple-neon";
 477   string BreakCharacters = ".";
 478 }
 479
 480 //===----------------------------------------------------------------------===//
 481 // Assembly printer
 482 //===----------------------------------------------------------------------===//
 483 // AArch64 Uses the MC printer for asm output, so make sure the TableGen
 484 // AsmWriter bits get associated with the correct class.
 485 def GenericAsmWriter : AsmWriter {
 486   string AsmWriterClassName  = "InstPrinter";
 487   int PassSubtarget = 1;
 488   int Variant = 0;
 489   bit isMCAsmWriter = 1;
 490 }
 491
 492 def AppleAsmWriter : AsmWriter {
 493   let AsmWriterClassName = "AppleInstPrinter";
 494   int PassSubtarget = 1;
 495   int Variant = 1;
 496   int isMCAsmWriter = 1;
 497 }
 498
 499 //===----------------------------------------------------------------------===//
 500 // Target Declaration
 501 //===----------------------------------------------------------------------===//
 502
 503 def AArch64 : Target {
 504   let InstructionSet = AArch64InstrInfo;
 505   let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
 506   let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];
 507 }