contrib/llvm/lib/Target/AArch64/AArch64.td

   1 //=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 //===----------------------------------------------------------------------===//
  14 // Target-independent interfaces which we are implementing.
  15 //===----------------------------------------------------------------------===//
  16
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // AArch64 Subtarget features.
  21 //
  22
  23 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
  24                                        "Enable ARMv8 FP">;
  25
  26 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
  27   "Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
  28
  29 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
  30   "Enable cryptographic instructions">;
  31
  32 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
  33   "Enable ARMv8 CRC-32 checksum instructions">;
  34
  35 def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
  36   "Enable ARMv8 Reliability, Availability and Serviceability Extensions">;
  37
  38 def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true",
  39   "Enable ARMv8.1 Large System Extension (LSE) atomic instructions">;
  40
  41 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
  42   "Enable ARMv8 PMUv3 Performance Monitors extension">;
  43
  44 def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
  45   "Full FP16", [FeatureFPARMv8]>;
  46
  47 def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true",
  48   "Enable Statistical Profiling extension">;
  49
  50 /// Cyclone has register move instructions which are "free".
  51 def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
  52                                         "Has zero-cycle register moves">;
  53
  54 /// Cyclone has instructions which zero registers for "free".
  55 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
  56                                         "Has zero-cycle zeroing instructions">;
  57
  58 def FeatureStrictAlign : SubtargetFeature<"strict-align",
  59                                           "StrictAlign", "true",
  60                                           "Disallow all unaligned memory "
  61                                           "access">;
  62
  63 def FeatureReserveX18 : SubtargetFeature<"reserve-x18", "ReserveX18", "true",
  64                                          "Reserve X18, making it unavailable "
  65                                          "as a GPR">;
  66
  67 def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",
  68                                     "Use alias analysis during codegen">;
  69
  70 def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps",
  71     "true",
  72     "balance mix of odd and even D-registers for fp multiply(-accumulate) ops">;
  73
  74 def FeaturePredictableSelectIsExpensive : SubtargetFeature<
  75     "predictable-select-expensive", "PredictableSelectIsExpensive", "true",
  76     "Prefer likely predicted branches over selects">;
  77
  78 def FeatureCustomCheapAsMoveHandling : SubtargetFeature<"custom-cheap-as-move",
  79     "CustomAsCheapAsMove", "true",
  80     "Use custom code for TargetInstrInfo::isAsCheapAsAMove()">;
  81
  82 def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
  83     "UsePostRAScheduler", "true", "Schedule again after register allocation">;
  84
  85 def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store",
  86     "Misaligned128StoreIsSlow", "true", "Misaligned 128 bit stores are slow">;
  87
  88 def FeatureSlowPaired128 : SubtargetFeature<"slow-paired-128",
  89     "Paired128IsSlow", "true", "Paired 128 bit loads and stores are slow">;
  90
  91 def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature<
  92     "alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern",
  93     "true", "Use alternative pattern for sextload convert to f32">;
  94
  95 def FeatureArithmeticBccFusion : SubtargetFeature<
  96     "arith-bcc-fusion", "HasArithmeticBccFusion", "true",
  97     "CPU fuses arithmetic+bcc operations">;
  98
  99 def FeatureArithmeticCbzFusion : SubtargetFeature<
 100     "arith-cbz-fusion", "HasArithmeticCbzFusion", "true",
 101     "CPU fuses arithmetic + cbz/cbnz operations">;
 102
 103 def FeatureDisableLatencySchedHeuristic : SubtargetFeature<
 104     "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",
 105     "Disable latency scheduling heuristic">;
 106
 107 def FeatureUseRSqrt : SubtargetFeature<
 108     "use-reciprocal-square-root", "UseRSqrt", "true",
 109     "Use the reciprocal square root approximation">;
 110
 111 //===----------------------------------------------------------------------===//
 112 // Architectures.
 113 //
 114
 115 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
 116   "Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE]>;
 117
 118 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
 119   "Support ARM v8.2a instructions", [HasV8_1aOps, FeatureRAS]>;
 120
 121 //===----------------------------------------------------------------------===//
 122 // Register File Description
 123 //===----------------------------------------------------------------------===//
 124
 125 include "AArch64RegisterInfo.td"
 126 include "AArch64CallingConvention.td"
 127
 128 //===----------------------------------------------------------------------===//
 129 // Instruction Descriptions
 130 //===----------------------------------------------------------------------===//
 131
 132 include "AArch64Schedule.td"
 133 include "AArch64InstrInfo.td"
 134
 135 def AArch64InstrInfo : InstrInfo;
 136
 137 //===----------------------------------------------------------------------===//
 138 // Named operands for MRS/MSR/TLBI/...
 139 //===----------------------------------------------------------------------===//
 140
 141 include "AArch64SystemOperands.td"
 142
 143 //===----------------------------------------------------------------------===//
 144 // AArch64 Processors supported.
 145 //
 146 include "AArch64SchedA53.td"
 147 include "AArch64SchedA57.td"
 148 include "AArch64SchedCyclone.td"
 149 include "AArch64SchedFalkor.td"
 150 include "AArch64SchedKryo.td"
 151 include "AArch64SchedM1.td"
 152 include "AArch64SchedVulcan.td"
 153
 154 def ProcA35     : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
 155                                    "Cortex-A35 ARM processors", [
 156                                    FeatureCRC,
 157                                    FeatureCrypto,
 158                                    FeatureFPARMv8,
 159                                    FeatureNEON,
 160                                    FeaturePerfMon
 161                                    ]>;
 162
 163 def ProcA53     : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
 164                                    "Cortex-A53 ARM processors", [
 165                                    FeatureBalanceFPOps,
 166                                    FeatureCRC,
 167                                    FeatureCrypto,
 168                                    FeatureCustomCheapAsMoveHandling,
 169                                    FeatureFPARMv8,
 170                                    FeatureNEON,
 171                                    FeaturePerfMon,
 172                                    FeaturePostRAScheduler,
 173                                    FeatureUseAA
 174                                    ]>;
 175
 176 def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
 177                                    "Cortex-A57 ARM processors", [
 178                                    FeatureBalanceFPOps,
 179                                    FeatureCRC,
 180                                    FeatureCrypto,
 181                                    FeatureCustomCheapAsMoveHandling,
 182                                    FeatureFPARMv8,
 183                                    FeatureNEON,
 184                                    FeaturePerfMon,
 185                                    FeaturePostRAScheduler,
 186                                    FeaturePredictableSelectIsExpensive
 187                                    ]>;
 188
 189 def ProcA72     : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
 190                                    "Cortex-A72 ARM processors", [
 191                                    FeatureCRC,
 192                                    FeatureCrypto,
 193                                    FeatureFPARMv8,
 194                                    FeatureNEON,
 195                                    FeaturePerfMon
 196                                    ]>;
 197
 198 def ProcA73     : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
 199                                    "Cortex-A73 ARM processors", [
 200                                    FeatureCRC,
 201                                    FeatureCrypto,
 202                                    FeatureFPARMv8,
 203                                    FeatureNEON,
 204                                    FeaturePerfMon
 205                                    ]>;
 206
 207 def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
 208                                    "Cyclone", [
 209                                    FeatureAlternateSExtLoadCVTF32Pattern,
 210                                    FeatureCrypto,
 211                                    FeatureDisableLatencySchedHeuristic,
 212                                    FeatureFPARMv8,
 213                                    FeatureArithmeticBccFusion,
 214                                    FeatureArithmeticCbzFusion,
 215                                    FeatureNEON,
 216                                    FeaturePerfMon,
 217                                    FeatureSlowMisaligned128Store,
 218                                    FeatureZCRegMove,
 219                                    FeatureZCZeroing
 220                                    ]>;
 221
 222 def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1",
 223                                     "Samsung Exynos-M1 processors",
 224                                     [FeatureSlowPaired128,
 225                                      FeatureCRC,
 226                                      FeatureCrypto,
 227                                      FeatureCustomCheapAsMoveHandling,
 228                                      FeatureFPARMv8,
 229                                      FeatureNEON,
 230                                      FeaturePerfMon,
 231                                      FeaturePostRAScheduler,
 232                                      FeatureSlowMisaligned128Store,
 233                                      FeatureUseRSqrt,
 234                                      FeatureZCZeroing]>;
 235
 236 def ProcExynosM2 : SubtargetFeature<"exynosm2", "ARMProcFamily", "ExynosM1",
 237                                     "Samsung Exynos-M2/M3 processors",
 238                                     [FeatureSlowPaired128,
 239                                      FeatureCRC,
 240                                      FeatureCrypto,
 241                                      FeatureCustomCheapAsMoveHandling,
 242                                      FeatureFPARMv8,
 243                                      FeatureNEON,
 244                                      FeaturePerfMon,
 245                                      FeaturePostRAScheduler,
 246                                      FeatureSlowMisaligned128Store,
 247                                      FeatureZCZeroing]>;
 248
 249 def ProcKryo    : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",
 250                                    "Qualcomm Kryo processors", [
 251                                    FeatureCRC,
 252                                    FeatureCrypto,
 253                                    FeatureCustomCheapAsMoveHandling,
 254                                    FeatureFPARMv8,
 255                                    FeatureNEON,
 256                                    FeaturePerfMon,
 257                                    FeaturePostRAScheduler,
 258                                    FeaturePredictableSelectIsExpensive,
 259                                    FeatureZCZeroing
 260                                    ]>;
 261
 262 def ProcFalkor  : SubtargetFeature<"falkor", "ARMProcFamily", "Falkor",
 263                                    "Qualcomm Falkor processors", [
 264                                    FeatureCRC,
 265                                    FeatureCrypto,
 266                                    FeatureCustomCheapAsMoveHandling,
 267                                    FeatureFPARMv8,
 268                                    FeatureNEON,
 269                                    FeaturePerfMon,
 270                                    FeaturePostRAScheduler,
 271                                    FeaturePredictableSelectIsExpensive,
 272                                    FeatureZCZeroing
 273                                    ]>;
 274
 275 def ProcVulcan  : SubtargetFeature<"vulcan", "ARMProcFamily", "Vulcan",
 276                                    "Broadcom Vulcan processors", [
 277                                    FeatureCRC,
 278                                    FeatureCrypto,
 279                                    FeatureFPARMv8,
 280                                    FeatureArithmeticBccFusion,
 281                                    FeatureNEON,
 282                                    FeaturePostRAScheduler,
 283                                    FeaturePredictableSelectIsExpensive,
 284                                    HasV8_1aOps]>;
 285
 286 def : ProcessorModel<"generic", NoSchedModel, [
 287                      FeatureCRC,
 288                      FeatureFPARMv8,
 289                      FeatureNEON,
 290                      FeaturePerfMon,
 291                      FeaturePostRAScheduler
 292                      ]>;
 293
 294 // FIXME: Cortex-A35 is currently modelled as a Cortex-A53
 295 def : ProcessorModel<"cortex-a35", CortexA53Model, [ProcA35]>;
 296 def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
 297 def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
 298 // FIXME: Cortex-A72 and Cortex-A73 are currently modelled as an Cortex-A57.
 299 def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA72]>;
 300 def : ProcessorModel<"cortex-a73", CortexA57Model, [ProcA73]>;
 301 def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
 302 def : ProcessorModel<"exynos-m1", ExynosM1Model, [ProcExynosM1]>;
 303 def : ProcessorModel<"exynos-m2", ExynosM1Model, [ProcExynosM2]>;
 304 def : ProcessorModel<"exynos-m3", ExynosM1Model, [ProcExynosM2]>;
 305 def : ProcessorModel<"falkor", FalkorModel, [ProcFalkor]>;
 306 def : ProcessorModel<"kryo", KryoModel, [ProcKryo]>;
 307 def : ProcessorModel<"vulcan", VulcanModel, [ProcVulcan]>;
 308
 309 //===----------------------------------------------------------------------===//
 310 // Assembly parser
 311 //===----------------------------------------------------------------------===//
 312
 313 def GenericAsmParserVariant : AsmParserVariant {
 314   int Variant = 0;
 315   string Name = "generic";
 316   string BreakCharacters = ".";
 317 }
 318
 319 def AppleAsmParserVariant : AsmParserVariant {
 320   int Variant = 1;
 321   string Name = "apple-neon";
 322   string BreakCharacters = ".";
 323 }
 324
 325 //===----------------------------------------------------------------------===//
 326 // Assembly printer
 327 //===----------------------------------------------------------------------===//
 328 // AArch64 Uses the MC printer for asm output, so make sure the TableGen
 329 // AsmWriter bits get associated with the correct class.
 330 def GenericAsmWriter : AsmWriter {
 331   string AsmWriterClassName  = "InstPrinter";
 332   int PassSubtarget = 1;
 333   int Variant = 0;
 334   bit isMCAsmWriter = 1;
 335 }
 336
 337 def AppleAsmWriter : AsmWriter {
 338   let AsmWriterClassName = "AppleInstPrinter";
 339   int PassSubtarget = 1;
 340   int Variant = 1;
 341   int isMCAsmWriter = 1;
 342 }
 343
 344 //===----------------------------------------------------------------------===//
 345 // Target Declaration
 346 //===----------------------------------------------------------------------===//
 347
 348 def AArch64 : Target {
 349   let InstructionSet = AArch64InstrInfo;
 350   let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
 351   let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];
 352 }