contrib/llvm/lib/Target/AArch64/AArch64.td

   1 //=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 //===----------------------------------------------------------------------===//
  14 // Target-independent interfaces which we are implementing.
  15 //===----------------------------------------------------------------------===//
  16
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // AArch64 Subtarget features.
  21 //
  22
  23 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
  24                                        "Enable ARMv8 FP">;
  25
  26 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
  27   "Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
  28
  29 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
  30   "Enable cryptographic instructions", [FeatureNEON]>;
  31
  32 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
  33   "Enable ARMv8 CRC-32 checksum instructions">;
  34
  35 def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
  36   "Enable ARMv8 Reliability, Availability and Serviceability Extensions">;
  37
  38 def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true",
  39   "Enable ARMv8.1 Large System Extension (LSE) atomic instructions">;
  40
  41 def FeatureRDM : SubtargetFeature<"rdm", "HasRDM", "true",
  42   "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions">;
  43
  44 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
  45   "Enable ARMv8 PMUv3 Performance Monitors extension">;
  46
  47 def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
  48   "Full FP16", [FeatureFPARMv8]>;
  49
  50 def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true",
  51   "Enable Statistical Profiling extension">;
  52
  53 /// Cyclone has register move instructions which are "free".
  54 def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
  55                                         "Has zero-cycle register moves">;
  56
  57 /// Cyclone has instructions which zero registers for "free".
  58 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
  59                                         "Has zero-cycle zeroing instructions">;
  60
  61 def FeatureStrictAlign : SubtargetFeature<"strict-align",
  62                                           "StrictAlign", "true",
  63                                           "Disallow all unaligned memory "
  64                                           "access">;
  65
  66 def FeatureReserveX18 : SubtargetFeature<"reserve-x18", "ReserveX18", "true",
  67                                          "Reserve X18, making it unavailable "
  68                                          "as a GPR">;
  69
  70 def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",
  71                                     "Use alias analysis during codegen">;
  72
  73 def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps",
  74     "true",
  75     "balance mix of odd and even D-registers for fp multiply(-accumulate) ops">;
  76
  77 def FeaturePredictableSelectIsExpensive : SubtargetFeature<
  78     "predictable-select-expensive", "PredictableSelectIsExpensive", "true",
  79     "Prefer likely predicted branches over selects">;
  80
  81 def FeatureCustomCheapAsMoveHandling : SubtargetFeature<"custom-cheap-as-move",
  82     "CustomAsCheapAsMove", "true",
  83     "Use custom code for TargetInstrInfo::isAsCheapAsAMove()">;
  84
  85 def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
  86     "UsePostRAScheduler", "true", "Schedule again after register allocation">;
  87
  88 def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store",
  89     "Misaligned128StoreIsSlow", "true", "Misaligned 128 bit stores are slow">;
  90
  91 def FeatureSlowPaired128 : SubtargetFeature<"slow-paired-128",
  92     "Paired128IsSlow", "true", "Paired 128 bit loads and stores are slow">;
  93
  94 def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature<
  95     "alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern",
  96     "true", "Use alternative pattern for sextload convert to f32">;
  97
  98 def FeatureArithmeticBccFusion : SubtargetFeature<
  99     "arith-bcc-fusion", "HasArithmeticBccFusion", "true",
 100     "CPU fuses arithmetic+bcc operations">;
 101
 102 def FeatureArithmeticCbzFusion : SubtargetFeature<
 103     "arith-cbz-fusion", "HasArithmeticCbzFusion", "true",
 104     "CPU fuses arithmetic + cbz/cbnz operations">;
 105
 106 def FeatureFuseAES : SubtargetFeature<
 107     "fuse-aes", "HasFuseAES", "true",
 108     "CPU fuses AES crypto operations">;
 109
 110 def FeatureFuseLiterals : SubtargetFeature<
 111     "fuse-literals", "HasFuseLiterals", "true",
 112     "CPU fuses literal generation operations">;
 113
 114 def FeatureDisableLatencySchedHeuristic : SubtargetFeature<
 115     "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",
 116     "Disable latency scheduling heuristic">;
 117
 118 def FeatureUseRSqrt : SubtargetFeature<
 119     "use-reciprocal-square-root", "UseRSqrt", "true",
 120     "Use the reciprocal square root approximation">;
 121
 122 def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates",
 123                                         "NegativeImmediates", "false",
 124                                         "Convert immediates and instructions "
 125                                         "to their negated or complemented "
 126                                         "equivalent when the immediate does "
 127                                         "not fit in the encoding.">;
 128
 129 def FeatureLSLFast : SubtargetFeature<
 130     "lsl-fast", "HasLSLFast", "true",
 131     "CPU has a fastpath logical shift of up to 3 places">;
 132 //===----------------------------------------------------------------------===//
 133 // Architectures.
 134 //
 135
 136 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
 137   "Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE, FeatureRDM]>;
 138
 139 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
 140   "Support ARM v8.2a instructions", [HasV8_1aOps, FeatureRAS]>;
 141
 142 //===----------------------------------------------------------------------===//
 143 // Register File Description
 144 //===----------------------------------------------------------------------===//
 145
 146 include "AArch64RegisterInfo.td"
 147 include "AArch64RegisterBanks.td"
 148 include "AArch64CallingConvention.td"
 149
 150 //===----------------------------------------------------------------------===//
 151 // Instruction Descriptions
 152 //===----------------------------------------------------------------------===//
 153
 154 include "AArch64Schedule.td"
 155 include "AArch64InstrInfo.td"
 156
 157 def AArch64InstrInfo : InstrInfo;
 158
 159 //===----------------------------------------------------------------------===//
 160 // Named operands for MRS/MSR/TLBI/...
 161 //===----------------------------------------------------------------------===//
 162
 163 include "AArch64SystemOperands.td"
 164
 165 //===----------------------------------------------------------------------===//
 166 // AArch64 Processors supported.
 167 //
 168 include "AArch64SchedA53.td"
 169 include "AArch64SchedA57.td"
 170 include "AArch64SchedCyclone.td"
 171 include "AArch64SchedFalkor.td"
 172 include "AArch64SchedKryo.td"
 173 include "AArch64SchedM1.td"
 174 include "AArch64SchedThunderX.td"
 175 include "AArch64SchedThunderX2T99.td"
 176
 177 def ProcA35     : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
 178                                    "Cortex-A35 ARM processors", [
 179                                    FeatureCRC,
 180                                    FeatureCrypto,
 181                                    FeatureFPARMv8,
 182                                    FeatureNEON,
 183                                    FeaturePerfMon
 184                                    ]>;
 185
 186 def ProcA53     : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
 187                                    "Cortex-A53 ARM processors", [
 188                                    FeatureBalanceFPOps,
 189                                    FeatureCRC,
 190                                    FeatureCrypto,
 191                                    FeatureCustomCheapAsMoveHandling,
 192                                    FeatureFPARMv8,
 193                                    FeatureFuseAES,
 194                                    FeatureNEON,
 195                                    FeaturePerfMon,
 196                                    FeaturePostRAScheduler,
 197                                    FeatureUseAA
 198                                    ]>;
 199
 200 def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
 201                                    "Cortex-A57 ARM processors", [
 202                                    FeatureBalanceFPOps,
 203                                    FeatureCRC,
 204                                    FeatureCrypto,
 205                                    FeatureCustomCheapAsMoveHandling,
 206                                    FeatureFPARMv8,
 207                                    FeatureFuseAES,
 208                                    FeatureFuseLiterals,
 209                                    FeatureNEON,
 210                                    FeaturePerfMon,
 211                                    FeaturePostRAScheduler,
 212                                    FeaturePredictableSelectIsExpensive
 213                                    ]>;
 214
 215 def ProcA72     : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
 216                                    "Cortex-A72 ARM processors", [
 217                                    FeatureCRC,
 218                                    FeatureCrypto,
 219                                    FeatureFPARMv8,
 220                                    FeatureFuseAES,
 221                                    FeatureNEON,
 222                                    FeaturePerfMon
 223                                    ]>;
 224
 225 def ProcA73     : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
 226                                    "Cortex-A73 ARM processors", [
 227                                    FeatureCRC,
 228                                    FeatureCrypto,
 229                                    FeatureFPARMv8,
 230                                    FeatureFuseAES,
 231                                    FeatureNEON,
 232                                    FeaturePerfMon
 233                                    ]>;
 234
 235 def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
 236                                    "Cyclone", [
 237                                    FeatureAlternateSExtLoadCVTF32Pattern,
 238                                    FeatureCrypto,
 239                                    FeatureDisableLatencySchedHeuristic,
 240                                    FeatureFPARMv8,
 241                                    FeatureArithmeticBccFusion,
 242                                    FeatureArithmeticCbzFusion,
 243                                    FeatureNEON,
 244                                    FeaturePerfMon,
 245                                    FeatureSlowMisaligned128Store,
 246                                    FeatureZCRegMove,
 247                                    FeatureZCZeroing
 248                                    ]>;
 249
 250 def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1",
 251                                     "Samsung Exynos-M1 processors",
 252                                     [FeatureSlowPaired128,
 253                                      FeatureCRC,
 254                                      FeatureCrypto,
 255                                      FeatureCustomCheapAsMoveHandling,
 256                                      FeatureFPARMv8,
 257                                      FeatureFuseAES,
 258                                      FeatureNEON,
 259                                      FeaturePerfMon,
 260                                      FeaturePostRAScheduler,
 261                                      FeatureSlowMisaligned128Store,
 262                                      FeatureUseRSqrt,
 263                                      FeatureZCZeroing]>;
 264
 265 def ProcExynosM2 : SubtargetFeature<"exynosm2", "ARMProcFamily", "ExynosM1",
 266                                     "Samsung Exynos-M2/M3 processors",
 267                                     [FeatureSlowPaired128,
 268                                      FeatureCRC,
 269                                      FeatureCrypto,
 270                                      FeatureCustomCheapAsMoveHandling,
 271                                      FeatureFPARMv8,
 272                                      FeatureNEON,
 273                                      FeaturePerfMon,
 274                                      FeaturePostRAScheduler,
 275                                      FeatureSlowMisaligned128Store,
 276                                      FeatureZCZeroing]>;
 277
 278 def ProcKryo    : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",
 279                                    "Qualcomm Kryo processors", [
 280                                    FeatureCRC,
 281                                    FeatureCrypto,
 282                                    FeatureCustomCheapAsMoveHandling,
 283                                    FeatureFPARMv8,
 284                                    FeatureNEON,
 285                                    FeaturePerfMon,
 286                                    FeaturePostRAScheduler,
 287                                    FeaturePredictableSelectIsExpensive,
 288                                    FeatureZCZeroing,
 289                                    FeatureLSLFast
 290                                    ]>;
 291
 292 def ProcFalkor  : SubtargetFeature<"falkor", "ARMProcFamily", "Falkor",
 293                                    "Qualcomm Falkor processors", [
 294                                    FeatureCRC,
 295                                    FeatureCrypto,
 296                                    FeatureCustomCheapAsMoveHandling,
 297                                    FeatureFPARMv8,
 298                                    FeatureNEON,
 299                                    FeaturePerfMon,
 300                                    FeaturePostRAScheduler,
 301                                    FeaturePredictableSelectIsExpensive,
 302                                    FeatureRDM,
 303                                    FeatureZCZeroing,
 304                                    FeatureLSLFast
 305                                    ]>;
 306
 307 def ProcThunderX2T99  : SubtargetFeature<"thunderx2t99", "ARMProcFamily",
 308                                          "ThunderX2T99",
 309                                          "Cavium ThunderX2 processors", [
 310                                           FeatureCRC,
 311                                           FeatureCrypto,
 312                                           FeatureFPARMv8,
 313                                           FeatureArithmeticBccFusion,
 314                                           FeatureNEON,
 315                                           FeaturePostRAScheduler,
 316                                           FeaturePredictableSelectIsExpensive,
 317                                           FeatureLSE,
 318                                           HasV8_1aOps]>;
 319
 320 def ProcThunderX : SubtargetFeature<"thunderx", "ARMProcFamily", "ThunderX",
 321                                     "Cavium ThunderX processors", [
 322                                     FeatureCRC,
 323                                     FeatureCrypto,
 324                                     FeatureFPARMv8,
 325                                     FeaturePerfMon,
 326                                     FeaturePostRAScheduler,
 327                                     FeaturePredictableSelectIsExpensive,
 328                                     FeatureNEON]>;
 329
 330 def ProcThunderXT88 : SubtargetFeature<"thunderxt88", "ARMProcFamily",
 331                                        "ThunderXT88",
 332                                        "Cavium ThunderX processors", [
 333                                        FeatureCRC,
 334                                        FeatureCrypto,
 335                                        FeatureFPARMv8,
 336                                        FeaturePerfMon,
 337                                        FeaturePostRAScheduler,
 338                                        FeaturePredictableSelectIsExpensive,
 339                                        FeatureNEON]>;
 340
 341 def ProcThunderXT81 : SubtargetFeature<"thunderxt81", "ARMProcFamily",
 342                                        "ThunderXT81",
 343                                        "Cavium ThunderX processors", [
 344                                        FeatureCRC,
 345                                        FeatureCrypto,
 346                                        FeatureFPARMv8,
 347                                        FeaturePerfMon,
 348                                        FeaturePostRAScheduler,
 349                                        FeaturePredictableSelectIsExpensive,
 350                                        FeatureNEON]>;
 351
 352 def ProcThunderXT83 : SubtargetFeature<"thunderxt83", "ARMProcFamily",
 353                                        "ThunderXT83",
 354                                        "Cavium ThunderX processors", [
 355                                        FeatureCRC,
 356                                        FeatureCrypto,
 357                                        FeatureFPARMv8,
 358                                        FeaturePerfMon,
 359                                        FeaturePostRAScheduler,
 360                                        FeaturePredictableSelectIsExpensive,
 361                                        FeatureNEON]>;
 362
 363 def : ProcessorModel<"generic", NoSchedModel, [
 364                      FeatureFPARMv8,
 365                      FeatureNEON,
 366                      FeaturePerfMon,
 367                      FeaturePostRAScheduler
 368                      ]>;
 369
 370 // FIXME: Cortex-A35 is currently modeled as a Cortex-A53.
 371 def : ProcessorModel<"cortex-a35", CortexA53Model, [ProcA35]>;
 372 def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
 373 def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
 374 // FIXME: Cortex-A72 and Cortex-A73 are currently modeled as a Cortex-A57.
 375 def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA72]>;
 376 def : ProcessorModel<"cortex-a73", CortexA57Model, [ProcA73]>;
 377 def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
 378 def : ProcessorModel<"exynos-m1", ExynosM1Model, [ProcExynosM1]>;
 379 def : ProcessorModel<"exynos-m2", ExynosM1Model, [ProcExynosM2]>;
 380 def : ProcessorModel<"exynos-m3", ExynosM1Model, [ProcExynosM2]>;
 381 def : ProcessorModel<"falkor", FalkorModel, [ProcFalkor]>;
 382 def : ProcessorModel<"kryo", KryoModel, [ProcKryo]>;
 383 // Cavium ThunderX/ThunderX T8X  Processors
 384 def : ProcessorModel<"thunderx", ThunderXT8XModel,  [ProcThunderX]>;
 385 def : ProcessorModel<"thunderxt88", ThunderXT8XModel,  [ProcThunderXT88]>;
 386 def : ProcessorModel<"thunderxt81", ThunderXT8XModel,  [ProcThunderXT81]>;
 387 def : ProcessorModel<"thunderxt83", ThunderXT8XModel,  [ProcThunderXT83]>;
 388 // Cavium ThunderX2T9X  Processors. Formerly Broadcom Vulcan.
 389 def : ProcessorModel<"thunderx2t99", ThunderX2T99Model, [ProcThunderX2T99]>;
 390
 391 //===----------------------------------------------------------------------===//
 392 // Assembly parser
 393 //===----------------------------------------------------------------------===//
 394
 395 def GenericAsmParserVariant : AsmParserVariant {
 396   int Variant = 0;
 397   string Name = "generic";
 398   string BreakCharacters = ".";
 399 }
 400
 401 def AppleAsmParserVariant : AsmParserVariant {
 402   int Variant = 1;
 403   string Name = "apple-neon";
 404   string BreakCharacters = ".";
 405 }
 406
 407 //===----------------------------------------------------------------------===//
 408 // Assembly printer
 409 //===----------------------------------------------------------------------===//
 410 // AArch64 Uses the MC printer for asm output, so make sure the TableGen
 411 // AsmWriter bits get associated with the correct class.
 412 def GenericAsmWriter : AsmWriter {
 413   string AsmWriterClassName  = "InstPrinter";
 414   int PassSubtarget = 1;
 415   int Variant = 0;
 416   bit isMCAsmWriter = 1;
 417 }
 418
 419 def AppleAsmWriter : AsmWriter {
 420   let AsmWriterClassName = "AppleInstPrinter";
 421   int PassSubtarget = 1;
 422   int Variant = 1;
 423   int isMCAsmWriter = 1;
 424 }
 425
 426 //===----------------------------------------------------------------------===//
 427 // Target Declaration
 428 //===----------------------------------------------------------------------===//
 429
 430 def AArch64 : Target {
 431   let InstructionSet = AArch64InstrInfo;
 432   let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
 433   let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];
 434 }