1 //=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // Target-independent interfaces which we are implementing.
15 //===----------------------------------------------------------------------===//
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // AArch64 Subtarget features.
23 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
26 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
27 "Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
29 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
30 "Enable cryptographic instructions">;
32 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
33 "Enable ARMv8 CRC-32 checksum instructions">;
35 def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
36 "Enable ARMv8 Reliability, Availability and Serviceability Extensions">;
38 def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true",
39 "Enable ARMv8.1 Large System Extension (LSE) atomic instructions">;
41 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
42 "Enable ARMv8 PMUv3 Performance Monitors extension">;
44 def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
45 "Full FP16", [FeatureFPARMv8]>;
47 def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true",
48 "Enable Statistical Profiling extension">;
50 /// Cyclone has register move instructions which are "free".
51 def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
52 "Has zero-cycle register moves">;
54 /// Cyclone has instructions which zero registers for "free".
55 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
56 "Has zero-cycle zeroing instructions">;
58 def FeatureStrictAlign : SubtargetFeature<"strict-align",
59 "StrictAlign", "true",
60 "Disallow all unaligned memory "
63 def FeatureReserveX18 : SubtargetFeature<"reserve-x18", "ReserveX18", "true",
64 "Reserve X18, making it unavailable "
67 def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",
68 "Use alias analysis during codegen">;
70 def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps",
72 "balance mix of odd and even D-registers for fp multiply(-accumulate) ops">;
74 def FeaturePredictableSelectIsExpensive : SubtargetFeature<
75 "predictable-select-expensive", "PredictableSelectIsExpensive", "true",
76 "Prefer likely predicted branches over selects">;
78 def FeatureCustomCheapAsMoveHandling : SubtargetFeature<"custom-cheap-as-move",
79 "CustomAsCheapAsMove", "true",
80 "Use custom code for TargetInstrInfo::isAsCheapAsAMove()">;
82 def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
83 "UsePostRAScheduler", "true", "Schedule again after register allocation">;
85 def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store",
86 "Misaligned128StoreIsSlow", "true", "Misaligned 128 bit stores are slow">;
88 def FeatureAvoidQuadLdStPairs : SubtargetFeature<"no-quad-ldst-pairs",
89 "AvoidQuadLdStPairs", "true",
90 "Do not form quad load/store pair operations">;
92 def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature<
93 "alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern",
94 "true", "Use alternative pattern for sextload convert to f32">;
96 def FeatureArithmeticBccFusion : SubtargetFeature<
97 "arith-bcc-fusion", "HasArithmeticBccFusion", "true",
98 "CPU fuses arithmetic+bcc operations">;
100 def FeatureArithmeticCbzFusion : SubtargetFeature<
101 "arith-cbz-fusion", "HasArithmeticCbzFusion", "true",
102 "CPU fuses arithmetic + cbz/cbnz operations">;
104 def FeatureDisableLatencySchedHeuristic : SubtargetFeature<
105 "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",
106 "Disable latency scheduling heuristic">;
108 def FeatureUseRSqrt : SubtargetFeature<
109 "use-reciprocal-square-root", "UseRSqrt", "true",
110 "Use the reciprocal square root approximation">;
112 //===----------------------------------------------------------------------===//
116 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
117 "Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE]>;
119 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
120 "Support ARM v8.2a instructions", [HasV8_1aOps, FeatureRAS]>;
122 //===----------------------------------------------------------------------===//
123 // Register File Description
124 //===----------------------------------------------------------------------===//
126 include "AArch64RegisterInfo.td"
127 include "AArch64CallingConvention.td"
129 //===----------------------------------------------------------------------===//
130 // Instruction Descriptions
131 //===----------------------------------------------------------------------===//
133 include "AArch64Schedule.td"
134 include "AArch64InstrInfo.td"
136 def AArch64InstrInfo : InstrInfo;
138 //===----------------------------------------------------------------------===//
139 // Named operands for MRS/MSR/TLBI/...
140 //===----------------------------------------------------------------------===//
142 include "AArch64SystemOperands.td"
144 //===----------------------------------------------------------------------===//
145 // AArch64 Processors supported.
147 include "AArch64SchedA53.td"
148 include "AArch64SchedA57.td"
149 include "AArch64SchedCyclone.td"
150 include "AArch64SchedFalkor.td"
151 include "AArch64SchedKryo.td"
152 include "AArch64SchedM1.td"
153 include "AArch64SchedVulcan.td"
155 def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
156 "Cortex-A35 ARM processors", [
164 def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
165 "Cortex-A53 ARM processors", [
169 FeatureCustomCheapAsMoveHandling,
173 FeaturePostRAScheduler,
177 def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
178 "Cortex-A57 ARM processors", [
182 FeatureCustomCheapAsMoveHandling,
186 FeaturePostRAScheduler,
187 FeaturePredictableSelectIsExpensive
190 def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
191 "Cortex-A72 ARM processors", [
199 def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
200 "Cortex-A73 ARM processors", [
208 def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
210 FeatureAlternateSExtLoadCVTF32Pattern,
212 FeatureDisableLatencySchedHeuristic,
214 FeatureArithmeticBccFusion,
215 FeatureArithmeticCbzFusion,
218 FeatureSlowMisaligned128Store,
223 def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1",
224 "Samsung Exynos-M1 processors",
225 [FeatureAvoidQuadLdStPairs,
228 FeatureCustomCheapAsMoveHandling,
232 FeaturePostRAScheduler,
233 FeatureSlowMisaligned128Store,
237 def ProcExynosM2 : SubtargetFeature<"exynosm2", "ARMProcFamily", "ExynosM1",
238 "Samsung Exynos-M2/M3 processors",
239 [FeatureAvoidQuadLdStPairs,
242 FeatureCustomCheapAsMoveHandling,
246 FeaturePostRAScheduler,
247 FeatureSlowMisaligned128Store,
250 def ProcKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",
251 "Qualcomm Kryo processors", [
254 FeatureCustomCheapAsMoveHandling,
258 FeaturePostRAScheduler,
259 FeaturePredictableSelectIsExpensive,
263 def ProcFalkor : SubtargetFeature<"falkor", "ARMProcFamily", "Falkor",
264 "Qualcomm Falkor processors", [
267 FeatureCustomCheapAsMoveHandling,
271 FeaturePostRAScheduler,
272 FeaturePredictableSelectIsExpensive,
276 def ProcVulcan : SubtargetFeature<"vulcan", "ARMProcFamily", "Vulcan",
277 "Broadcom Vulcan processors", [
281 FeatureArithmeticBccFusion,
283 FeaturePostRAScheduler,
284 FeaturePredictableSelectIsExpensive,
287 def : ProcessorModel<"generic", NoSchedModel, [
292 FeaturePostRAScheduler
295 // FIXME: Cortex-A35 is currently modelled as a Cortex-A53
296 def : ProcessorModel<"cortex-a35", CortexA53Model, [ProcA35]>;
297 def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
298 def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
299 // FIXME: Cortex-A72 and Cortex-A73 are currently modelled as an Cortex-A57.
300 def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA72]>;
301 def : ProcessorModel<"cortex-a73", CortexA57Model, [ProcA73]>;
302 def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
303 def : ProcessorModel<"exynos-m1", ExynosM1Model, [ProcExynosM1]>;
304 def : ProcessorModel<"exynos-m2", ExynosM1Model, [ProcExynosM2]>;
305 def : ProcessorModel<"exynos-m3", ExynosM1Model, [ProcExynosM2]>;
306 def : ProcessorModel<"falkor", FalkorModel, [ProcFalkor]>;
307 def : ProcessorModel<"kryo", KryoModel, [ProcKryo]>;
308 def : ProcessorModel<"vulcan", VulcanModel, [ProcVulcan]>;
310 //===----------------------------------------------------------------------===//
312 //===----------------------------------------------------------------------===//
314 def GenericAsmParserVariant : AsmParserVariant {
316 string Name = "generic";
317 string BreakCharacters = ".";
320 def AppleAsmParserVariant : AsmParserVariant {
322 string Name = "apple-neon";
323 string BreakCharacters = ".";
326 //===----------------------------------------------------------------------===//
328 //===----------------------------------------------------------------------===//
329 // AArch64 Uses the MC printer for asm output, so make sure the TableGen
330 // AsmWriter bits get associated with the correct class.
331 def GenericAsmWriter : AsmWriter {
332 string AsmWriterClassName = "InstPrinter";
333 int PassSubtarget = 1;
335 bit isMCAsmWriter = 1;
338 def AppleAsmWriter : AsmWriter {
339 let AsmWriterClassName = "AppleInstPrinter";
340 int PassSubtarget = 1;
342 int isMCAsmWriter = 1;
345 //===----------------------------------------------------------------------===//
346 // Target Declaration
347 //===----------------------------------------------------------------------===//
349 def AArch64 : Target {
350 let InstructionSet = AArch64InstrInfo;
351 let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
352 let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];