1 //=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // Target-independent interfaces which we are implementing.
15 //===----------------------------------------------------------------------===//
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // AArch64 Subtarget features.
23 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
26 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
27 "Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
29 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
30 "Enable cryptographic instructions">;
32 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
33 "Enable ARMv8 CRC-32 checksum instructions">;
35 def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
36 "Enable ARMv8 Reliability, Availability and Serviceability Extensions">;
38 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
39 "Enable ARMv8 PMUv3 Performance Monitors extension">;
41 def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
42 "Full FP16", [FeatureFPARMv8]>;
44 def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true",
45 "Enable Statistical Profiling extension">;
47 /// Cyclone has register move instructions which are "free".
48 def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
49 "Has zero-cycle register moves">;
51 /// Cyclone has instructions which zero registers for "free".
52 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
53 "Has zero-cycle zeroing instructions">;
55 def FeatureStrictAlign : SubtargetFeature<"strict-align",
56 "StrictAlign", "true",
57 "Disallow all unaligned memory "
60 def FeatureReserveX18 : SubtargetFeature<"reserve-x18", "ReserveX18", "true",
61 "Reserve X18, making it unavailable "
64 def FeatureMergeNarrowLd : SubtargetFeature<"merge-narrow-ld",
65 "MergeNarrowLoads", "true",
66 "Merge narrow load instructions">;
68 def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",
69 "Use alias analysis during codegen">;
71 def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps",
73 "balance mix of odd and even D-registers for fp multiply(-accumulate) ops">;
75 def FeaturePredictableSelectIsExpensive : SubtargetFeature<
76 "predictable-select-expensive", "PredictableSelectIsExpensive", "true",
77 "Prefer likely predicted branches over selects">;
79 def FeatureCustomCheapAsMoveHandling : SubtargetFeature<"custom-cheap-as-move",
80 "CustomAsCheapAsMove", "true",
81 "Use custom code for TargetInstrInfo::isAsCheapAsAMove()">;
83 def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
84 "UsePostRAScheduler", "true", "Schedule again after register allocation">;
86 def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store",
87 "Misaligned128StoreIsSlow", "true", "Misaligned 128 bit stores are slow">;
89 def FeatureAvoidQuadLdStPairs : SubtargetFeature<"no-quad-ldst-pairs",
90 "AvoidQuadLdStPairs", "true",
91 "Do not form quad load/store pair operations">;
93 def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature<
94 "alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern",
95 "true", "Use alternative pattern for sextload convert to f32">;
97 def FeatureMacroOpFusion : SubtargetFeature<
98 "macroop-fusion", "HasMacroOpFusion", "true",
99 "CPU supports macro op fusion">;
101 def FeatureDisableLatencySchedHeuristic : SubtargetFeature<
102 "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",
103 "Disable latency scheduling heuristic">;
105 def FeatureUseRSqrt : SubtargetFeature<
106 "use-reverse-square-root", "UseRSqrt", "true", "Use reverse square root">;
108 //===----------------------------------------------------------------------===//
112 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
113 "Support ARM v8.1a instructions", [FeatureCRC]>;
115 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
116 "Support ARM v8.2a instructions", [HasV8_1aOps, FeatureRAS]>;
118 //===----------------------------------------------------------------------===//
119 // Register File Description
120 //===----------------------------------------------------------------------===//
122 include "AArch64RegisterInfo.td"
123 include "AArch64CallingConvention.td"
125 //===----------------------------------------------------------------------===//
126 // Instruction Descriptions
127 //===----------------------------------------------------------------------===//
129 include "AArch64Schedule.td"
130 include "AArch64InstrInfo.td"
132 def AArch64InstrInfo : InstrInfo;
134 //===----------------------------------------------------------------------===//
135 // Named operands for MRS/MSR/TLBI/...
136 //===----------------------------------------------------------------------===//
138 include "AArch64SystemOperands.td"
140 //===----------------------------------------------------------------------===//
141 // AArch64 Processors supported.
143 include "AArch64SchedA53.td"
144 include "AArch64SchedA57.td"
145 include "AArch64SchedCyclone.td"
146 include "AArch64SchedM1.td"
147 include "AArch64SchedKryo.td"
148 include "AArch64SchedVulcan.td"
150 def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
151 "Cortex-A35 ARM processors", [
159 def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
160 "Cortex-A53 ARM processors", [
164 FeatureCustomCheapAsMoveHandling,
168 FeaturePostRAScheduler,
172 def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
173 "Cortex-A57 ARM processors", [
177 FeatureCustomCheapAsMoveHandling,
179 FeatureMergeNarrowLd,
182 FeaturePostRAScheduler,
183 FeaturePredictableSelectIsExpensive
186 def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
187 "Cortex-A72 ARM processors", [
195 def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
196 "Cortex-A73 ARM processors", [
204 def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
206 FeatureAlternateSExtLoadCVTF32Pattern,
208 FeatureDisableLatencySchedHeuristic,
210 FeatureMacroOpFusion,
213 FeatureSlowMisaligned128Store,
218 def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1",
219 "Samsung Exynos-M1 processors", [
220 FeatureAvoidQuadLdStPairs,
223 FeatureCustomCheapAsMoveHandling,
227 FeaturePostRAScheduler,
231 def ProcKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",
232 "Qualcomm Kryo processors", [
235 FeatureCustomCheapAsMoveHandling,
237 FeatureMergeNarrowLd,
240 FeaturePostRAScheduler,
241 FeaturePredictableSelectIsExpensive,
245 def ProcVulcan : SubtargetFeature<"vulcan", "ARMProcFamily", "Vulcan",
246 "Broadcom Vulcan processors", [
250 FeatureMacroOpFusion,
252 FeaturePostRAScheduler,
253 FeaturePredictableSelectIsExpensive,
256 def : ProcessorModel<"generic", NoSchedModel, [
261 FeaturePostRAScheduler
264 // FIXME: Cortex-A35 is currently modelled as a Cortex-A53
265 def : ProcessorModel<"cortex-a35", CortexA53Model, [ProcA35]>;
266 def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
267 def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
268 // FIXME: Cortex-A72 and Cortex-A73 are currently modelled as an Cortex-A57.
269 def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA72]>;
270 def : ProcessorModel<"cortex-a73", CortexA57Model, [ProcA73]>;
271 def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
272 def : ProcessorModel<"exynos-m1", ExynosM1Model, [ProcExynosM1]>;
273 def : ProcessorModel<"kryo", KryoModel, [ProcKryo]>;
274 def : ProcessorModel<"vulcan", VulcanModel, [ProcVulcan]>;
276 //===----------------------------------------------------------------------===//
278 //===----------------------------------------------------------------------===//
280 def GenericAsmParserVariant : AsmParserVariant {
282 string Name = "generic";
283 string BreakCharacters = ".";
286 def AppleAsmParserVariant : AsmParserVariant {
288 string Name = "apple-neon";
289 string BreakCharacters = ".";
292 //===----------------------------------------------------------------------===//
294 //===----------------------------------------------------------------------===//
295 // AArch64 Uses the MC printer for asm output, so make sure the TableGen
296 // AsmWriter bits get associated with the correct class.
297 def GenericAsmWriter : AsmWriter {
298 string AsmWriterClassName = "InstPrinter";
299 int PassSubtarget = 1;
301 bit isMCAsmWriter = 1;
304 def AppleAsmWriter : AsmWriter {
305 let AsmWriterClassName = "AppleInstPrinter";
306 int PassSubtarget = 1;
308 int isMCAsmWriter = 1;
311 //===----------------------------------------------------------------------===//
312 // Target Declaration
313 //===----------------------------------------------------------------------===//
315 def AArch64 : Target {
316 let InstructionSet = AArch64InstrInfo;
317 let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
318 let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];