contrib/llvm/lib/Target/AArch64/AArch64.td

   1 //=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 //===----------------------------------------------------------------------===//
  14 // Target-independent interfaces which we are implementing.
  15 //===----------------------------------------------------------------------===//
  16
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // AArch64 Subtarget features.
  21 //
  22
  23 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
  24                                        "Enable ARMv8 FP">;
  25
  26 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
  27   "Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
  28
  29 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
  30   "Enable cryptographic instructions", [FeatureNEON]>;
  31
  32 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
  33   "Enable ARMv8 CRC-32 checksum instructions">;
  34
  35 def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
  36   "Enable ARMv8 Reliability, Availability and Serviceability Extensions">;
  37
  38 def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true",
  39   "Enable ARMv8.1 Large System Extension (LSE) atomic instructions">;
  40
  41 def FeatureRDM : SubtargetFeature<"rdm", "HasRDM", "true",
  42   "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions">;
  43
  44 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
  45   "Enable ARMv8 PMUv3 Performance Monitors extension">;
  46
  47 def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
  48   "Full FP16", [FeatureFPARMv8]>;
  49
  50 def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true",
  51   "Enable Statistical Profiling extension">;
  52
  53 def FeatureSVE : SubtargetFeature<"sve", "HasSVE", "true",
  54   "Enable Scalable Vector Extension (SVE) instructions">;
  55
  56 /// Cyclone has register move instructions which are "free".
  57 def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
  58                                         "Has zero-cycle register moves">;
  59
  60 /// Cyclone has instructions which zero registers for "free".
  61 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
  62                                         "Has zero-cycle zeroing instructions">;
  63
  64 def FeatureStrictAlign : SubtargetFeature<"strict-align",
  65                                           "StrictAlign", "true",
  66                                           "Disallow all unaligned memory "
  67                                           "access">;
  68
  69 def FeatureReserveX18 : SubtargetFeature<"reserve-x18", "ReserveX18", "true",
  70                                          "Reserve X18, making it unavailable "
  71                                          "as a GPR">;
  72
  73 def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",
  74                                     "Use alias analysis during codegen">;
  75
  76 def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps",
  77     "true",
  78     "balance mix of odd and even D-registers for fp multiply(-accumulate) ops">;
  79
  80 def FeaturePredictableSelectIsExpensive : SubtargetFeature<
  81     "predictable-select-expensive", "PredictableSelectIsExpensive", "true",
  82     "Prefer likely predicted branches over selects">;
  83
  84 def FeatureCustomCheapAsMoveHandling : SubtargetFeature<"custom-cheap-as-move",
  85     "CustomAsCheapAsMove", "true",
  86     "Use custom code for TargetInstrInfo::isAsCheapAsAMove()">;
  87
  88 def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
  89     "UsePostRAScheduler", "true", "Schedule again after register allocation">;
  90
  91 def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store",
  92     "Misaligned128StoreIsSlow", "true", "Misaligned 128 bit stores are slow">;
  93
  94 def FeatureSlowPaired128 : SubtargetFeature<"slow-paired-128",
  95     "Paired128IsSlow", "true", "Paired 128 bit loads and stores are slow">;
  96
  97 def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature<
  98     "alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern",
  99     "true", "Use alternative pattern for sextload convert to f32">;
 100
 101 def FeatureArithmeticBccFusion : SubtargetFeature<
 102     "arith-bcc-fusion", "HasArithmeticBccFusion", "true",
 103     "CPU fuses arithmetic+bcc operations">;
 104
 105 def FeatureArithmeticCbzFusion : SubtargetFeature<
 106     "arith-cbz-fusion", "HasArithmeticCbzFusion", "true",
 107     "CPU fuses arithmetic + cbz/cbnz operations">;
 108
 109 def FeatureFuseAES : SubtargetFeature<
 110     "fuse-aes", "HasFuseAES", "true",
 111     "CPU fuses AES crypto operations">;
 112
 113 def FeatureFuseLiterals : SubtargetFeature<
 114     "fuse-literals", "HasFuseLiterals", "true",
 115     "CPU fuses literal generation operations">;
 116
 117 def FeatureDisableLatencySchedHeuristic : SubtargetFeature<
 118     "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",
 119     "Disable latency scheduling heuristic">;
 120
 121 def FeatureUseRSqrt : SubtargetFeature<
 122     "use-reciprocal-square-root", "UseRSqrt", "true",
 123     "Use the reciprocal square root approximation">;
 124
 125 def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates",
 126                                         "NegativeImmediates", "false",
 127                                         "Convert immediates and instructions "
 128                                         "to their negated or complemented "
 129                                         "equivalent when the immediate does "
 130                                         "not fit in the encoding.">;
 131
 132 def FeatureLSLFast : SubtargetFeature<
 133     "lsl-fast", "HasLSLFast", "true",
 134     "CPU has a fastpath logical shift of up to 3 places">;
 135 //===----------------------------------------------------------------------===//
 136 // Architectures.
 137 //
 138
 139 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
 140   "Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE, FeatureRDM]>;
 141
 142 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
 143   "Support ARM v8.2a instructions", [HasV8_1aOps, FeatureRAS]>;
 144
 145 //===----------------------------------------------------------------------===//
 146 // Register File Description
 147 //===----------------------------------------------------------------------===//
 148
 149 include "AArch64RegisterInfo.td"
 150 include "AArch64RegisterBanks.td"
 151 include "AArch64CallingConvention.td"
 152
 153 //===----------------------------------------------------------------------===//
 154 // Instruction Descriptions
 155 //===----------------------------------------------------------------------===//
 156
 157 include "AArch64Schedule.td"
 158 include "AArch64InstrInfo.td"
 159
 160 def AArch64InstrInfo : InstrInfo;
 161
 162 //===----------------------------------------------------------------------===//
 163 // Named operands for MRS/MSR/TLBI/...
 164 //===----------------------------------------------------------------------===//
 165
 166 include "AArch64SystemOperands.td"
 167
 168 //===----------------------------------------------------------------------===//
 169 // AArch64 Processors supported.
 170 //
 171 include "AArch64SchedA53.td"
 172 include "AArch64SchedA57.td"
 173 include "AArch64SchedCyclone.td"
 174 include "AArch64SchedFalkor.td"
 175 include "AArch64SchedKryo.td"
 176 include "AArch64SchedM1.td"
 177 include "AArch64SchedThunderX.td"
 178 include "AArch64SchedThunderX2T99.td"
 179
 180 def ProcA35     : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
 181                                    "Cortex-A35 ARM processors", [
 182                                    FeatureCRC,
 183                                    FeatureCrypto,
 184                                    FeatureFPARMv8,
 185                                    FeatureNEON,
 186                                    FeaturePerfMon
 187                                    ]>;
 188
 189 def ProcA53     : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
 190                                    "Cortex-A53 ARM processors", [
 191                                    FeatureBalanceFPOps,
 192                                    FeatureCRC,
 193                                    FeatureCrypto,
 194                                    FeatureCustomCheapAsMoveHandling,
 195                                    FeatureFPARMv8,
 196                                    FeatureFuseAES,
 197                                    FeatureNEON,
 198                                    FeaturePerfMon,
 199                                    FeaturePostRAScheduler,
 200                                    FeatureUseAA
 201                                    ]>;
 202
 203 def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
 204                                    "Cortex-A57 ARM processors", [
 205                                    FeatureBalanceFPOps,
 206                                    FeatureCRC,
 207                                    FeatureCrypto,
 208                                    FeatureCustomCheapAsMoveHandling,
 209                                    FeatureFPARMv8,
 210                                    FeatureFuseAES,
 211                                    FeatureFuseLiterals,
 212                                    FeatureNEON,
 213                                    FeaturePerfMon,
 214                                    FeaturePostRAScheduler,
 215                                    FeaturePredictableSelectIsExpensive
 216                                    ]>;
 217
 218 def ProcA72     : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
 219                                    "Cortex-A72 ARM processors", [
 220                                    FeatureCRC,
 221                                    FeatureCrypto,
 222                                    FeatureFPARMv8,
 223                                    FeatureFuseAES,
 224                                    FeatureNEON,
 225                                    FeaturePerfMon
 226                                    ]>;
 227
 228 def ProcA73     : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
 229                                    "Cortex-A73 ARM processors", [
 230                                    FeatureCRC,
 231                                    FeatureCrypto,
 232                                    FeatureFPARMv8,
 233                                    FeatureFuseAES,
 234                                    FeatureNEON,
 235                                    FeaturePerfMon
 236                                    ]>;
 237
 238 def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
 239                                    "Cyclone", [
 240                                    FeatureAlternateSExtLoadCVTF32Pattern,
 241                                    FeatureCrypto,
 242                                    FeatureDisableLatencySchedHeuristic,
 243                                    FeatureFPARMv8,
 244                                    FeatureArithmeticBccFusion,
 245                                    FeatureArithmeticCbzFusion,
 246                                    FeatureNEON,
 247                                    FeaturePerfMon,
 248                                    FeatureSlowMisaligned128Store,
 249                                    FeatureZCRegMove,
 250                                    FeatureZCZeroing
 251                                    ]>;
 252
 253 def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1",
 254                                     "Samsung Exynos-M1 processors",
 255                                     [FeatureSlowPaired128,
 256                                      FeatureCRC,
 257                                      FeatureCrypto,
 258                                      FeatureCustomCheapAsMoveHandling,
 259                                      FeatureFPARMv8,
 260                                      FeatureFuseAES,
 261                                      FeatureNEON,
 262                                      FeaturePerfMon,
 263                                      FeaturePostRAScheduler,
 264                                      FeatureSlowMisaligned128Store,
 265                                      FeatureUseRSqrt,
 266                                      FeatureZCZeroing]>;
 267
 268 def ProcExynosM2 : SubtargetFeature<"exynosm2", "ARMProcFamily", "ExynosM1",
 269                                     "Samsung Exynos-M2/M3 processors",
 270                                     [FeatureSlowPaired128,
 271                                      FeatureCRC,
 272                                      FeatureCrypto,
 273                                      FeatureCustomCheapAsMoveHandling,
 274                                      FeatureFPARMv8,
 275                                      FeatureFuseAES,
 276                                      FeatureNEON,
 277                                      FeaturePerfMon,
 278                                      FeaturePostRAScheduler,
 279                                      FeatureSlowMisaligned128Store,
 280                                      FeatureZCZeroing]>;
 281
 282 def ProcKryo    : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",
 283                                    "Qualcomm Kryo processors", [
 284                                    FeatureCRC,
 285                                    FeatureCrypto,
 286                                    FeatureCustomCheapAsMoveHandling,
 287                                    FeatureFPARMv8,
 288                                    FeatureNEON,
 289                                    FeaturePerfMon,
 290                                    FeaturePostRAScheduler,
 291                                    FeaturePredictableSelectIsExpensive,
 292                                    FeatureZCZeroing,
 293                                    FeatureLSLFast
 294                                    ]>;
 295
 296 def ProcFalkor  : SubtargetFeature<"falkor", "ARMProcFamily", "Falkor",
 297                                    "Qualcomm Falkor processors", [
 298                                    FeatureCRC,
 299                                    FeatureCrypto,
 300                                    FeatureCustomCheapAsMoveHandling,
 301                                    FeatureFPARMv8,
 302                                    FeatureNEON,
 303                                    FeaturePerfMon,
 304                                    FeaturePostRAScheduler,
 305                                    FeaturePredictableSelectIsExpensive,
 306                                    FeatureRDM,
 307                                    FeatureZCZeroing,
 308                                    FeatureLSLFast
 309                                    ]>;
 310
 311 def ProcThunderX2T99  : SubtargetFeature<"thunderx2t99", "ARMProcFamily",
 312                                          "ThunderX2T99",
 313                                          "Cavium ThunderX2 processors", [
 314                                           FeatureCRC,
 315                                           FeatureCrypto,
 316                                           FeatureFPARMv8,
 317                                           FeatureArithmeticBccFusion,
 318                                           FeatureNEON,
 319                                           FeaturePostRAScheduler,
 320                                           FeaturePredictableSelectIsExpensive,
 321                                           FeatureLSE,
 322                                           HasV8_1aOps]>;
 323
 324 def ProcThunderX : SubtargetFeature<"thunderx", "ARMProcFamily", "ThunderX",
 325                                     "Cavium ThunderX processors", [
 326                                     FeatureCRC,
 327                                     FeatureCrypto,
 328                                     FeatureFPARMv8,
 329                                     FeaturePerfMon,
 330                                     FeaturePostRAScheduler,
 331                                     FeaturePredictableSelectIsExpensive,
 332                                     FeatureNEON]>;
 333
 334 def ProcThunderXT88 : SubtargetFeature<"thunderxt88", "ARMProcFamily",
 335                                        "ThunderXT88",
 336                                        "Cavium ThunderX processors", [
 337                                        FeatureCRC,
 338                                        FeatureCrypto,
 339                                        FeatureFPARMv8,
 340                                        FeaturePerfMon,
 341                                        FeaturePostRAScheduler,
 342                                        FeaturePredictableSelectIsExpensive,
 343                                        FeatureNEON]>;
 344
 345 def ProcThunderXT81 : SubtargetFeature<"thunderxt81", "ARMProcFamily",
 346                                        "ThunderXT81",
 347                                        "Cavium ThunderX processors", [
 348                                        FeatureCRC,
 349                                        FeatureCrypto,
 350                                        FeatureFPARMv8,
 351                                        FeaturePerfMon,
 352                                        FeaturePostRAScheduler,
 353                                        FeaturePredictableSelectIsExpensive,
 354                                        FeatureNEON]>;
 355
 356 def ProcThunderXT83 : SubtargetFeature<"thunderxt83", "ARMProcFamily",
 357                                        "ThunderXT83",
 358                                        "Cavium ThunderX processors", [
 359                                        FeatureCRC,
 360                                        FeatureCrypto,
 361                                        FeatureFPARMv8,
 362                                        FeaturePerfMon,
 363                                        FeaturePostRAScheduler,
 364                                        FeaturePredictableSelectIsExpensive,
 365                                        FeatureNEON]>;
 366
 367 def : ProcessorModel<"generic", NoSchedModel, [
 368                      FeatureFPARMv8,
 369                      FeatureFuseAES,
 370                      FeatureNEON,
 371                      FeaturePerfMon,
 372                      FeaturePostRAScheduler
 373                      ]>;
 374
 375 // FIXME: Cortex-A35 is currently modeled as a Cortex-A53.
 376 def : ProcessorModel<"cortex-a35", CortexA53Model, [ProcA35]>;
 377 def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
 378 def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
 379 // FIXME: Cortex-A72 and Cortex-A73 are currently modeled as a Cortex-A57.
 380 def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA72]>;
 381 def : ProcessorModel<"cortex-a73", CortexA57Model, [ProcA73]>;
 382 def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
 383 def : ProcessorModel<"exynos-m1", ExynosM1Model, [ProcExynosM1]>;
 384 def : ProcessorModel<"exynos-m2", ExynosM1Model, [ProcExynosM2]>;
 385 def : ProcessorModel<"exynos-m3", ExynosM1Model, [ProcExynosM2]>;
 386 def : ProcessorModel<"falkor", FalkorModel, [ProcFalkor]>;
 387 def : ProcessorModel<"kryo", KryoModel, [ProcKryo]>;
 388 // Cavium ThunderX/ThunderX T8X  Processors
 389 def : ProcessorModel<"thunderx", ThunderXT8XModel,  [ProcThunderX]>;
 390 def : ProcessorModel<"thunderxt88", ThunderXT8XModel,  [ProcThunderXT88]>;
 391 def : ProcessorModel<"thunderxt81", ThunderXT8XModel,  [ProcThunderXT81]>;
 392 def : ProcessorModel<"thunderxt83", ThunderXT8XModel,  [ProcThunderXT83]>;
 393 // Cavium ThunderX2T9X  Processors. Formerly Broadcom Vulcan.
 394 def : ProcessorModel<"thunderx2t99", ThunderX2T99Model, [ProcThunderX2T99]>;
 395
 396 //===----------------------------------------------------------------------===//
 397 // Assembly parser
 398 //===----------------------------------------------------------------------===//
 399
 400 def GenericAsmParserVariant : AsmParserVariant {
 401   int Variant = 0;
 402   string Name = "generic";
 403   string BreakCharacters = ".";
 404 }
 405
 406 def AppleAsmParserVariant : AsmParserVariant {
 407   int Variant = 1;
 408   string Name = "apple-neon";
 409   string BreakCharacters = ".";
 410 }
 411
 412 //===----------------------------------------------------------------------===//
 413 // Assembly printer
 414 //===----------------------------------------------------------------------===//
 415 // AArch64 Uses the MC printer for asm output, so make sure the TableGen
 416 // AsmWriter bits get associated with the correct class.
 417 def GenericAsmWriter : AsmWriter {
 418   string AsmWriterClassName  = "InstPrinter";
 419   int PassSubtarget = 1;
 420   int Variant = 0;
 421   bit isMCAsmWriter = 1;
 422 }
 423
 424 def AppleAsmWriter : AsmWriter {
 425   let AsmWriterClassName = "AppleInstPrinter";
 426   int PassSubtarget = 1;
 427   int Variant = 1;
 428   int isMCAsmWriter = 1;
 429 }
 430
 431 //===----------------------------------------------------------------------===//
 432 // Target Declaration
 433 //===----------------------------------------------------------------------===//
 434
 435 def AArch64 : Target {
 436   let InstructionSet = AArch64InstrInfo;
 437   let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
 438   let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];
 439 }