1 //=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // Target-independent interfaces which we are implementing.
15 //===----------------------------------------------------------------------===//
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // AArch64 Subtarget features.
23 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
26 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
27 "Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
29 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
30 "Enable cryptographic instructions", [FeatureNEON]>;
32 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
33 "Enable ARMv8 CRC-32 checksum instructions">;
35 def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
36 "Enable ARMv8 Reliability, Availability and Serviceability Extensions">;
38 def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true",
39 "Enable ARMv8.1 Large System Extension (LSE) atomic instructions">;
41 def FeatureRDM : SubtargetFeature<"rdm", "HasRDM", "true",
42 "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions">;
44 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
45 "Enable ARMv8 PMUv3 Performance Monitors extension">;
47 def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
48 "Full FP16", [FeatureFPARMv8]>;
50 def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true",
51 "Enable Statistical Profiling extension">;
53 def FeatureSVE : SubtargetFeature<"sve", "HasSVE", "true",
54 "Enable Scalable Vector Extension (SVE) instructions">;
56 /// Cyclone has register move instructions which are "free".
57 def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
58 "Has zero-cycle register moves">;
60 /// Cyclone has instructions which zero registers for "free".
61 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
62 "Has zero-cycle zeroing instructions">;
64 def FeatureStrictAlign : SubtargetFeature<"strict-align",
65 "StrictAlign", "true",
66 "Disallow all unaligned memory "
69 def FeatureReserveX18 : SubtargetFeature<"reserve-x18", "ReserveX18", "true",
70 "Reserve X18, making it unavailable "
73 def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",
74 "Use alias analysis during codegen">;
76 def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps",
78 "balance mix of odd and even D-registers for fp multiply(-accumulate) ops">;
80 def FeaturePredictableSelectIsExpensive : SubtargetFeature<
81 "predictable-select-expensive", "PredictableSelectIsExpensive", "true",
82 "Prefer likely predicted branches over selects">;
84 def FeatureCustomCheapAsMoveHandling : SubtargetFeature<"custom-cheap-as-move",
85 "CustomAsCheapAsMove", "true",
86 "Use custom code for TargetInstrInfo::isAsCheapAsAMove()">;
88 def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
89 "UsePostRAScheduler", "true", "Schedule again after register allocation">;
91 def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store",
92 "Misaligned128StoreIsSlow", "true", "Misaligned 128 bit stores are slow">;
94 def FeatureSlowPaired128 : SubtargetFeature<"slow-paired-128",
95 "Paired128IsSlow", "true", "Paired 128 bit loads and stores are slow">;
97 def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature<
98 "alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern",
99 "true", "Use alternative pattern for sextload convert to f32">;
101 def FeatureArithmeticBccFusion : SubtargetFeature<
102 "arith-bcc-fusion", "HasArithmeticBccFusion", "true",
103 "CPU fuses arithmetic+bcc operations">;
105 def FeatureArithmeticCbzFusion : SubtargetFeature<
106 "arith-cbz-fusion", "HasArithmeticCbzFusion", "true",
107 "CPU fuses arithmetic + cbz/cbnz operations">;
109 def FeatureFuseAES : SubtargetFeature<
110 "fuse-aes", "HasFuseAES", "true",
111 "CPU fuses AES crypto operations">;
113 def FeatureFuseLiterals : SubtargetFeature<
114 "fuse-literals", "HasFuseLiterals", "true",
115 "CPU fuses literal generation operations">;
117 def FeatureDisableLatencySchedHeuristic : SubtargetFeature<
118 "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",
119 "Disable latency scheduling heuristic">;
121 def FeatureUseRSqrt : SubtargetFeature<
122 "use-reciprocal-square-root", "UseRSqrt", "true",
123 "Use the reciprocal square root approximation">;
125 def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates",
126 "NegativeImmediates", "false",
127 "Convert immediates and instructions "
128 "to their negated or complemented "
129 "equivalent when the immediate does "
130 "not fit in the encoding.">;
132 def FeatureLSLFast : SubtargetFeature<
133 "lsl-fast", "HasLSLFast", "true",
134 "CPU has a fastpath logical shift of up to 3 places">;
135 //===----------------------------------------------------------------------===//
139 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
140 "Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE, FeatureRDM]>;
142 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
143 "Support ARM v8.2a instructions", [HasV8_1aOps, FeatureRAS]>;
145 //===----------------------------------------------------------------------===//
146 // Register File Description
147 //===----------------------------------------------------------------------===//
149 include "AArch64RegisterInfo.td"
150 include "AArch64RegisterBanks.td"
151 include "AArch64CallingConvention.td"
153 //===----------------------------------------------------------------------===//
154 // Instruction Descriptions
155 //===----------------------------------------------------------------------===//
157 include "AArch64Schedule.td"
158 include "AArch64InstrInfo.td"
160 def AArch64InstrInfo : InstrInfo;
162 //===----------------------------------------------------------------------===//
163 // Named operands for MRS/MSR/TLBI/...
164 //===----------------------------------------------------------------------===//
166 include "AArch64SystemOperands.td"
168 //===----------------------------------------------------------------------===//
169 // AArch64 Processors supported.
171 include "AArch64SchedA53.td"
172 include "AArch64SchedA57.td"
173 include "AArch64SchedCyclone.td"
174 include "AArch64SchedFalkor.td"
175 include "AArch64SchedKryo.td"
176 include "AArch64SchedM1.td"
177 include "AArch64SchedThunderX.td"
178 include "AArch64SchedThunderX2T99.td"
180 def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
181 "Cortex-A35 ARM processors", [
189 def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
190 "Cortex-A53 ARM processors", [
194 FeatureCustomCheapAsMoveHandling,
199 FeaturePostRAScheduler,
203 def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
204 "Cortex-A57 ARM processors", [
208 FeatureCustomCheapAsMoveHandling,
214 FeaturePostRAScheduler,
215 FeaturePredictableSelectIsExpensive
218 def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
219 "Cortex-A72 ARM processors", [
228 def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
229 "Cortex-A73 ARM processors", [
238 def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
240 FeatureAlternateSExtLoadCVTF32Pattern,
242 FeatureDisableLatencySchedHeuristic,
244 FeatureArithmeticBccFusion,
245 FeatureArithmeticCbzFusion,
248 FeatureSlowMisaligned128Store,
253 def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1",
254 "Samsung Exynos-M1 processors",
255 [FeatureSlowPaired128,
258 FeatureCustomCheapAsMoveHandling,
263 FeaturePostRAScheduler,
264 FeatureSlowMisaligned128Store,
268 def ProcExynosM2 : SubtargetFeature<"exynosm2", "ARMProcFamily", "ExynosM1",
269 "Samsung Exynos-M2/M3 processors",
270 [FeatureSlowPaired128,
273 FeatureCustomCheapAsMoveHandling,
278 FeaturePostRAScheduler,
279 FeatureSlowMisaligned128Store,
282 def ProcKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",
283 "Qualcomm Kryo processors", [
286 FeatureCustomCheapAsMoveHandling,
290 FeaturePostRAScheduler,
291 FeaturePredictableSelectIsExpensive,
296 def ProcFalkor : SubtargetFeature<"falkor", "ARMProcFamily", "Falkor",
297 "Qualcomm Falkor processors", [
300 FeatureCustomCheapAsMoveHandling,
304 FeaturePostRAScheduler,
305 FeaturePredictableSelectIsExpensive,
311 def ProcThunderX2T99 : SubtargetFeature<"thunderx2t99", "ARMProcFamily",
313 "Cavium ThunderX2 processors", [
317 FeatureArithmeticBccFusion,
319 FeaturePostRAScheduler,
320 FeaturePredictableSelectIsExpensive,
324 def ProcThunderX : SubtargetFeature<"thunderx", "ARMProcFamily", "ThunderX",
325 "Cavium ThunderX processors", [
330 FeaturePostRAScheduler,
331 FeaturePredictableSelectIsExpensive,
334 def ProcThunderXT88 : SubtargetFeature<"thunderxt88", "ARMProcFamily",
336 "Cavium ThunderX processors", [
341 FeaturePostRAScheduler,
342 FeaturePredictableSelectIsExpensive,
345 def ProcThunderXT81 : SubtargetFeature<"thunderxt81", "ARMProcFamily",
347 "Cavium ThunderX processors", [
352 FeaturePostRAScheduler,
353 FeaturePredictableSelectIsExpensive,
356 def ProcThunderXT83 : SubtargetFeature<"thunderxt83", "ARMProcFamily",
358 "Cavium ThunderX processors", [
363 FeaturePostRAScheduler,
364 FeaturePredictableSelectIsExpensive,
367 def : ProcessorModel<"generic", NoSchedModel, [
372 FeaturePostRAScheduler
375 // FIXME: Cortex-A35 is currently modeled as a Cortex-A53.
376 def : ProcessorModel<"cortex-a35", CortexA53Model, [ProcA35]>;
377 def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
378 def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
379 // FIXME: Cortex-A72 and Cortex-A73 are currently modeled as a Cortex-A57.
380 def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA72]>;
381 def : ProcessorModel<"cortex-a73", CortexA57Model, [ProcA73]>;
382 def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
383 def : ProcessorModel<"exynos-m1", ExynosM1Model, [ProcExynosM1]>;
384 def : ProcessorModel<"exynos-m2", ExynosM1Model, [ProcExynosM2]>;
385 def : ProcessorModel<"exynos-m3", ExynosM1Model, [ProcExynosM2]>;
386 def : ProcessorModel<"falkor", FalkorModel, [ProcFalkor]>;
387 def : ProcessorModel<"kryo", KryoModel, [ProcKryo]>;
388 // Cavium ThunderX/ThunderX T8X Processors
389 def : ProcessorModel<"thunderx", ThunderXT8XModel, [ProcThunderX]>;
390 def : ProcessorModel<"thunderxt88", ThunderXT8XModel, [ProcThunderXT88]>;
391 def : ProcessorModel<"thunderxt81", ThunderXT8XModel, [ProcThunderXT81]>;
392 def : ProcessorModel<"thunderxt83", ThunderXT8XModel, [ProcThunderXT83]>;
393 // Cavium ThunderX2T9X Processors. Formerly Broadcom Vulcan.
394 def : ProcessorModel<"thunderx2t99", ThunderX2T99Model, [ProcThunderX2T99]>;
396 //===----------------------------------------------------------------------===//
398 //===----------------------------------------------------------------------===//
400 def GenericAsmParserVariant : AsmParserVariant {
402 string Name = "generic";
403 string BreakCharacters = ".";
406 def AppleAsmParserVariant : AsmParserVariant {
408 string Name = "apple-neon";
409 string BreakCharacters = ".";
412 //===----------------------------------------------------------------------===//
414 //===----------------------------------------------------------------------===//
415 // AArch64 Uses the MC printer for asm output, so make sure the TableGen
416 // AsmWriter bits get associated with the correct class.
417 def GenericAsmWriter : AsmWriter {
418 string AsmWriterClassName = "InstPrinter";
419 int PassSubtarget = 1;
421 bit isMCAsmWriter = 1;
424 def AppleAsmWriter : AsmWriter {
425 let AsmWriterClassName = "AppleInstPrinter";
426 int PassSubtarget = 1;
428 int isMCAsmWriter = 1;
431 //===----------------------------------------------------------------------===//
432 // Target Declaration
433 //===----------------------------------------------------------------------===//
435 def AArch64 : Target {
436 let InstructionSet = AArch64InstrInfo;
437 let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
438 let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];