1 //=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // Target-independent interfaces which we are implementing.
15 //===----------------------------------------------------------------------===//
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // AArch64 Subtarget features.
23 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
26 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
27 "Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
29 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
30 "Enable cryptographic instructions", [FeatureNEON]>;
32 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
33 "Enable ARMv8 CRC-32 checksum instructions">;
35 def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
36 "Enable ARMv8 Reliability, Availability and Serviceability Extensions">;
38 def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true",
39 "Enable ARMv8.1 Large System Extension (LSE) atomic instructions">;
41 def FeatureRDM : SubtargetFeature<"rdm", "HasRDM", "true",
42 "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions">;
44 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
45 "Enable ARMv8 PMUv3 Performance Monitors extension">;
47 def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
48 "Full FP16", [FeatureFPARMv8]>;
50 def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true",
51 "Enable Statistical Profiling extension">;
53 /// Cyclone has register move instructions which are "free".
54 def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
55 "Has zero-cycle register moves">;
57 /// Cyclone has instructions which zero registers for "free".
58 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
59 "Has zero-cycle zeroing instructions">;
61 def FeatureStrictAlign : SubtargetFeature<"strict-align",
62 "StrictAlign", "true",
63 "Disallow all unaligned memory "
66 def FeatureReserveX18 : SubtargetFeature<"reserve-x18", "ReserveX18", "true",
67 "Reserve X18, making it unavailable "
70 def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",
71 "Use alias analysis during codegen">;
73 def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps",
75 "balance mix of odd and even D-registers for fp multiply(-accumulate) ops">;
77 def FeaturePredictableSelectIsExpensive : SubtargetFeature<
78 "predictable-select-expensive", "PredictableSelectIsExpensive", "true",
79 "Prefer likely predicted branches over selects">;
81 def FeatureCustomCheapAsMoveHandling : SubtargetFeature<"custom-cheap-as-move",
82 "CustomAsCheapAsMove", "true",
83 "Use custom code for TargetInstrInfo::isAsCheapAsAMove()">;
85 def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
86 "UsePostRAScheduler", "true", "Schedule again after register allocation">;
88 def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store",
89 "Misaligned128StoreIsSlow", "true", "Misaligned 128 bit stores are slow">;
91 def FeatureSlowPaired128 : SubtargetFeature<"slow-paired-128",
92 "Paired128IsSlow", "true", "Paired 128 bit loads and stores are slow">;
94 def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature<
95 "alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern",
96 "true", "Use alternative pattern for sextload convert to f32">;
98 def FeatureArithmeticBccFusion : SubtargetFeature<
99 "arith-bcc-fusion", "HasArithmeticBccFusion", "true",
100 "CPU fuses arithmetic+bcc operations">;
102 def FeatureArithmeticCbzFusion : SubtargetFeature<
103 "arith-cbz-fusion", "HasArithmeticCbzFusion", "true",
104 "CPU fuses arithmetic + cbz/cbnz operations">;
106 def FeatureFuseAES : SubtargetFeature<
107 "fuse-aes", "HasFuseAES", "true",
108 "CPU fuses AES crypto operations">;
110 def FeatureFuseLiterals : SubtargetFeature<
111 "fuse-literals", "HasFuseLiterals", "true",
112 "CPU fuses literal generation operations">;
114 def FeatureDisableLatencySchedHeuristic : SubtargetFeature<
115 "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",
116 "Disable latency scheduling heuristic">;
118 def FeatureUseRSqrt : SubtargetFeature<
119 "use-reciprocal-square-root", "UseRSqrt", "true",
120 "Use the reciprocal square root approximation">;
122 def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates",
123 "NegativeImmediates", "false",
124 "Convert immediates and instructions "
125 "to their negated or complemented "
126 "equivalent when the immediate does "
127 "not fit in the encoding.">;
129 def FeatureLSLFast : SubtargetFeature<
130 "lsl-fast", "HasLSLFast", "true",
131 "CPU has a fastpath logical shift of up to 3 places">;
132 //===----------------------------------------------------------------------===//
136 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
137 "Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE, FeatureRDM]>;
139 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
140 "Support ARM v8.2a instructions", [HasV8_1aOps, FeatureRAS]>;
142 //===----------------------------------------------------------------------===//
143 // Register File Description
144 //===----------------------------------------------------------------------===//
146 include "AArch64RegisterInfo.td"
147 include "AArch64RegisterBanks.td"
148 include "AArch64CallingConvention.td"
150 //===----------------------------------------------------------------------===//
151 // Instruction Descriptions
152 //===----------------------------------------------------------------------===//
154 include "AArch64Schedule.td"
155 include "AArch64InstrInfo.td"
157 def AArch64InstrInfo : InstrInfo;
159 //===----------------------------------------------------------------------===//
160 // Named operands for MRS/MSR/TLBI/...
161 //===----------------------------------------------------------------------===//
163 include "AArch64SystemOperands.td"
165 //===----------------------------------------------------------------------===//
166 // AArch64 Processors supported.
168 include "AArch64SchedA53.td"
169 include "AArch64SchedA57.td"
170 include "AArch64SchedCyclone.td"
171 include "AArch64SchedFalkor.td"
172 include "AArch64SchedKryo.td"
173 include "AArch64SchedM1.td"
174 include "AArch64SchedThunderX.td"
175 include "AArch64SchedThunderX2T99.td"
177 def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
178 "Cortex-A35 ARM processors", [
186 def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
187 "Cortex-A53 ARM processors", [
191 FeatureCustomCheapAsMoveHandling,
195 FeaturePostRAScheduler,
199 def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
200 "Cortex-A57 ARM processors", [
204 FeatureCustomCheapAsMoveHandling,
210 FeaturePostRAScheduler,
211 FeaturePredictableSelectIsExpensive
214 def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
215 "Cortex-A72 ARM processors", [
223 def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
224 "Cortex-A73 ARM processors", [
232 def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
234 FeatureAlternateSExtLoadCVTF32Pattern,
236 FeatureDisableLatencySchedHeuristic,
238 FeatureArithmeticBccFusion,
239 FeatureArithmeticCbzFusion,
242 FeatureSlowMisaligned128Store,
247 def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1",
248 "Samsung Exynos-M1 processors",
249 [FeatureSlowPaired128,
252 FeatureCustomCheapAsMoveHandling,
257 FeaturePostRAScheduler,
258 FeatureSlowMisaligned128Store,
262 def ProcExynosM2 : SubtargetFeature<"exynosm2", "ARMProcFamily", "ExynosM1",
263 "Samsung Exynos-M2/M3 processors",
264 [FeatureSlowPaired128,
267 FeatureCustomCheapAsMoveHandling,
271 FeaturePostRAScheduler,
272 FeatureSlowMisaligned128Store,
275 def ProcKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",
276 "Qualcomm Kryo processors", [
279 FeatureCustomCheapAsMoveHandling,
283 FeaturePostRAScheduler,
284 FeaturePredictableSelectIsExpensive,
289 def ProcFalkor : SubtargetFeature<"falkor", "ARMProcFamily", "Falkor",
290 "Qualcomm Falkor processors", [
293 FeatureCustomCheapAsMoveHandling,
297 FeaturePostRAScheduler,
298 FeaturePredictableSelectIsExpensive,
304 def ProcThunderX2T99 : SubtargetFeature<"thunderx2t99", "ARMProcFamily",
306 "Cavium ThunderX2 processors", [
310 FeatureArithmeticBccFusion,
312 FeaturePostRAScheduler,
313 FeaturePredictableSelectIsExpensive,
317 def ProcThunderX : SubtargetFeature<"thunderx", "ARMProcFamily", "ThunderX",
318 "Cavium ThunderX processors", [
323 FeaturePostRAScheduler,
324 FeaturePredictableSelectIsExpensive,
327 def ProcThunderXT88 : SubtargetFeature<"thunderxt88", "ARMProcFamily",
329 "Cavium ThunderX processors", [
334 FeaturePostRAScheduler,
335 FeaturePredictableSelectIsExpensive,
338 def ProcThunderXT81 : SubtargetFeature<"thunderxt81", "ARMProcFamily",
340 "Cavium ThunderX processors", [
345 FeaturePostRAScheduler,
346 FeaturePredictableSelectIsExpensive,
349 def ProcThunderXT83 : SubtargetFeature<"thunderxt83", "ARMProcFamily",
351 "Cavium ThunderX processors", [
356 FeaturePostRAScheduler,
357 FeaturePredictableSelectIsExpensive,
360 def : ProcessorModel<"generic", NoSchedModel, [
364 FeaturePostRAScheduler
367 // FIXME: Cortex-A35 is currently modeled as a Cortex-A53.
368 def : ProcessorModel<"cortex-a35", CortexA53Model, [ProcA35]>;
369 def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
370 def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
371 // FIXME: Cortex-A72 and Cortex-A73 are currently modeled as a Cortex-A57.
372 def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA72]>;
373 def : ProcessorModel<"cortex-a73", CortexA57Model, [ProcA73]>;
374 def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
375 def : ProcessorModel<"exynos-m1", ExynosM1Model, [ProcExynosM1]>;
376 def : ProcessorModel<"exynos-m2", ExynosM1Model, [ProcExynosM2]>;
377 def : ProcessorModel<"exynos-m3", ExynosM1Model, [ProcExynosM2]>;
378 def : ProcessorModel<"falkor", FalkorModel, [ProcFalkor]>;
379 def : ProcessorModel<"kryo", KryoModel, [ProcKryo]>;
380 // Cavium ThunderX/ThunderX T8X Processors
381 def : ProcessorModel<"thunderx", ThunderXT8XModel, [ProcThunderX]>;
382 def : ProcessorModel<"thunderxt88", ThunderXT8XModel, [ProcThunderXT88]>;
383 def : ProcessorModel<"thunderxt81", ThunderXT8XModel, [ProcThunderXT81]>;
384 def : ProcessorModel<"thunderxt83", ThunderXT8XModel, [ProcThunderXT83]>;
385 // Cavium ThunderX2T9X Processors. Formerly Broadcom Vulcan.
386 def : ProcessorModel<"thunderx2t99", ThunderX2T99Model, [ProcThunderX2T99]>;
388 //===----------------------------------------------------------------------===//
390 //===----------------------------------------------------------------------===//
392 def GenericAsmParserVariant : AsmParserVariant {
394 string Name = "generic";
395 string BreakCharacters = ".";
398 def AppleAsmParserVariant : AsmParserVariant {
400 string Name = "apple-neon";
401 string BreakCharacters = ".";
404 //===----------------------------------------------------------------------===//
406 //===----------------------------------------------------------------------===//
407 // AArch64 Uses the MC printer for asm output, so make sure the TableGen
408 // AsmWriter bits get associated with the correct class.
409 def GenericAsmWriter : AsmWriter {
410 string AsmWriterClassName = "InstPrinter";
411 int PassSubtarget = 1;
413 bit isMCAsmWriter = 1;
416 def AppleAsmWriter : AsmWriter {
417 let AsmWriterClassName = "AppleInstPrinter";
418 int PassSubtarget = 1;
420 int isMCAsmWriter = 1;
423 //===----------------------------------------------------------------------===//
424 // Target Declaration
425 //===----------------------------------------------------------------------===//
427 def AArch64 : Target {
428 let InstructionSet = AArch64InstrInfo;
429 let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
430 let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];