1 //===-- AArch64A53Fix835769.cpp -------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This pass changes code to work around Cortex-A53 erratum 835769.
10 // It works around it by inserting a nop instruction in code sequences that
11 // in some circumstances may trigger the erratum.
12 // It inserts a nop instruction between a sequence of the following 2 classes
14 // instr 1: mem-instr (including loads, stores and prefetches).
15 // instr 2: non-SIMD integer multiply-accumulate writing 64-bit X registers.
16 //===----------------------------------------------------------------------===//
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineFunctionPass.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/TargetInstrInfo.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/raw_ostream.h"
31 #define DEBUG_TYPE "aarch64-fix-cortex-a53-835769"
33 STATISTIC(NumNopsAdded, "Number of Nops added to work around erratum 835769");
35 //===----------------------------------------------------------------------===//
38 // Is the instruction a match for the instruction that comes first in the
39 // sequence of instructions that can trigger the erratum?
40 static bool isFirstInstructionInSequence(MachineInstr *MI) {
41 // Must return true if this instruction is a load, a store or a prefetch.
42 switch (MI->getOpcode()) {
44 case AArch64::PRFMroW:
45 case AArch64::PRFMroX:
50 return MI->mayLoadOrStore();
54 // Is the instruction a match for the instruction that comes second in the
55 // sequence that can trigger the erratum?
56 static bool isSecondInstructionInSequence(MachineInstr *MI) {
57 // Must return true for non-SIMD integer multiply-accumulates, writing
58 // to a 64-bit register.
59 switch (MI->getOpcode()) {
60 // Erratum cannot be triggered when the destination register is 32 bits,
61 // therefore only include the following.
62 case AArch64::MSUBXrrr:
63 case AArch64::MADDXrrr:
64 case AArch64::SMADDLrrr:
65 case AArch64::SMSUBLrrr:
66 case AArch64::UMADDLrrr:
67 case AArch64::UMSUBLrrr:
68 // Erratum can only be triggered by multiply-adds, not by regular
69 // non-accumulating multiplies, i.e. when Ra=XZR='11111'
70 return MI->getOperand(3).getReg() != AArch64::XZR;
77 //===----------------------------------------------------------------------===//
80 class AArch64A53Fix835769 : public MachineFunctionPass {
81 const TargetInstrInfo *TII;
85 explicit AArch64A53Fix835769() : MachineFunctionPass(ID) {
86 initializeAArch64A53Fix835769Pass(*PassRegistry::getPassRegistry());
89 bool runOnMachineFunction(MachineFunction &F) override;
91 MachineFunctionProperties getRequiredProperties() const override {
92 return MachineFunctionProperties().set(
93 MachineFunctionProperties::Property::NoVRegs);
96 StringRef getPassName() const override {
97 return "Workaround A53 erratum 835769 pass";
100 void getAnalysisUsage(AnalysisUsage &AU) const override {
101 AU.setPreservesCFG();
102 MachineFunctionPass::getAnalysisUsage(AU);
106 bool runOnBasicBlock(MachineBasicBlock &MBB);
108 char AArch64A53Fix835769::ID = 0;
110 } // end anonymous namespace
112 INITIALIZE_PASS(AArch64A53Fix835769, "aarch64-fix-cortex-a53-835769-pass",
113 "AArch64 fix for A53 erratum 835769", false, false)
115 //===----------------------------------------------------------------------===//
118 AArch64A53Fix835769::runOnMachineFunction(MachineFunction &F) {
119 DEBUG(dbgs() << "***** AArch64A53Fix835769 *****\n");
120 bool Changed = false;
121 TII = F.getSubtarget().getInstrInfo();
123 for (auto &MBB : F) {
124 Changed |= runOnBasicBlock(MBB);
129 // Return the block that was fallen through to get to MBB, if any,
130 // otherwise nullptr.
131 static MachineBasicBlock *getBBFallenThrough(MachineBasicBlock *MBB,
132 const TargetInstrInfo *TII) {
133 // Get the previous machine basic block in the function.
134 MachineFunction::iterator MBBI(MBB);
136 // Can't go off top of function.
137 if (MBBI == MBB->getParent()->begin())
140 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
141 SmallVector<MachineOperand, 2> Cond;
143 MachineBasicBlock *PrevBB = &*std::prev(MBBI);
144 for (MachineBasicBlock *S : MBB->predecessors())
145 if (S == PrevBB && !TII->analyzeBranch(*PrevBB, TBB, FBB, Cond) && !TBB &&
152 // Iterate through fallen through blocks trying to find a previous non-pseudo if
153 // there is one, otherwise return nullptr. Only look for instructions in
154 // previous blocks, not the current block, since we only use this to look at
156 static MachineInstr *getLastNonPseudo(MachineBasicBlock &MBB,
157 const TargetInstrInfo *TII) {
158 MachineBasicBlock *FMBB = &MBB;
160 // If there is no non-pseudo in the current block, loop back around and try
161 // the previous block (if there is one).
162 while ((FMBB = getBBFallenThrough(FMBB, TII))) {
163 for (MachineInstr &I : make_range(FMBB->rbegin(), FMBB->rend()))
168 // There was no previous non-pseudo in the fallen through blocks
172 static void insertNopBeforeInstruction(MachineBasicBlock &MBB, MachineInstr* MI,
173 const TargetInstrInfo *TII) {
174 // If we are the first instruction of the block, put the NOP at the end of
175 // the previous fallthrough block
176 if (MI == &MBB.front()) {
177 MachineInstr *I = getLastNonPseudo(MBB, TII);
178 assert(I && "Expected instruction");
179 DebugLoc DL = I->getDebugLoc();
180 BuildMI(I->getParent(), DL, TII->get(AArch64::HINT)).addImm(0);
183 DebugLoc DL = MI->getDebugLoc();
184 BuildMI(MBB, MI, DL, TII->get(AArch64::HINT)).addImm(0);
191 AArch64A53Fix835769::runOnBasicBlock(MachineBasicBlock &MBB) {
192 bool Changed = false;
193 DEBUG(dbgs() << "Running on MBB: " << MBB << " - scanning instructions...\n");
195 // First, scan the basic block, looking for a sequence of 2 instructions
196 // that match the conditions under which the erratum may trigger.
198 // List of terminating instructions in matching sequences
199 std::vector<MachineInstr*> Sequences;
201 MachineInstr *PrevInstr = nullptr;
203 // Try and find the last non-pseudo instruction in any fallen through blocks,
204 // if there isn't one, then we use nullptr to represent that.
205 PrevInstr = getLastNonPseudo(MBB, TII);
207 for (auto &MI : MBB) {
208 MachineInstr *CurrInstr = &MI;
209 DEBUG(dbgs() << " Examining: " << MI);
211 DEBUG(dbgs() << " PrevInstr: " << *PrevInstr
212 << " CurrInstr: " << *CurrInstr
213 << " isFirstInstructionInSequence(PrevInstr): "
214 << isFirstInstructionInSequence(PrevInstr) << "\n"
215 << " isSecondInstructionInSequence(CurrInstr): "
216 << isSecondInstructionInSequence(CurrInstr) << "\n");
217 if (isFirstInstructionInSequence(PrevInstr) &&
218 isSecondInstructionInSequence(CurrInstr)) {
219 DEBUG(dbgs() << " ** pattern found at Idx " << Idx << "!\n");
220 Sequences.push_back(CurrInstr);
223 if (!CurrInstr->isPseudo())
224 PrevInstr = CurrInstr;
228 DEBUG(dbgs() << "Scan complete, " << Sequences.size()
229 << " occurrences of pattern found.\n");
231 // Then update the basic block, inserting nops between the detected sequences.
232 for (auto &MI : Sequences) {
234 insertNopBeforeInstruction(MBB, MI, TII);
240 // Factory function used by AArch64TargetMachine to add the pass to
242 FunctionPass *llvm::createAArch64A53Fix835769() {
243 return new AArch64A53Fix835769();