1 //===-- AArch64A57FPLoadBalancing.cpp - Balance FP ops statically on A57---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // For best-case performance on Cortex-A57, we should try to use a balanced
10 // mix of odd and even D-registers when performing a critical sequence of
11 // independent, non-quadword FP/ASIMD floating-point multiply or
12 // multiply-accumulate operations.
14 // This pass attempts to detect situations where the register allocation may
15 // adversely affect this load balancing and to change the registers used so as
16 // to better utilize the CPU.
18 // Ideally we'd just take each multiply or multiply-accumulate in turn and
19 // allocate it alternating even or odd registers. However, multiply-accumulates
20 // are most efficiently performed in the same functional unit as their
21 // accumulation operand. Therefore this pass tries to find maximal sequences
22 // ("Chains") of multiply-accumulates linked via their accumulation operand,
23 // and assign them all the same "color" (oddness/evenness).
25 // This optimization affects S-register and D-register floating point
26 // multiplies and FMADD/FMAs, as well as vector (floating point only) muls and
27 // FMADD/FMA. Q register instructions (and 128-bit vector instructions) are
29 //===----------------------------------------------------------------------===//
32 #include "AArch64InstrInfo.h"
33 #include "AArch64Subtarget.h"
34 #include "llvm/ADT/BitVector.h"
35 #include "llvm/ADT/EquivalenceClasses.h"
36 #include "llvm/CodeGen/MachineFunction.h"
37 #include "llvm/CodeGen/MachineFunctionPass.h"
38 #include "llvm/CodeGen/MachineInstr.h"
39 #include "llvm/CodeGen/MachineInstrBuilder.h"
40 #include "llvm/CodeGen/MachineRegisterInfo.h"
41 #include "llvm/CodeGen/RegisterClassInfo.h"
42 #include "llvm/CodeGen/RegisterScavenging.h"
43 #include "llvm/Support/CommandLine.h"
44 #include "llvm/Support/Debug.h"
45 #include "llvm/Support/raw_ostream.h"
48 #define DEBUG_TYPE "aarch64-a57-fp-load-balancing"
50 // Enforce the algorithm to use the scavenged register even when the original
51 // destination register is the correct color. Used for testing.
53 TransformAll("aarch64-a57-fp-load-balancing-force-all",
54 cl::desc("Always modify dest registers regardless of color"),
55 cl::init(false), cl::Hidden);
57 // Never use the balance information obtained from chains - return a specific
58 // color always. Used for testing.
59 static cl::opt<unsigned>
60 OverrideBalance("aarch64-a57-fp-load-balancing-override",
61 cl::desc("Ignore balance information, always return "
62 "(1: Even, 2: Odd)."),
63 cl::init(0), cl::Hidden);
65 //===----------------------------------------------------------------------===//
68 // Is the instruction a type of multiply on 64-bit (or 32-bit) FPRs?
69 static bool isMul(MachineInstr *MI) {
70 switch (MI->getOpcode()) {
71 case AArch64::FMULSrr:
72 case AArch64::FNMULSrr:
73 case AArch64::FMULDrr:
74 case AArch64::FNMULDrr:
81 // Is the instruction a type of FP multiply-accumulate on 64-bit (or 32-bit) FPRs?
82 static bool isMla(MachineInstr *MI) {
83 switch (MI->getOpcode()) {
84 case AArch64::FMSUBSrrr:
85 case AArch64::FMADDSrrr:
86 case AArch64::FNMSUBSrrr:
87 case AArch64::FNMADDSrrr:
88 case AArch64::FMSUBDrrr:
89 case AArch64::FMADDDrrr:
90 case AArch64::FNMSUBDrrr:
91 case AArch64::FNMADDDrrr:
98 //===----------------------------------------------------------------------===//
101 /// A "color", which is either even or odd. Yes, these aren't really colors
102 /// but the algorithm is conceptually doing two-color graph coloring.
103 enum class Color { Even, Odd };
105 static const char *ColorNames[2] = { "Even", "Odd" };
110 class AArch64A57FPLoadBalancing : public MachineFunctionPass {
111 MachineRegisterInfo *MRI;
112 const TargetRegisterInfo *TRI;
113 RegisterClassInfo RCI;
117 explicit AArch64A57FPLoadBalancing() : MachineFunctionPass(ID) {
118 initializeAArch64A57FPLoadBalancingPass(*PassRegistry::getPassRegistry());
121 bool runOnMachineFunction(MachineFunction &F) override;
123 MachineFunctionProperties getRequiredProperties() const override {
124 return MachineFunctionProperties().set(
125 MachineFunctionProperties::Property::NoVRegs);
128 StringRef getPassName() const override {
129 return "A57 FP Anti-dependency breaker";
132 void getAnalysisUsage(AnalysisUsage &AU) const override {
133 AU.setPreservesCFG();
134 MachineFunctionPass::getAnalysisUsage(AU);
138 bool runOnBasicBlock(MachineBasicBlock &MBB);
139 bool colorChainSet(std::vector<Chain*> GV, MachineBasicBlock &MBB,
141 bool colorChain(Chain *G, Color C, MachineBasicBlock &MBB);
142 int scavengeRegister(Chain *G, Color C, MachineBasicBlock &MBB);
143 void scanInstruction(MachineInstr *MI, unsigned Idx,
144 std::map<unsigned, Chain*> &Active,
145 std::vector<std::unique_ptr<Chain>> &AllChains);
146 void maybeKillChain(MachineOperand &MO, unsigned Idx,
147 std::map<unsigned, Chain*> &RegChains);
148 Color getColor(unsigned Register);
149 Chain *getAndEraseNext(Color PreferredColor, std::vector<Chain*> &L);
153 char AArch64A57FPLoadBalancing::ID = 0;
155 INITIALIZE_PASS_BEGIN(AArch64A57FPLoadBalancing, DEBUG_TYPE,
156 "AArch64 A57 FP Load-Balancing", false, false)
157 INITIALIZE_PASS_END(AArch64A57FPLoadBalancing, DEBUG_TYPE,
158 "AArch64 A57 FP Load-Balancing", false, false)
161 /// A Chain is a sequence of instructions that are linked together by
162 /// an accumulation operand. For example:
165 /// fmla def d1, ?, ?, killed d0
166 /// fmla def d2, ?, ?, killed d1
168 /// There may be other instructions interleaved in the sequence that
169 /// do not belong to the chain. These other instructions must not use
170 /// the "chain" register at any point.
172 /// We currently only support chains where the "chain" operand is killed
173 /// at each link in the chain for simplicity.
174 /// A chain has three important instructions - Start, Last and Kill.
175 /// * The start instruction is the first instruction in the chain.
176 /// * Last is the final instruction in the chain.
177 /// * Kill may or may not be defined. If defined, Kill is the instruction
178 /// where the outgoing value of the Last instruction is killed.
179 /// This information is important as if we know the outgoing value is
180 /// killed with no intervening uses, we can safely change its register.
182 /// Without a kill instruction, we must assume the outgoing value escapes
183 /// beyond our model and either must not change its register or must
184 /// create a fixup FMOV to keep the old register value consistent.
188 /// The important (marker) instructions.
189 MachineInstr *StartInst, *LastInst, *KillInst;
190 /// The index, from the start of the basic block, that each marker
191 /// appears. These are stored so we can do quick interval tests.
192 unsigned StartInstIdx, LastInstIdx, KillInstIdx;
193 /// All instructions in the chain.
194 std::set<MachineInstr*> Insts;
195 /// True if KillInst cannot be modified. If this is true,
196 /// we cannot change LastInst's outgoing register.
197 /// This will be true for tied values and regmasks.
198 bool KillIsImmutable;
199 /// The "color" of LastInst. This will be the preferred chain color,
200 /// as changing intermediate nodes is easy but changing the last
201 /// instruction can be more tricky.
204 Chain(MachineInstr *MI, unsigned Idx, Color C)
205 : StartInst(MI), LastInst(MI), KillInst(nullptr),
206 StartInstIdx(Idx), LastInstIdx(Idx), KillInstIdx(0),
211 /// Add a new instruction into the chain. The instruction's dest operand
212 /// has the given color.
213 void add(MachineInstr *MI, unsigned Idx, Color C) {
217 assert((KillInstIdx == 0 || LastInstIdx < KillInstIdx) &&
218 "Chain: broken invariant. A Chain can only be killed after its last "
224 /// Return true if MI is a member of the chain.
225 bool contains(MachineInstr &MI) { return Insts.count(&MI) > 0; }
227 /// Return the number of instructions in the chain.
228 unsigned size() const {
232 /// Inform the chain that its last active register (the dest register of
233 /// LastInst) is killed by MI with no intervening uses or defs.
234 void setKill(MachineInstr *MI, unsigned Idx, bool Immutable) {
237 KillIsImmutable = Immutable;
238 assert((KillInstIdx == 0 || LastInstIdx < KillInstIdx) &&
239 "Chain: broken invariant. A Chain can only be killed after its last "
243 /// Return the first instruction in the chain.
244 MachineInstr *getStart() const { return StartInst; }
245 /// Return the last instruction in the chain.
246 MachineInstr *getLast() const { return LastInst; }
247 /// Return the "kill" instruction (as set with setKill()) or NULL.
248 MachineInstr *getKill() const { return KillInst; }
249 /// Return an instruction that can be used as an iterator for the end
250 /// of the chain. This is the maximum of KillInst (if set) and LastInst.
251 MachineBasicBlock::iterator end() const {
252 return ++MachineBasicBlock::iterator(KillInst ? KillInst : LastInst);
254 MachineBasicBlock::iterator begin() const { return getStart(); }
256 /// Can the Kill instruction (assuming one exists) be modified?
257 bool isKillImmutable() const { return KillIsImmutable; }
259 /// Return the preferred color of this chain.
260 Color getPreferredColor() {
261 if (OverrideBalance != 0)
262 return OverrideBalance == 1 ? Color::Even : Color::Odd;
266 /// Return true if this chain (StartInst..KillInst) overlaps with Other.
267 bool rangeOverlapsWith(const Chain &Other) const {
268 unsigned End = KillInst ? KillInstIdx : LastInstIdx;
269 unsigned OtherEnd = Other.KillInst ?
270 Other.KillInstIdx : Other.LastInstIdx;
272 return StartInstIdx <= OtherEnd && Other.StartInstIdx <= End;
275 /// Return true if this chain starts before Other.
276 bool startsBefore(const Chain *Other) const {
277 return StartInstIdx < Other->StartInstIdx;
280 /// Return true if the group will require a fixup MOV at the end.
281 bool requiresFixup() const {
282 return (getKill() && isKillImmutable()) || !getKill();
285 /// Return a simple string representation of the chain.
286 std::string str() const {
288 raw_string_ostream OS(S);
291 StartInst->print(OS, /* SkipOpers= */true);
293 LastInst->print(OS, /* SkipOpers= */true);
296 KillInst->print(OS, /* SkipOpers= */true);
306 } // end anonymous namespace
308 //===----------------------------------------------------------------------===//
310 bool AArch64A57FPLoadBalancing::runOnMachineFunction(MachineFunction &F) {
311 if (skipFunction(F.getFunction()))
314 if (!F.getSubtarget<AArch64Subtarget>().balanceFPOps())
317 bool Changed = false;
318 DEBUG(dbgs() << "***** AArch64A57FPLoadBalancing *****\n");
320 MRI = &F.getRegInfo();
321 TRI = F.getRegInfo().getTargetRegisterInfo();
322 RCI.runOnMachineFunction(F);
324 for (auto &MBB : F) {
325 Changed |= runOnBasicBlock(MBB);
331 bool AArch64A57FPLoadBalancing::runOnBasicBlock(MachineBasicBlock &MBB) {
332 bool Changed = false;
333 DEBUG(dbgs() << "Running on MBB: " << MBB << " - scanning instructions...\n");
335 // First, scan the basic block producing a set of chains.
337 // The currently "active" chains - chains that can be added to and haven't
338 // been killed yet. This is keyed by register - all chains can only have one
339 // "link" register between each inst in the chain.
340 std::map<unsigned, Chain*> ActiveChains;
341 std::vector<std::unique_ptr<Chain>> AllChains;
344 scanInstruction(&MI, Idx++, ActiveChains, AllChains);
346 DEBUG(dbgs() << "Scan complete, "<< AllChains.size() << " chains created.\n");
348 // Group the chains into disjoint sets based on their liveness range. This is
349 // a poor-man's version of graph coloring. Ideally we'd create an interference
350 // graph and perform full-on graph coloring on that, but;
351 // (a) That's rather heavyweight for only two colors.
352 // (b) We expect multiple disjoint interference regions - in practice the live
353 // range of chains is quite small and they are clustered between loads
355 EquivalenceClasses<Chain*> EC;
356 for (auto &I : AllChains)
359 for (auto &I : AllChains)
360 for (auto &J : AllChains)
361 if (I != J && I->rangeOverlapsWith(*J))
362 EC.unionSets(I.get(), J.get());
363 DEBUG(dbgs() << "Created " << EC.getNumClasses() << " disjoint sets.\n");
365 // Now we assume that every member of an equivalence class interferes
366 // with every other member of that class, and with no members of other classes.
368 // Convert the EquivalenceClasses to a simpler set of sets.
369 std::vector<std::vector<Chain*> > V;
370 for (auto I = EC.begin(), E = EC.end(); I != E; ++I) {
371 std::vector<Chain*> Cs(EC.member_begin(I), EC.member_end());
372 if (Cs.empty()) continue;
373 V.push_back(std::move(Cs));
376 // Now we have a set of sets, order them by start address so
377 // we can iterate over them sequentially.
378 std::sort(V.begin(), V.end(),
379 [](const std::vector<Chain*> &A,
380 const std::vector<Chain*> &B) {
381 return A.front()->startsBefore(B.front());
384 // As we only have two colors, we can track the global (BB-level) balance of
385 // odds versus evens. We aim to keep this near zero to keep both execution
387 // Positive means we're even-heavy, negative we're odd-heavy.
389 // FIXME: If chains have interdependencies, for example:
392 // We do not model this and may color each one differently, assuming we'll
393 // get ILP when we obviously can't. This hasn't been seen to be a problem
394 // in practice so far, so we simplify the algorithm by ignoring it.
398 Changed |= colorChainSet(std::move(I), MBB, Parity);
403 Chain *AArch64A57FPLoadBalancing::getAndEraseNext(Color PreferredColor,
404 std::vector<Chain*> &L) {
408 // We try and get the best candidate from L to color next, given that our
409 // preferred color is "PreferredColor". L is ordered from larger to smaller
410 // chains. It is beneficial to color the large chains before the small chains,
411 // but if we can't find a chain of the maximum length with the preferred color,
412 // we fuzz the size and look for slightly smaller chains before giving up and
413 // returning a chain that must be recolored.
415 // FIXME: Does this need to be configurable?
416 const unsigned SizeFuzz = 1;
417 unsigned MinSize = L.front()->size() - SizeFuzz;
418 for (auto I = L.begin(), E = L.end(); I != E; ++I) {
419 if ((*I)->size() <= MinSize) {
420 // We've gone past the size limit. Return the previous item.
426 if ((*I)->getPreferredColor() == PreferredColor) {
433 // Bailout case - just return the first item.
434 Chain *Ch = L.front();
439 bool AArch64A57FPLoadBalancing::colorChainSet(std::vector<Chain*> GV,
440 MachineBasicBlock &MBB,
442 bool Changed = false;
443 DEBUG(dbgs() << "colorChainSet(): #sets=" << GV.size() << "\n");
445 // Sort by descending size order so that we allocate the most important
447 // Tie-break equivalent sizes by sorting chains requiring fixups before
448 // those without fixups. The logic here is that we should look at the
449 // chains that we cannot change before we look at those we can,
450 // so the parity counter is updated and we know what color we should
452 // Final tie-break with instruction order so pass output is stable (i.e. not
453 // dependent on malloc'd pointer values).
454 std::sort(GV.begin(), GV.end(), [](const Chain *G1, const Chain *G2) {
455 if (G1->size() != G2->size())
456 return G1->size() > G2->size();
457 if (G1->requiresFixup() != G2->requiresFixup())
458 return G1->requiresFixup() > G2->requiresFixup();
459 // Make sure startsBefore() produces a stable final order.
460 assert((G1 == G2 || (G1->startsBefore(G2) ^ G2->startsBefore(G1))) &&
461 "Starts before not total order!");
462 return G1->startsBefore(G2);
465 Color PreferredColor = Parity < 0 ? Color::Even : Color::Odd;
466 while (Chain *G = getAndEraseNext(PreferredColor, GV)) {
467 // Start off by assuming we'll color to our own preferred color.
468 Color C = PreferredColor;
470 // But if we really don't care, use the chain's preferred color.
471 C = G->getPreferredColor();
473 DEBUG(dbgs() << " - Parity=" << Parity << ", Color="
474 << ColorNames[(int)C] << "\n");
476 // If we'll need a fixup FMOV, don't bother. Testing has shown that this
477 // happens infrequently and when it does it has at least a 50% chance of
478 // slowing code down instead of speeding it up.
479 if (G->requiresFixup() && C != G->getPreferredColor()) {
480 C = G->getPreferredColor();
481 DEBUG(dbgs() << " - " << G->str() << " - not worthwhile changing; "
482 "color remains " << ColorNames[(int)C] << "\n");
485 Changed |= colorChain(G, C, MBB);
487 Parity += (C == Color::Even) ? G->size() : -G->size();
488 PreferredColor = Parity < 0 ? Color::Even : Color::Odd;
494 int AArch64A57FPLoadBalancing::scavengeRegister(Chain *G, Color C,
495 MachineBasicBlock &MBB) {
496 // Can we find an appropriate register that is available throughout the life
497 // of the chain? Simulate liveness backwards until the end of the chain.
498 LiveRegUnits Units(*TRI);
499 Units.addLiveOuts(MBB);
500 MachineBasicBlock::iterator I = MBB.end();
501 MachineBasicBlock::iterator ChainEnd = G->end();
502 while (I != ChainEnd) {
504 Units.stepBackward(*I);
507 // Check which register units are alive throughout the chain.
508 MachineBasicBlock::iterator ChainBegin = G->begin();
509 assert(ChainBegin != ChainEnd && "Chain should contain instructions");
512 Units.accumulate(*I);
513 } while (I != ChainBegin);
515 // Make sure we allocate in-order, to get the cheapest registers first.
516 unsigned RegClassID = ChainBegin->getDesc().OpInfo[0].RegClass;
517 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID));
518 for (auto Reg : Ord) {
519 if (!Units.available(Reg))
521 if (C == getColor(Reg))
528 bool AArch64A57FPLoadBalancing::colorChain(Chain *G, Color C,
529 MachineBasicBlock &MBB) {
530 bool Changed = false;
531 DEBUG(dbgs() << " - colorChain(" << G->str() << ", "
532 << ColorNames[(int)C] << ")\n");
534 // Try and obtain a free register of the right class. Without a register
535 // to play with we cannot continue.
536 int Reg = scavengeRegister(G, C, MBB);
538 DEBUG(dbgs() << "Scavenging (thus coloring) failed!\n");
541 DEBUG(dbgs() << " - Scavenged register: " << printReg(Reg, TRI) << "\n");
543 std::map<unsigned, unsigned> Substs;
544 for (MachineInstr &I : *G) {
545 if (!G->contains(I) && (&I != G->getKill() || G->isKillImmutable()))
548 // I is a member of G, or I is a mutable instruction that kills G.
550 std::vector<unsigned> ToErase;
551 for (auto &U : I.operands()) {
552 if (U.isReg() && U.isUse() && Substs.find(U.getReg()) != Substs.end()) {
553 unsigned OrigReg = U.getReg();
554 U.setReg(Substs[OrigReg]);
556 // Don't erase straight away, because there may be other operands
557 // that also reference this substitution!
558 ToErase.push_back(OrigReg);
559 } else if (U.isRegMask()) {
560 for (auto J : Substs) {
561 if (U.clobbersPhysReg(J.first))
562 ToErase.push_back(J.first);
566 // Now it's safe to remove the substs identified earlier.
567 for (auto J : ToErase)
570 // Only change the def if this isn't the last instruction.
571 if (&I != G->getKill()) {
572 MachineOperand &MO = I.getOperand(0);
574 bool Change = TransformAll || getColor(MO.getReg()) != C;
575 if (G->requiresFixup() && &I == G->getLast())
579 Substs[MO.getReg()] = Reg;
586 assert(Substs.size() == 0 && "No substitutions should be left active!");
589 DEBUG(dbgs() << " - Kill instruction seen.\n");
591 // We didn't have a kill instruction, but we didn't seem to need to change
592 // the destination register anyway.
593 DEBUG(dbgs() << " - Destination register not changed.\n");
598 void AArch64A57FPLoadBalancing::scanInstruction(
599 MachineInstr *MI, unsigned Idx, std::map<unsigned, Chain *> &ActiveChains,
600 std::vector<std::unique_ptr<Chain>> &AllChains) {
601 // Inspect "MI", updating ActiveChains and AllChains.
605 for (auto &I : MI->uses())
606 maybeKillChain(I, Idx, ActiveChains);
607 for (auto &I : MI->defs())
608 maybeKillChain(I, Idx, ActiveChains);
610 // Create a new chain. Multiplies don't require forwarding so can go on any
612 unsigned DestReg = MI->getOperand(0).getReg();
614 DEBUG(dbgs() << "New chain started for register " << printReg(DestReg, TRI)
617 auto G = llvm::make_unique<Chain>(MI, Idx, getColor(DestReg));
618 ActiveChains[DestReg] = G.get();
619 AllChains.push_back(std::move(G));
621 } else if (isMla(MI)) {
623 // It is beneficial to keep MLAs on the same functional unit as their
624 // accumulator operand.
625 unsigned DestReg = MI->getOperand(0).getReg();
626 unsigned AccumReg = MI->getOperand(3).getReg();
628 maybeKillChain(MI->getOperand(1), Idx, ActiveChains);
629 maybeKillChain(MI->getOperand(2), Idx, ActiveChains);
630 if (DestReg != AccumReg)
631 maybeKillChain(MI->getOperand(0), Idx, ActiveChains);
633 if (ActiveChains.find(AccumReg) != ActiveChains.end()) {
634 DEBUG(dbgs() << "Chain found for accumulator register "
635 << printReg(AccumReg, TRI) << " in MI " << *MI);
637 // For simplicity we only chain together sequences of MULs/MLAs where the
638 // accumulator register is killed on each instruction. This means we don't
639 // need to track other uses of the registers we want to rewrite.
641 // FIXME: We could extend to handle the non-kill cases for more coverage.
642 if (MI->getOperand(3).isKill()) {
644 DEBUG(dbgs() << "Instruction was successfully added to chain.\n");
645 ActiveChains[AccumReg]->add(MI, Idx, getColor(DestReg));
646 // Handle cases where the destination is not the same as the accumulator.
647 if (DestReg != AccumReg) {
648 ActiveChains[DestReg] = ActiveChains[AccumReg];
649 ActiveChains.erase(AccumReg);
654 DEBUG(dbgs() << "Cannot add to chain because accumulator operand wasn't "
655 << "marked <kill>!\n");
656 maybeKillChain(MI->getOperand(3), Idx, ActiveChains);
659 DEBUG(dbgs() << "Creating new chain for dest register "
660 << printReg(DestReg, TRI) << "\n");
661 auto G = llvm::make_unique<Chain>(MI, Idx, getColor(DestReg));
662 ActiveChains[DestReg] = G.get();
663 AllChains.push_back(std::move(G));
667 // Non-MUL or MLA instruction. Invalidate any chain in the uses or defs
669 for (auto &I : MI->uses())
670 maybeKillChain(I, Idx, ActiveChains);
671 for (auto &I : MI->defs())
672 maybeKillChain(I, Idx, ActiveChains);
677 void AArch64A57FPLoadBalancing::
678 maybeKillChain(MachineOperand &MO, unsigned Idx,
679 std::map<unsigned, Chain*> &ActiveChains) {
680 // Given an operand and the set of active chains (keyed by register),
681 // determine if a chain should be ended and remove from ActiveChains.
682 MachineInstr *MI = MO.getParent();
686 // If this is a KILL of a current chain, record it.
687 if (MO.isKill() && ActiveChains.find(MO.getReg()) != ActiveChains.end()) {
688 DEBUG(dbgs() << "Kill seen for chain " << printReg(MO.getReg(), TRI)
690 ActiveChains[MO.getReg()]->setKill(MI, Idx, /*Immutable=*/MO.isTied());
692 ActiveChains.erase(MO.getReg());
694 } else if (MO.isRegMask()) {
696 for (auto I = ActiveChains.begin(), E = ActiveChains.end();
698 if (MO.clobbersPhysReg(I->first)) {
699 DEBUG(dbgs() << "Kill (regmask) seen for chain "
700 << printReg(I->first, TRI) << "\n");
701 I->second->setKill(MI, Idx, /*Immutable=*/true);
702 ActiveChains.erase(I++);
710 Color AArch64A57FPLoadBalancing::getColor(unsigned Reg) {
711 if ((TRI->getEncodingValue(Reg) % 2) == 0)
717 // Factory function used by AArch64TargetMachine to add the pass to the passmanager.
718 FunctionPass *llvm::createAArch64A57FPLoadBalancing() {
719 return new AArch64A57FPLoadBalancing();