1 //===-- AArch64AsmPrinter.cpp - AArch64 LLVM assembly writer --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to the AArch64 assembly language.
13 //===----------------------------------------------------------------------===//
15 #include "MCTargetDesc/AArch64AddressingModes.h"
17 #include "AArch64MCInstLower.h"
18 #include "AArch64MachineFunctionInfo.h"
19 #include "AArch64RegisterInfo.h"
20 #include "AArch64Subtarget.h"
21 #include "InstPrinter/AArch64InstPrinter.h"
22 #include "MCTargetDesc/AArch64MCExpr.h"
23 #include "llvm/ADT/SmallString.h"
24 #include "llvm/ADT/StringSwitch.h"
25 #include "llvm/ADT/Twine.h"
26 #include "llvm/CodeGen/AsmPrinter.h"
27 #include "llvm/CodeGen/MachineInstr.h"
28 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
29 #include "llvm/CodeGen/StackMaps.h"
30 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
31 #include "llvm/IR/DataLayout.h"
32 #include "llvm/IR/DebugInfo.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCContext.h"
35 #include "llvm/MC/MCInst.h"
36 #include "llvm/MC/MCInstBuilder.h"
37 #include "llvm/MC/MCLinkerOptimizationHint.h"
38 #include "llvm/MC/MCStreamer.h"
39 #include "llvm/MC/MCSymbol.h"
40 #include "llvm/MC/MCSymbolELF.h"
41 #include "llvm/MC/MCSectionELF.h"
42 #include "llvm/MC/MCSectionMachO.h"
43 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/TargetRegistry.h"
45 #include "llvm/Support/raw_ostream.h"
48 #define DEBUG_TYPE "asm-printer"
52 class AArch64AsmPrinter : public AsmPrinter {
53 AArch64MCInstLower MCInstLowering;
55 const AArch64Subtarget *STI;
58 AArch64AsmPrinter(TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer)
59 : AsmPrinter(TM, std::move(Streamer)), MCInstLowering(OutContext, *this),
60 SM(*this), AArch64FI(nullptr) {}
62 StringRef getPassName() const override { return "AArch64 Assembly Printer"; }
64 /// \brief Wrapper for MCInstLowering.lowerOperand() for the
65 /// tblgen'erated pseudo lowering.
66 bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const {
67 return MCInstLowering.lowerOperand(MO, MCOp);
70 void LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM,
71 const MachineInstr &MI);
72 void LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM,
73 const MachineInstr &MI);
75 void LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI);
76 void LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI);
77 void LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI);
79 void EmitSled(const MachineInstr &MI, SledKind Kind);
81 /// \brief tblgen'erated driver function for lowering simple MI->MC
82 /// pseudo instructions.
83 bool emitPseudoExpansionLowering(MCStreamer &OutStreamer,
84 const MachineInstr *MI);
86 void EmitInstruction(const MachineInstr *MI) override;
88 void getAnalysisUsage(AnalysisUsage &AU) const override {
89 AsmPrinter::getAnalysisUsage(AU);
93 bool runOnMachineFunction(MachineFunction &F) override {
94 AArch64FI = F.getInfo<AArch64FunctionInfo>();
95 STI = static_cast<const AArch64Subtarget*>(&F.getSubtarget());
96 bool Result = AsmPrinter::runOnMachineFunction(F);
102 void printOperand(const MachineInstr *MI, unsigned OpNum, raw_ostream &O);
103 bool printAsmMRegister(const MachineOperand &MO, char Mode, raw_ostream &O);
104 bool printAsmRegInClass(const MachineOperand &MO,
105 const TargetRegisterClass *RC, bool isVector,
108 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
109 unsigned AsmVariant, const char *ExtraCode,
110 raw_ostream &O) override;
111 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
112 unsigned AsmVariant, const char *ExtraCode,
113 raw_ostream &O) override;
115 void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS);
117 void EmitFunctionBodyEnd() override;
119 MCSymbol *GetCPISymbol(unsigned CPID) const override;
120 void EmitEndOfAsmFile(Module &M) override;
121 AArch64FunctionInfo *AArch64FI;
123 /// \brief Emit the LOHs contained in AArch64FI.
126 /// Emit instruction to set float register to zero.
127 void EmitFMov0(const MachineInstr &MI);
129 typedef std::map<const MachineInstr *, MCSymbol *> MInstToMCSymbol;
130 MInstToMCSymbol LOHInstToLabel;
133 } // end of anonymous namespace
135 //===----------------------------------------------------------------------===//
137 void AArch64AsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI)
139 EmitSled(MI, SledKind::FUNCTION_ENTER);
142 void AArch64AsmPrinter::LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI)
144 EmitSled(MI, SledKind::FUNCTION_EXIT);
147 void AArch64AsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI)
149 EmitSled(MI, SledKind::TAIL_CALL);
152 void AArch64AsmPrinter::EmitSled(const MachineInstr &MI, SledKind Kind)
154 static const int8_t NoopsInSledCount = 7;
155 // We want to emit the following pattern:
160 // ; 7 NOP instructions (28 bytes)
163 // We need the 28 bytes (7 instructions) because at runtime, we'd be patching
164 // over the full 32 bytes (8 instructions) with the following pattern:
166 // STP X0, X30, [SP, #-16]! ; push X0 and the link register to the stack
167 // LDR W0, #12 ; W0 := function ID
168 // LDR X16,#12 ; X16 := addr of __xray_FunctionEntry or __xray_FunctionExit
169 // BLR X16 ; call the tracing trampoline
170 // ;DATA: 32 bits of function ID
171 // ;DATA: lower 32 bits of the address of the trampoline
172 // ;DATA: higher 32 bits of the address of the trampoline
173 // LDP X0, X30, [SP], #16 ; pop X0 and the link register from the stack
175 OutStreamer->EmitCodeAlignment(4);
176 auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
177 OutStreamer->EmitLabel(CurSled);
178 auto Target = OutContext.createTempSymbol();
180 // Emit "B #32" instruction, which jumps over the next 28 bytes.
181 // The operand has to be the number of 4-byte instructions to jump over,
182 // including the current instruction.
183 EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::B).addImm(8));
185 for (int8_t I = 0; I < NoopsInSledCount; I++)
186 EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0));
188 OutStreamer->EmitLabel(Target);
189 recordSled(CurSled, MI, Kind);
192 void AArch64AsmPrinter::EmitEndOfAsmFile(Module &M) {
193 const Triple &TT = TM.getTargetTriple();
194 if (TT.isOSBinFormatMachO()) {
195 // Funny Darwin hack: This flag tells the linker that no global symbols
196 // contain code that falls through to other global symbols (e.g. the obvious
197 // implementation of multiple entry points). If this doesn't occur, the
198 // linker can safely perform dead code stripping. Since LLVM never
199 // generates code that does this, it is always safe to set.
200 OutStreamer->EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
201 SM.serializeToStackMapSection();
205 void AArch64AsmPrinter::EmitLOHs() {
206 SmallVector<MCSymbol *, 3> MCArgs;
208 for (const auto &D : AArch64FI->getLOHContainer()) {
209 for (const MachineInstr *MI : D.getArgs()) {
210 MInstToMCSymbol::iterator LabelIt = LOHInstToLabel.find(MI);
211 assert(LabelIt != LOHInstToLabel.end() &&
212 "Label hasn't been inserted for LOH related instruction");
213 MCArgs.push_back(LabelIt->second);
215 OutStreamer->EmitLOHDirective(D.getKind(), MCArgs);
220 void AArch64AsmPrinter::EmitFunctionBodyEnd() {
221 if (!AArch64FI->getLOHRelated().empty())
225 /// GetCPISymbol - Return the symbol for the specified constant pool entry.
226 MCSymbol *AArch64AsmPrinter::GetCPISymbol(unsigned CPID) const {
227 // Darwin uses a linker-private symbol name for constant-pools (to
228 // avoid addends on the relocation?), ELF has no such concept and
229 // uses a normal private symbol.
230 if (!getDataLayout().getLinkerPrivateGlobalPrefix().empty())
231 return OutContext.getOrCreateSymbol(
232 Twine(getDataLayout().getLinkerPrivateGlobalPrefix()) + "CPI" +
233 Twine(getFunctionNumber()) + "_" + Twine(CPID));
235 return OutContext.getOrCreateSymbol(
236 Twine(getDataLayout().getPrivateGlobalPrefix()) + "CPI" +
237 Twine(getFunctionNumber()) + "_" + Twine(CPID));
240 void AArch64AsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNum,
242 const MachineOperand &MO = MI->getOperand(OpNum);
243 switch (MO.getType()) {
245 llvm_unreachable("<unknown operand type>");
246 case MachineOperand::MO_Register: {
247 unsigned Reg = MO.getReg();
248 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
249 assert(!MO.getSubReg() && "Subregs should be eliminated!");
250 O << AArch64InstPrinter::getRegisterName(Reg);
253 case MachineOperand::MO_Immediate: {
254 int64_t Imm = MO.getImm();
258 case MachineOperand::MO_GlobalAddress: {
259 const GlobalValue *GV = MO.getGlobal();
260 MCSymbol *Sym = getSymbol(GV);
262 // FIXME: Can we get anything other than a plain symbol here?
263 assert(!MO.getTargetFlags() && "Unknown operand target flag!");
266 printOffset(MO.getOffset(), O);
272 bool AArch64AsmPrinter::printAsmMRegister(const MachineOperand &MO, char Mode,
274 unsigned Reg = MO.getReg();
277 return true; // Unknown mode.
279 Reg = getWRegFromXReg(Reg);
282 Reg = getXRegFromWReg(Reg);
286 O << AArch64InstPrinter::getRegisterName(Reg);
290 // Prints the register in MO using class RC using the offset in the
291 // new register class. This should not be used for cross class
293 bool AArch64AsmPrinter::printAsmRegInClass(const MachineOperand &MO,
294 const TargetRegisterClass *RC,
295 bool isVector, raw_ostream &O) {
296 assert(MO.isReg() && "Should only get here with a register!");
297 const TargetRegisterInfo *RI = STI->getRegisterInfo();
298 unsigned Reg = MO.getReg();
299 unsigned RegToPrint = RC->getRegister(RI->getEncodingValue(Reg));
300 assert(RI->regsOverlap(RegToPrint, Reg));
301 O << AArch64InstPrinter::getRegisterName(
302 RegToPrint, isVector ? AArch64::vreg : AArch64::NoRegAltName);
306 bool AArch64AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
308 const char *ExtraCode, raw_ostream &O) {
309 const MachineOperand &MO = MI->getOperand(OpNum);
311 // First try the generic code, which knows about modifiers like 'c' and 'n'.
312 if (!AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O))
315 // Does this asm operand have a single letter operand modifier?
316 if (ExtraCode && ExtraCode[0]) {
317 if (ExtraCode[1] != 0)
318 return true; // Unknown modifier.
320 switch (ExtraCode[0]) {
322 return true; // Unknown modifier.
323 case 'w': // Print W register
324 case 'x': // Print X register
326 return printAsmMRegister(MO, ExtraCode[0], O);
327 if (MO.isImm() && MO.getImm() == 0) {
328 unsigned Reg = ExtraCode[0] == 'w' ? AArch64::WZR : AArch64::XZR;
329 O << AArch64InstPrinter::getRegisterName(Reg);
332 printOperand(MI, OpNum, O);
334 case 'b': // Print B register.
335 case 'h': // Print H register.
336 case 's': // Print S register.
337 case 'd': // Print D register.
338 case 'q': // Print Q register.
340 const TargetRegisterClass *RC;
341 switch (ExtraCode[0]) {
343 RC = &AArch64::FPR8RegClass;
346 RC = &AArch64::FPR16RegClass;
349 RC = &AArch64::FPR32RegClass;
352 RC = &AArch64::FPR64RegClass;
355 RC = &AArch64::FPR128RegClass;
360 return printAsmRegInClass(MO, RC, false /* vector */, O);
362 printOperand(MI, OpNum, O);
367 // According to ARM, we should emit x and v registers unless we have a
370 unsigned Reg = MO.getReg();
372 // If this is a w or x register, print an x register.
373 if (AArch64::GPR32allRegClass.contains(Reg) ||
374 AArch64::GPR64allRegClass.contains(Reg))
375 return printAsmMRegister(MO, 'x', O);
377 // If this is a b, h, s, d, or q register, print it as a v register.
378 return printAsmRegInClass(MO, &AArch64::FPR128RegClass, true /* vector */,
382 printOperand(MI, OpNum, O);
386 bool AArch64AsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
389 const char *ExtraCode,
391 if (ExtraCode && ExtraCode[0])
392 return true; // Unknown modifier.
394 const MachineOperand &MO = MI->getOperand(OpNum);
395 assert(MO.isReg() && "unexpected inline asm memory operand");
396 O << "[" << AArch64InstPrinter::getRegisterName(MO.getReg()) << "]";
400 void AArch64AsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
402 unsigned NOps = MI->getNumOperands();
404 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
405 // cast away const; DIetc do not take const operands for some reason.
406 OS << cast<DILocalVariable>(MI->getOperand(NOps - 2).getMetadata())
409 // Frame address. Currently handles register +- offset only.
410 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
412 printOperand(MI, 0, OS);
414 printOperand(MI, 1, OS);
417 printOperand(MI, NOps - 2, OS);
420 void AArch64AsmPrinter::LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM,
421 const MachineInstr &MI) {
422 unsigned NumNOPBytes = StackMapOpers(&MI).getNumPatchBytes();
424 SM.recordStackMap(MI);
425 assert(NumNOPBytes % 4 == 0 && "Invalid number of NOP bytes requested!");
427 // Scan ahead to trim the shadow.
428 const MachineBasicBlock &MBB = *MI.getParent();
429 MachineBasicBlock::const_iterator MII(MI);
431 while (NumNOPBytes > 0) {
432 if (MII == MBB.end() || MII->isCall() ||
433 MII->getOpcode() == AArch64::DBG_VALUE ||
434 MII->getOpcode() == TargetOpcode::PATCHPOINT ||
435 MII->getOpcode() == TargetOpcode::STACKMAP)
442 for (unsigned i = 0; i < NumNOPBytes; i += 4)
443 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0));
446 // Lower a patchpoint of the form:
447 // [<def>], <id>, <numBytes>, <target>, <numArgs>
448 void AArch64AsmPrinter::LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM,
449 const MachineInstr &MI) {
450 SM.recordPatchPoint(MI);
452 PatchPointOpers Opers(&MI);
454 int64_t CallTarget = Opers.getCallTarget().getImm();
455 unsigned EncodedBytes = 0;
457 assert((CallTarget & 0xFFFFFFFFFFFF) == CallTarget &&
458 "High 16 bits of call target should be zero.");
459 unsigned ScratchReg = MI.getOperand(Opers.getNextScratchIdx()).getReg();
461 // Materialize the jump address:
462 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVZXi)
464 .addImm((CallTarget >> 32) & 0xFFFF)
466 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVKXi)
469 .addImm((CallTarget >> 16) & 0xFFFF)
471 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVKXi)
474 .addImm(CallTarget & 0xFFFF)
476 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::BLR).addReg(ScratchReg));
479 unsigned NumBytes = Opers.getNumPatchBytes();
480 assert(NumBytes >= EncodedBytes &&
481 "Patchpoint can't request size less than the length of a call.");
482 assert((NumBytes - EncodedBytes) % 4 == 0 &&
483 "Invalid number of NOP bytes requested!");
484 for (unsigned i = EncodedBytes; i < NumBytes; i += 4)
485 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0));
488 void AArch64AsmPrinter::EmitFMov0(const MachineInstr &MI) {
489 unsigned DestReg = MI.getOperand(0).getReg();
490 if (STI->hasZeroCycleZeroing()) {
491 // Convert S/D register to corresponding Q register
492 if (AArch64::S0 <= DestReg && DestReg <= AArch64::S31) {
493 DestReg = AArch64::Q0 + (DestReg - AArch64::S0);
495 assert(AArch64::D0 <= DestReg && DestReg <= AArch64::D31);
496 DestReg = AArch64::Q0 + (DestReg - AArch64::D0);
499 MOVI.setOpcode(AArch64::MOVIv2d_ns);
500 MOVI.addOperand(MCOperand::createReg(DestReg));
501 MOVI.addOperand(MCOperand::createImm(0));
502 EmitToStreamer(*OutStreamer, MOVI);
505 switch (MI.getOpcode()) {
506 default: llvm_unreachable("Unexpected opcode");
507 case AArch64::FMOVS0:
508 FMov.setOpcode(AArch64::FMOVWSr);
509 FMov.addOperand(MCOperand::createReg(DestReg));
510 FMov.addOperand(MCOperand::createReg(AArch64::WZR));
512 case AArch64::FMOVD0:
513 FMov.setOpcode(AArch64::FMOVXDr);
514 FMov.addOperand(MCOperand::createReg(DestReg));
515 FMov.addOperand(MCOperand::createReg(AArch64::XZR));
518 EmitToStreamer(*OutStreamer, FMov);
522 // Simple pseudo-instructions have their lowering (with expansion to real
523 // instructions) auto-generated.
524 #include "AArch64GenMCPseudoLowering.inc"
526 void AArch64AsmPrinter::EmitInstruction(const MachineInstr *MI) {
527 // Do any auto-generated pseudo lowerings.
528 if (emitPseudoExpansionLowering(*OutStreamer, MI))
531 if (AArch64FI->getLOHRelated().count(MI)) {
532 // Generate a label for LOH related instruction
533 MCSymbol *LOHLabel = createTempSymbol("loh");
534 // Associate the instruction with the label
535 LOHInstToLabel[MI] = LOHLabel;
536 OutStreamer->EmitLabel(LOHLabel);
539 // Do any manual lowerings.
540 switch (MI->getOpcode()) {
543 case AArch64::DBG_VALUE: {
544 if (isVerbose() && OutStreamer->hasRawTextSupport()) {
545 SmallString<128> TmpStr;
546 raw_svector_ostream OS(TmpStr);
547 PrintDebugValueComment(MI, OS);
548 OutStreamer->EmitRawText(StringRef(OS.str()));
553 // Tail calls use pseudo instructions so they have the proper code-gen
554 // attributes (isCall, isReturn, etc.). We lower them to the real
556 case AArch64::TCRETURNri: {
558 TmpInst.setOpcode(AArch64::BR);
559 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
560 EmitToStreamer(*OutStreamer, TmpInst);
563 case AArch64::TCRETURNdi: {
565 MCInstLowering.lowerOperand(MI->getOperand(0), Dest);
567 TmpInst.setOpcode(AArch64::B);
568 TmpInst.addOperand(Dest);
569 EmitToStreamer(*OutStreamer, TmpInst);
572 case AArch64::TLSDESC_CALLSEQ: {
574 /// adrp x0, :tlsdesc:var
575 /// ldr x1, [x0, #:tlsdesc_lo12:var]
576 /// add x0, x0, #:tlsdesc_lo12:var
579 /// (TPIDR_EL0 offset now in x0)
580 const MachineOperand &MO_Sym = MI->getOperand(0);
581 MachineOperand MO_TLSDESC_LO12(MO_Sym), MO_TLSDESC(MO_Sym);
582 MCOperand Sym, SymTLSDescLo12, SymTLSDesc;
583 MO_TLSDESC_LO12.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGEOFF);
584 MO_TLSDESC.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGE);
585 MCInstLowering.lowerOperand(MO_Sym, Sym);
586 MCInstLowering.lowerOperand(MO_TLSDESC_LO12, SymTLSDescLo12);
587 MCInstLowering.lowerOperand(MO_TLSDESC, SymTLSDesc);
590 Adrp.setOpcode(AArch64::ADRP);
591 Adrp.addOperand(MCOperand::createReg(AArch64::X0));
592 Adrp.addOperand(SymTLSDesc);
593 EmitToStreamer(*OutStreamer, Adrp);
596 Ldr.setOpcode(AArch64::LDRXui);
597 Ldr.addOperand(MCOperand::createReg(AArch64::X1));
598 Ldr.addOperand(MCOperand::createReg(AArch64::X0));
599 Ldr.addOperand(SymTLSDescLo12);
600 Ldr.addOperand(MCOperand::createImm(0));
601 EmitToStreamer(*OutStreamer, Ldr);
604 Add.setOpcode(AArch64::ADDXri);
605 Add.addOperand(MCOperand::createReg(AArch64::X0));
606 Add.addOperand(MCOperand::createReg(AArch64::X0));
607 Add.addOperand(SymTLSDescLo12);
608 Add.addOperand(MCOperand::createImm(AArch64_AM::getShiftValue(0)));
609 EmitToStreamer(*OutStreamer, Add);
611 // Emit a relocation-annotation. This expands to no code, but requests
612 // the following instruction gets an R_AARCH64_TLSDESC_CALL.
614 TLSDescCall.setOpcode(AArch64::TLSDESCCALL);
615 TLSDescCall.addOperand(Sym);
616 EmitToStreamer(*OutStreamer, TLSDescCall);
619 Blr.setOpcode(AArch64::BLR);
620 Blr.addOperand(MCOperand::createReg(AArch64::X1));
621 EmitToStreamer(*OutStreamer, Blr);
626 case AArch64::FMOVS0:
627 case AArch64::FMOVD0:
631 case TargetOpcode::STACKMAP:
632 return LowerSTACKMAP(*OutStreamer, SM, *MI);
634 case TargetOpcode::PATCHPOINT:
635 return LowerPATCHPOINT(*OutStreamer, SM, *MI);
637 case TargetOpcode::PATCHABLE_FUNCTION_ENTER:
638 LowerPATCHABLE_FUNCTION_ENTER(*MI);
641 case TargetOpcode::PATCHABLE_FUNCTION_EXIT:
642 LowerPATCHABLE_FUNCTION_EXIT(*MI);
645 case TargetOpcode::PATCHABLE_TAIL_CALL:
646 LowerPATCHABLE_TAIL_CALL(*MI);
650 // Finally, do the automated lowerings for everything else.
652 MCInstLowering.Lower(MI, TmpInst);
653 EmitToStreamer(*OutStreamer, TmpInst);
656 // Force static initialization.
657 extern "C" void LLVMInitializeAArch64AsmPrinter() {
658 RegisterAsmPrinter<AArch64AsmPrinter> X(getTheAArch64leTarget());
659 RegisterAsmPrinter<AArch64AsmPrinter> Y(getTheAArch64beTarget());
660 RegisterAsmPrinter<AArch64AsmPrinter> Z(getTheARM64Target());