1 //===-- AArch64CondBrTuning.cpp --- Conditional branch tuning for AArch64 -===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file contains a pass that transforms CBZ/CBNZ/TBZ/TBNZ instructions
11 /// into a conditional branch (B.cond), when the NZCV flags can be set for
12 /// "free". This is preferred on targets that have more flexibility when
13 /// scheduling B.cond instructions as compared to CBZ/CBNZ/TBZ/TBNZ (assuming
14 /// all other variables are equal). This can also reduce register pressure.
18 /// 1) add w8, w0, w1 -> cmn w0, w1 ; CMN is an alias of ADDS.
19 /// cbz w8, .LBB_2 -> b.eq .LBB0_2
21 /// 2) add w8, w0, w1 -> adds w8, w0, w1 ; w8 has multiple uses.
22 /// cbz w8, .LBB1_2 -> b.eq .LBB1_2
24 /// 3) sub w8, w0, w1 -> subs w8, w0, w1 ; w8 has multiple uses.
25 /// tbz w8, #31, .LBB6_2 -> b.pl .LBB6_2
27 //===----------------------------------------------------------------------===//
30 #include "AArch64Subtarget.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineFunctionPass.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/MachineTraceMetrics.h"
36 #include "llvm/CodeGen/Passes.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/Target/TargetInstrInfo.h"
40 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "llvm/Target/TargetSubtargetInfo.h"
45 #define DEBUG_TYPE "aarch64-cond-br-tuning"
46 #define AARCH64_CONDBR_TUNING_NAME "AArch64 Conditional Branch Tuning"
49 class AArch64CondBrTuning : public MachineFunctionPass {
50 const AArch64InstrInfo *TII;
51 const TargetRegisterInfo *TRI;
53 MachineRegisterInfo *MRI;
57 AArch64CondBrTuning() : MachineFunctionPass(ID) {
58 initializeAArch64CondBrTuningPass(*PassRegistry::getPassRegistry());
60 void getAnalysisUsage(AnalysisUsage &AU) const override;
61 bool runOnMachineFunction(MachineFunction &MF) override;
62 StringRef getPassName() const override { return AARCH64_CONDBR_TUNING_NAME; }
65 MachineInstr *getOperandDef(const MachineOperand &MO);
66 MachineInstr *convertToFlagSetting(MachineInstr &MI, bool IsFlagSetting);
67 MachineInstr *convertToCondBr(MachineInstr &MI);
68 bool tryToTuneBranch(MachineInstr &MI, MachineInstr &DefMI);
70 } // end anonymous namespace
72 char AArch64CondBrTuning::ID = 0;
74 INITIALIZE_PASS(AArch64CondBrTuning, "aarch64-cond-br-tuning",
75 AARCH64_CONDBR_TUNING_NAME, false, false)
77 void AArch64CondBrTuning::getAnalysisUsage(AnalysisUsage &AU) const {
79 MachineFunctionPass::getAnalysisUsage(AU);
82 MachineInstr *AArch64CondBrTuning::getOperandDef(const MachineOperand &MO) {
83 if (!TargetRegisterInfo::isVirtualRegister(MO.getReg()))
85 return MRI->getUniqueVRegDef(MO.getReg());
88 MachineInstr *AArch64CondBrTuning::convertToFlagSetting(MachineInstr &MI,
90 // If this is already the flag setting version of the instruction (e.g., SUBS)
91 // just make sure the implicit-def of NZCV isn't marked dead.
93 for (unsigned I = MI.getNumExplicitOperands(), E = MI.getNumOperands();
95 MachineOperand &MO = MI.getOperand(I);
96 if (MO.isReg() && MO.isDead() && MO.getReg() == AArch64::NZCV)
102 unsigned NewOpc = TII->convertToFlagSettingOpc(MI.getOpcode(), Is64Bit);
103 unsigned NewDestReg = MI.getOperand(0).getReg();
104 if (MRI->hasOneNonDBGUse(MI.getOperand(0).getReg()))
105 NewDestReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
107 MachineInstrBuilder MIB = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
108 TII->get(NewOpc), NewDestReg);
109 for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I)
110 MIB.add(MI.getOperand(I));
115 MachineInstr *AArch64CondBrTuning::convertToCondBr(MachineInstr &MI) {
116 AArch64CC::CondCode CC;
117 MachineBasicBlock *TargetMBB = TII->getBranchDestBlock(MI);
118 switch (MI.getOpcode()) {
120 llvm_unreachable("Unexpected opcode!");
139 return BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), TII->get(AArch64::Bcc))
144 bool AArch64CondBrTuning::tryToTuneBranch(MachineInstr &MI,
145 MachineInstr &DefMI) {
146 // We don't want NZCV bits live across blocks.
147 if (MI.getParent() != DefMI.getParent())
150 bool IsFlagSetting = true;
151 unsigned MIOpc = MI.getOpcode();
152 MachineInstr *NewCmp = nullptr, *NewBr = nullptr;
153 switch (DefMI.getOpcode()) {
156 case AArch64::ADDWri:
157 case AArch64::ADDWrr:
158 case AArch64::ADDWrs:
159 case AArch64::ADDWrx:
160 case AArch64::ANDWri:
161 case AArch64::ANDWrr:
162 case AArch64::ANDWrs:
163 case AArch64::BICWrr:
164 case AArch64::BICWrs:
165 case AArch64::SUBWri:
166 case AArch64::SUBWrr:
167 case AArch64::SUBWrs:
168 case AArch64::SUBWrx:
169 IsFlagSetting = false;
171 case AArch64::ADDSWri:
172 case AArch64::ADDSWrr:
173 case AArch64::ADDSWrs:
174 case AArch64::ADDSWrx:
175 case AArch64::ANDSWri:
176 case AArch64::ANDSWrr:
177 case AArch64::ANDSWrs:
178 case AArch64::BICSWrr:
179 case AArch64::BICSWrs:
180 case AArch64::SUBSWri:
181 case AArch64::SUBSWrr:
182 case AArch64::SUBSWrs:
183 case AArch64::SUBSWrx:
186 llvm_unreachable("Unexpected opcode!");
192 // Check to see if the TBZ/TBNZ is checking the sign bit.
193 if ((MIOpc == AArch64::TBZW || MIOpc == AArch64::TBNZW) &&
194 MI.getOperand(1).getImm() != 31)
197 // There must not be any instruction between DefMI and MI that clobbers or
199 MachineBasicBlock::iterator I(DefMI), E(MI);
200 for (I = std::next(I); I != E; ++I) {
201 if (I->modifiesRegister(AArch64::NZCV, TRI) ||
202 I->readsRegister(AArch64::NZCV, TRI))
205 DEBUG(dbgs() << " Replacing instructions:\n ");
206 DEBUG(DefMI.print(dbgs()));
207 DEBUG(dbgs() << " ");
208 DEBUG(MI.print(dbgs()));
210 NewCmp = convertToFlagSetting(DefMI, IsFlagSetting);
211 NewBr = convertToCondBr(MI);
216 case AArch64::ADDXri:
217 case AArch64::ADDXrr:
218 case AArch64::ADDXrs:
219 case AArch64::ADDXrx:
220 case AArch64::ANDXri:
221 case AArch64::ANDXrr:
222 case AArch64::ANDXrs:
223 case AArch64::BICXrr:
224 case AArch64::BICXrs:
225 case AArch64::SUBXri:
226 case AArch64::SUBXrr:
227 case AArch64::SUBXrs:
228 case AArch64::SUBXrx:
229 IsFlagSetting = false;
231 case AArch64::ADDSXri:
232 case AArch64::ADDSXrr:
233 case AArch64::ADDSXrs:
234 case AArch64::ADDSXrx:
235 case AArch64::ANDSXri:
236 case AArch64::ANDSXrr:
237 case AArch64::ANDSXrs:
238 case AArch64::BICSXrr:
239 case AArch64::BICSXrs:
240 case AArch64::SUBSXri:
241 case AArch64::SUBSXrr:
242 case AArch64::SUBSXrs:
243 case AArch64::SUBSXrx:
246 llvm_unreachable("Unexpected opcode!");
251 case AArch64::TBNZX: {
252 // Check to see if the TBZ/TBNZ is checking the sign bit.
253 if ((MIOpc == AArch64::TBZX || MIOpc == AArch64::TBNZX) &&
254 MI.getOperand(1).getImm() != 63)
256 // There must not be any instruction between DefMI and MI that clobbers or
258 MachineBasicBlock::iterator I(DefMI), E(MI);
259 for (I = std::next(I); I != E; ++I) {
260 if (I->modifiesRegister(AArch64::NZCV, TRI) ||
261 I->readsRegister(AArch64::NZCV, TRI))
264 DEBUG(dbgs() << " Replacing instructions:\n ");
265 DEBUG(DefMI.print(dbgs()));
266 DEBUG(dbgs() << " ");
267 DEBUG(MI.print(dbgs()));
269 NewCmp = convertToFlagSetting(DefMI, IsFlagSetting);
270 NewBr = convertToCondBr(MI);
276 (void)NewCmp; (void)NewBr;
277 assert(NewCmp && NewBr && "Expected new instructions.");
279 DEBUG(dbgs() << " with instruction:\n ");
280 DEBUG(NewCmp->print(dbgs()));
281 DEBUG(dbgs() << " ");
282 DEBUG(NewBr->print(dbgs()));
284 // If this was a flag setting version of the instruction, we use the original
285 // instruction by just clearing the dead marked on the implicit-def of NCZV.
286 // Therefore, we should not erase this instruction.
288 DefMI.eraseFromParent();
289 MI.eraseFromParent();
293 bool AArch64CondBrTuning::runOnMachineFunction(MachineFunction &MF) {
294 if (skipFunction(*MF.getFunction()))
297 DEBUG(dbgs() << "********** AArch64 Conditional Branch Tuning **********\n"
298 << "********** Function: " << MF.getName() << '\n');
300 TII = static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo());
301 TRI = MF.getSubtarget().getRegisterInfo();
302 MRI = &MF.getRegInfo();
304 bool Changed = false;
305 for (MachineBasicBlock &MBB : MF) {
306 bool LocalChange = false;
307 for (MachineBasicBlock::iterator I = MBB.getFirstTerminator(),
310 MachineInstr &MI = *I;
311 switch (MI.getOpcode()) {
322 MachineInstr *DefMI = getOperandDef(MI.getOperand(0));
323 LocalChange = (DefMI && tryToTuneBranch(MI, *DefMI));
326 // If the optimization was successful, we can't optimize any other
327 // branches because doing so would clobber the NZCV flags.
337 FunctionPass *llvm::createAArch64CondBrTuning() {
338 return new AArch64CondBrTuning();