1 //==-- AArch64DeadRegisterDefinitions.cpp - Replace dead defs w/ zero reg --==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 /// \file When allowed by the instruction, replace a dead definition of a GPR
10 /// with the zero register. This makes the code a bit friendlier towards the
11 /// hardware's register renamer.
12 //===----------------------------------------------------------------------===//
15 #include "AArch64RegisterInfo.h"
16 #include "llvm/ADT/Statistic.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineFunctionPass.h"
19 #include "llvm/CodeGen/MachineInstr.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/raw_ostream.h"
23 #include "llvm/Target/TargetSubtargetInfo.h"
24 #include "llvm/Target/TargetInstrInfo.h"
27 #define DEBUG_TYPE "aarch64-dead-defs"
29 STATISTIC(NumDeadDefsReplaced, "Number of dead definitions replaced");
31 #define AARCH64_DEAD_REG_DEF_NAME "AArch64 Dead register definitions"
34 class AArch64DeadRegisterDefinitions : public MachineFunctionPass {
36 const TargetRegisterInfo *TRI;
37 const MachineRegisterInfo *MRI;
38 const TargetInstrInfo *TII;
40 void processMachineBasicBlock(MachineBasicBlock &MBB);
42 static char ID; // Pass identification, replacement for typeid.
43 AArch64DeadRegisterDefinitions() : MachineFunctionPass(ID) {
44 initializeAArch64DeadRegisterDefinitionsPass(
45 *PassRegistry::getPassRegistry());
48 bool runOnMachineFunction(MachineFunction &F) override;
50 StringRef getPassName() const override { return AARCH64_DEAD_REG_DEF_NAME; }
52 void getAnalysisUsage(AnalysisUsage &AU) const override {
54 MachineFunctionPass::getAnalysisUsage(AU);
57 char AArch64DeadRegisterDefinitions::ID = 0;
58 } // end anonymous namespace
60 INITIALIZE_PASS(AArch64DeadRegisterDefinitions, "aarch64-dead-defs",
61 AARCH64_DEAD_REG_DEF_NAME, false, false)
63 static bool usesFrameIndex(const MachineInstr &MI) {
64 for (const MachineOperand &MO : MI.uses())
70 void AArch64DeadRegisterDefinitions::processMachineBasicBlock(
71 MachineBasicBlock &MBB) {
72 const MachineFunction &MF = *MBB.getParent();
73 for (MachineInstr &MI : MBB) {
74 if (usesFrameIndex(MI)) {
75 // We need to skip this instruction because while it appears to have a
76 // dead def it uses a frame index which might expand into a multi
77 // instruction sequence during EPI.
78 DEBUG(dbgs() << " Ignoring, operand is frame index\n");
81 if (MI.definesRegister(AArch64::XZR) || MI.definesRegister(AArch64::WZR)) {
82 // It is not allowed to write to the same register (not even the zero
83 // register) twice in a single instruction.
84 DEBUG(dbgs() << " Ignoring, XZR or WZR already used by the instruction\n");
87 const MCInstrDesc &Desc = MI.getDesc();
88 for (int I = 0, E = Desc.getNumDefs(); I != E; ++I) {
89 MachineOperand &MO = MI.getOperand(I);
90 if (!MO.isReg() || !MO.isDef())
92 // We should not have any relevant physreg defs that are replacable by
93 // zero before register allocation. So we just check for dead vreg defs.
94 unsigned Reg = MO.getReg();
95 if (!TargetRegisterInfo::isVirtualRegister(Reg) ||
96 (!MO.isDead() && !MRI->use_nodbg_empty(Reg)))
98 assert(!MO.isImplicit() && "Unexpected implicit def!");
99 DEBUG(dbgs() << " Dead def operand #" << I << " in:\n ";
101 // Be careful not to change the register if it's a tied operand.
102 if (MI.isRegTiedToUseOperand(I)) {
103 DEBUG(dbgs() << " Ignoring, def is tied operand.\n");
106 const TargetRegisterClass *RC = TII->getRegClass(Desc, I, TRI, MF);
109 DEBUG(dbgs() << " Ignoring, register is not a GPR.\n");
111 } else if (RC->contains(AArch64::WZR))
112 NewReg = AArch64::WZR;
113 else if (RC->contains(AArch64::XZR))
114 NewReg = AArch64::XZR;
116 DEBUG(dbgs() << " Ignoring, register is not a GPR.\n");
119 DEBUG(dbgs() << " Replacing with zero register. New:\n ");
122 DEBUG(MI.print(dbgs()));
123 ++NumDeadDefsReplaced;
125 // Only replace one dead register, see check for zero register above.
131 // Scan the function for instructions that have a dead definition of a
132 // register. Replace that register with the zero register when possible.
133 bool AArch64DeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) {
134 if (skipFunction(*MF.getFunction()))
137 TRI = MF.getSubtarget().getRegisterInfo();
138 TII = MF.getSubtarget().getInstrInfo();
139 MRI = &MF.getRegInfo();
140 DEBUG(dbgs() << "***** AArch64DeadRegisterDefinitions *****\n");
143 processMachineBasicBlock(MBB);
147 FunctionPass *llvm::createAArch64DeadRegisterDefinitions() {
148 return new AArch64DeadRegisterDefinitions();