1 //===- AArch64GenRegisterBankInfo.def ----------------------------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file defines all the static objects used by AArch64RegisterBankInfo.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_BUILD_GLOBAL_ISEL
15 #error "You shouldn't build this"
19 RegisterBankInfo::PartialMapping AArch64GenRegisterBankInfo::PartMappings[]{
20 /* StartIdx, Length, RegBank */
21 // 0: FPR 32-bit value.
22 {0, 32, AArch64::FPRRegBank},
23 // 1: FPR 64-bit value.
24 {0, 64, AArch64::FPRRegBank},
25 // 2: FPR 128-bit value.
26 {0, 128, AArch64::FPRRegBank},
27 // 3: FPR 256-bit value.
28 {0, 256, AArch64::FPRRegBank},
29 // 4: FPR 512-bit value.
30 {0, 512, AArch64::FPRRegBank},
31 // 5: GPR 32-bit value.
32 {0, 32, AArch64::GPRRegBank},
33 // 6: GPR 64-bit value.
34 {0, 64, AArch64::GPRRegBank},
38 RegisterBankInfo::ValueMapping AArch64GenRegisterBankInfo::ValMappings[]{
39 /* BreakDown, NumBreakDowns */
42 // 3-operands instructions (all binary operations should end up with one of
44 // 1: FPR 32-bit value. <-- This must match First3OpsIdx.
45 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
46 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
47 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
48 // 4: FPR 64-bit value.
49 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
50 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
51 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
52 // 7: FPR 128-bit value.
53 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR128 - PMI_Min], 1},
54 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR128 - PMI_Min], 1},
55 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR128 - PMI_Min], 1},
56 // 10: FPR 256-bit value.
57 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR256 - PMI_Min], 1},
58 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR256 - PMI_Min], 1},
59 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR256 - PMI_Min], 1},
60 // 13: FPR 512-bit value.
61 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR512 - PMI_Min], 1},
62 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR512 - PMI_Min], 1},
63 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR512 - PMI_Min], 1},
64 // 16: GPR 32-bit value.
65 {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
66 {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
67 {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
68 // 19: GPR 64-bit value. <-- This must match Last3OpsIdx.
69 {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
70 {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
71 {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
72 // Cross register bank copies.
73 // 22: FPR 32-bit value to GPR 32-bit value. <-- This must match
74 // FirstCrossRegCpyIdx.
75 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
76 {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
77 // 24: FPR 64-bit value to GPR 64-bit value.
78 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
79 {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
80 // 26: FPR 128-bit value to GPR 128-bit value (invalid)
83 // 28: FPR 256-bit value to GPR 256-bit value (invalid)
86 // 30: FPR 512-bit value to GPR 512-bit value (invalid)
89 // 32: GPR 32-bit value to FPR 32-bit value.
90 {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
91 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
92 // 34: GPR 64-bit value to FPR 64-bit value. <-- This must match
93 // LastCrossRegCpyIdx.
94 {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
95 {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
98 bool AArch64GenRegisterBankInfo::checkPartialMap(unsigned Idx,
101 const RegisterBank &RB) {
102 const PartialMapping &Map = PartMappings[Idx - PartialMappingIdx::PMI_Min];
103 return Map.StartIdx == ValStartIdx && Map.Length == ValLength &&
107 bool AArch64GenRegisterBankInfo::checkValueMapImpl(unsigned Idx,
108 unsigned FirstInBank,
111 unsigned PartialMapBaseIdx = Idx - PartialMappingIdx::PMI_Min;
112 const ValueMapping &Map =
113 AArch64GenRegisterBankInfo::getValueMapping((PartialMappingIdx)FirstInBank, Size)[Offset];
114 return Map.BreakDown == &PartMappings[PartialMapBaseIdx] &&
115 Map.NumBreakDowns == 1;
118 bool AArch64GenRegisterBankInfo::checkPartialMappingIdx(
119 PartialMappingIdx FirstAlias, PartialMappingIdx LastAlias,
120 ArrayRef<PartialMappingIdx> Order) {
121 if (Order.front() != FirstAlias)
123 if (Order.back() != LastAlias)
125 if (Order.front() > Order.back())
128 PartialMappingIdx Previous = Order.front();
130 for (const auto &Current : Order) {
135 if (Previous + 1 != Current)
142 unsigned AArch64GenRegisterBankInfo::getRegBankBaseIdxOffset(unsigned RBIdx,
144 if (RBIdx == PMI_FirstGPR) {
151 if (RBIdx == PMI_FirstFPR) {
167 const RegisterBankInfo::ValueMapping *
168 AArch64GenRegisterBankInfo::getValueMapping(PartialMappingIdx RBIdx,
170 assert(RBIdx != PartialMappingIdx::PMI_None && "No mapping needed for that");
171 unsigned BaseIdxOffset = getRegBankBaseIdxOffset(RBIdx, Size);
172 if (BaseIdxOffset == -1u)
173 return &ValMappings[InvalidIdx];
175 unsigned ValMappingIdx =
176 First3OpsIdx + (RBIdx - PartialMappingIdx::PMI_Min + BaseIdxOffset) *
177 ValueMappingIdx::DistanceBetweenRegBanks;
178 assert(ValMappingIdx >= First3OpsIdx && ValMappingIdx <= Last3OpsIdx &&
179 "Mapping out of bound");
181 return &ValMappings[ValMappingIdx];
184 AArch64GenRegisterBankInfo::PartialMappingIdx
185 AArch64GenRegisterBankInfo::BankIDToCopyMapIdx[]{
191 const RegisterBankInfo::ValueMapping *
192 AArch64GenRegisterBankInfo::getCopyMapping(unsigned DstBankID,
193 unsigned SrcBankID, unsigned Size) {
194 assert(DstBankID < AArch64::NumRegisterBanks && "Invalid bank ID");
195 assert(SrcBankID < AArch64::NumRegisterBanks && "Invalid bank ID");
196 PartialMappingIdx DstRBIdx = BankIDToCopyMapIdx[DstBankID];
197 PartialMappingIdx SrcRBIdx = BankIDToCopyMapIdx[SrcBankID];
198 assert(DstRBIdx != PMI_None && "No such mapping");
199 assert(SrcRBIdx != PMI_None && "No such mapping");
201 if (DstRBIdx == SrcRBIdx)
202 return getValueMapping(DstRBIdx, Size);
204 assert(Size <= 64 && "GPR cannot handle that size");
205 unsigned ValMappingIdx =
206 FirstCrossRegCpyIdx +
207 (DstRBIdx - PMI_Min + getRegBankBaseIdxOffset(DstRBIdx, Size)) *
208 ValueMappingIdx::DistanceBetweenCrossRegCpy;
209 assert(ValMappingIdx >= FirstCrossRegCpyIdx &&
210 ValMappingIdx <= LastCrossRegCpyIdx && "Mapping out of bound");
211 return &ValMappings[ValMappingIdx];
213 } // End llvm namespace.