1 //===-- AArch64ISelDAGToDAG.cpp - A dag to dag inst selector for AArch64 --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the AArch64 target.
12 //===----------------------------------------------------------------------===//
14 #include "AArch64TargetMachine.h"
15 #include "MCTargetDesc/AArch64AddressingModes.h"
16 #include "llvm/ADT/APSInt.h"
17 #include "llvm/CodeGen/SelectionDAGISel.h"
18 #include "llvm/IR/Function.h" // To access function attributes.
19 #include "llvm/IR/GlobalValue.h"
20 #include "llvm/IR/Intrinsics.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/MathExtras.h"
24 #include "llvm/Support/raw_ostream.h"
28 #define DEBUG_TYPE "aarch64-isel"
30 //===--------------------------------------------------------------------===//
31 /// AArch64DAGToDAGISel - AArch64 specific code to select AArch64 machine
32 /// instructions for SelectionDAG operations.
36 class AArch64DAGToDAGISel : public SelectionDAGISel {
38 /// Subtarget - Keep a pointer to the AArch64Subtarget around so that we can
39 /// make the right decision when generating code for different targets.
40 const AArch64Subtarget *Subtarget;
45 explicit AArch64DAGToDAGISel(AArch64TargetMachine &tm,
46 CodeGenOpt::Level OptLevel)
47 : SelectionDAGISel(tm, OptLevel), Subtarget(nullptr),
50 StringRef getPassName() const override {
51 return "AArch64 Instruction Selection";
54 bool runOnMachineFunction(MachineFunction &MF) override {
55 ForCodeSize = MF.getFunction()->optForSize();
56 Subtarget = &MF.getSubtarget<AArch64Subtarget>();
57 return SelectionDAGISel::runOnMachineFunction(MF);
60 void Select(SDNode *Node) override;
62 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
63 /// inline asm expressions.
64 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
65 unsigned ConstraintID,
66 std::vector<SDValue> &OutOps) override;
68 bool tryMLAV64LaneV128(SDNode *N);
69 bool tryMULLV64LaneV128(unsigned IntNo, SDNode *N);
70 bool SelectArithExtendedRegister(SDValue N, SDValue &Reg, SDValue &Shift);
71 bool SelectArithImmed(SDValue N, SDValue &Val, SDValue &Shift);
72 bool SelectNegArithImmed(SDValue N, SDValue &Val, SDValue &Shift);
73 bool SelectArithShiftedRegister(SDValue N, SDValue &Reg, SDValue &Shift) {
74 return SelectShiftedRegister(N, false, Reg, Shift);
76 bool SelectLogicalShiftedRegister(SDValue N, SDValue &Reg, SDValue &Shift) {
77 return SelectShiftedRegister(N, true, Reg, Shift);
79 bool SelectAddrModeIndexed7S8(SDValue N, SDValue &Base, SDValue &OffImm) {
80 return SelectAddrModeIndexed7S(N, 1, Base, OffImm);
82 bool SelectAddrModeIndexed7S16(SDValue N, SDValue &Base, SDValue &OffImm) {
83 return SelectAddrModeIndexed7S(N, 2, Base, OffImm);
85 bool SelectAddrModeIndexed7S32(SDValue N, SDValue &Base, SDValue &OffImm) {
86 return SelectAddrModeIndexed7S(N, 4, Base, OffImm);
88 bool SelectAddrModeIndexed7S64(SDValue N, SDValue &Base, SDValue &OffImm) {
89 return SelectAddrModeIndexed7S(N, 8, Base, OffImm);
91 bool SelectAddrModeIndexed7S128(SDValue N, SDValue &Base, SDValue &OffImm) {
92 return SelectAddrModeIndexed7S(N, 16, Base, OffImm);
94 bool SelectAddrModeIndexed8(SDValue N, SDValue &Base, SDValue &OffImm) {
95 return SelectAddrModeIndexed(N, 1, Base, OffImm);
97 bool SelectAddrModeIndexed16(SDValue N, SDValue &Base, SDValue &OffImm) {
98 return SelectAddrModeIndexed(N, 2, Base, OffImm);
100 bool SelectAddrModeIndexed32(SDValue N, SDValue &Base, SDValue &OffImm) {
101 return SelectAddrModeIndexed(N, 4, Base, OffImm);
103 bool SelectAddrModeIndexed64(SDValue N, SDValue &Base, SDValue &OffImm) {
104 return SelectAddrModeIndexed(N, 8, Base, OffImm);
106 bool SelectAddrModeIndexed128(SDValue N, SDValue &Base, SDValue &OffImm) {
107 return SelectAddrModeIndexed(N, 16, Base, OffImm);
109 bool SelectAddrModeUnscaled8(SDValue N, SDValue &Base, SDValue &OffImm) {
110 return SelectAddrModeUnscaled(N, 1, Base, OffImm);
112 bool SelectAddrModeUnscaled16(SDValue N, SDValue &Base, SDValue &OffImm) {
113 return SelectAddrModeUnscaled(N, 2, Base, OffImm);
115 bool SelectAddrModeUnscaled32(SDValue N, SDValue &Base, SDValue &OffImm) {
116 return SelectAddrModeUnscaled(N, 4, Base, OffImm);
118 bool SelectAddrModeUnscaled64(SDValue N, SDValue &Base, SDValue &OffImm) {
119 return SelectAddrModeUnscaled(N, 8, Base, OffImm);
121 bool SelectAddrModeUnscaled128(SDValue N, SDValue &Base, SDValue &OffImm) {
122 return SelectAddrModeUnscaled(N, 16, Base, OffImm);
126 bool SelectAddrModeWRO(SDValue N, SDValue &Base, SDValue &Offset,
127 SDValue &SignExtend, SDValue &DoShift) {
128 return SelectAddrModeWRO(N, Width / 8, Base, Offset, SignExtend, DoShift);
132 bool SelectAddrModeXRO(SDValue N, SDValue &Base, SDValue &Offset,
133 SDValue &SignExtend, SDValue &DoShift) {
134 return SelectAddrModeXRO(N, Width / 8, Base, Offset, SignExtend, DoShift);
138 /// Form sequences of consecutive 64/128-bit registers for use in NEON
139 /// instructions making use of a vector-list (e.g. ldN, tbl). Vecs must have
140 /// between 1 and 4 elements. If it contains a single element that is returned
141 /// unchanged; otherwise a REG_SEQUENCE value is returned.
142 SDValue createDTuple(ArrayRef<SDValue> Vecs);
143 SDValue createQTuple(ArrayRef<SDValue> Vecs);
145 /// Generic helper for the createDTuple/createQTuple
146 /// functions. Those should almost always be called instead.
147 SDValue createTuple(ArrayRef<SDValue> Vecs, const unsigned RegClassIDs[],
148 const unsigned SubRegs[]);
150 void SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, bool isExt);
152 bool tryIndexedLoad(SDNode *N);
154 void SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
156 void SelectPostLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
158 void SelectLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
159 void SelectPostLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
161 void SelectStore(SDNode *N, unsigned NumVecs, unsigned Opc);
162 void SelectPostStore(SDNode *N, unsigned NumVecs, unsigned Opc);
163 void SelectStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
164 void SelectPostStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
166 bool tryBitfieldExtractOp(SDNode *N);
167 bool tryBitfieldExtractOpFromSExt(SDNode *N);
168 bool tryBitfieldInsertOp(SDNode *N);
169 bool tryBitfieldInsertInZeroOp(SDNode *N);
171 bool tryReadRegister(SDNode *N);
172 bool tryWriteRegister(SDNode *N);
174 // Include the pieces autogenerated from the target description.
175 #include "AArch64GenDAGISel.inc"
178 bool SelectShiftedRegister(SDValue N, bool AllowROR, SDValue &Reg,
180 bool SelectAddrModeIndexed7S(SDValue N, unsigned Size, SDValue &Base,
182 bool SelectAddrModeIndexed(SDValue N, unsigned Size, SDValue &Base,
184 bool SelectAddrModeUnscaled(SDValue N, unsigned Size, SDValue &Base,
186 bool SelectAddrModeWRO(SDValue N, unsigned Size, SDValue &Base,
187 SDValue &Offset, SDValue &SignExtend,
189 bool SelectAddrModeXRO(SDValue N, unsigned Size, SDValue &Base,
190 SDValue &Offset, SDValue &SignExtend,
192 bool isWorthFolding(SDValue V) const;
193 bool SelectExtendedSHL(SDValue N, unsigned Size, bool WantExtend,
194 SDValue &Offset, SDValue &SignExtend);
196 template<unsigned RegWidth>
197 bool SelectCVTFixedPosOperand(SDValue N, SDValue &FixedPos) {
198 return SelectCVTFixedPosOperand(N, FixedPos, RegWidth);
201 bool SelectCVTFixedPosOperand(SDValue N, SDValue &FixedPos, unsigned Width);
203 void SelectCMP_SWAP(SDNode *N);
206 } // end anonymous namespace
208 /// isIntImmediate - This method tests to see if the node is a constant
209 /// operand. If so Imm will receive the 32-bit value.
210 static bool isIntImmediate(const SDNode *N, uint64_t &Imm) {
211 if (const ConstantSDNode *C = dyn_cast<const ConstantSDNode>(N)) {
212 Imm = C->getZExtValue();
218 // isIntImmediate - This method tests to see if a constant operand.
219 // If so Imm will receive the value.
220 static bool isIntImmediate(SDValue N, uint64_t &Imm) {
221 return isIntImmediate(N.getNode(), Imm);
224 // isOpcWithIntImmediate - This method tests to see if the node is a specific
225 // opcode and that it has a immediate integer right operand.
226 // If so Imm will receive the 32 bit value.
227 static bool isOpcWithIntImmediate(const SDNode *N, unsigned Opc,
229 return N->getOpcode() == Opc &&
230 isIntImmediate(N->getOperand(1).getNode(), Imm);
233 bool AArch64DAGToDAGISel::SelectInlineAsmMemoryOperand(
234 const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
235 switch(ConstraintID) {
237 llvm_unreachable("Unexpected asm memory constraint");
238 case InlineAsm::Constraint_i:
239 case InlineAsm::Constraint_m:
240 case InlineAsm::Constraint_Q:
241 // Require the address to be in a register. That is safe for all AArch64
242 // variants and it is hard to do anything much smarter without knowing
243 // how the operand is used.
244 OutOps.push_back(Op);
250 /// SelectArithImmed - Select an immediate value that can be represented as
251 /// a 12-bit value shifted left by either 0 or 12. If so, return true with
252 /// Val set to the 12-bit value and Shift set to the shifter operand.
253 bool AArch64DAGToDAGISel::SelectArithImmed(SDValue N, SDValue &Val,
255 // This function is called from the addsub_shifted_imm ComplexPattern,
256 // which lists [imm] as the list of opcode it's interested in, however
257 // we still need to check whether the operand is actually an immediate
258 // here because the ComplexPattern opcode list is only used in
259 // root-level opcode matching.
260 if (!isa<ConstantSDNode>(N.getNode()))
263 uint64_t Immed = cast<ConstantSDNode>(N.getNode())->getZExtValue();
266 if (Immed >> 12 == 0) {
268 } else if ((Immed & 0xfff) == 0 && Immed >> 24 == 0) {
274 unsigned ShVal = AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt);
276 Val = CurDAG->getTargetConstant(Immed, dl, MVT::i32);
277 Shift = CurDAG->getTargetConstant(ShVal, dl, MVT::i32);
281 /// SelectNegArithImmed - As above, but negates the value before trying to
283 bool AArch64DAGToDAGISel::SelectNegArithImmed(SDValue N, SDValue &Val,
285 // This function is called from the addsub_shifted_imm ComplexPattern,
286 // which lists [imm] as the list of opcode it's interested in, however
287 // we still need to check whether the operand is actually an immediate
288 // here because the ComplexPattern opcode list is only used in
289 // root-level opcode matching.
290 if (!isa<ConstantSDNode>(N.getNode()))
293 // The immediate operand must be a 24-bit zero-extended immediate.
294 uint64_t Immed = cast<ConstantSDNode>(N.getNode())->getZExtValue();
296 // This negation is almost always valid, but "cmp wN, #0" and "cmn wN, #0"
297 // have the opposite effect on the C flag, so this pattern mustn't match under
298 // those circumstances.
302 if (N.getValueType() == MVT::i32)
303 Immed = ~((uint32_t)Immed) + 1;
305 Immed = ~Immed + 1ULL;
306 if (Immed & 0xFFFFFFFFFF000000ULL)
309 Immed &= 0xFFFFFFULL;
310 return SelectArithImmed(CurDAG->getConstant(Immed, SDLoc(N), MVT::i32), Val,
314 /// getShiftTypeForNode - Translate a shift node to the corresponding
316 static AArch64_AM::ShiftExtendType getShiftTypeForNode(SDValue N) {
317 switch (N.getOpcode()) {
319 return AArch64_AM::InvalidShiftExtend;
321 return AArch64_AM::LSL;
323 return AArch64_AM::LSR;
325 return AArch64_AM::ASR;
327 return AArch64_AM::ROR;
331 /// \brief Determine whether it is worth it to fold SHL into the addressing
333 static bool isWorthFoldingSHL(SDValue V) {
334 assert(V.getOpcode() == ISD::SHL && "invalid opcode");
335 // It is worth folding logical shift of up to three places.
336 auto *CSD = dyn_cast<ConstantSDNode>(V.getOperand(1));
339 unsigned ShiftVal = CSD->getZExtValue();
343 // Check if this particular node is reused in any non-memory related
344 // operation. If yes, do not try to fold this node into the address
345 // computation, since the computation will be kept.
346 const SDNode *Node = V.getNode();
347 for (SDNode *UI : Node->uses())
348 if (!isa<MemSDNode>(*UI))
349 for (SDNode *UII : UI->uses())
350 if (!isa<MemSDNode>(*UII))
355 /// \brief Determine whether it is worth to fold V into an extended register.
356 bool AArch64DAGToDAGISel::isWorthFolding(SDValue V) const {
357 // Trivial if we are optimizing for code size or if there is only
358 // one use of the value.
359 if (ForCodeSize || V.hasOneUse())
361 // If a subtarget has a fastpath LSL we can fold a logical shift into
362 // the addressing mode and save a cycle.
363 if (Subtarget->hasLSLFast() && V.getOpcode() == ISD::SHL &&
364 isWorthFoldingSHL(V))
366 if (Subtarget->hasLSLFast() && V.getOpcode() == ISD::ADD) {
367 const SDValue LHS = V.getOperand(0);
368 const SDValue RHS = V.getOperand(1);
369 if (LHS.getOpcode() == ISD::SHL && isWorthFoldingSHL(LHS))
371 if (RHS.getOpcode() == ISD::SHL && isWorthFoldingSHL(RHS))
375 // It hurts otherwise, since the value will be reused.
379 /// SelectShiftedRegister - Select a "shifted register" operand. If the value
380 /// is not shifted, set the Shift operand to default of "LSL 0". The logical
381 /// instructions allow the shifted register to be rotated, but the arithmetic
382 /// instructions do not. The AllowROR parameter specifies whether ROR is
384 bool AArch64DAGToDAGISel::SelectShiftedRegister(SDValue N, bool AllowROR,
385 SDValue &Reg, SDValue &Shift) {
386 AArch64_AM::ShiftExtendType ShType = getShiftTypeForNode(N);
387 if (ShType == AArch64_AM::InvalidShiftExtend)
389 if (!AllowROR && ShType == AArch64_AM::ROR)
392 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
393 unsigned BitSize = N.getValueSizeInBits();
394 unsigned Val = RHS->getZExtValue() & (BitSize - 1);
395 unsigned ShVal = AArch64_AM::getShifterImm(ShType, Val);
397 Reg = N.getOperand(0);
398 Shift = CurDAG->getTargetConstant(ShVal, SDLoc(N), MVT::i32);
399 return isWorthFolding(N);
405 /// getExtendTypeForNode - Translate an extend node to the corresponding
406 /// ExtendType value.
407 static AArch64_AM::ShiftExtendType
408 getExtendTypeForNode(SDValue N, bool IsLoadStore = false) {
409 if (N.getOpcode() == ISD::SIGN_EXTEND ||
410 N.getOpcode() == ISD::SIGN_EXTEND_INREG) {
412 if (N.getOpcode() == ISD::SIGN_EXTEND_INREG)
413 SrcVT = cast<VTSDNode>(N.getOperand(1))->getVT();
415 SrcVT = N.getOperand(0).getValueType();
417 if (!IsLoadStore && SrcVT == MVT::i8)
418 return AArch64_AM::SXTB;
419 else if (!IsLoadStore && SrcVT == MVT::i16)
420 return AArch64_AM::SXTH;
421 else if (SrcVT == MVT::i32)
422 return AArch64_AM::SXTW;
423 assert(SrcVT != MVT::i64 && "extend from 64-bits?");
425 return AArch64_AM::InvalidShiftExtend;
426 } else if (N.getOpcode() == ISD::ZERO_EXTEND ||
427 N.getOpcode() == ISD::ANY_EXTEND) {
428 EVT SrcVT = N.getOperand(0).getValueType();
429 if (!IsLoadStore && SrcVT == MVT::i8)
430 return AArch64_AM::UXTB;
431 else if (!IsLoadStore && SrcVT == MVT::i16)
432 return AArch64_AM::UXTH;
433 else if (SrcVT == MVT::i32)
434 return AArch64_AM::UXTW;
435 assert(SrcVT != MVT::i64 && "extend from 64-bits?");
437 return AArch64_AM::InvalidShiftExtend;
438 } else if (N.getOpcode() == ISD::AND) {
439 ConstantSDNode *CSD = dyn_cast<ConstantSDNode>(N.getOperand(1));
441 return AArch64_AM::InvalidShiftExtend;
442 uint64_t AndMask = CSD->getZExtValue();
446 return AArch64_AM::InvalidShiftExtend;
448 return !IsLoadStore ? AArch64_AM::UXTB : AArch64_AM::InvalidShiftExtend;
450 return !IsLoadStore ? AArch64_AM::UXTH : AArch64_AM::InvalidShiftExtend;
452 return AArch64_AM::UXTW;
456 return AArch64_AM::InvalidShiftExtend;
459 // Helper for SelectMLAV64LaneV128 - Recognize high lane extracts.
460 static bool checkHighLaneIndex(SDNode *DL, SDValue &LaneOp, int &LaneIdx) {
461 if (DL->getOpcode() != AArch64ISD::DUPLANE16 &&
462 DL->getOpcode() != AArch64ISD::DUPLANE32)
465 SDValue SV = DL->getOperand(0);
466 if (SV.getOpcode() != ISD::INSERT_SUBVECTOR)
469 SDValue EV = SV.getOperand(1);
470 if (EV.getOpcode() != ISD::EXTRACT_SUBVECTOR)
473 ConstantSDNode *DLidx = cast<ConstantSDNode>(DL->getOperand(1).getNode());
474 ConstantSDNode *EVidx = cast<ConstantSDNode>(EV.getOperand(1).getNode());
475 LaneIdx = DLidx->getSExtValue() + EVidx->getSExtValue();
476 LaneOp = EV.getOperand(0);
481 // Helper for SelectOpcV64LaneV128 - Recognize operations where one operand is a
482 // high lane extract.
483 static bool checkV64LaneV128(SDValue Op0, SDValue Op1, SDValue &StdOp,
484 SDValue &LaneOp, int &LaneIdx) {
486 if (!checkHighLaneIndex(Op0.getNode(), LaneOp, LaneIdx)) {
488 if (!checkHighLaneIndex(Op0.getNode(), LaneOp, LaneIdx))
495 /// SelectMLAV64LaneV128 - AArch64 supports vector MLAs where one multiplicand
496 /// is a lane in the upper half of a 128-bit vector. Recognize and select this
497 /// so that we don't emit unnecessary lane extracts.
498 bool AArch64DAGToDAGISel::tryMLAV64LaneV128(SDNode *N) {
500 SDValue Op0 = N->getOperand(0);
501 SDValue Op1 = N->getOperand(1);
502 SDValue MLAOp1; // Will hold ordinary multiplicand for MLA.
503 SDValue MLAOp2; // Will hold lane-accessed multiplicand for MLA.
504 int LaneIdx = -1; // Will hold the lane index.
506 if (Op1.getOpcode() != ISD::MUL ||
507 !checkV64LaneV128(Op1.getOperand(0), Op1.getOperand(1), MLAOp1, MLAOp2,
510 if (Op1.getOpcode() != ISD::MUL ||
511 !checkV64LaneV128(Op1.getOperand(0), Op1.getOperand(1), MLAOp1, MLAOp2,
516 SDValue LaneIdxVal = CurDAG->getTargetConstant(LaneIdx, dl, MVT::i64);
518 SDValue Ops[] = { Op0, MLAOp1, MLAOp2, LaneIdxVal };
520 unsigned MLAOpc = ~0U;
522 switch (N->getSimpleValueType(0).SimpleTy) {
524 llvm_unreachable("Unrecognized MLA.");
526 MLAOpc = AArch64::MLAv4i16_indexed;
529 MLAOpc = AArch64::MLAv8i16_indexed;
532 MLAOpc = AArch64::MLAv2i32_indexed;
535 MLAOpc = AArch64::MLAv4i32_indexed;
539 ReplaceNode(N, CurDAG->getMachineNode(MLAOpc, dl, N->getValueType(0), Ops));
543 bool AArch64DAGToDAGISel::tryMULLV64LaneV128(unsigned IntNo, SDNode *N) {
549 if (!checkV64LaneV128(N->getOperand(1), N->getOperand(2), SMULLOp0, SMULLOp1,
553 SDValue LaneIdxVal = CurDAG->getTargetConstant(LaneIdx, dl, MVT::i64);
555 SDValue Ops[] = { SMULLOp0, SMULLOp1, LaneIdxVal };
557 unsigned SMULLOpc = ~0U;
559 if (IntNo == Intrinsic::aarch64_neon_smull) {
560 switch (N->getSimpleValueType(0).SimpleTy) {
562 llvm_unreachable("Unrecognized SMULL.");
564 SMULLOpc = AArch64::SMULLv4i16_indexed;
567 SMULLOpc = AArch64::SMULLv2i32_indexed;
570 } else if (IntNo == Intrinsic::aarch64_neon_umull) {
571 switch (N->getSimpleValueType(0).SimpleTy) {
573 llvm_unreachable("Unrecognized SMULL.");
575 SMULLOpc = AArch64::UMULLv4i16_indexed;
578 SMULLOpc = AArch64::UMULLv2i32_indexed;
582 llvm_unreachable("Unrecognized intrinsic.");
584 ReplaceNode(N, CurDAG->getMachineNode(SMULLOpc, dl, N->getValueType(0), Ops));
588 /// Instructions that accept extend modifiers like UXTW expect the register
589 /// being extended to be a GPR32, but the incoming DAG might be acting on a
590 /// GPR64 (either via SEXT_INREG or AND). Extract the appropriate low bits if
591 /// this is the case.
592 static SDValue narrowIfNeeded(SelectionDAG *CurDAG, SDValue N) {
593 if (N.getValueType() == MVT::i32)
597 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32);
598 MachineSDNode *Node = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
599 dl, MVT::i32, N, SubReg);
600 return SDValue(Node, 0);
604 /// SelectArithExtendedRegister - Select a "extended register" operand. This
605 /// operand folds in an extend followed by an optional left shift.
606 bool AArch64DAGToDAGISel::SelectArithExtendedRegister(SDValue N, SDValue &Reg,
608 unsigned ShiftVal = 0;
609 AArch64_AM::ShiftExtendType Ext;
611 if (N.getOpcode() == ISD::SHL) {
612 ConstantSDNode *CSD = dyn_cast<ConstantSDNode>(N.getOperand(1));
615 ShiftVal = CSD->getZExtValue();
619 Ext = getExtendTypeForNode(N.getOperand(0));
620 if (Ext == AArch64_AM::InvalidShiftExtend)
623 Reg = N.getOperand(0).getOperand(0);
625 Ext = getExtendTypeForNode(N);
626 if (Ext == AArch64_AM::InvalidShiftExtend)
629 Reg = N.getOperand(0);
631 // Don't match if free 32-bit -> 64-bit zext can be used instead.
632 if (Ext == AArch64_AM::UXTW &&
633 Reg->getValueType(0).getSizeInBits() == 32 && isDef32(*Reg.getNode()))
637 // AArch64 mandates that the RHS of the operation must use the smallest
638 // register class that could contain the size being extended from. Thus,
639 // if we're folding a (sext i8), we need the RHS to be a GPR32, even though
640 // there might not be an actual 32-bit value in the program. We can
641 // (harmlessly) synthesize one by injected an EXTRACT_SUBREG here.
642 assert(Ext != AArch64_AM::UXTX && Ext != AArch64_AM::SXTX);
643 Reg = narrowIfNeeded(CurDAG, Reg);
644 Shift = CurDAG->getTargetConstant(getArithExtendImm(Ext, ShiftVal), SDLoc(N),
646 return isWorthFolding(N);
649 /// If there's a use of this ADDlow that's not itself a load/store then we'll
650 /// need to create a real ADD instruction from it anyway and there's no point in
651 /// folding it into the mem op. Theoretically, it shouldn't matter, but there's
652 /// a single pseudo-instruction for an ADRP/ADD pair so over-aggressive folding
653 /// leads to duplicated ADRP instructions.
654 static bool isWorthFoldingADDlow(SDValue N) {
655 for (auto Use : N->uses()) {
656 if (Use->getOpcode() != ISD::LOAD && Use->getOpcode() != ISD::STORE &&
657 Use->getOpcode() != ISD::ATOMIC_LOAD &&
658 Use->getOpcode() != ISD::ATOMIC_STORE)
661 // ldar and stlr have much more restrictive addressing modes (just a
663 if (isStrongerThanMonotonic(cast<MemSDNode>(Use)->getOrdering()))
670 /// SelectAddrModeIndexed7S - Select a "register plus scaled signed 7-bit
671 /// immediate" address. The "Size" argument is the size in bytes of the memory
672 /// reference, which determines the scale.
673 bool AArch64DAGToDAGISel::SelectAddrModeIndexed7S(SDValue N, unsigned Size,
677 const DataLayout &DL = CurDAG->getDataLayout();
678 const TargetLowering *TLI = getTargetLowering();
679 if (N.getOpcode() == ISD::FrameIndex) {
680 int FI = cast<FrameIndexSDNode>(N)->getIndex();
681 Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy(DL));
682 OffImm = CurDAG->getTargetConstant(0, dl, MVT::i64);
686 // As opposed to the (12-bit) Indexed addressing mode below, the 7-bit signed
687 // selected here doesn't support labels/immediates, only base+offset.
689 if (CurDAG->isBaseWithConstantOffset(N)) {
690 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
691 int64_t RHSC = RHS->getSExtValue();
692 unsigned Scale = Log2_32(Size);
693 if ((RHSC & (Size - 1)) == 0 && RHSC >= -(0x40 << Scale) &&
694 RHSC < (0x40 << Scale)) {
695 Base = N.getOperand(0);
696 if (Base.getOpcode() == ISD::FrameIndex) {
697 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
698 Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy(DL));
700 OffImm = CurDAG->getTargetConstant(RHSC >> Scale, dl, MVT::i64);
706 // Base only. The address will be materialized into a register before
707 // the memory is accessed.
708 // add x0, Xbase, #offset
711 OffImm = CurDAG->getTargetConstant(0, dl, MVT::i64);
715 /// SelectAddrModeIndexed - Select a "register plus scaled unsigned 12-bit
716 /// immediate" address. The "Size" argument is the size in bytes of the memory
717 /// reference, which determines the scale.
718 bool AArch64DAGToDAGISel::SelectAddrModeIndexed(SDValue N, unsigned Size,
719 SDValue &Base, SDValue &OffImm) {
721 const DataLayout &DL = CurDAG->getDataLayout();
722 const TargetLowering *TLI = getTargetLowering();
723 if (N.getOpcode() == ISD::FrameIndex) {
724 int FI = cast<FrameIndexSDNode>(N)->getIndex();
725 Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy(DL));
726 OffImm = CurDAG->getTargetConstant(0, dl, MVT::i64);
730 if (N.getOpcode() == AArch64ISD::ADDlow && isWorthFoldingADDlow(N)) {
731 GlobalAddressSDNode *GAN =
732 dyn_cast<GlobalAddressSDNode>(N.getOperand(1).getNode());
733 Base = N.getOperand(0);
734 OffImm = N.getOperand(1);
738 const GlobalValue *GV = GAN->getGlobal();
739 unsigned Alignment = GV->getAlignment();
740 Type *Ty = GV->getValueType();
741 if (Alignment == 0 && Ty->isSized())
742 Alignment = DL.getABITypeAlignment(Ty);
744 if (Alignment >= Size)
748 if (CurDAG->isBaseWithConstantOffset(N)) {
749 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
750 int64_t RHSC = (int64_t)RHS->getZExtValue();
751 unsigned Scale = Log2_32(Size);
752 if ((RHSC & (Size - 1)) == 0 && RHSC >= 0 && RHSC < (0x1000 << Scale)) {
753 Base = N.getOperand(0);
754 if (Base.getOpcode() == ISD::FrameIndex) {
755 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
756 Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy(DL));
758 OffImm = CurDAG->getTargetConstant(RHSC >> Scale, dl, MVT::i64);
764 // Before falling back to our general case, check if the unscaled
765 // instructions can handle this. If so, that's preferable.
766 if (SelectAddrModeUnscaled(N, Size, Base, OffImm))
769 // Base only. The address will be materialized into a register before
770 // the memory is accessed.
771 // add x0, Xbase, #offset
774 OffImm = CurDAG->getTargetConstant(0, dl, MVT::i64);
778 /// SelectAddrModeUnscaled - Select a "register plus unscaled signed 9-bit
779 /// immediate" address. This should only match when there is an offset that
780 /// is not valid for a scaled immediate addressing mode. The "Size" argument
781 /// is the size in bytes of the memory reference, which is needed here to know
782 /// what is valid for a scaled immediate.
783 bool AArch64DAGToDAGISel::SelectAddrModeUnscaled(SDValue N, unsigned Size,
786 if (!CurDAG->isBaseWithConstantOffset(N))
788 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
789 int64_t RHSC = RHS->getSExtValue();
790 // If the offset is valid as a scaled immediate, don't match here.
791 if ((RHSC & (Size - 1)) == 0 && RHSC >= 0 &&
792 RHSC < (0x1000 << Log2_32(Size)))
794 if (RHSC >= -256 && RHSC < 256) {
795 Base = N.getOperand(0);
796 if (Base.getOpcode() == ISD::FrameIndex) {
797 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
798 const TargetLowering *TLI = getTargetLowering();
799 Base = CurDAG->getTargetFrameIndex(
800 FI, TLI->getPointerTy(CurDAG->getDataLayout()));
802 OffImm = CurDAG->getTargetConstant(RHSC, SDLoc(N), MVT::i64);
809 static SDValue Widen(SelectionDAG *CurDAG, SDValue N) {
811 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32);
812 SDValue ImpDef = SDValue(
813 CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, MVT::i64), 0);
814 MachineSDNode *Node = CurDAG->getMachineNode(
815 TargetOpcode::INSERT_SUBREG, dl, MVT::i64, ImpDef, N, SubReg);
816 return SDValue(Node, 0);
819 /// \brief Check if the given SHL node (\p N), can be used to form an
820 /// extended register for an addressing mode.
821 bool AArch64DAGToDAGISel::SelectExtendedSHL(SDValue N, unsigned Size,
822 bool WantExtend, SDValue &Offset,
823 SDValue &SignExtend) {
824 assert(N.getOpcode() == ISD::SHL && "Invalid opcode.");
825 ConstantSDNode *CSD = dyn_cast<ConstantSDNode>(N.getOperand(1));
826 if (!CSD || (CSD->getZExtValue() & 0x7) != CSD->getZExtValue())
831 AArch64_AM::ShiftExtendType Ext =
832 getExtendTypeForNode(N.getOperand(0), true);
833 if (Ext == AArch64_AM::InvalidShiftExtend)
836 Offset = narrowIfNeeded(CurDAG, N.getOperand(0).getOperand(0));
837 SignExtend = CurDAG->getTargetConstant(Ext == AArch64_AM::SXTW, dl,
840 Offset = N.getOperand(0);
841 SignExtend = CurDAG->getTargetConstant(0, dl, MVT::i32);
844 unsigned LegalShiftVal = Log2_32(Size);
845 unsigned ShiftVal = CSD->getZExtValue();
847 if (ShiftVal != 0 && ShiftVal != LegalShiftVal)
850 return isWorthFolding(N);
853 bool AArch64DAGToDAGISel::SelectAddrModeWRO(SDValue N, unsigned Size,
854 SDValue &Base, SDValue &Offset,
857 if (N.getOpcode() != ISD::ADD)
859 SDValue LHS = N.getOperand(0);
860 SDValue RHS = N.getOperand(1);
863 // We don't want to match immediate adds here, because they are better lowered
864 // to the register-immediate addressing modes.
865 if (isa<ConstantSDNode>(LHS) || isa<ConstantSDNode>(RHS))
868 // Check if this particular node is reused in any non-memory related
869 // operation. If yes, do not try to fold this node into the address
870 // computation, since the computation will be kept.
871 const SDNode *Node = N.getNode();
872 for (SDNode *UI : Node->uses()) {
873 if (!isa<MemSDNode>(*UI))
877 // Remember if it is worth folding N when it produces extended register.
878 bool IsExtendedRegisterWorthFolding = isWorthFolding(N);
880 // Try to match a shifted extend on the RHS.
881 if (IsExtendedRegisterWorthFolding && RHS.getOpcode() == ISD::SHL &&
882 SelectExtendedSHL(RHS, Size, true, Offset, SignExtend)) {
884 DoShift = CurDAG->getTargetConstant(true, dl, MVT::i32);
888 // Try to match a shifted extend on the LHS.
889 if (IsExtendedRegisterWorthFolding && LHS.getOpcode() == ISD::SHL &&
890 SelectExtendedSHL(LHS, Size, true, Offset, SignExtend)) {
892 DoShift = CurDAG->getTargetConstant(true, dl, MVT::i32);
896 // There was no shift, whatever else we find.
897 DoShift = CurDAG->getTargetConstant(false, dl, MVT::i32);
899 AArch64_AM::ShiftExtendType Ext = AArch64_AM::InvalidShiftExtend;
900 // Try to match an unshifted extend on the LHS.
901 if (IsExtendedRegisterWorthFolding &&
902 (Ext = getExtendTypeForNode(LHS, true)) !=
903 AArch64_AM::InvalidShiftExtend) {
905 Offset = narrowIfNeeded(CurDAG, LHS.getOperand(0));
906 SignExtend = CurDAG->getTargetConstant(Ext == AArch64_AM::SXTW, dl,
908 if (isWorthFolding(LHS))
912 // Try to match an unshifted extend on the RHS.
913 if (IsExtendedRegisterWorthFolding &&
914 (Ext = getExtendTypeForNode(RHS, true)) !=
915 AArch64_AM::InvalidShiftExtend) {
917 Offset = narrowIfNeeded(CurDAG, RHS.getOperand(0));
918 SignExtend = CurDAG->getTargetConstant(Ext == AArch64_AM::SXTW, dl,
920 if (isWorthFolding(RHS))
927 // Check if the given immediate is preferred by ADD. If an immediate can be
928 // encoded in an ADD, or it can be encoded in an "ADD LSL #12" and can not be
929 // encoded by one MOVZ, return true.
930 static bool isPreferredADD(int64_t ImmOff) {
931 // Constant in [0x0, 0xfff] can be encoded in ADD.
932 if ((ImmOff & 0xfffffffffffff000LL) == 0x0LL)
934 // Check if it can be encoded in an "ADD LSL #12".
935 if ((ImmOff & 0xffffffffff000fffLL) == 0x0LL)
936 // As a single MOVZ is faster than a "ADD of LSL #12", ignore such constant.
937 return (ImmOff & 0xffffffffff00ffffLL) != 0x0LL &&
938 (ImmOff & 0xffffffffffff0fffLL) != 0x0LL;
942 bool AArch64DAGToDAGISel::SelectAddrModeXRO(SDValue N, unsigned Size,
943 SDValue &Base, SDValue &Offset,
946 if (N.getOpcode() != ISD::ADD)
948 SDValue LHS = N.getOperand(0);
949 SDValue RHS = N.getOperand(1);
952 // Check if this particular node is reused in any non-memory related
953 // operation. If yes, do not try to fold this node into the address
954 // computation, since the computation will be kept.
955 const SDNode *Node = N.getNode();
956 for (SDNode *UI : Node->uses()) {
957 if (!isa<MemSDNode>(*UI))
961 // Watch out if RHS is a wide immediate, it can not be selected into
962 // [BaseReg+Imm] addressing mode. Also it may not be able to be encoded into
963 // ADD/SUB. Instead it will use [BaseReg + 0] address mode and generate
964 // instructions like:
965 // MOV X0, WideImmediate
966 // ADD X1, BaseReg, X0
968 // For such situation, using [BaseReg, XReg] addressing mode can save one
970 // MOV X0, WideImmediate
971 // LDR X2, [BaseReg, X0]
972 if (isa<ConstantSDNode>(RHS)) {
973 int64_t ImmOff = (int64_t)cast<ConstantSDNode>(RHS)->getZExtValue();
974 unsigned Scale = Log2_32(Size);
975 // Skip the immediate can be selected by load/store addressing mode.
976 // Also skip the immediate can be encoded by a single ADD (SUB is also
977 // checked by using -ImmOff).
978 if ((ImmOff % Size == 0 && ImmOff >= 0 && ImmOff < (0x1000 << Scale)) ||
979 isPreferredADD(ImmOff) || isPreferredADD(-ImmOff))
982 SDValue Ops[] = { RHS };
984 CurDAG->getMachineNode(AArch64::MOVi64imm, DL, MVT::i64, Ops);
985 SDValue MOVIV = SDValue(MOVI, 0);
986 // This ADD of two X register will be selected into [Reg+Reg] mode.
987 N = CurDAG->getNode(ISD::ADD, DL, MVT::i64, LHS, MOVIV);
990 // Remember if it is worth folding N when it produces extended register.
991 bool IsExtendedRegisterWorthFolding = isWorthFolding(N);
993 // Try to match a shifted extend on the RHS.
994 if (IsExtendedRegisterWorthFolding && RHS.getOpcode() == ISD::SHL &&
995 SelectExtendedSHL(RHS, Size, false, Offset, SignExtend)) {
997 DoShift = CurDAG->getTargetConstant(true, DL, MVT::i32);
1001 // Try to match a shifted extend on the LHS.
1002 if (IsExtendedRegisterWorthFolding && LHS.getOpcode() == ISD::SHL &&
1003 SelectExtendedSHL(LHS, Size, false, Offset, SignExtend)) {
1005 DoShift = CurDAG->getTargetConstant(true, DL, MVT::i32);
1009 // Match any non-shifted, non-extend, non-immediate add expression.
1012 SignExtend = CurDAG->getTargetConstant(false, DL, MVT::i32);
1013 DoShift = CurDAG->getTargetConstant(false, DL, MVT::i32);
1014 // Reg1 + Reg2 is free: no check needed.
1018 SDValue AArch64DAGToDAGISel::createDTuple(ArrayRef<SDValue> Regs) {
1019 static const unsigned RegClassIDs[] = {
1020 AArch64::DDRegClassID, AArch64::DDDRegClassID, AArch64::DDDDRegClassID};
1021 static const unsigned SubRegs[] = {AArch64::dsub0, AArch64::dsub1,
1022 AArch64::dsub2, AArch64::dsub3};
1024 return createTuple(Regs, RegClassIDs, SubRegs);
1027 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) {
1028 static const unsigned RegClassIDs[] = {
1029 AArch64::QQRegClassID, AArch64::QQQRegClassID, AArch64::QQQQRegClassID};
1030 static const unsigned SubRegs[] = {AArch64::qsub0, AArch64::qsub1,
1031 AArch64::qsub2, AArch64::qsub3};
1033 return createTuple(Regs, RegClassIDs, SubRegs);
1036 SDValue AArch64DAGToDAGISel::createTuple(ArrayRef<SDValue> Regs,
1037 const unsigned RegClassIDs[],
1038 const unsigned SubRegs[]) {
1039 // There's no special register-class for a vector-list of 1 element: it's just
1041 if (Regs.size() == 1)
1044 assert(Regs.size() >= 2 && Regs.size() <= 4);
1048 SmallVector<SDValue, 4> Ops;
1050 // First operand of REG_SEQUENCE is the desired RegClass.
1052 CurDAG->getTargetConstant(RegClassIDs[Regs.size() - 2], DL, MVT::i32));
1054 // Then we get pairs of source & subregister-position for the components.
1055 for (unsigned i = 0; i < Regs.size(); ++i) {
1056 Ops.push_back(Regs[i]);
1057 Ops.push_back(CurDAG->getTargetConstant(SubRegs[i], DL, MVT::i32));
1061 CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL, MVT::Untyped, Ops);
1062 return SDValue(N, 0);
1065 void AArch64DAGToDAGISel::SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc,
1068 EVT VT = N->getValueType(0);
1070 unsigned ExtOff = isExt;
1072 // Form a REG_SEQUENCE to force register allocation.
1073 unsigned Vec0Off = ExtOff + 1;
1074 SmallVector<SDValue, 4> Regs(N->op_begin() + Vec0Off,
1075 N->op_begin() + Vec0Off + NumVecs);
1076 SDValue RegSeq = createQTuple(Regs);
1078 SmallVector<SDValue, 6> Ops;
1080 Ops.push_back(N->getOperand(1));
1081 Ops.push_back(RegSeq);
1082 Ops.push_back(N->getOperand(NumVecs + ExtOff + 1));
1083 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, VT, Ops));
1086 bool AArch64DAGToDAGISel::tryIndexedLoad(SDNode *N) {
1087 LoadSDNode *LD = cast<LoadSDNode>(N);
1088 if (LD->isUnindexed())
1090 EVT VT = LD->getMemoryVT();
1091 EVT DstVT = N->getValueType(0);
1092 ISD::MemIndexedMode AM = LD->getAddressingMode();
1093 bool IsPre = AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
1095 // We're not doing validity checking here. That was done when checking
1096 // if we should mark the load as indexed or not. We're just selecting
1097 // the right instruction.
1098 unsigned Opcode = 0;
1100 ISD::LoadExtType ExtType = LD->getExtensionType();
1101 bool InsertTo64 = false;
1103 Opcode = IsPre ? AArch64::LDRXpre : AArch64::LDRXpost;
1104 else if (VT == MVT::i32) {
1105 if (ExtType == ISD::NON_EXTLOAD)
1106 Opcode = IsPre ? AArch64::LDRWpre : AArch64::LDRWpost;
1107 else if (ExtType == ISD::SEXTLOAD)
1108 Opcode = IsPre ? AArch64::LDRSWpre : AArch64::LDRSWpost;
1110 Opcode = IsPre ? AArch64::LDRWpre : AArch64::LDRWpost;
1112 // The result of the load is only i32. It's the subreg_to_reg that makes
1116 } else if (VT == MVT::i16) {
1117 if (ExtType == ISD::SEXTLOAD) {
1118 if (DstVT == MVT::i64)
1119 Opcode = IsPre ? AArch64::LDRSHXpre : AArch64::LDRSHXpost;
1121 Opcode = IsPre ? AArch64::LDRSHWpre : AArch64::LDRSHWpost;
1123 Opcode = IsPre ? AArch64::LDRHHpre : AArch64::LDRHHpost;
1124 InsertTo64 = DstVT == MVT::i64;
1125 // The result of the load is only i32. It's the subreg_to_reg that makes
1129 } else if (VT == MVT::i8) {
1130 if (ExtType == ISD::SEXTLOAD) {
1131 if (DstVT == MVT::i64)
1132 Opcode = IsPre ? AArch64::LDRSBXpre : AArch64::LDRSBXpost;
1134 Opcode = IsPre ? AArch64::LDRSBWpre : AArch64::LDRSBWpost;
1136 Opcode = IsPre ? AArch64::LDRBBpre : AArch64::LDRBBpost;
1137 InsertTo64 = DstVT == MVT::i64;
1138 // The result of the load is only i32. It's the subreg_to_reg that makes
1142 } else if (VT == MVT::f16) {
1143 Opcode = IsPre ? AArch64::LDRHpre : AArch64::LDRHpost;
1144 } else if (VT == MVT::f32) {
1145 Opcode = IsPre ? AArch64::LDRSpre : AArch64::LDRSpost;
1146 } else if (VT == MVT::f64 || VT.is64BitVector()) {
1147 Opcode = IsPre ? AArch64::LDRDpre : AArch64::LDRDpost;
1148 } else if (VT.is128BitVector()) {
1149 Opcode = IsPre ? AArch64::LDRQpre : AArch64::LDRQpost;
1152 SDValue Chain = LD->getChain();
1153 SDValue Base = LD->getBasePtr();
1154 ConstantSDNode *OffsetOp = cast<ConstantSDNode>(LD->getOffset());
1155 int OffsetVal = (int)OffsetOp->getZExtValue();
1157 SDValue Offset = CurDAG->getTargetConstant(OffsetVal, dl, MVT::i64);
1158 SDValue Ops[] = { Base, Offset, Chain };
1159 SDNode *Res = CurDAG->getMachineNode(Opcode, dl, MVT::i64, DstVT,
1161 // Either way, we're replacing the node, so tell the caller that.
1162 SDValue LoadedVal = SDValue(Res, 1);
1164 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32);
1166 SDValue(CurDAG->getMachineNode(
1167 AArch64::SUBREG_TO_REG, dl, MVT::i64,
1168 CurDAG->getTargetConstant(0, dl, MVT::i64), LoadedVal,
1173 ReplaceUses(SDValue(N, 0), LoadedVal);
1174 ReplaceUses(SDValue(N, 1), SDValue(Res, 0));
1175 ReplaceUses(SDValue(N, 2), SDValue(Res, 2));
1176 CurDAG->RemoveDeadNode(N);
1180 void AArch64DAGToDAGISel::SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
1181 unsigned SubRegIdx) {
1183 EVT VT = N->getValueType(0);
1184 SDValue Chain = N->getOperand(0);
1186 SDValue Ops[] = {N->getOperand(2), // Mem operand;
1189 const EVT ResTys[] = {MVT::Untyped, MVT::Other};
1191 SDNode *Ld = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
1192 SDValue SuperReg = SDValue(Ld, 0);
1193 for (unsigned i = 0; i < NumVecs; ++i)
1194 ReplaceUses(SDValue(N, i),
1195 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg));
1197 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1));
1199 // Transfer memoperands.
1200 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1201 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1202 cast<MachineSDNode>(Ld)->setMemRefs(MemOp, MemOp + 1);
1204 CurDAG->RemoveDeadNode(N);
1207 void AArch64DAGToDAGISel::SelectPostLoad(SDNode *N, unsigned NumVecs,
1208 unsigned Opc, unsigned SubRegIdx) {
1210 EVT VT = N->getValueType(0);
1211 SDValue Chain = N->getOperand(0);
1213 SDValue Ops[] = {N->getOperand(1), // Mem operand
1214 N->getOperand(2), // Incremental
1217 const EVT ResTys[] = {MVT::i64, // Type of the write back register
1218 MVT::Untyped, MVT::Other};
1220 SDNode *Ld = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
1222 // Update uses of write back register
1223 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0));
1225 // Update uses of vector list
1226 SDValue SuperReg = SDValue(Ld, 1);
1228 ReplaceUses(SDValue(N, 0), SuperReg);
1230 for (unsigned i = 0; i < NumVecs; ++i)
1231 ReplaceUses(SDValue(N, i),
1232 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg));
1235 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(Ld, 2));
1236 CurDAG->RemoveDeadNode(N);
1239 void AArch64DAGToDAGISel::SelectStore(SDNode *N, unsigned NumVecs,
1242 EVT VT = N->getOperand(2)->getValueType(0);
1244 // Form a REG_SEQUENCE to force register allocation.
1245 bool Is128Bit = VT.getSizeInBits() == 128;
1246 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
1247 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs);
1249 SDValue Ops[] = {RegSeq, N->getOperand(NumVecs + 2), N->getOperand(0)};
1250 SDNode *St = CurDAG->getMachineNode(Opc, dl, N->getValueType(0), Ops);
1252 // Transfer memoperands.
1253 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1254 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1255 cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1);
1260 void AArch64DAGToDAGISel::SelectPostStore(SDNode *N, unsigned NumVecs,
1263 EVT VT = N->getOperand(2)->getValueType(0);
1264 const EVT ResTys[] = {MVT::i64, // Type of the write back register
1265 MVT::Other}; // Type for the Chain
1267 // Form a REG_SEQUENCE to force register allocation.
1268 bool Is128Bit = VT.getSizeInBits() == 128;
1269 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);
1270 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs);
1272 SDValue Ops[] = {RegSeq,
1273 N->getOperand(NumVecs + 1), // base register
1274 N->getOperand(NumVecs + 2), // Incremental
1275 N->getOperand(0)}; // Chain
1276 SDNode *St = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
1282 /// WidenVector - Given a value in the V64 register class, produce the
1283 /// equivalent value in the V128 register class.
1288 WidenVector(SelectionDAG &DAG) : DAG(DAG) {}
1290 SDValue operator()(SDValue V64Reg) {
1291 EVT VT = V64Reg.getValueType();
1292 unsigned NarrowSize = VT.getVectorNumElements();
1293 MVT EltTy = VT.getVectorElementType().getSimpleVT();
1294 MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize);
1298 SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, WideTy), 0);
1299 return DAG.getTargetInsertSubreg(AArch64::dsub, DL, WideTy, Undef, V64Reg);
1304 /// NarrowVector - Given a value in the V128 register class, produce the
1305 /// equivalent value in the V64 register class.
1306 static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) {
1307 EVT VT = V128Reg.getValueType();
1308 unsigned WideSize = VT.getVectorNumElements();
1309 MVT EltTy = VT.getVectorElementType().getSimpleVT();
1310 MVT NarrowTy = MVT::getVectorVT(EltTy, WideSize / 2);
1312 return DAG.getTargetExtractSubreg(AArch64::dsub, SDLoc(V128Reg), NarrowTy,
1316 void AArch64DAGToDAGISel::SelectLoadLane(SDNode *N, unsigned NumVecs,
1319 EVT VT = N->getValueType(0);
1320 bool Narrow = VT.getSizeInBits() == 64;
1322 // Form a REG_SEQUENCE to force register allocation.
1323 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
1326 transform(Regs, Regs.begin(),
1327 WidenVector(*CurDAG));
1329 SDValue RegSeq = createQTuple(Regs);
1331 const EVT ResTys[] = {MVT::Untyped, MVT::Other};
1334 cast<ConstantSDNode>(N->getOperand(NumVecs + 2))->getZExtValue();
1336 SDValue Ops[] = {RegSeq, CurDAG->getTargetConstant(LaneNo, dl, MVT::i64),
1337 N->getOperand(NumVecs + 3), N->getOperand(0)};
1338 SDNode *Ld = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
1339 SDValue SuperReg = SDValue(Ld, 0);
1341 EVT WideVT = RegSeq.getOperand(1)->getValueType(0);
1342 static const unsigned QSubs[] = { AArch64::qsub0, AArch64::qsub1,
1343 AArch64::qsub2, AArch64::qsub3 };
1344 for (unsigned i = 0; i < NumVecs; ++i) {
1345 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT, SuperReg);
1347 NV = NarrowVector(NV, *CurDAG);
1348 ReplaceUses(SDValue(N, i), NV);
1351 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1));
1352 CurDAG->RemoveDeadNode(N);
1355 void AArch64DAGToDAGISel::SelectPostLoadLane(SDNode *N, unsigned NumVecs,
1358 EVT VT = N->getValueType(0);
1359 bool Narrow = VT.getSizeInBits() == 64;
1361 // Form a REG_SEQUENCE to force register allocation.
1362 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);
1365 transform(Regs, Regs.begin(),
1366 WidenVector(*CurDAG));
1368 SDValue RegSeq = createQTuple(Regs);
1370 const EVT ResTys[] = {MVT::i64, // Type of the write back register
1371 RegSeq->getValueType(0), MVT::Other};
1374 cast<ConstantSDNode>(N->getOperand(NumVecs + 1))->getZExtValue();
1376 SDValue Ops[] = {RegSeq,
1377 CurDAG->getTargetConstant(LaneNo, dl,
1378 MVT::i64), // Lane Number
1379 N->getOperand(NumVecs + 2), // Base register
1380 N->getOperand(NumVecs + 3), // Incremental
1382 SDNode *Ld = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
1384 // Update uses of the write back register
1385 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0));
1387 // Update uses of the vector list
1388 SDValue SuperReg = SDValue(Ld, 1);
1390 ReplaceUses(SDValue(N, 0),
1391 Narrow ? NarrowVector(SuperReg, *CurDAG) : SuperReg);
1393 EVT WideVT = RegSeq.getOperand(1)->getValueType(0);
1394 static const unsigned QSubs[] = { AArch64::qsub0, AArch64::qsub1,
1395 AArch64::qsub2, AArch64::qsub3 };
1396 for (unsigned i = 0; i < NumVecs; ++i) {
1397 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT,
1400 NV = NarrowVector(NV, *CurDAG);
1401 ReplaceUses(SDValue(N, i), NV);
1406 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(Ld, 2));
1407 CurDAG->RemoveDeadNode(N);
1410 void AArch64DAGToDAGISel::SelectStoreLane(SDNode *N, unsigned NumVecs,
1413 EVT VT = N->getOperand(2)->getValueType(0);
1414 bool Narrow = VT.getSizeInBits() == 64;
1416 // Form a REG_SEQUENCE to force register allocation.
1417 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
1420 transform(Regs, Regs.begin(),
1421 WidenVector(*CurDAG));
1423 SDValue RegSeq = createQTuple(Regs);
1426 cast<ConstantSDNode>(N->getOperand(NumVecs + 2))->getZExtValue();
1428 SDValue Ops[] = {RegSeq, CurDAG->getTargetConstant(LaneNo, dl, MVT::i64),
1429 N->getOperand(NumVecs + 3), N->getOperand(0)};
1430 SDNode *St = CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops);
1432 // Transfer memoperands.
1433 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1434 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1435 cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1);
1440 void AArch64DAGToDAGISel::SelectPostStoreLane(SDNode *N, unsigned NumVecs,
1443 EVT VT = N->getOperand(2)->getValueType(0);
1444 bool Narrow = VT.getSizeInBits() == 64;
1446 // Form a REG_SEQUENCE to force register allocation.
1447 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);
1450 transform(Regs, Regs.begin(),
1451 WidenVector(*CurDAG));
1453 SDValue RegSeq = createQTuple(Regs);
1455 const EVT ResTys[] = {MVT::i64, // Type of the write back register
1459 cast<ConstantSDNode>(N->getOperand(NumVecs + 1))->getZExtValue();
1461 SDValue Ops[] = {RegSeq, CurDAG->getTargetConstant(LaneNo, dl, MVT::i64),
1462 N->getOperand(NumVecs + 2), // Base Register
1463 N->getOperand(NumVecs + 3), // Incremental
1465 SDNode *St = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
1467 // Transfer memoperands.
1468 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1469 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1470 cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1);
1475 static bool isBitfieldExtractOpFromAnd(SelectionDAG *CurDAG, SDNode *N,
1476 unsigned &Opc, SDValue &Opd0,
1477 unsigned &LSB, unsigned &MSB,
1478 unsigned NumberOfIgnoredLowBits,
1479 bool BiggerPattern) {
1480 assert(N->getOpcode() == ISD::AND &&
1481 "N must be a AND operation to call this function");
1483 EVT VT = N->getValueType(0);
1485 // Here we can test the type of VT and return false when the type does not
1486 // match, but since it is done prior to that call in the current context
1487 // we turned that into an assert to avoid redundant code.
1488 assert((VT == MVT::i32 || VT == MVT::i64) &&
1489 "Type checking must have been done before calling this function");
1491 // FIXME: simplify-demanded-bits in DAGCombine will probably have
1492 // changed the AND node to a 32-bit mask operation. We'll have to
1493 // undo that as part of the transform here if we want to catch all
1494 // the opportunities.
1495 // Currently the NumberOfIgnoredLowBits argument helps to recover
1496 // form these situations when matching bigger pattern (bitfield insert).
1498 // For unsigned extracts, check for a shift right and mask
1499 uint64_t AndImm = 0;
1500 if (!isOpcWithIntImmediate(N, ISD::AND, AndImm))
1503 const SDNode *Op0 = N->getOperand(0).getNode();
1505 // Because of simplify-demanded-bits in DAGCombine, the mask may have been
1506 // simplified. Try to undo that
1507 AndImm |= (1 << NumberOfIgnoredLowBits) - 1;
1509 // The immediate is a mask of the low bits iff imm & (imm+1) == 0
1510 if (AndImm & (AndImm + 1))
1513 bool ClampMSB = false;
1514 uint64_t SrlImm = 0;
1515 // Handle the SRL + ANY_EXTEND case.
1516 if (VT == MVT::i64 && Op0->getOpcode() == ISD::ANY_EXTEND &&
1517 isOpcWithIntImmediate(Op0->getOperand(0).getNode(), ISD::SRL, SrlImm)) {
1518 // Extend the incoming operand of the SRL to 64-bit.
1519 Opd0 = Widen(CurDAG, Op0->getOperand(0).getOperand(0));
1520 // Make sure to clamp the MSB so that we preserve the semantics of the
1521 // original operations.
1523 } else if (VT == MVT::i32 && Op0->getOpcode() == ISD::TRUNCATE &&
1524 isOpcWithIntImmediate(Op0->getOperand(0).getNode(), ISD::SRL,
1526 // If the shift result was truncated, we can still combine them.
1527 Opd0 = Op0->getOperand(0).getOperand(0);
1529 // Use the type of SRL node.
1530 VT = Opd0->getValueType(0);
1531 } else if (isOpcWithIntImmediate(Op0, ISD::SRL, SrlImm)) {
1532 Opd0 = Op0->getOperand(0);
1533 } else if (BiggerPattern) {
1534 // Let's pretend a 0 shift right has been performed.
1535 // The resulting code will be at least as good as the original one
1536 // plus it may expose more opportunities for bitfield insert pattern.
1537 // FIXME: Currently we limit this to the bigger pattern, because
1538 // some optimizations expect AND and not UBFM.
1539 Opd0 = N->getOperand(0);
1543 // Bail out on large immediates. This happens when no proper
1544 // combining/constant folding was performed.
1545 if (!BiggerPattern && (SrlImm <= 0 || SrlImm >= VT.getSizeInBits())) {
1547 << ": Found large shift immediate, this should not happen\n"));
1552 MSB = SrlImm + (VT == MVT::i32 ? countTrailingOnes<uint32_t>(AndImm)
1553 : countTrailingOnes<uint64_t>(AndImm)) -
1556 // Since we're moving the extend before the right shift operation, we need
1557 // to clamp the MSB to make sure we don't shift in undefined bits instead of
1558 // the zeros which would get shifted in with the original right shift
1560 MSB = MSB > 31 ? 31 : MSB;
1562 Opc = VT == MVT::i32 ? AArch64::UBFMWri : AArch64::UBFMXri;
1566 static bool isBitfieldExtractOpFromSExtInReg(SDNode *N, unsigned &Opc,
1567 SDValue &Opd0, unsigned &Immr,
1569 assert(N->getOpcode() == ISD::SIGN_EXTEND_INREG);
1571 EVT VT = N->getValueType(0);
1572 unsigned BitWidth = VT.getSizeInBits();
1573 assert((VT == MVT::i32 || VT == MVT::i64) &&
1574 "Type checking must have been done before calling this function");
1576 SDValue Op = N->getOperand(0);
1577 if (Op->getOpcode() == ISD::TRUNCATE) {
1578 Op = Op->getOperand(0);
1579 VT = Op->getValueType(0);
1580 BitWidth = VT.getSizeInBits();
1584 if (!isOpcWithIntImmediate(Op.getNode(), ISD::SRL, ShiftImm) &&
1585 !isOpcWithIntImmediate(Op.getNode(), ISD::SRA, ShiftImm))
1588 unsigned Width = cast<VTSDNode>(N->getOperand(1))->getVT().getSizeInBits();
1589 if (ShiftImm + Width > BitWidth)
1592 Opc = (VT == MVT::i32) ? AArch64::SBFMWri : AArch64::SBFMXri;
1593 Opd0 = Op.getOperand(0);
1595 Imms = ShiftImm + Width - 1;
1599 static bool isSeveralBitsExtractOpFromShr(SDNode *N, unsigned &Opc,
1600 SDValue &Opd0, unsigned &LSB,
1602 // We are looking for the following pattern which basically extracts several
1603 // continuous bits from the source value and places it from the LSB of the
1604 // destination value, all other bits of the destination value or set to zero:
1606 // Value2 = AND Value, MaskImm
1607 // SRL Value2, ShiftImm
1609 // with MaskImm >> ShiftImm to search for the bit width.
1611 // This gets selected into a single UBFM:
1613 // UBFM Value, ShiftImm, BitWide + SrlImm -1
1616 if (N->getOpcode() != ISD::SRL)
1619 uint64_t AndMask = 0;
1620 if (!isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, AndMask))
1623 Opd0 = N->getOperand(0).getOperand(0);
1625 uint64_t SrlImm = 0;
1626 if (!isIntImmediate(N->getOperand(1), SrlImm))
1629 // Check whether we really have several bits extract here.
1630 unsigned BitWide = 64 - countLeadingOnes(~(AndMask >> SrlImm));
1631 if (BitWide && isMask_64(AndMask >> SrlImm)) {
1632 if (N->getValueType(0) == MVT::i32)
1633 Opc = AArch64::UBFMWri;
1635 Opc = AArch64::UBFMXri;
1638 MSB = BitWide + SrlImm - 1;
1645 static bool isBitfieldExtractOpFromShr(SDNode *N, unsigned &Opc, SDValue &Opd0,
1646 unsigned &Immr, unsigned &Imms,
1647 bool BiggerPattern) {
1648 assert((N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL) &&
1649 "N must be a SHR/SRA operation to call this function");
1651 EVT VT = N->getValueType(0);
1653 // Here we can test the type of VT and return false when the type does not
1654 // match, but since it is done prior to that call in the current context
1655 // we turned that into an assert to avoid redundant code.
1656 assert((VT == MVT::i32 || VT == MVT::i64) &&
1657 "Type checking must have been done before calling this function");
1659 // Check for AND + SRL doing several bits extract.
1660 if (isSeveralBitsExtractOpFromShr(N, Opc, Opd0, Immr, Imms))
1663 // We're looking for a shift of a shift.
1664 uint64_t ShlImm = 0;
1665 uint64_t TruncBits = 0;
1666 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, ShlImm)) {
1667 Opd0 = N->getOperand(0).getOperand(0);
1668 } else if (VT == MVT::i32 && N->getOpcode() == ISD::SRL &&
1669 N->getOperand(0).getNode()->getOpcode() == ISD::TRUNCATE) {
1670 // We are looking for a shift of truncate. Truncate from i64 to i32 could
1671 // be considered as setting high 32 bits as zero. Our strategy here is to
1672 // always generate 64bit UBFM. This consistency will help the CSE pass
1673 // later find more redundancy.
1674 Opd0 = N->getOperand(0).getOperand(0);
1675 TruncBits = Opd0->getValueType(0).getSizeInBits() - VT.getSizeInBits();
1676 VT = Opd0->getValueType(0);
1677 assert(VT == MVT::i64 && "the promoted type should be i64");
1678 } else if (BiggerPattern) {
1679 // Let's pretend a 0 shift left has been performed.
1680 // FIXME: Currently we limit this to the bigger pattern case,
1681 // because some optimizations expect AND and not UBFM
1682 Opd0 = N->getOperand(0);
1686 // Missing combines/constant folding may have left us with strange
1688 if (ShlImm >= VT.getSizeInBits()) {
1690 << ": Found large shift immediate, this should not happen\n"));
1694 uint64_t SrlImm = 0;
1695 if (!isIntImmediate(N->getOperand(1), SrlImm))
1698 assert(SrlImm > 0 && SrlImm < VT.getSizeInBits() &&
1699 "bad amount in shift node!");
1700 int immr = SrlImm - ShlImm;
1701 Immr = immr < 0 ? immr + VT.getSizeInBits() : immr;
1702 Imms = VT.getSizeInBits() - ShlImm - TruncBits - 1;
1703 // SRA requires a signed extraction
1705 Opc = N->getOpcode() == ISD::SRA ? AArch64::SBFMWri : AArch64::UBFMWri;
1707 Opc = N->getOpcode() == ISD::SRA ? AArch64::SBFMXri : AArch64::UBFMXri;
1711 bool AArch64DAGToDAGISel::tryBitfieldExtractOpFromSExt(SDNode *N) {
1712 assert(N->getOpcode() == ISD::SIGN_EXTEND);
1714 EVT VT = N->getValueType(0);
1715 EVT NarrowVT = N->getOperand(0)->getValueType(0);
1716 if (VT != MVT::i64 || NarrowVT != MVT::i32)
1720 SDValue Op = N->getOperand(0);
1721 if (!isOpcWithIntImmediate(Op.getNode(), ISD::SRA, ShiftImm))
1725 // Extend the incoming operand of the shift to 64-bits.
1726 SDValue Opd0 = Widen(CurDAG, Op.getOperand(0));
1727 unsigned Immr = ShiftImm;
1728 unsigned Imms = NarrowVT.getSizeInBits() - 1;
1729 SDValue Ops[] = {Opd0, CurDAG->getTargetConstant(Immr, dl, VT),
1730 CurDAG->getTargetConstant(Imms, dl, VT)};
1731 CurDAG->SelectNodeTo(N, AArch64::SBFMXri, VT, Ops);
1735 static bool isBitfieldExtractOp(SelectionDAG *CurDAG, SDNode *N, unsigned &Opc,
1736 SDValue &Opd0, unsigned &Immr, unsigned &Imms,
1737 unsigned NumberOfIgnoredLowBits = 0,
1738 bool BiggerPattern = false) {
1739 if (N->getValueType(0) != MVT::i32 && N->getValueType(0) != MVT::i64)
1742 switch (N->getOpcode()) {
1744 if (!N->isMachineOpcode())
1748 return isBitfieldExtractOpFromAnd(CurDAG, N, Opc, Opd0, Immr, Imms,
1749 NumberOfIgnoredLowBits, BiggerPattern);
1752 return isBitfieldExtractOpFromShr(N, Opc, Opd0, Immr, Imms, BiggerPattern);
1754 case ISD::SIGN_EXTEND_INREG:
1755 return isBitfieldExtractOpFromSExtInReg(N, Opc, Opd0, Immr, Imms);
1758 unsigned NOpc = N->getMachineOpcode();
1762 case AArch64::SBFMWri:
1763 case AArch64::UBFMWri:
1764 case AArch64::SBFMXri:
1765 case AArch64::UBFMXri:
1767 Opd0 = N->getOperand(0);
1768 Immr = cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
1769 Imms = cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
1776 bool AArch64DAGToDAGISel::tryBitfieldExtractOp(SDNode *N) {
1777 unsigned Opc, Immr, Imms;
1779 if (!isBitfieldExtractOp(CurDAG, N, Opc, Opd0, Immr, Imms))
1782 EVT VT = N->getValueType(0);
1785 // If the bit extract operation is 64bit but the original type is 32bit, we
1786 // need to add one EXTRACT_SUBREG.
1787 if ((Opc == AArch64::SBFMXri || Opc == AArch64::UBFMXri) && VT == MVT::i32) {
1788 SDValue Ops64[] = {Opd0, CurDAG->getTargetConstant(Immr, dl, MVT::i64),
1789 CurDAG->getTargetConstant(Imms, dl, MVT::i64)};
1791 SDNode *BFM = CurDAG->getMachineNode(Opc, dl, MVT::i64, Ops64);
1792 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32);
1793 ReplaceNode(N, CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl,
1794 MVT::i32, SDValue(BFM, 0), SubReg));
1798 SDValue Ops[] = {Opd0, CurDAG->getTargetConstant(Immr, dl, VT),
1799 CurDAG->getTargetConstant(Imms, dl, VT)};
1800 CurDAG->SelectNodeTo(N, Opc, VT, Ops);
1804 /// Does DstMask form a complementary pair with the mask provided by
1805 /// BitsToBeInserted, suitable for use in a BFI instruction. Roughly speaking,
1806 /// this asks whether DstMask zeroes precisely those bits that will be set by
1808 static bool isBitfieldDstMask(uint64_t DstMask, const APInt &BitsToBeInserted,
1809 unsigned NumberOfIgnoredHighBits, EVT VT) {
1810 assert((VT == MVT::i32 || VT == MVT::i64) &&
1811 "i32 or i64 mask type expected!");
1812 unsigned BitWidth = VT.getSizeInBits() - NumberOfIgnoredHighBits;
1814 APInt SignificantDstMask = APInt(BitWidth, DstMask);
1815 APInt SignificantBitsToBeInserted = BitsToBeInserted.zextOrTrunc(BitWidth);
1817 return (SignificantDstMask & SignificantBitsToBeInserted) == 0 &&
1818 (SignificantDstMask | SignificantBitsToBeInserted).isAllOnesValue();
1821 // Look for bits that will be useful for later uses.
1822 // A bit is consider useless as soon as it is dropped and never used
1823 // before it as been dropped.
1824 // E.g., looking for useful bit of x
1827 // After #1, x useful bits are 0x7, then the useful bits of x, live through
1829 // After #2, the useful bits of x are 0x4.
1830 // However, if x is used on an unpredicatable instruction, then all its bits
1836 static void getUsefulBits(SDValue Op, APInt &UsefulBits, unsigned Depth = 0);
1838 static void getUsefulBitsFromAndWithImmediate(SDValue Op, APInt &UsefulBits,
1841 cast<const ConstantSDNode>(Op.getOperand(1).getNode())->getZExtValue();
1842 Imm = AArch64_AM::decodeLogicalImmediate(Imm, UsefulBits.getBitWidth());
1843 UsefulBits &= APInt(UsefulBits.getBitWidth(), Imm);
1844 getUsefulBits(Op, UsefulBits, Depth + 1);
1847 static void getUsefulBitsFromBitfieldMoveOpd(SDValue Op, APInt &UsefulBits,
1848 uint64_t Imm, uint64_t MSB,
1850 // inherit the bitwidth value
1851 APInt OpUsefulBits(UsefulBits);
1855 OpUsefulBits = OpUsefulBits.shl(MSB - Imm + 1);
1857 // The interesting part will be in the lower part of the result
1858 getUsefulBits(Op, OpUsefulBits, Depth + 1);
1859 // The interesting part was starting at Imm in the argument
1860 OpUsefulBits = OpUsefulBits.shl(Imm);
1862 OpUsefulBits = OpUsefulBits.shl(MSB + 1);
1864 // The interesting part will be shifted in the result
1865 OpUsefulBits = OpUsefulBits.shl(OpUsefulBits.getBitWidth() - Imm);
1866 getUsefulBits(Op, OpUsefulBits, Depth + 1);
1867 // The interesting part was at zero in the argument
1868 OpUsefulBits = OpUsefulBits.lshr(OpUsefulBits.getBitWidth() - Imm);
1871 UsefulBits &= OpUsefulBits;
1874 static void getUsefulBitsFromUBFM(SDValue Op, APInt &UsefulBits,
1877 cast<const ConstantSDNode>(Op.getOperand(1).getNode())->getZExtValue();
1879 cast<const ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue();
1881 getUsefulBitsFromBitfieldMoveOpd(Op, UsefulBits, Imm, MSB, Depth);
1884 static void getUsefulBitsFromOrWithShiftedReg(SDValue Op, APInt &UsefulBits,
1886 uint64_t ShiftTypeAndValue =
1887 cast<const ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue();
1888 APInt Mask(UsefulBits);
1889 Mask.clearAllBits();
1892 if (AArch64_AM::getShiftType(ShiftTypeAndValue) == AArch64_AM::LSL) {
1894 uint64_t ShiftAmt = AArch64_AM::getShiftValue(ShiftTypeAndValue);
1895 Mask = Mask.shl(ShiftAmt);
1896 getUsefulBits(Op, Mask, Depth + 1);
1897 Mask = Mask.lshr(ShiftAmt);
1898 } else if (AArch64_AM::getShiftType(ShiftTypeAndValue) == AArch64_AM::LSR) {
1900 // We do not handle AArch64_AM::ASR, because the sign will change the
1901 // number of useful bits
1902 uint64_t ShiftAmt = AArch64_AM::getShiftValue(ShiftTypeAndValue);
1903 Mask = Mask.lshr(ShiftAmt);
1904 getUsefulBits(Op, Mask, Depth + 1);
1905 Mask = Mask.shl(ShiftAmt);
1912 static void getUsefulBitsFromBFM(SDValue Op, SDValue Orig, APInt &UsefulBits,
1915 cast<const ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue();
1917 cast<const ConstantSDNode>(Op.getOperand(3).getNode())->getZExtValue();
1919 APInt OpUsefulBits(UsefulBits);
1922 APInt ResultUsefulBits(UsefulBits.getBitWidth(), 0);
1923 ResultUsefulBits.flipAllBits();
1924 APInt Mask(UsefulBits.getBitWidth(), 0);
1926 getUsefulBits(Op, ResultUsefulBits, Depth + 1);
1929 // The instruction is a BFXIL.
1930 uint64_t Width = MSB - Imm + 1;
1933 OpUsefulBits = OpUsefulBits.shl(Width);
1936 if (Op.getOperand(1) == Orig) {
1937 // Copy the low bits from the result to bits starting from LSB.
1938 Mask = ResultUsefulBits & OpUsefulBits;
1939 Mask = Mask.shl(LSB);
1942 if (Op.getOperand(0) == Orig)
1943 // Bits starting from LSB in the input contribute to the result.
1944 Mask |= (ResultUsefulBits & ~OpUsefulBits);
1946 // The instruction is a BFI.
1947 uint64_t Width = MSB + 1;
1948 uint64_t LSB = UsefulBits.getBitWidth() - Imm;
1950 OpUsefulBits = OpUsefulBits.shl(Width);
1952 OpUsefulBits = OpUsefulBits.shl(LSB);
1954 if (Op.getOperand(1) == Orig) {
1955 // Copy the bits from the result to the zero bits.
1956 Mask = ResultUsefulBits & OpUsefulBits;
1957 Mask = Mask.lshr(LSB);
1960 if (Op.getOperand(0) == Orig)
1961 Mask |= (ResultUsefulBits & ~OpUsefulBits);
1967 static void getUsefulBitsForUse(SDNode *UserNode, APInt &UsefulBits,
1968 SDValue Orig, unsigned Depth) {
1970 // Users of this node should have already been instruction selected
1971 // FIXME: Can we turn that into an assert?
1972 if (!UserNode->isMachineOpcode())
1975 switch (UserNode->getMachineOpcode()) {
1978 case AArch64::ANDSWri:
1979 case AArch64::ANDSXri:
1980 case AArch64::ANDWri:
1981 case AArch64::ANDXri:
1982 // We increment Depth only when we call the getUsefulBits
1983 return getUsefulBitsFromAndWithImmediate(SDValue(UserNode, 0), UsefulBits,
1985 case AArch64::UBFMWri:
1986 case AArch64::UBFMXri:
1987 return getUsefulBitsFromUBFM(SDValue(UserNode, 0), UsefulBits, Depth);
1989 case AArch64::ORRWrs:
1990 case AArch64::ORRXrs:
1991 if (UserNode->getOperand(1) != Orig)
1993 return getUsefulBitsFromOrWithShiftedReg(SDValue(UserNode, 0), UsefulBits,
1995 case AArch64::BFMWri:
1996 case AArch64::BFMXri:
1997 return getUsefulBitsFromBFM(SDValue(UserNode, 0), Orig, UsefulBits, Depth);
1999 case AArch64::STRBBui:
2000 case AArch64::STURBBi:
2001 if (UserNode->getOperand(0) != Orig)
2003 UsefulBits &= APInt(UsefulBits.getBitWidth(), 0xff);
2006 case AArch64::STRHHui:
2007 case AArch64::STURHHi:
2008 if (UserNode->getOperand(0) != Orig)
2010 UsefulBits &= APInt(UsefulBits.getBitWidth(), 0xffff);
2015 static void getUsefulBits(SDValue Op, APInt &UsefulBits, unsigned Depth) {
2018 // Initialize UsefulBits
2020 unsigned Bitwidth = Op.getScalarValueSizeInBits();
2021 // At the beginning, assume every produced bits is useful
2022 UsefulBits = APInt(Bitwidth, 0);
2023 UsefulBits.flipAllBits();
2025 APInt UsersUsefulBits(UsefulBits.getBitWidth(), 0);
2027 for (SDNode *Node : Op.getNode()->uses()) {
2028 // A use cannot produce useful bits
2029 APInt UsefulBitsForUse = APInt(UsefulBits);
2030 getUsefulBitsForUse(Node, UsefulBitsForUse, Op, Depth);
2031 UsersUsefulBits |= UsefulBitsForUse;
2033 // UsefulBits contains the produced bits that are meaningful for the
2034 // current definition, thus a user cannot make a bit meaningful at
2036 UsefulBits &= UsersUsefulBits;
2039 /// Create a machine node performing a notional SHL of Op by ShlAmount. If
2040 /// ShlAmount is negative, do a (logical) right-shift instead. If ShlAmount is
2041 /// 0, return Op unchanged.
2042 static SDValue getLeftShift(SelectionDAG *CurDAG, SDValue Op, int ShlAmount) {
2046 EVT VT = Op.getValueType();
2048 unsigned BitWidth = VT.getSizeInBits();
2049 unsigned UBFMOpc = BitWidth == 32 ? AArch64::UBFMWri : AArch64::UBFMXri;
2052 if (ShlAmount > 0) {
2053 // LSL wD, wN, #Amt == UBFM wD, wN, #32-Amt, #31-Amt
2054 ShiftNode = CurDAG->getMachineNode(
2055 UBFMOpc, dl, VT, Op,
2056 CurDAG->getTargetConstant(BitWidth - ShlAmount, dl, VT),
2057 CurDAG->getTargetConstant(BitWidth - 1 - ShlAmount, dl, VT));
2059 // LSR wD, wN, #Amt == UBFM wD, wN, #Amt, #32-1
2060 assert(ShlAmount < 0 && "expected right shift");
2061 int ShrAmount = -ShlAmount;
2062 ShiftNode = CurDAG->getMachineNode(
2063 UBFMOpc, dl, VT, Op, CurDAG->getTargetConstant(ShrAmount, dl, VT),
2064 CurDAG->getTargetConstant(BitWidth - 1, dl, VT));
2067 return SDValue(ShiftNode, 0);
2070 /// Does this tree qualify as an attempt to move a bitfield into position,
2071 /// essentially "(and (shl VAL, N), Mask)".
2072 static bool isBitfieldPositioningOp(SelectionDAG *CurDAG, SDValue Op,
2074 SDValue &Src, int &ShiftAmount,
2076 EVT VT = Op.getValueType();
2077 unsigned BitWidth = VT.getSizeInBits();
2079 assert(BitWidth == 32 || BitWidth == 64);
2081 APInt KnownZero, KnownOne;
2082 CurDAG->computeKnownBits(Op, KnownZero, KnownOne);
2084 // Non-zero in the sense that they're not provably zero, which is the key
2085 // point if we want to use this value
2086 uint64_t NonZeroBits = (~KnownZero).getZExtValue();
2088 // Discard a constant AND mask if present. It's safe because the node will
2089 // already have been factored into the computeKnownBits calculation above.
2091 if (isOpcWithIntImmediate(Op.getNode(), ISD::AND, AndImm)) {
2092 assert((~APInt(BitWidth, AndImm) & ~KnownZero) == 0);
2093 Op = Op.getOperand(0);
2096 // Don't match if the SHL has more than one use, since then we'll end up
2097 // generating SHL+UBFIZ instead of just keeping SHL+AND.
2098 if (!BiggerPattern && !Op.hasOneUse())
2102 if (!isOpcWithIntImmediate(Op.getNode(), ISD::SHL, ShlImm))
2104 Op = Op.getOperand(0);
2106 if (!isShiftedMask_64(NonZeroBits))
2109 ShiftAmount = countTrailingZeros(NonZeroBits);
2110 MaskWidth = countTrailingOnes(NonZeroBits >> ShiftAmount);
2112 // BFI encompasses sufficiently many nodes that it's worth inserting an extra
2113 // LSL/LSR if the mask in NonZeroBits doesn't quite match up with the ISD::SHL
2114 // amount. BiggerPattern is true when this pattern is being matched for BFI,
2115 // BiggerPattern is false when this pattern is being matched for UBFIZ, in
2116 // which case it is not profitable to insert an extra shift.
2117 if (ShlImm - ShiftAmount != 0 && !BiggerPattern)
2119 Src = getLeftShift(CurDAG, Op, ShlImm - ShiftAmount);
2124 static bool isShiftedMask(uint64_t Mask, EVT VT) {
2125 assert(VT == MVT::i32 || VT == MVT::i64);
2127 return isShiftedMask_32(Mask);
2128 return isShiftedMask_64(Mask);
2131 // Generate a BFI/BFXIL from 'or (and X, MaskImm), OrImm' iff the value being
2132 // inserted only sets known zero bits.
2133 static bool tryBitfieldInsertOpFromOrAndImm(SDNode *N, SelectionDAG *CurDAG) {
2134 assert(N->getOpcode() == ISD::OR && "Expect a OR operation");
2136 EVT VT = N->getValueType(0);
2137 if (VT != MVT::i32 && VT != MVT::i64)
2140 unsigned BitWidth = VT.getSizeInBits();
2143 if (!isOpcWithIntImmediate(N, ISD::OR, OrImm))
2146 // Skip this transformation if the ORR immediate can be encoded in the ORR.
2147 // Otherwise, we'll trade an AND+ORR for ORR+BFI/BFXIL, which is most likely
2148 // performance neutral.
2149 if (AArch64_AM::isLogicalImmediate(OrImm, BitWidth))
2153 SDValue And = N->getOperand(0);
2154 // Must be a single use AND with an immediate operand.
2155 if (!And.hasOneUse() ||
2156 !isOpcWithIntImmediate(And.getNode(), ISD::AND, MaskImm))
2159 // Compute the Known Zero for the AND as this allows us to catch more general
2160 // cases than just looking for AND with imm.
2161 APInt KnownZero, KnownOne;
2162 CurDAG->computeKnownBits(And, KnownZero, KnownOne);
2164 // Non-zero in the sense that they're not provably zero, which is the key
2165 // point if we want to use this value.
2166 uint64_t NotKnownZero = (~KnownZero).getZExtValue();
2168 // The KnownZero mask must be a shifted mask (e.g., 1110..011, 11100..00).
2169 if (!isShiftedMask(KnownZero.getZExtValue(), VT))
2172 // The bits being inserted must only set those bits that are known to be zero.
2173 if ((OrImm & NotKnownZero) != 0) {
2174 // FIXME: It's okay if the OrImm sets NotKnownZero bits to 1, but we don't
2175 // currently handle this case.
2179 // BFI/BFXIL dst, src, #lsb, #width.
2180 int LSB = countTrailingOnes(NotKnownZero);
2181 int Width = BitWidth - APInt(BitWidth, NotKnownZero).countPopulation();
2183 // BFI/BFXIL is an alias of BFM, so translate to BFM operands.
2184 unsigned ImmR = (BitWidth - LSB) % BitWidth;
2185 unsigned ImmS = Width - 1;
2187 // If we're creating a BFI instruction avoid cases where we need more
2188 // instructions to materialize the BFI constant as compared to the original
2189 // ORR. A BFXIL will use the same constant as the original ORR, so the code
2190 // should be no worse in this case.
2191 bool IsBFI = LSB != 0;
2192 uint64_t BFIImm = OrImm >> LSB;
2193 if (IsBFI && !AArch64_AM::isLogicalImmediate(BFIImm, BitWidth)) {
2194 // We have a BFI instruction and we know the constant can't be materialized
2195 // with a ORR-immediate with the zero register.
2196 unsigned OrChunks = 0, BFIChunks = 0;
2197 for (unsigned Shift = 0; Shift < BitWidth; Shift += 16) {
2198 if (((OrImm >> Shift) & 0xFFFF) != 0)
2200 if (((BFIImm >> Shift) & 0xFFFF) != 0)
2203 if (BFIChunks > OrChunks)
2207 // Materialize the constant to be inserted.
2209 unsigned MOVIOpc = VT == MVT::i32 ? AArch64::MOVi32imm : AArch64::MOVi64imm;
2210 SDNode *MOVI = CurDAG->getMachineNode(
2211 MOVIOpc, DL, VT, CurDAG->getTargetConstant(BFIImm, DL, VT));
2213 // Create the BFI/BFXIL instruction.
2214 SDValue Ops[] = {And.getOperand(0), SDValue(MOVI, 0),
2215 CurDAG->getTargetConstant(ImmR, DL, VT),
2216 CurDAG->getTargetConstant(ImmS, DL, VT)};
2217 unsigned Opc = (VT == MVT::i32) ? AArch64::BFMWri : AArch64::BFMXri;
2218 CurDAG->SelectNodeTo(N, Opc, VT, Ops);
2222 static bool tryBitfieldInsertOpFromOr(SDNode *N, const APInt &UsefulBits,
2223 SelectionDAG *CurDAG) {
2224 assert(N->getOpcode() == ISD::OR && "Expect a OR operation");
2226 EVT VT = N->getValueType(0);
2227 if (VT != MVT::i32 && VT != MVT::i64)
2230 unsigned BitWidth = VT.getSizeInBits();
2232 // Because of simplify-demanded-bits in DAGCombine, involved masks may not
2233 // have the expected shape. Try to undo that.
2235 unsigned NumberOfIgnoredLowBits = UsefulBits.countTrailingZeros();
2236 unsigned NumberOfIgnoredHighBits = UsefulBits.countLeadingZeros();
2238 // Given a OR operation, check if we have the following pattern
2239 // ubfm c, b, imm, imm2 (or something that does the same jobs, see
2240 // isBitfieldExtractOp)
2241 // d = e & mask2 ; where mask is a binary sequence of 1..10..0 and
2242 // countTrailingZeros(mask2) == imm2 - imm + 1
2244 // if yes, replace the OR instruction with:
2245 // f = BFM Opd0, Opd1, LSB, MSB ; where LSB = imm, and MSB = imm2
2247 // OR is commutative, check all combinations of operand order and values of
2248 // BiggerPattern, i.e.
2249 // Opd0, Opd1, BiggerPattern=false
2250 // Opd1, Opd0, BiggerPattern=false
2251 // Opd0, Opd1, BiggerPattern=true
2252 // Opd1, Opd0, BiggerPattern=true
2253 // Several of these combinations may match, so check with BiggerPattern=false
2254 // first since that will produce better results by matching more instructions
2255 // and/or inserting fewer extra instructions.
2256 for (int I = 0; I < 4; ++I) {
2259 unsigned ImmR, ImmS;
2260 bool BiggerPattern = I / 2;
2261 SDValue OrOpd0Val = N->getOperand(I % 2);
2262 SDNode *OrOpd0 = OrOpd0Val.getNode();
2263 SDValue OrOpd1Val = N->getOperand((I + 1) % 2);
2264 SDNode *OrOpd1 = OrOpd1Val.getNode();
2268 if (isBitfieldExtractOp(CurDAG, OrOpd0, BFXOpc, Src, ImmR, ImmS,
2269 NumberOfIgnoredLowBits, BiggerPattern)) {
2270 // Check that the returned opcode is compatible with the pattern,
2271 // i.e., same type and zero extended (U and not S)
2272 if ((BFXOpc != AArch64::UBFMXri && VT == MVT::i64) ||
2273 (BFXOpc != AArch64::UBFMWri && VT == MVT::i32))
2276 // Compute the width of the bitfield insertion
2278 Width = ImmS - ImmR + 1;
2279 // FIXME: This constraint is to catch bitfield insertion we may
2280 // want to widen the pattern if we want to grab general bitfied
2285 // If the mask on the insertee is correct, we have a BFXIL operation. We
2286 // can share the ImmR and ImmS values from the already-computed UBFM.
2287 } else if (isBitfieldPositioningOp(CurDAG, OrOpd0Val,
2289 Src, DstLSB, Width)) {
2290 ImmR = (BitWidth - DstLSB) % BitWidth;
2295 // Check the second part of the pattern
2296 EVT VT = OrOpd1->getValueType(0);
2297 assert((VT == MVT::i32 || VT == MVT::i64) && "unexpected OR operand");
2299 // Compute the Known Zero for the candidate of the first operand.
2300 // This allows to catch more general case than just looking for
2301 // AND with imm. Indeed, simplify-demanded-bits may have removed
2302 // the AND instruction because it proves it was useless.
2303 APInt KnownZero, KnownOne;
2304 CurDAG->computeKnownBits(OrOpd1Val, KnownZero, KnownOne);
2306 // Check if there is enough room for the second operand to appear
2308 APInt BitsToBeInserted =
2309 APInt::getBitsSet(KnownZero.getBitWidth(), DstLSB, DstLSB + Width);
2311 if ((BitsToBeInserted & ~KnownZero) != 0)
2314 // Set the first operand
2316 if (isOpcWithIntImmediate(OrOpd1, ISD::AND, Imm) &&
2317 isBitfieldDstMask(Imm, BitsToBeInserted, NumberOfIgnoredHighBits, VT))
2318 // In that case, we can eliminate the AND
2319 Dst = OrOpd1->getOperand(0);
2321 // Maybe the AND has been removed by simplify-demanded-bits
2322 // or is useful because it discards more bits
2327 SDValue Ops[] = {Dst, Src, CurDAG->getTargetConstant(ImmR, DL, VT),
2328 CurDAG->getTargetConstant(ImmS, DL, VT)};
2329 unsigned Opc = (VT == MVT::i32) ? AArch64::BFMWri : AArch64::BFMXri;
2330 CurDAG->SelectNodeTo(N, Opc, VT, Ops);
2334 // Generate a BFXIL from 'or (and X, Mask0Imm), (and Y, Mask1Imm)' iff
2335 // Mask0Imm and ~Mask1Imm are equivalent and one of the MaskImms is a shifted
2336 // mask (e.g., 0x000ffff0).
2337 uint64_t Mask0Imm, Mask1Imm;
2338 SDValue And0 = N->getOperand(0);
2339 SDValue And1 = N->getOperand(1);
2340 if (And0.hasOneUse() && And1.hasOneUse() &&
2341 isOpcWithIntImmediate(And0.getNode(), ISD::AND, Mask0Imm) &&
2342 isOpcWithIntImmediate(And1.getNode(), ISD::AND, Mask1Imm) &&
2343 APInt(BitWidth, Mask0Imm) == ~APInt(BitWidth, Mask1Imm) &&
2344 (isShiftedMask(Mask0Imm, VT) || isShiftedMask(Mask1Imm, VT))) {
2346 // ORR is commutative, so canonicalize to the form 'or (and X, Mask0Imm),
2347 // (and Y, Mask1Imm)' where Mask1Imm is the shifted mask masking off the
2348 // bits to be inserted.
2349 if (isShiftedMask(Mask0Imm, VT)) {
2350 std::swap(And0, And1);
2351 std::swap(Mask0Imm, Mask1Imm);
2354 SDValue Src = And1->getOperand(0);
2355 SDValue Dst = And0->getOperand(0);
2356 unsigned LSB = countTrailingZeros(Mask1Imm);
2357 int Width = BitWidth - APInt(BitWidth, Mask0Imm).countPopulation();
2359 // The BFXIL inserts the low-order bits from a source register, so right
2360 // shift the needed bits into place.
2362 unsigned ShiftOpc = (VT == MVT::i32) ? AArch64::UBFMWri : AArch64::UBFMXri;
2363 SDNode *LSR = CurDAG->getMachineNode(
2364 ShiftOpc, DL, VT, Src, CurDAG->getTargetConstant(LSB, DL, VT),
2365 CurDAG->getTargetConstant(BitWidth - 1, DL, VT));
2367 // BFXIL is an alias of BFM, so translate to BFM operands.
2368 unsigned ImmR = (BitWidth - LSB) % BitWidth;
2369 unsigned ImmS = Width - 1;
2371 // Create the BFXIL instruction.
2372 SDValue Ops[] = {Dst, SDValue(LSR, 0),
2373 CurDAG->getTargetConstant(ImmR, DL, VT),
2374 CurDAG->getTargetConstant(ImmS, DL, VT)};
2375 unsigned Opc = (VT == MVT::i32) ? AArch64::BFMWri : AArch64::BFMXri;
2376 CurDAG->SelectNodeTo(N, Opc, VT, Ops);
2383 bool AArch64DAGToDAGISel::tryBitfieldInsertOp(SDNode *N) {
2384 if (N->getOpcode() != ISD::OR)
2388 getUsefulBits(SDValue(N, 0), NUsefulBits);
2390 // If all bits are not useful, just return UNDEF.
2392 CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF, N->getValueType(0));
2396 if (tryBitfieldInsertOpFromOr(N, NUsefulBits, CurDAG))
2399 return tryBitfieldInsertOpFromOrAndImm(N, CurDAG);
2402 /// SelectBitfieldInsertInZeroOp - Match a UBFIZ instruction that is the
2403 /// equivalent of a left shift by a constant amount followed by an and masking
2404 /// out a contiguous set of bits.
2405 bool AArch64DAGToDAGISel::tryBitfieldInsertInZeroOp(SDNode *N) {
2406 if (N->getOpcode() != ISD::AND)
2409 EVT VT = N->getValueType(0);
2410 if (VT != MVT::i32 && VT != MVT::i64)
2415 if (!isBitfieldPositioningOp(CurDAG, SDValue(N, 0), /*BiggerPattern=*/false,
2416 Op0, DstLSB, Width))
2419 // ImmR is the rotate right amount.
2420 unsigned ImmR = (VT.getSizeInBits() - DstLSB) % VT.getSizeInBits();
2421 // ImmS is the most significant bit of the source to be moved.
2422 unsigned ImmS = Width - 1;
2425 SDValue Ops[] = {Op0, CurDAG->getTargetConstant(ImmR, DL, VT),
2426 CurDAG->getTargetConstant(ImmS, DL, VT)};
2427 unsigned Opc = (VT == MVT::i32) ? AArch64::UBFMWri : AArch64::UBFMXri;
2428 CurDAG->SelectNodeTo(N, Opc, VT, Ops);
2433 AArch64DAGToDAGISel::SelectCVTFixedPosOperand(SDValue N, SDValue &FixedPos,
2434 unsigned RegWidth) {
2436 if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N))
2437 FVal = CN->getValueAPF();
2438 else if (LoadSDNode *LN = dyn_cast<LoadSDNode>(N)) {
2439 // Some otherwise illegal constants are allowed in this case.
2440 if (LN->getOperand(1).getOpcode() != AArch64ISD::ADDlow ||
2441 !isa<ConstantPoolSDNode>(LN->getOperand(1)->getOperand(1)))
2444 ConstantPoolSDNode *CN =
2445 dyn_cast<ConstantPoolSDNode>(LN->getOperand(1)->getOperand(1));
2446 FVal = cast<ConstantFP>(CN->getConstVal())->getValueAPF();
2450 // An FCVT[SU] instruction performs: convertToInt(Val * 2^fbits) where fbits
2451 // is between 1 and 32 for a destination w-register, or 1 and 64 for an
2454 // By this stage, we've detected (fp_to_[su]int (fmul Val, THIS_NODE)) so we
2455 // want THIS_NODE to be 2^fbits. This is much easier to deal with using
2459 // fbits is between 1 and 64 in the worst-case, which means the fmul
2460 // could have 2^64 as an actual operand. Need 65 bits of precision.
2461 APSInt IntVal(65, true);
2462 FVal.convertToInteger(IntVal, APFloat::rmTowardZero, &IsExact);
2464 // N.b. isPowerOf2 also checks for > 0.
2465 if (!IsExact || !IntVal.isPowerOf2()) return false;
2466 unsigned FBits = IntVal.logBase2();
2468 // Checks above should have guaranteed that we haven't lost information in
2469 // finding FBits, but it must still be in range.
2470 if (FBits == 0 || FBits > RegWidth) return false;
2472 FixedPos = CurDAG->getTargetConstant(FBits, SDLoc(N), MVT::i32);
2476 // Inspects a register string of the form o0:op1:CRn:CRm:op2 gets the fields
2477 // of the string and obtains the integer values from them and combines these
2478 // into a single value to be used in the MRS/MSR instruction.
2479 static int getIntOperandFromRegisterString(StringRef RegString) {
2480 SmallVector<StringRef, 5> Fields;
2481 RegString.split(Fields, ':');
2483 if (Fields.size() == 1)
2486 assert(Fields.size() == 5
2487 && "Invalid number of fields in read register string");
2489 SmallVector<int, 5> Ops;
2490 bool AllIntFields = true;
2492 for (StringRef Field : Fields) {
2494 AllIntFields &= !Field.getAsInteger(10, IntField);
2495 Ops.push_back(IntField);
2498 assert(AllIntFields &&
2499 "Unexpected non-integer value in special register string.");
2501 // Need to combine the integer fields of the string into a single value
2502 // based on the bit encoding of MRS/MSR instruction.
2503 return (Ops[0] << 14) | (Ops[1] << 11) | (Ops[2] << 7) |
2504 (Ops[3] << 3) | (Ops[4]);
2507 // Lower the read_register intrinsic to an MRS instruction node if the special
2508 // register string argument is either of the form detailed in the ALCE (the
2509 // form described in getIntOperandsFromRegsterString) or is a named register
2510 // known by the MRS SysReg mapper.
2511 bool AArch64DAGToDAGISel::tryReadRegister(SDNode *N) {
2512 const MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(N->getOperand(1));
2513 const MDString *RegString = dyn_cast<MDString>(MD->getMD()->getOperand(0));
2516 int Reg = getIntOperandFromRegisterString(RegString->getString());
2518 ReplaceNode(N, CurDAG->getMachineNode(
2519 AArch64::MRS, DL, N->getSimpleValueType(0), MVT::Other,
2520 CurDAG->getTargetConstant(Reg, DL, MVT::i32),
2525 // Use the sysreg mapper to map the remaining possible strings to the
2526 // value for the register to be used for the instruction operand.
2527 auto TheReg = AArch64SysReg::lookupSysRegByName(RegString->getString());
2528 if (TheReg && TheReg->Readable &&
2529 TheReg->haveFeatures(Subtarget->getFeatureBits()))
2530 Reg = TheReg->Encoding;
2532 Reg = AArch64SysReg::parseGenericRegister(RegString->getString());
2535 ReplaceNode(N, CurDAG->getMachineNode(
2536 AArch64::MRS, DL, N->getSimpleValueType(0), MVT::Other,
2537 CurDAG->getTargetConstant(Reg, DL, MVT::i32),
2545 // Lower the write_register intrinsic to an MSR instruction node if the special
2546 // register string argument is either of the form detailed in the ALCE (the
2547 // form described in getIntOperandsFromRegsterString) or is a named register
2548 // known by the MSR SysReg mapper.
2549 bool AArch64DAGToDAGISel::tryWriteRegister(SDNode *N) {
2550 const MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(N->getOperand(1));
2551 const MDString *RegString = dyn_cast<MDString>(MD->getMD()->getOperand(0));
2554 int Reg = getIntOperandFromRegisterString(RegString->getString());
2557 N, CurDAG->getMachineNode(AArch64::MSR, DL, MVT::Other,
2558 CurDAG->getTargetConstant(Reg, DL, MVT::i32),
2559 N->getOperand(2), N->getOperand(0)));
2563 // Check if the register was one of those allowed as the pstatefield value in
2564 // the MSR (immediate) instruction. To accept the values allowed in the
2565 // pstatefield for the MSR (immediate) instruction, we also require that an
2566 // immediate value has been provided as an argument, we know that this is
2567 // the case as it has been ensured by semantic checking.
2568 auto PMapper = AArch64PState::lookupPStateByName(RegString->getString());;
2570 assert (isa<ConstantSDNode>(N->getOperand(2))
2571 && "Expected a constant integer expression.");
2572 unsigned Reg = PMapper->Encoding;
2573 uint64_t Immed = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
2575 if (Reg == AArch64PState::PAN || Reg == AArch64PState::UAO) {
2576 assert(Immed < 2 && "Bad imm");
2577 State = AArch64::MSRpstateImm1;
2579 assert(Immed < 16 && "Bad imm");
2580 State = AArch64::MSRpstateImm4;
2582 ReplaceNode(N, CurDAG->getMachineNode(
2583 State, DL, MVT::Other,
2584 CurDAG->getTargetConstant(Reg, DL, MVT::i32),
2585 CurDAG->getTargetConstant(Immed, DL, MVT::i16),
2590 // Use the sysreg mapper to attempt to map the remaining possible strings
2591 // to the value for the register to be used for the MSR (register)
2592 // instruction operand.
2593 auto TheReg = AArch64SysReg::lookupSysRegByName(RegString->getString());
2594 if (TheReg && TheReg->Writeable &&
2595 TheReg->haveFeatures(Subtarget->getFeatureBits()))
2596 Reg = TheReg->Encoding;
2598 Reg = AArch64SysReg::parseGenericRegister(RegString->getString());
2600 ReplaceNode(N, CurDAG->getMachineNode(
2601 AArch64::MSR, DL, MVT::Other,
2602 CurDAG->getTargetConstant(Reg, DL, MVT::i32),
2603 N->getOperand(2), N->getOperand(0)));
2610 /// We've got special pseudo-instructions for these
2611 void AArch64DAGToDAGISel::SelectCMP_SWAP(SDNode *N) {
2613 EVT MemTy = cast<MemSDNode>(N)->getMemoryVT();
2614 if (MemTy == MVT::i8)
2615 Opcode = AArch64::CMP_SWAP_8;
2616 else if (MemTy == MVT::i16)
2617 Opcode = AArch64::CMP_SWAP_16;
2618 else if (MemTy == MVT::i32)
2619 Opcode = AArch64::CMP_SWAP_32;
2620 else if (MemTy == MVT::i64)
2621 Opcode = AArch64::CMP_SWAP_64;
2623 llvm_unreachable("Unknown AtomicCmpSwap type");
2625 MVT RegTy = MemTy == MVT::i64 ? MVT::i64 : MVT::i32;
2626 SDValue Ops[] = {N->getOperand(1), N->getOperand(2), N->getOperand(3),
2628 SDNode *CmpSwap = CurDAG->getMachineNode(
2630 CurDAG->getVTList(RegTy, MVT::i32, MVT::Other), Ops);
2632 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2633 MemOp[0] = cast<MemSDNode>(N)->getMemOperand();
2634 cast<MachineSDNode>(CmpSwap)->setMemRefs(MemOp, MemOp + 1);
2636 ReplaceUses(SDValue(N, 0), SDValue(CmpSwap, 0));
2637 ReplaceUses(SDValue(N, 1), SDValue(CmpSwap, 2));
2638 CurDAG->RemoveDeadNode(N);
2641 void AArch64DAGToDAGISel::Select(SDNode *Node) {
2642 // Dump information about the Node being selected
2643 DEBUG(errs() << "Selecting: ");
2644 DEBUG(Node->dump(CurDAG));
2645 DEBUG(errs() << "\n");
2647 // If we have a custom node, we already have selected!
2648 if (Node->isMachineOpcode()) {
2649 DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
2650 Node->setNodeId(-1);
2654 // Few custom selection stuff.
2655 EVT VT = Node->getValueType(0);
2657 switch (Node->getOpcode()) {
2661 case ISD::ATOMIC_CMP_SWAP:
2662 SelectCMP_SWAP(Node);
2665 case ISD::READ_REGISTER:
2666 if (tryReadRegister(Node))
2670 case ISD::WRITE_REGISTER:
2671 if (tryWriteRegister(Node))
2676 if (tryMLAV64LaneV128(Node))
2681 // Try to select as an indexed load. Fall through to normal processing
2683 if (tryIndexedLoad(Node))
2691 case ISD::SIGN_EXTEND_INREG:
2692 if (tryBitfieldExtractOp(Node))
2694 if (tryBitfieldInsertInZeroOp(Node))
2698 case ISD::SIGN_EXTEND:
2699 if (tryBitfieldExtractOpFromSExt(Node))
2704 if (tryBitfieldInsertOp(Node))
2708 case ISD::EXTRACT_VECTOR_ELT: {
2709 // Extracting lane zero is a special case where we can just use a plain
2710 // EXTRACT_SUBREG instruction, which will become FMOV. This is easier for
2711 // the rest of the compiler, especially the register allocator and copyi
2712 // propagation, to reason about, so is preferred when it's possible to
2714 ConstantSDNode *LaneNode = cast<ConstantSDNode>(Node->getOperand(1));
2715 // Bail and use the default Select() for non-zero lanes.
2716 if (LaneNode->getZExtValue() != 0)
2718 // If the element type is not the same as the result type, likewise
2719 // bail and use the default Select(), as there's more to do than just
2720 // a cross-class COPY. This catches extracts of i8 and i16 elements
2721 // since they will need an explicit zext.
2722 if (VT != Node->getOperand(0).getValueType().getVectorElementType())
2725 switch (Node->getOperand(0)
2727 .getVectorElementType()
2730 llvm_unreachable("Unexpected vector element type!");
2732 SubReg = AArch64::dsub;
2735 SubReg = AArch64::ssub;
2738 SubReg = AArch64::hsub;
2741 llvm_unreachable("unexpected zext-requiring extract element!");
2743 SDValue Extract = CurDAG->getTargetExtractSubreg(SubReg, SDLoc(Node), VT,
2744 Node->getOperand(0));
2745 DEBUG(dbgs() << "ISEL: Custom selection!\n=> ");
2746 DEBUG(Extract->dumpr(CurDAG));
2747 DEBUG(dbgs() << "\n");
2748 ReplaceNode(Node, Extract.getNode());
2751 case ISD::Constant: {
2752 // Materialize zero constants as copies from WZR/XZR. This allows
2753 // the coalescer to propagate these into other instructions.
2754 ConstantSDNode *ConstNode = cast<ConstantSDNode>(Node);
2755 if (ConstNode->isNullValue()) {
2756 if (VT == MVT::i32) {
2757 SDValue New = CurDAG->getCopyFromReg(
2758 CurDAG->getEntryNode(), SDLoc(Node), AArch64::WZR, MVT::i32);
2759 ReplaceNode(Node, New.getNode());
2761 } else if (VT == MVT::i64) {
2762 SDValue New = CurDAG->getCopyFromReg(
2763 CurDAG->getEntryNode(), SDLoc(Node), AArch64::XZR, MVT::i64);
2764 ReplaceNode(Node, New.getNode());
2771 case ISD::FrameIndex: {
2772 // Selects to ADDXri FI, 0 which in turn will become ADDXri SP, imm.
2773 int FI = cast<FrameIndexSDNode>(Node)->getIndex();
2774 unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0);
2775 const TargetLowering *TLI = getTargetLowering();
2776 SDValue TFI = CurDAG->getTargetFrameIndex(
2777 FI, TLI->getPointerTy(CurDAG->getDataLayout()));
2779 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, DL, MVT::i32),
2780 CurDAG->getTargetConstant(Shifter, DL, MVT::i32) };
2781 CurDAG->SelectNodeTo(Node, AArch64::ADDXri, MVT::i64, Ops);
2784 case ISD::INTRINSIC_W_CHAIN: {
2785 unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
2789 case Intrinsic::aarch64_ldaxp:
2790 case Intrinsic::aarch64_ldxp: {
2792 IntNo == Intrinsic::aarch64_ldaxp ? AArch64::LDAXPX : AArch64::LDXPX;
2793 SDValue MemAddr = Node->getOperand(2);
2795 SDValue Chain = Node->getOperand(0);
2797 SDNode *Ld = CurDAG->getMachineNode(Op, DL, MVT::i64, MVT::i64,
2798 MVT::Other, MemAddr, Chain);
2800 // Transfer memoperands.
2801 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2802 MemOp[0] = cast<MemIntrinsicSDNode>(Node)->getMemOperand();
2803 cast<MachineSDNode>(Ld)->setMemRefs(MemOp, MemOp + 1);
2804 ReplaceNode(Node, Ld);
2807 case Intrinsic::aarch64_stlxp:
2808 case Intrinsic::aarch64_stxp: {
2810 IntNo == Intrinsic::aarch64_stlxp ? AArch64::STLXPX : AArch64::STXPX;
2812 SDValue Chain = Node->getOperand(0);
2813 SDValue ValLo = Node->getOperand(2);
2814 SDValue ValHi = Node->getOperand(3);
2815 SDValue MemAddr = Node->getOperand(4);
2817 // Place arguments in the right order.
2818 SDValue Ops[] = {ValLo, ValHi, MemAddr, Chain};
2820 SDNode *St = CurDAG->getMachineNode(Op, DL, MVT::i32, MVT::Other, Ops);
2821 // Transfer memoperands.
2822 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2823 MemOp[0] = cast<MemIntrinsicSDNode>(Node)->getMemOperand();
2824 cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1);
2826 ReplaceNode(Node, St);
2829 case Intrinsic::aarch64_neon_ld1x2:
2830 if (VT == MVT::v8i8) {
2831 SelectLoad(Node, 2, AArch64::LD1Twov8b, AArch64::dsub0);
2833 } else if (VT == MVT::v16i8) {
2834 SelectLoad(Node, 2, AArch64::LD1Twov16b, AArch64::qsub0);
2836 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
2837 SelectLoad(Node, 2, AArch64::LD1Twov4h, AArch64::dsub0);
2839 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
2840 SelectLoad(Node, 2, AArch64::LD1Twov8h, AArch64::qsub0);
2842 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
2843 SelectLoad(Node, 2, AArch64::LD1Twov2s, AArch64::dsub0);
2845 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
2846 SelectLoad(Node, 2, AArch64::LD1Twov4s, AArch64::qsub0);
2848 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
2849 SelectLoad(Node, 2, AArch64::LD1Twov1d, AArch64::dsub0);
2851 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
2852 SelectLoad(Node, 2, AArch64::LD1Twov2d, AArch64::qsub0);
2856 case Intrinsic::aarch64_neon_ld1x3:
2857 if (VT == MVT::v8i8) {
2858 SelectLoad(Node, 3, AArch64::LD1Threev8b, AArch64::dsub0);
2860 } else if (VT == MVT::v16i8) {
2861 SelectLoad(Node, 3, AArch64::LD1Threev16b, AArch64::qsub0);
2863 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
2864 SelectLoad(Node, 3, AArch64::LD1Threev4h, AArch64::dsub0);
2866 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
2867 SelectLoad(Node, 3, AArch64::LD1Threev8h, AArch64::qsub0);
2869 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
2870 SelectLoad(Node, 3, AArch64::LD1Threev2s, AArch64::dsub0);
2872 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
2873 SelectLoad(Node, 3, AArch64::LD1Threev4s, AArch64::qsub0);
2875 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
2876 SelectLoad(Node, 3, AArch64::LD1Threev1d, AArch64::dsub0);
2878 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
2879 SelectLoad(Node, 3, AArch64::LD1Threev2d, AArch64::qsub0);
2883 case Intrinsic::aarch64_neon_ld1x4:
2884 if (VT == MVT::v8i8) {
2885 SelectLoad(Node, 4, AArch64::LD1Fourv8b, AArch64::dsub0);
2887 } else if (VT == MVT::v16i8) {
2888 SelectLoad(Node, 4, AArch64::LD1Fourv16b, AArch64::qsub0);
2890 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
2891 SelectLoad(Node, 4, AArch64::LD1Fourv4h, AArch64::dsub0);
2893 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
2894 SelectLoad(Node, 4, AArch64::LD1Fourv8h, AArch64::qsub0);
2896 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
2897 SelectLoad(Node, 4, AArch64::LD1Fourv2s, AArch64::dsub0);
2899 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
2900 SelectLoad(Node, 4, AArch64::LD1Fourv4s, AArch64::qsub0);
2902 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
2903 SelectLoad(Node, 4, AArch64::LD1Fourv1d, AArch64::dsub0);
2905 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
2906 SelectLoad(Node, 4, AArch64::LD1Fourv2d, AArch64::qsub0);
2910 case Intrinsic::aarch64_neon_ld2:
2911 if (VT == MVT::v8i8) {
2912 SelectLoad(Node, 2, AArch64::LD2Twov8b, AArch64::dsub0);
2914 } else if (VT == MVT::v16i8) {
2915 SelectLoad(Node, 2, AArch64::LD2Twov16b, AArch64::qsub0);
2917 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
2918 SelectLoad(Node, 2, AArch64::LD2Twov4h, AArch64::dsub0);
2920 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
2921 SelectLoad(Node, 2, AArch64::LD2Twov8h, AArch64::qsub0);
2923 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
2924 SelectLoad(Node, 2, AArch64::LD2Twov2s, AArch64::dsub0);
2926 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
2927 SelectLoad(Node, 2, AArch64::LD2Twov4s, AArch64::qsub0);
2929 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
2930 SelectLoad(Node, 2, AArch64::LD1Twov1d, AArch64::dsub0);
2932 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
2933 SelectLoad(Node, 2, AArch64::LD2Twov2d, AArch64::qsub0);
2937 case Intrinsic::aarch64_neon_ld3:
2938 if (VT == MVT::v8i8) {
2939 SelectLoad(Node, 3, AArch64::LD3Threev8b, AArch64::dsub0);
2941 } else if (VT == MVT::v16i8) {
2942 SelectLoad(Node, 3, AArch64::LD3Threev16b, AArch64::qsub0);
2944 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
2945 SelectLoad(Node, 3, AArch64::LD3Threev4h, AArch64::dsub0);
2947 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
2948 SelectLoad(Node, 3, AArch64::LD3Threev8h, AArch64::qsub0);
2950 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
2951 SelectLoad(Node, 3, AArch64::LD3Threev2s, AArch64::dsub0);
2953 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
2954 SelectLoad(Node, 3, AArch64::LD3Threev4s, AArch64::qsub0);
2956 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
2957 SelectLoad(Node, 3, AArch64::LD1Threev1d, AArch64::dsub0);
2959 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
2960 SelectLoad(Node, 3, AArch64::LD3Threev2d, AArch64::qsub0);
2964 case Intrinsic::aarch64_neon_ld4:
2965 if (VT == MVT::v8i8) {
2966 SelectLoad(Node, 4, AArch64::LD4Fourv8b, AArch64::dsub0);
2968 } else if (VT == MVT::v16i8) {
2969 SelectLoad(Node, 4, AArch64::LD4Fourv16b, AArch64::qsub0);
2971 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
2972 SelectLoad(Node, 4, AArch64::LD4Fourv4h, AArch64::dsub0);
2974 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
2975 SelectLoad(Node, 4, AArch64::LD4Fourv8h, AArch64::qsub0);
2977 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
2978 SelectLoad(Node, 4, AArch64::LD4Fourv2s, AArch64::dsub0);
2980 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
2981 SelectLoad(Node, 4, AArch64::LD4Fourv4s, AArch64::qsub0);
2983 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
2984 SelectLoad(Node, 4, AArch64::LD1Fourv1d, AArch64::dsub0);
2986 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
2987 SelectLoad(Node, 4, AArch64::LD4Fourv2d, AArch64::qsub0);
2991 case Intrinsic::aarch64_neon_ld2r:
2992 if (VT == MVT::v8i8) {
2993 SelectLoad(Node, 2, AArch64::LD2Rv8b, AArch64::dsub0);
2995 } else if (VT == MVT::v16i8) {
2996 SelectLoad(Node, 2, AArch64::LD2Rv16b, AArch64::qsub0);
2998 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
2999 SelectLoad(Node, 2, AArch64::LD2Rv4h, AArch64::dsub0);
3001 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3002 SelectLoad(Node, 2, AArch64::LD2Rv8h, AArch64::qsub0);
3004 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3005 SelectLoad(Node, 2, AArch64::LD2Rv2s, AArch64::dsub0);
3007 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3008 SelectLoad(Node, 2, AArch64::LD2Rv4s, AArch64::qsub0);
3010 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3011 SelectLoad(Node, 2, AArch64::LD2Rv1d, AArch64::dsub0);
3013 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3014 SelectLoad(Node, 2, AArch64::LD2Rv2d, AArch64::qsub0);
3018 case Intrinsic::aarch64_neon_ld3r:
3019 if (VT == MVT::v8i8) {
3020 SelectLoad(Node, 3, AArch64::LD3Rv8b, AArch64::dsub0);
3022 } else if (VT == MVT::v16i8) {
3023 SelectLoad(Node, 3, AArch64::LD3Rv16b, AArch64::qsub0);
3025 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3026 SelectLoad(Node, 3, AArch64::LD3Rv4h, AArch64::dsub0);
3028 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3029 SelectLoad(Node, 3, AArch64::LD3Rv8h, AArch64::qsub0);
3031 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3032 SelectLoad(Node, 3, AArch64::LD3Rv2s, AArch64::dsub0);
3034 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3035 SelectLoad(Node, 3, AArch64::LD3Rv4s, AArch64::qsub0);
3037 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3038 SelectLoad(Node, 3, AArch64::LD3Rv1d, AArch64::dsub0);
3040 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3041 SelectLoad(Node, 3, AArch64::LD3Rv2d, AArch64::qsub0);
3045 case Intrinsic::aarch64_neon_ld4r:
3046 if (VT == MVT::v8i8) {
3047 SelectLoad(Node, 4, AArch64::LD4Rv8b, AArch64::dsub0);
3049 } else if (VT == MVT::v16i8) {
3050 SelectLoad(Node, 4, AArch64::LD4Rv16b, AArch64::qsub0);
3052 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3053 SelectLoad(Node, 4, AArch64::LD4Rv4h, AArch64::dsub0);
3055 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3056 SelectLoad(Node, 4, AArch64::LD4Rv8h, AArch64::qsub0);
3058 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3059 SelectLoad(Node, 4, AArch64::LD4Rv2s, AArch64::dsub0);
3061 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3062 SelectLoad(Node, 4, AArch64::LD4Rv4s, AArch64::qsub0);
3064 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3065 SelectLoad(Node, 4, AArch64::LD4Rv1d, AArch64::dsub0);
3067 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3068 SelectLoad(Node, 4, AArch64::LD4Rv2d, AArch64::qsub0);
3072 case Intrinsic::aarch64_neon_ld2lane:
3073 if (VT == MVT::v16i8 || VT == MVT::v8i8) {
3074 SelectLoadLane(Node, 2, AArch64::LD2i8);
3076 } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
3078 SelectLoadLane(Node, 2, AArch64::LD2i16);
3080 } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
3082 SelectLoadLane(Node, 2, AArch64::LD2i32);
3084 } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
3086 SelectLoadLane(Node, 2, AArch64::LD2i64);
3090 case Intrinsic::aarch64_neon_ld3lane:
3091 if (VT == MVT::v16i8 || VT == MVT::v8i8) {
3092 SelectLoadLane(Node, 3, AArch64::LD3i8);
3094 } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
3096 SelectLoadLane(Node, 3, AArch64::LD3i16);
3098 } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
3100 SelectLoadLane(Node, 3, AArch64::LD3i32);
3102 } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
3104 SelectLoadLane(Node, 3, AArch64::LD3i64);
3108 case Intrinsic::aarch64_neon_ld4lane:
3109 if (VT == MVT::v16i8 || VT == MVT::v8i8) {
3110 SelectLoadLane(Node, 4, AArch64::LD4i8);
3112 } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
3114 SelectLoadLane(Node, 4, AArch64::LD4i16);
3116 } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
3118 SelectLoadLane(Node, 4, AArch64::LD4i32);
3120 } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
3122 SelectLoadLane(Node, 4, AArch64::LD4i64);
3128 case ISD::INTRINSIC_WO_CHAIN: {
3129 unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
3133 case Intrinsic::aarch64_neon_tbl2:
3134 SelectTable(Node, 2,
3135 VT == MVT::v8i8 ? AArch64::TBLv8i8Two : AArch64::TBLv16i8Two,
3138 case Intrinsic::aarch64_neon_tbl3:
3139 SelectTable(Node, 3, VT == MVT::v8i8 ? AArch64::TBLv8i8Three
3140 : AArch64::TBLv16i8Three,
3143 case Intrinsic::aarch64_neon_tbl4:
3144 SelectTable(Node, 4, VT == MVT::v8i8 ? AArch64::TBLv8i8Four
3145 : AArch64::TBLv16i8Four,
3148 case Intrinsic::aarch64_neon_tbx2:
3149 SelectTable(Node, 2,
3150 VT == MVT::v8i8 ? AArch64::TBXv8i8Two : AArch64::TBXv16i8Two,
3153 case Intrinsic::aarch64_neon_tbx3:
3154 SelectTable(Node, 3, VT == MVT::v8i8 ? AArch64::TBXv8i8Three
3155 : AArch64::TBXv16i8Three,
3158 case Intrinsic::aarch64_neon_tbx4:
3159 SelectTable(Node, 4, VT == MVT::v8i8 ? AArch64::TBXv8i8Four
3160 : AArch64::TBXv16i8Four,
3163 case Intrinsic::aarch64_neon_smull:
3164 case Intrinsic::aarch64_neon_umull:
3165 if (tryMULLV64LaneV128(IntNo, Node))
3171 case ISD::INTRINSIC_VOID: {
3172 unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
3173 if (Node->getNumOperands() >= 3)
3174 VT = Node->getOperand(2)->getValueType(0);
3178 case Intrinsic::aarch64_neon_st1x2: {
3179 if (VT == MVT::v8i8) {
3180 SelectStore(Node, 2, AArch64::ST1Twov8b);
3182 } else if (VT == MVT::v16i8) {
3183 SelectStore(Node, 2, AArch64::ST1Twov16b);
3185 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3186 SelectStore(Node, 2, AArch64::ST1Twov4h);
3188 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3189 SelectStore(Node, 2, AArch64::ST1Twov8h);
3191 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3192 SelectStore(Node, 2, AArch64::ST1Twov2s);
3194 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3195 SelectStore(Node, 2, AArch64::ST1Twov4s);
3197 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3198 SelectStore(Node, 2, AArch64::ST1Twov2d);
3200 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3201 SelectStore(Node, 2, AArch64::ST1Twov1d);
3206 case Intrinsic::aarch64_neon_st1x3: {
3207 if (VT == MVT::v8i8) {
3208 SelectStore(Node, 3, AArch64::ST1Threev8b);
3210 } else if (VT == MVT::v16i8) {
3211 SelectStore(Node, 3, AArch64::ST1Threev16b);
3213 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3214 SelectStore(Node, 3, AArch64::ST1Threev4h);
3216 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3217 SelectStore(Node, 3, AArch64::ST1Threev8h);
3219 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3220 SelectStore(Node, 3, AArch64::ST1Threev2s);
3222 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3223 SelectStore(Node, 3, AArch64::ST1Threev4s);
3225 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3226 SelectStore(Node, 3, AArch64::ST1Threev2d);
3228 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3229 SelectStore(Node, 3, AArch64::ST1Threev1d);
3234 case Intrinsic::aarch64_neon_st1x4: {
3235 if (VT == MVT::v8i8) {
3236 SelectStore(Node, 4, AArch64::ST1Fourv8b);
3238 } else if (VT == MVT::v16i8) {
3239 SelectStore(Node, 4, AArch64::ST1Fourv16b);
3241 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3242 SelectStore(Node, 4, AArch64::ST1Fourv4h);
3244 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3245 SelectStore(Node, 4, AArch64::ST1Fourv8h);
3247 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3248 SelectStore(Node, 4, AArch64::ST1Fourv2s);
3250 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3251 SelectStore(Node, 4, AArch64::ST1Fourv4s);
3253 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3254 SelectStore(Node, 4, AArch64::ST1Fourv2d);
3256 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3257 SelectStore(Node, 4, AArch64::ST1Fourv1d);
3262 case Intrinsic::aarch64_neon_st2: {
3263 if (VT == MVT::v8i8) {
3264 SelectStore(Node, 2, AArch64::ST2Twov8b);
3266 } else if (VT == MVT::v16i8) {
3267 SelectStore(Node, 2, AArch64::ST2Twov16b);
3269 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3270 SelectStore(Node, 2, AArch64::ST2Twov4h);
3272 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3273 SelectStore(Node, 2, AArch64::ST2Twov8h);
3275 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3276 SelectStore(Node, 2, AArch64::ST2Twov2s);
3278 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3279 SelectStore(Node, 2, AArch64::ST2Twov4s);
3281 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3282 SelectStore(Node, 2, AArch64::ST2Twov2d);
3284 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3285 SelectStore(Node, 2, AArch64::ST1Twov1d);
3290 case Intrinsic::aarch64_neon_st3: {
3291 if (VT == MVT::v8i8) {
3292 SelectStore(Node, 3, AArch64::ST3Threev8b);
3294 } else if (VT == MVT::v16i8) {
3295 SelectStore(Node, 3, AArch64::ST3Threev16b);
3297 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3298 SelectStore(Node, 3, AArch64::ST3Threev4h);
3300 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3301 SelectStore(Node, 3, AArch64::ST3Threev8h);
3303 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3304 SelectStore(Node, 3, AArch64::ST3Threev2s);
3306 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3307 SelectStore(Node, 3, AArch64::ST3Threev4s);
3309 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3310 SelectStore(Node, 3, AArch64::ST3Threev2d);
3312 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3313 SelectStore(Node, 3, AArch64::ST1Threev1d);
3318 case Intrinsic::aarch64_neon_st4: {
3319 if (VT == MVT::v8i8) {
3320 SelectStore(Node, 4, AArch64::ST4Fourv8b);
3322 } else if (VT == MVT::v16i8) {
3323 SelectStore(Node, 4, AArch64::ST4Fourv16b);
3325 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3326 SelectStore(Node, 4, AArch64::ST4Fourv4h);
3328 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3329 SelectStore(Node, 4, AArch64::ST4Fourv8h);
3331 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3332 SelectStore(Node, 4, AArch64::ST4Fourv2s);
3334 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3335 SelectStore(Node, 4, AArch64::ST4Fourv4s);
3337 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3338 SelectStore(Node, 4, AArch64::ST4Fourv2d);
3340 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3341 SelectStore(Node, 4, AArch64::ST1Fourv1d);
3346 case Intrinsic::aarch64_neon_st2lane: {
3347 if (VT == MVT::v16i8 || VT == MVT::v8i8) {
3348 SelectStoreLane(Node, 2, AArch64::ST2i8);
3350 } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
3352 SelectStoreLane(Node, 2, AArch64::ST2i16);
3354 } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
3356 SelectStoreLane(Node, 2, AArch64::ST2i32);
3358 } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
3360 SelectStoreLane(Node, 2, AArch64::ST2i64);
3365 case Intrinsic::aarch64_neon_st3lane: {
3366 if (VT == MVT::v16i8 || VT == MVT::v8i8) {
3367 SelectStoreLane(Node, 3, AArch64::ST3i8);
3369 } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
3371 SelectStoreLane(Node, 3, AArch64::ST3i16);
3373 } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
3375 SelectStoreLane(Node, 3, AArch64::ST3i32);
3377 } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
3379 SelectStoreLane(Node, 3, AArch64::ST3i64);
3384 case Intrinsic::aarch64_neon_st4lane: {
3385 if (VT == MVT::v16i8 || VT == MVT::v8i8) {
3386 SelectStoreLane(Node, 4, AArch64::ST4i8);
3388 } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
3390 SelectStoreLane(Node, 4, AArch64::ST4i16);
3392 } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
3394 SelectStoreLane(Node, 4, AArch64::ST4i32);
3396 } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
3398 SelectStoreLane(Node, 4, AArch64::ST4i64);
3406 case AArch64ISD::LD2post: {
3407 if (VT == MVT::v8i8) {
3408 SelectPostLoad(Node, 2, AArch64::LD2Twov8b_POST, AArch64::dsub0);
3410 } else if (VT == MVT::v16i8) {
3411 SelectPostLoad(Node, 2, AArch64::LD2Twov16b_POST, AArch64::qsub0);
3413 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3414 SelectPostLoad(Node, 2, AArch64::LD2Twov4h_POST, AArch64::dsub0);
3416 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3417 SelectPostLoad(Node, 2, AArch64::LD2Twov8h_POST, AArch64::qsub0);
3419 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3420 SelectPostLoad(Node, 2, AArch64::LD2Twov2s_POST, AArch64::dsub0);
3422 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3423 SelectPostLoad(Node, 2, AArch64::LD2Twov4s_POST, AArch64::qsub0);
3425 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3426 SelectPostLoad(Node, 2, AArch64::LD1Twov1d_POST, AArch64::dsub0);
3428 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3429 SelectPostLoad(Node, 2, AArch64::LD2Twov2d_POST, AArch64::qsub0);
3434 case AArch64ISD::LD3post: {
3435 if (VT == MVT::v8i8) {
3436 SelectPostLoad(Node, 3, AArch64::LD3Threev8b_POST, AArch64::dsub0);
3438 } else if (VT == MVT::v16i8) {
3439 SelectPostLoad(Node, 3, AArch64::LD3Threev16b_POST, AArch64::qsub0);
3441 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3442 SelectPostLoad(Node, 3, AArch64::LD3Threev4h_POST, AArch64::dsub0);
3444 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3445 SelectPostLoad(Node, 3, AArch64::LD3Threev8h_POST, AArch64::qsub0);
3447 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3448 SelectPostLoad(Node, 3, AArch64::LD3Threev2s_POST, AArch64::dsub0);
3450 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3451 SelectPostLoad(Node, 3, AArch64::LD3Threev4s_POST, AArch64::qsub0);
3453 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3454 SelectPostLoad(Node, 3, AArch64::LD1Threev1d_POST, AArch64::dsub0);
3456 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3457 SelectPostLoad(Node, 3, AArch64::LD3Threev2d_POST, AArch64::qsub0);
3462 case AArch64ISD::LD4post: {
3463 if (VT == MVT::v8i8) {
3464 SelectPostLoad(Node, 4, AArch64::LD4Fourv8b_POST, AArch64::dsub0);
3466 } else if (VT == MVT::v16i8) {
3467 SelectPostLoad(Node, 4, AArch64::LD4Fourv16b_POST, AArch64::qsub0);
3469 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3470 SelectPostLoad(Node, 4, AArch64::LD4Fourv4h_POST, AArch64::dsub0);
3472 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3473 SelectPostLoad(Node, 4, AArch64::LD4Fourv8h_POST, AArch64::qsub0);
3475 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3476 SelectPostLoad(Node, 4, AArch64::LD4Fourv2s_POST, AArch64::dsub0);
3478 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3479 SelectPostLoad(Node, 4, AArch64::LD4Fourv4s_POST, AArch64::qsub0);
3481 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3482 SelectPostLoad(Node, 4, AArch64::LD1Fourv1d_POST, AArch64::dsub0);
3484 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3485 SelectPostLoad(Node, 4, AArch64::LD4Fourv2d_POST, AArch64::qsub0);
3490 case AArch64ISD::LD1x2post: {
3491 if (VT == MVT::v8i8) {
3492 SelectPostLoad(Node, 2, AArch64::LD1Twov8b_POST, AArch64::dsub0);
3494 } else if (VT == MVT::v16i8) {
3495 SelectPostLoad(Node, 2, AArch64::LD1Twov16b_POST, AArch64::qsub0);
3497 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3498 SelectPostLoad(Node, 2, AArch64::LD1Twov4h_POST, AArch64::dsub0);
3500 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3501 SelectPostLoad(Node, 2, AArch64::LD1Twov8h_POST, AArch64::qsub0);
3503 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3504 SelectPostLoad(Node, 2, AArch64::LD1Twov2s_POST, AArch64::dsub0);
3506 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3507 SelectPostLoad(Node, 2, AArch64::LD1Twov4s_POST, AArch64::qsub0);
3509 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3510 SelectPostLoad(Node, 2, AArch64::LD1Twov1d_POST, AArch64::dsub0);
3512 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3513 SelectPostLoad(Node, 2, AArch64::LD1Twov2d_POST, AArch64::qsub0);
3518 case AArch64ISD::LD1x3post: {
3519 if (VT == MVT::v8i8) {
3520 SelectPostLoad(Node, 3, AArch64::LD1Threev8b_POST, AArch64::dsub0);
3522 } else if (VT == MVT::v16i8) {
3523 SelectPostLoad(Node, 3, AArch64::LD1Threev16b_POST, AArch64::qsub0);
3525 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3526 SelectPostLoad(Node, 3, AArch64::LD1Threev4h_POST, AArch64::dsub0);
3528 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3529 SelectPostLoad(Node, 3, AArch64::LD1Threev8h_POST, AArch64::qsub0);
3531 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3532 SelectPostLoad(Node, 3, AArch64::LD1Threev2s_POST, AArch64::dsub0);
3534 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3535 SelectPostLoad(Node, 3, AArch64::LD1Threev4s_POST, AArch64::qsub0);
3537 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3538 SelectPostLoad(Node, 3, AArch64::LD1Threev1d_POST, AArch64::dsub0);
3540 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3541 SelectPostLoad(Node, 3, AArch64::LD1Threev2d_POST, AArch64::qsub0);
3546 case AArch64ISD::LD1x4post: {
3547 if (VT == MVT::v8i8) {
3548 SelectPostLoad(Node, 4, AArch64::LD1Fourv8b_POST, AArch64::dsub0);
3550 } else if (VT == MVT::v16i8) {
3551 SelectPostLoad(Node, 4, AArch64::LD1Fourv16b_POST, AArch64::qsub0);
3553 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3554 SelectPostLoad(Node, 4, AArch64::LD1Fourv4h_POST, AArch64::dsub0);
3556 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3557 SelectPostLoad(Node, 4, AArch64::LD1Fourv8h_POST, AArch64::qsub0);
3559 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3560 SelectPostLoad(Node, 4, AArch64::LD1Fourv2s_POST, AArch64::dsub0);
3562 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3563 SelectPostLoad(Node, 4, AArch64::LD1Fourv4s_POST, AArch64::qsub0);
3565 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3566 SelectPostLoad(Node, 4, AArch64::LD1Fourv1d_POST, AArch64::dsub0);
3568 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3569 SelectPostLoad(Node, 4, AArch64::LD1Fourv2d_POST, AArch64::qsub0);
3574 case AArch64ISD::LD1DUPpost: {
3575 if (VT == MVT::v8i8) {
3576 SelectPostLoad(Node, 1, AArch64::LD1Rv8b_POST, AArch64::dsub0);
3578 } else if (VT == MVT::v16i8) {
3579 SelectPostLoad(Node, 1, AArch64::LD1Rv16b_POST, AArch64::qsub0);
3581 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3582 SelectPostLoad(Node, 1, AArch64::LD1Rv4h_POST, AArch64::dsub0);
3584 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3585 SelectPostLoad(Node, 1, AArch64::LD1Rv8h_POST, AArch64::qsub0);
3587 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3588 SelectPostLoad(Node, 1, AArch64::LD1Rv2s_POST, AArch64::dsub0);
3590 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3591 SelectPostLoad(Node, 1, AArch64::LD1Rv4s_POST, AArch64::qsub0);
3593 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3594 SelectPostLoad(Node, 1, AArch64::LD1Rv1d_POST, AArch64::dsub0);
3596 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3597 SelectPostLoad(Node, 1, AArch64::LD1Rv2d_POST, AArch64::qsub0);
3602 case AArch64ISD::LD2DUPpost: {
3603 if (VT == MVT::v8i8) {
3604 SelectPostLoad(Node, 2, AArch64::LD2Rv8b_POST, AArch64::dsub0);
3606 } else if (VT == MVT::v16i8) {
3607 SelectPostLoad(Node, 2, AArch64::LD2Rv16b_POST, AArch64::qsub0);
3609 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3610 SelectPostLoad(Node, 2, AArch64::LD2Rv4h_POST, AArch64::dsub0);
3612 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3613 SelectPostLoad(Node, 2, AArch64::LD2Rv8h_POST, AArch64::qsub0);
3615 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3616 SelectPostLoad(Node, 2, AArch64::LD2Rv2s_POST, AArch64::dsub0);
3618 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3619 SelectPostLoad(Node, 2, AArch64::LD2Rv4s_POST, AArch64::qsub0);
3621 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3622 SelectPostLoad(Node, 2, AArch64::LD2Rv1d_POST, AArch64::dsub0);
3624 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3625 SelectPostLoad(Node, 2, AArch64::LD2Rv2d_POST, AArch64::qsub0);
3630 case AArch64ISD::LD3DUPpost: {
3631 if (VT == MVT::v8i8) {
3632 SelectPostLoad(Node, 3, AArch64::LD3Rv8b_POST, AArch64::dsub0);
3634 } else if (VT == MVT::v16i8) {
3635 SelectPostLoad(Node, 3, AArch64::LD3Rv16b_POST, AArch64::qsub0);
3637 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3638 SelectPostLoad(Node, 3, AArch64::LD3Rv4h_POST, AArch64::dsub0);
3640 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3641 SelectPostLoad(Node, 3, AArch64::LD3Rv8h_POST, AArch64::qsub0);
3643 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3644 SelectPostLoad(Node, 3, AArch64::LD3Rv2s_POST, AArch64::dsub0);
3646 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3647 SelectPostLoad(Node, 3, AArch64::LD3Rv4s_POST, AArch64::qsub0);
3649 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3650 SelectPostLoad(Node, 3, AArch64::LD3Rv1d_POST, AArch64::dsub0);
3652 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3653 SelectPostLoad(Node, 3, AArch64::LD3Rv2d_POST, AArch64::qsub0);
3658 case AArch64ISD::LD4DUPpost: {
3659 if (VT == MVT::v8i8) {
3660 SelectPostLoad(Node, 4, AArch64::LD4Rv8b_POST, AArch64::dsub0);
3662 } else if (VT == MVT::v16i8) {
3663 SelectPostLoad(Node, 4, AArch64::LD4Rv16b_POST, AArch64::qsub0);
3665 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3666 SelectPostLoad(Node, 4, AArch64::LD4Rv4h_POST, AArch64::dsub0);
3668 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3669 SelectPostLoad(Node, 4, AArch64::LD4Rv8h_POST, AArch64::qsub0);
3671 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3672 SelectPostLoad(Node, 4, AArch64::LD4Rv2s_POST, AArch64::dsub0);
3674 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3675 SelectPostLoad(Node, 4, AArch64::LD4Rv4s_POST, AArch64::qsub0);
3677 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3678 SelectPostLoad(Node, 4, AArch64::LD4Rv1d_POST, AArch64::dsub0);
3680 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3681 SelectPostLoad(Node, 4, AArch64::LD4Rv2d_POST, AArch64::qsub0);
3686 case AArch64ISD::LD1LANEpost: {
3687 if (VT == MVT::v16i8 || VT == MVT::v8i8) {
3688 SelectPostLoadLane(Node, 1, AArch64::LD1i8_POST);
3690 } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
3692 SelectPostLoadLane(Node, 1, AArch64::LD1i16_POST);
3694 } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
3696 SelectPostLoadLane(Node, 1, AArch64::LD1i32_POST);
3698 } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
3700 SelectPostLoadLane(Node, 1, AArch64::LD1i64_POST);
3705 case AArch64ISD::LD2LANEpost: {
3706 if (VT == MVT::v16i8 || VT == MVT::v8i8) {
3707 SelectPostLoadLane(Node, 2, AArch64::LD2i8_POST);
3709 } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
3711 SelectPostLoadLane(Node, 2, AArch64::LD2i16_POST);
3713 } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
3715 SelectPostLoadLane(Node, 2, AArch64::LD2i32_POST);
3717 } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
3719 SelectPostLoadLane(Node, 2, AArch64::LD2i64_POST);
3724 case AArch64ISD::LD3LANEpost: {
3725 if (VT == MVT::v16i8 || VT == MVT::v8i8) {
3726 SelectPostLoadLane(Node, 3, AArch64::LD3i8_POST);
3728 } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
3730 SelectPostLoadLane(Node, 3, AArch64::LD3i16_POST);
3732 } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
3734 SelectPostLoadLane(Node, 3, AArch64::LD3i32_POST);
3736 } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
3738 SelectPostLoadLane(Node, 3, AArch64::LD3i64_POST);
3743 case AArch64ISD::LD4LANEpost: {
3744 if (VT == MVT::v16i8 || VT == MVT::v8i8) {
3745 SelectPostLoadLane(Node, 4, AArch64::LD4i8_POST);
3747 } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
3749 SelectPostLoadLane(Node, 4, AArch64::LD4i16_POST);
3751 } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
3753 SelectPostLoadLane(Node, 4, AArch64::LD4i32_POST);
3755 } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
3757 SelectPostLoadLane(Node, 4, AArch64::LD4i64_POST);
3762 case AArch64ISD::ST2post: {
3763 VT = Node->getOperand(1).getValueType();
3764 if (VT == MVT::v8i8) {
3765 SelectPostStore(Node, 2, AArch64::ST2Twov8b_POST);
3767 } else if (VT == MVT::v16i8) {
3768 SelectPostStore(Node, 2, AArch64::ST2Twov16b_POST);
3770 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3771 SelectPostStore(Node, 2, AArch64::ST2Twov4h_POST);
3773 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3774 SelectPostStore(Node, 2, AArch64::ST2Twov8h_POST);
3776 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3777 SelectPostStore(Node, 2, AArch64::ST2Twov2s_POST);
3779 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3780 SelectPostStore(Node, 2, AArch64::ST2Twov4s_POST);
3782 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3783 SelectPostStore(Node, 2, AArch64::ST2Twov2d_POST);
3785 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3786 SelectPostStore(Node, 2, AArch64::ST1Twov1d_POST);
3791 case AArch64ISD::ST3post: {
3792 VT = Node->getOperand(1).getValueType();
3793 if (VT == MVT::v8i8) {
3794 SelectPostStore(Node, 3, AArch64::ST3Threev8b_POST);
3796 } else if (VT == MVT::v16i8) {
3797 SelectPostStore(Node, 3, AArch64::ST3Threev16b_POST);
3799 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3800 SelectPostStore(Node, 3, AArch64::ST3Threev4h_POST);
3802 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3803 SelectPostStore(Node, 3, AArch64::ST3Threev8h_POST);
3805 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3806 SelectPostStore(Node, 3, AArch64::ST3Threev2s_POST);
3808 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3809 SelectPostStore(Node, 3, AArch64::ST3Threev4s_POST);
3811 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3812 SelectPostStore(Node, 3, AArch64::ST3Threev2d_POST);
3814 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3815 SelectPostStore(Node, 3, AArch64::ST1Threev1d_POST);
3820 case AArch64ISD::ST4post: {
3821 VT = Node->getOperand(1).getValueType();
3822 if (VT == MVT::v8i8) {
3823 SelectPostStore(Node, 4, AArch64::ST4Fourv8b_POST);
3825 } else if (VT == MVT::v16i8) {
3826 SelectPostStore(Node, 4, AArch64::ST4Fourv16b_POST);
3828 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3829 SelectPostStore(Node, 4, AArch64::ST4Fourv4h_POST);
3831 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3832 SelectPostStore(Node, 4, AArch64::ST4Fourv8h_POST);
3834 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3835 SelectPostStore(Node, 4, AArch64::ST4Fourv2s_POST);
3837 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3838 SelectPostStore(Node, 4, AArch64::ST4Fourv4s_POST);
3840 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3841 SelectPostStore(Node, 4, AArch64::ST4Fourv2d_POST);
3843 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3844 SelectPostStore(Node, 4, AArch64::ST1Fourv1d_POST);
3849 case AArch64ISD::ST1x2post: {
3850 VT = Node->getOperand(1).getValueType();
3851 if (VT == MVT::v8i8) {
3852 SelectPostStore(Node, 2, AArch64::ST1Twov8b_POST);
3854 } else if (VT == MVT::v16i8) {
3855 SelectPostStore(Node, 2, AArch64::ST1Twov16b_POST);
3857 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3858 SelectPostStore(Node, 2, AArch64::ST1Twov4h_POST);
3860 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3861 SelectPostStore(Node, 2, AArch64::ST1Twov8h_POST);
3863 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3864 SelectPostStore(Node, 2, AArch64::ST1Twov2s_POST);
3866 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3867 SelectPostStore(Node, 2, AArch64::ST1Twov4s_POST);
3869 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3870 SelectPostStore(Node, 2, AArch64::ST1Twov1d_POST);
3872 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3873 SelectPostStore(Node, 2, AArch64::ST1Twov2d_POST);
3878 case AArch64ISD::ST1x3post: {
3879 VT = Node->getOperand(1).getValueType();
3880 if (VT == MVT::v8i8) {
3881 SelectPostStore(Node, 3, AArch64::ST1Threev8b_POST);
3883 } else if (VT == MVT::v16i8) {
3884 SelectPostStore(Node, 3, AArch64::ST1Threev16b_POST);
3886 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3887 SelectPostStore(Node, 3, AArch64::ST1Threev4h_POST);
3889 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3890 SelectPostStore(Node, 3, AArch64::ST1Threev8h_POST);
3892 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3893 SelectPostStore(Node, 3, AArch64::ST1Threev2s_POST);
3895 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3896 SelectPostStore(Node, 3, AArch64::ST1Threev4s_POST);
3898 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3899 SelectPostStore(Node, 3, AArch64::ST1Threev1d_POST);
3901 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3902 SelectPostStore(Node, 3, AArch64::ST1Threev2d_POST);
3907 case AArch64ISD::ST1x4post: {
3908 VT = Node->getOperand(1).getValueType();
3909 if (VT == MVT::v8i8) {
3910 SelectPostStore(Node, 4, AArch64::ST1Fourv8b_POST);
3912 } else if (VT == MVT::v16i8) {
3913 SelectPostStore(Node, 4, AArch64::ST1Fourv16b_POST);
3915 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3916 SelectPostStore(Node, 4, AArch64::ST1Fourv4h_POST);
3918 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3919 SelectPostStore(Node, 4, AArch64::ST1Fourv8h_POST);
3921 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3922 SelectPostStore(Node, 4, AArch64::ST1Fourv2s_POST);
3924 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3925 SelectPostStore(Node, 4, AArch64::ST1Fourv4s_POST);
3927 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3928 SelectPostStore(Node, 4, AArch64::ST1Fourv1d_POST);
3930 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3931 SelectPostStore(Node, 4, AArch64::ST1Fourv2d_POST);
3936 case AArch64ISD::ST2LANEpost: {
3937 VT = Node->getOperand(1).getValueType();
3938 if (VT == MVT::v16i8 || VT == MVT::v8i8) {
3939 SelectPostStoreLane(Node, 2, AArch64::ST2i8_POST);
3941 } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
3943 SelectPostStoreLane(Node, 2, AArch64::ST2i16_POST);
3945 } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
3947 SelectPostStoreLane(Node, 2, AArch64::ST2i32_POST);
3949 } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
3951 SelectPostStoreLane(Node, 2, AArch64::ST2i64_POST);
3956 case AArch64ISD::ST3LANEpost: {
3957 VT = Node->getOperand(1).getValueType();
3958 if (VT == MVT::v16i8 || VT == MVT::v8i8) {
3959 SelectPostStoreLane(Node, 3, AArch64::ST3i8_POST);
3961 } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
3963 SelectPostStoreLane(Node, 3, AArch64::ST3i16_POST);
3965 } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
3967 SelectPostStoreLane(Node, 3, AArch64::ST3i32_POST);
3969 } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
3971 SelectPostStoreLane(Node, 3, AArch64::ST3i64_POST);
3976 case AArch64ISD::ST4LANEpost: {
3977 VT = Node->getOperand(1).getValueType();
3978 if (VT == MVT::v16i8 || VT == MVT::v8i8) {
3979 SelectPostStoreLane(Node, 4, AArch64::ST4i8_POST);
3981 } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
3983 SelectPostStoreLane(Node, 4, AArch64::ST4i16_POST);
3985 } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
3987 SelectPostStoreLane(Node, 4, AArch64::ST4i32_POST);
3989 } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
3991 SelectPostStoreLane(Node, 4, AArch64::ST4i64_POST);
3998 // Select the default instruction
4002 /// createAArch64ISelDag - This pass converts a legalized DAG into a
4003 /// AArch64-specific DAG, ready for instruction scheduling.
4004 FunctionPass *llvm::createAArch64ISelDag(AArch64TargetMachine &TM,
4005 CodeGenOpt::Level OptLevel) {
4006 return new AArch64DAGToDAGISel(TM, OptLevel);