1 //===-- AArch64ISelDAGToDAG.cpp - A dag to dag inst selector for AArch64 --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the AArch64 target.
12 //===----------------------------------------------------------------------===//
14 #include "AArch64TargetMachine.h"
15 #include "MCTargetDesc/AArch64AddressingModes.h"
16 #include "llvm/ADT/APSInt.h"
17 #include "llvm/CodeGen/SelectionDAGISel.h"
18 #include "llvm/IR/Function.h" // To access function attributes.
19 #include "llvm/IR/GlobalValue.h"
20 #include "llvm/IR/Intrinsics.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/KnownBits.h"
24 #include "llvm/Support/MathExtras.h"
25 #include "llvm/Support/raw_ostream.h"
29 #define DEBUG_TYPE "aarch64-isel"
31 //===--------------------------------------------------------------------===//
32 /// AArch64DAGToDAGISel - AArch64 specific code to select AArch64 machine
33 /// instructions for SelectionDAG operations.
37 class AArch64DAGToDAGISel : public SelectionDAGISel {
39 /// Subtarget - Keep a pointer to the AArch64Subtarget around so that we can
40 /// make the right decision when generating code for different targets.
41 const AArch64Subtarget *Subtarget;
46 explicit AArch64DAGToDAGISel(AArch64TargetMachine &tm,
47 CodeGenOpt::Level OptLevel)
48 : SelectionDAGISel(tm, OptLevel), Subtarget(nullptr),
51 StringRef getPassName() const override {
52 return "AArch64 Instruction Selection";
55 bool runOnMachineFunction(MachineFunction &MF) override {
56 ForCodeSize = MF.getFunction().optForSize();
57 Subtarget = &MF.getSubtarget<AArch64Subtarget>();
58 return SelectionDAGISel::runOnMachineFunction(MF);
61 void Select(SDNode *Node) override;
63 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
64 /// inline asm expressions.
65 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
66 unsigned ConstraintID,
67 std::vector<SDValue> &OutOps) override;
69 bool tryMLAV64LaneV128(SDNode *N);
70 bool tryMULLV64LaneV128(unsigned IntNo, SDNode *N);
71 bool SelectArithExtendedRegister(SDValue N, SDValue &Reg, SDValue &Shift);
72 bool SelectArithImmed(SDValue N, SDValue &Val, SDValue &Shift);
73 bool SelectNegArithImmed(SDValue N, SDValue &Val, SDValue &Shift);
74 bool SelectArithShiftedRegister(SDValue N, SDValue &Reg, SDValue &Shift) {
75 return SelectShiftedRegister(N, false, Reg, Shift);
77 bool SelectLogicalShiftedRegister(SDValue N, SDValue &Reg, SDValue &Shift) {
78 return SelectShiftedRegister(N, true, Reg, Shift);
80 bool SelectAddrModeIndexed7S8(SDValue N, SDValue &Base, SDValue &OffImm) {
81 return SelectAddrModeIndexed7S(N, 1, Base, OffImm);
83 bool SelectAddrModeIndexed7S16(SDValue N, SDValue &Base, SDValue &OffImm) {
84 return SelectAddrModeIndexed7S(N, 2, Base, OffImm);
86 bool SelectAddrModeIndexed7S32(SDValue N, SDValue &Base, SDValue &OffImm) {
87 return SelectAddrModeIndexed7S(N, 4, Base, OffImm);
89 bool SelectAddrModeIndexed7S64(SDValue N, SDValue &Base, SDValue &OffImm) {
90 return SelectAddrModeIndexed7S(N, 8, Base, OffImm);
92 bool SelectAddrModeIndexed7S128(SDValue N, SDValue &Base, SDValue &OffImm) {
93 return SelectAddrModeIndexed7S(N, 16, Base, OffImm);
95 bool SelectAddrModeIndexed8(SDValue N, SDValue &Base, SDValue &OffImm) {
96 return SelectAddrModeIndexed(N, 1, Base, OffImm);
98 bool SelectAddrModeIndexed16(SDValue N, SDValue &Base, SDValue &OffImm) {
99 return SelectAddrModeIndexed(N, 2, Base, OffImm);
101 bool SelectAddrModeIndexed32(SDValue N, SDValue &Base, SDValue &OffImm) {
102 return SelectAddrModeIndexed(N, 4, Base, OffImm);
104 bool SelectAddrModeIndexed64(SDValue N, SDValue &Base, SDValue &OffImm) {
105 return SelectAddrModeIndexed(N, 8, Base, OffImm);
107 bool SelectAddrModeIndexed128(SDValue N, SDValue &Base, SDValue &OffImm) {
108 return SelectAddrModeIndexed(N, 16, Base, OffImm);
110 bool SelectAddrModeUnscaled8(SDValue N, SDValue &Base, SDValue &OffImm) {
111 return SelectAddrModeUnscaled(N, 1, Base, OffImm);
113 bool SelectAddrModeUnscaled16(SDValue N, SDValue &Base, SDValue &OffImm) {
114 return SelectAddrModeUnscaled(N, 2, Base, OffImm);
116 bool SelectAddrModeUnscaled32(SDValue N, SDValue &Base, SDValue &OffImm) {
117 return SelectAddrModeUnscaled(N, 4, Base, OffImm);
119 bool SelectAddrModeUnscaled64(SDValue N, SDValue &Base, SDValue &OffImm) {
120 return SelectAddrModeUnscaled(N, 8, Base, OffImm);
122 bool SelectAddrModeUnscaled128(SDValue N, SDValue &Base, SDValue &OffImm) {
123 return SelectAddrModeUnscaled(N, 16, Base, OffImm);
127 bool SelectAddrModeWRO(SDValue N, SDValue &Base, SDValue &Offset,
128 SDValue &SignExtend, SDValue &DoShift) {
129 return SelectAddrModeWRO(N, Width / 8, Base, Offset, SignExtend, DoShift);
133 bool SelectAddrModeXRO(SDValue N, SDValue &Base, SDValue &Offset,
134 SDValue &SignExtend, SDValue &DoShift) {
135 return SelectAddrModeXRO(N, Width / 8, Base, Offset, SignExtend, DoShift);
139 /// Form sequences of consecutive 64/128-bit registers for use in NEON
140 /// instructions making use of a vector-list (e.g. ldN, tbl). Vecs must have
141 /// between 1 and 4 elements. If it contains a single element that is returned
142 /// unchanged; otherwise a REG_SEQUENCE value is returned.
143 SDValue createDTuple(ArrayRef<SDValue> Vecs);
144 SDValue createQTuple(ArrayRef<SDValue> Vecs);
146 /// Generic helper for the createDTuple/createQTuple
147 /// functions. Those should almost always be called instead.
148 SDValue createTuple(ArrayRef<SDValue> Vecs, const unsigned RegClassIDs[],
149 const unsigned SubRegs[]);
151 void SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, bool isExt);
153 bool tryIndexedLoad(SDNode *N);
155 void SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
157 void SelectPostLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
159 void SelectLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
160 void SelectPostLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
162 void SelectStore(SDNode *N, unsigned NumVecs, unsigned Opc);
163 void SelectPostStore(SDNode *N, unsigned NumVecs, unsigned Opc);
164 void SelectStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
165 void SelectPostStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
167 bool tryBitfieldExtractOp(SDNode *N);
168 bool tryBitfieldExtractOpFromSExt(SDNode *N);
169 bool tryBitfieldInsertOp(SDNode *N);
170 bool tryBitfieldInsertInZeroOp(SDNode *N);
172 bool tryReadRegister(SDNode *N);
173 bool tryWriteRegister(SDNode *N);
175 // Include the pieces autogenerated from the target description.
176 #include "AArch64GenDAGISel.inc"
179 bool SelectShiftedRegister(SDValue N, bool AllowROR, SDValue &Reg,
181 bool SelectAddrModeIndexed7S(SDValue N, unsigned Size, SDValue &Base,
183 bool SelectAddrModeIndexed(SDValue N, unsigned Size, SDValue &Base,
185 bool SelectAddrModeUnscaled(SDValue N, unsigned Size, SDValue &Base,
187 bool SelectAddrModeWRO(SDValue N, unsigned Size, SDValue &Base,
188 SDValue &Offset, SDValue &SignExtend,
190 bool SelectAddrModeXRO(SDValue N, unsigned Size, SDValue &Base,
191 SDValue &Offset, SDValue &SignExtend,
193 bool isWorthFolding(SDValue V) const;
194 bool SelectExtendedSHL(SDValue N, unsigned Size, bool WantExtend,
195 SDValue &Offset, SDValue &SignExtend);
197 template<unsigned RegWidth>
198 bool SelectCVTFixedPosOperand(SDValue N, SDValue &FixedPos) {
199 return SelectCVTFixedPosOperand(N, FixedPos, RegWidth);
202 bool SelectCVTFixedPosOperand(SDValue N, SDValue &FixedPos, unsigned Width);
204 bool SelectCMP_SWAP(SDNode *N);
207 } // end anonymous namespace
209 /// isIntImmediate - This method tests to see if the node is a constant
210 /// operand. If so Imm will receive the 32-bit value.
211 static bool isIntImmediate(const SDNode *N, uint64_t &Imm) {
212 if (const ConstantSDNode *C = dyn_cast<const ConstantSDNode>(N)) {
213 Imm = C->getZExtValue();
219 // isIntImmediate - This method tests to see if a constant operand.
220 // If so Imm will receive the value.
221 static bool isIntImmediate(SDValue N, uint64_t &Imm) {
222 return isIntImmediate(N.getNode(), Imm);
225 // isOpcWithIntImmediate - This method tests to see if the node is a specific
226 // opcode and that it has a immediate integer right operand.
227 // If so Imm will receive the 32 bit value.
228 static bool isOpcWithIntImmediate(const SDNode *N, unsigned Opc,
230 return N->getOpcode() == Opc &&
231 isIntImmediate(N->getOperand(1).getNode(), Imm);
234 bool AArch64DAGToDAGISel::SelectInlineAsmMemoryOperand(
235 const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
236 switch(ConstraintID) {
238 llvm_unreachable("Unexpected asm memory constraint");
239 case InlineAsm::Constraint_i:
240 case InlineAsm::Constraint_m:
241 case InlineAsm::Constraint_Q:
242 // We need to make sure that this one operand does not end up in XZR, thus
243 // require the address to be in a PointerRegClass register.
244 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
245 const TargetRegisterClass *TRC = TRI->getPointerRegClass(*MF);
247 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i64);
249 SDValue(CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
250 dl, Op.getValueType(),
252 OutOps.push_back(NewOp);
258 /// SelectArithImmed - Select an immediate value that can be represented as
259 /// a 12-bit value shifted left by either 0 or 12. If so, return true with
260 /// Val set to the 12-bit value and Shift set to the shifter operand.
261 bool AArch64DAGToDAGISel::SelectArithImmed(SDValue N, SDValue &Val,
263 // This function is called from the addsub_shifted_imm ComplexPattern,
264 // which lists [imm] as the list of opcode it's interested in, however
265 // we still need to check whether the operand is actually an immediate
266 // here because the ComplexPattern opcode list is only used in
267 // root-level opcode matching.
268 if (!isa<ConstantSDNode>(N.getNode()))
271 uint64_t Immed = cast<ConstantSDNode>(N.getNode())->getZExtValue();
274 if (Immed >> 12 == 0) {
276 } else if ((Immed & 0xfff) == 0 && Immed >> 24 == 0) {
282 unsigned ShVal = AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt);
284 Val = CurDAG->getTargetConstant(Immed, dl, MVT::i32);
285 Shift = CurDAG->getTargetConstant(ShVal, dl, MVT::i32);
289 /// SelectNegArithImmed - As above, but negates the value before trying to
291 bool AArch64DAGToDAGISel::SelectNegArithImmed(SDValue N, SDValue &Val,
293 // This function is called from the addsub_shifted_imm ComplexPattern,
294 // which lists [imm] as the list of opcode it's interested in, however
295 // we still need to check whether the operand is actually an immediate
296 // here because the ComplexPattern opcode list is only used in
297 // root-level opcode matching.
298 if (!isa<ConstantSDNode>(N.getNode()))
301 // The immediate operand must be a 24-bit zero-extended immediate.
302 uint64_t Immed = cast<ConstantSDNode>(N.getNode())->getZExtValue();
304 // This negation is almost always valid, but "cmp wN, #0" and "cmn wN, #0"
305 // have the opposite effect on the C flag, so this pattern mustn't match under
306 // those circumstances.
310 if (N.getValueType() == MVT::i32)
311 Immed = ~((uint32_t)Immed) + 1;
313 Immed = ~Immed + 1ULL;
314 if (Immed & 0xFFFFFFFFFF000000ULL)
317 Immed &= 0xFFFFFFULL;
318 return SelectArithImmed(CurDAG->getConstant(Immed, SDLoc(N), MVT::i32), Val,
322 /// getShiftTypeForNode - Translate a shift node to the corresponding
324 static AArch64_AM::ShiftExtendType getShiftTypeForNode(SDValue N) {
325 switch (N.getOpcode()) {
327 return AArch64_AM::InvalidShiftExtend;
329 return AArch64_AM::LSL;
331 return AArch64_AM::LSR;
333 return AArch64_AM::ASR;
335 return AArch64_AM::ROR;
339 /// \brief Determine whether it is worth it to fold SHL into the addressing
341 static bool isWorthFoldingSHL(SDValue V) {
342 assert(V.getOpcode() == ISD::SHL && "invalid opcode");
343 // It is worth folding logical shift of up to three places.
344 auto *CSD = dyn_cast<ConstantSDNode>(V.getOperand(1));
347 unsigned ShiftVal = CSD->getZExtValue();
351 // Check if this particular node is reused in any non-memory related
352 // operation. If yes, do not try to fold this node into the address
353 // computation, since the computation will be kept.
354 const SDNode *Node = V.getNode();
355 for (SDNode *UI : Node->uses())
356 if (!isa<MemSDNode>(*UI))
357 for (SDNode *UII : UI->uses())
358 if (!isa<MemSDNode>(*UII))
363 /// \brief Determine whether it is worth to fold V into an extended register.
364 bool AArch64DAGToDAGISel::isWorthFolding(SDValue V) const {
365 // Trivial if we are optimizing for code size or if there is only
366 // one use of the value.
367 if (ForCodeSize || V.hasOneUse())
369 // If a subtarget has a fastpath LSL we can fold a logical shift into
370 // the addressing mode and save a cycle.
371 if (Subtarget->hasLSLFast() && V.getOpcode() == ISD::SHL &&
372 isWorthFoldingSHL(V))
374 if (Subtarget->hasLSLFast() && V.getOpcode() == ISD::ADD) {
375 const SDValue LHS = V.getOperand(0);
376 const SDValue RHS = V.getOperand(1);
377 if (LHS.getOpcode() == ISD::SHL && isWorthFoldingSHL(LHS))
379 if (RHS.getOpcode() == ISD::SHL && isWorthFoldingSHL(RHS))
383 // It hurts otherwise, since the value will be reused.
387 /// SelectShiftedRegister - Select a "shifted register" operand. If the value
388 /// is not shifted, set the Shift operand to default of "LSL 0". The logical
389 /// instructions allow the shifted register to be rotated, but the arithmetic
390 /// instructions do not. The AllowROR parameter specifies whether ROR is
392 bool AArch64DAGToDAGISel::SelectShiftedRegister(SDValue N, bool AllowROR,
393 SDValue &Reg, SDValue &Shift) {
394 AArch64_AM::ShiftExtendType ShType = getShiftTypeForNode(N);
395 if (ShType == AArch64_AM::InvalidShiftExtend)
397 if (!AllowROR && ShType == AArch64_AM::ROR)
400 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
401 unsigned BitSize = N.getValueSizeInBits();
402 unsigned Val = RHS->getZExtValue() & (BitSize - 1);
403 unsigned ShVal = AArch64_AM::getShifterImm(ShType, Val);
405 Reg = N.getOperand(0);
406 Shift = CurDAG->getTargetConstant(ShVal, SDLoc(N), MVT::i32);
407 return isWorthFolding(N);
413 /// getExtendTypeForNode - Translate an extend node to the corresponding
414 /// ExtendType value.
415 static AArch64_AM::ShiftExtendType
416 getExtendTypeForNode(SDValue N, bool IsLoadStore = false) {
417 if (N.getOpcode() == ISD::SIGN_EXTEND ||
418 N.getOpcode() == ISD::SIGN_EXTEND_INREG) {
420 if (N.getOpcode() == ISD::SIGN_EXTEND_INREG)
421 SrcVT = cast<VTSDNode>(N.getOperand(1))->getVT();
423 SrcVT = N.getOperand(0).getValueType();
425 if (!IsLoadStore && SrcVT == MVT::i8)
426 return AArch64_AM::SXTB;
427 else if (!IsLoadStore && SrcVT == MVT::i16)
428 return AArch64_AM::SXTH;
429 else if (SrcVT == MVT::i32)
430 return AArch64_AM::SXTW;
431 assert(SrcVT != MVT::i64 && "extend from 64-bits?");
433 return AArch64_AM::InvalidShiftExtend;
434 } else if (N.getOpcode() == ISD::ZERO_EXTEND ||
435 N.getOpcode() == ISD::ANY_EXTEND) {
436 EVT SrcVT = N.getOperand(0).getValueType();
437 if (!IsLoadStore && SrcVT == MVT::i8)
438 return AArch64_AM::UXTB;
439 else if (!IsLoadStore && SrcVT == MVT::i16)
440 return AArch64_AM::UXTH;
441 else if (SrcVT == MVT::i32)
442 return AArch64_AM::UXTW;
443 assert(SrcVT != MVT::i64 && "extend from 64-bits?");
445 return AArch64_AM::InvalidShiftExtend;
446 } else if (N.getOpcode() == ISD::AND) {
447 ConstantSDNode *CSD = dyn_cast<ConstantSDNode>(N.getOperand(1));
449 return AArch64_AM::InvalidShiftExtend;
450 uint64_t AndMask = CSD->getZExtValue();
454 return AArch64_AM::InvalidShiftExtend;
456 return !IsLoadStore ? AArch64_AM::UXTB : AArch64_AM::InvalidShiftExtend;
458 return !IsLoadStore ? AArch64_AM::UXTH : AArch64_AM::InvalidShiftExtend;
460 return AArch64_AM::UXTW;
464 return AArch64_AM::InvalidShiftExtend;
467 // Helper for SelectMLAV64LaneV128 - Recognize high lane extracts.
468 static bool checkHighLaneIndex(SDNode *DL, SDValue &LaneOp, int &LaneIdx) {
469 if (DL->getOpcode() != AArch64ISD::DUPLANE16 &&
470 DL->getOpcode() != AArch64ISD::DUPLANE32)
473 SDValue SV = DL->getOperand(0);
474 if (SV.getOpcode() != ISD::INSERT_SUBVECTOR)
477 SDValue EV = SV.getOperand(1);
478 if (EV.getOpcode() != ISD::EXTRACT_SUBVECTOR)
481 ConstantSDNode *DLidx = cast<ConstantSDNode>(DL->getOperand(1).getNode());
482 ConstantSDNode *EVidx = cast<ConstantSDNode>(EV.getOperand(1).getNode());
483 LaneIdx = DLidx->getSExtValue() + EVidx->getSExtValue();
484 LaneOp = EV.getOperand(0);
489 // Helper for SelectOpcV64LaneV128 - Recognize operations where one operand is a
490 // high lane extract.
491 static bool checkV64LaneV128(SDValue Op0, SDValue Op1, SDValue &StdOp,
492 SDValue &LaneOp, int &LaneIdx) {
494 if (!checkHighLaneIndex(Op0.getNode(), LaneOp, LaneIdx)) {
496 if (!checkHighLaneIndex(Op0.getNode(), LaneOp, LaneIdx))
503 /// SelectMLAV64LaneV128 - AArch64 supports vector MLAs where one multiplicand
504 /// is a lane in the upper half of a 128-bit vector. Recognize and select this
505 /// so that we don't emit unnecessary lane extracts.
506 bool AArch64DAGToDAGISel::tryMLAV64LaneV128(SDNode *N) {
508 SDValue Op0 = N->getOperand(0);
509 SDValue Op1 = N->getOperand(1);
510 SDValue MLAOp1; // Will hold ordinary multiplicand for MLA.
511 SDValue MLAOp2; // Will hold lane-accessed multiplicand for MLA.
512 int LaneIdx = -1; // Will hold the lane index.
514 if (Op1.getOpcode() != ISD::MUL ||
515 !checkV64LaneV128(Op1.getOperand(0), Op1.getOperand(1), MLAOp1, MLAOp2,
518 if (Op1.getOpcode() != ISD::MUL ||
519 !checkV64LaneV128(Op1.getOperand(0), Op1.getOperand(1), MLAOp1, MLAOp2,
524 SDValue LaneIdxVal = CurDAG->getTargetConstant(LaneIdx, dl, MVT::i64);
526 SDValue Ops[] = { Op0, MLAOp1, MLAOp2, LaneIdxVal };
528 unsigned MLAOpc = ~0U;
530 switch (N->getSimpleValueType(0).SimpleTy) {
532 llvm_unreachable("Unrecognized MLA.");
534 MLAOpc = AArch64::MLAv4i16_indexed;
537 MLAOpc = AArch64::MLAv8i16_indexed;
540 MLAOpc = AArch64::MLAv2i32_indexed;
543 MLAOpc = AArch64::MLAv4i32_indexed;
547 ReplaceNode(N, CurDAG->getMachineNode(MLAOpc, dl, N->getValueType(0), Ops));
551 bool AArch64DAGToDAGISel::tryMULLV64LaneV128(unsigned IntNo, SDNode *N) {
557 if (!checkV64LaneV128(N->getOperand(1), N->getOperand(2), SMULLOp0, SMULLOp1,
561 SDValue LaneIdxVal = CurDAG->getTargetConstant(LaneIdx, dl, MVT::i64);
563 SDValue Ops[] = { SMULLOp0, SMULLOp1, LaneIdxVal };
565 unsigned SMULLOpc = ~0U;
567 if (IntNo == Intrinsic::aarch64_neon_smull) {
568 switch (N->getSimpleValueType(0).SimpleTy) {
570 llvm_unreachable("Unrecognized SMULL.");
572 SMULLOpc = AArch64::SMULLv4i16_indexed;
575 SMULLOpc = AArch64::SMULLv2i32_indexed;
578 } else if (IntNo == Intrinsic::aarch64_neon_umull) {
579 switch (N->getSimpleValueType(0).SimpleTy) {
581 llvm_unreachable("Unrecognized SMULL.");
583 SMULLOpc = AArch64::UMULLv4i16_indexed;
586 SMULLOpc = AArch64::UMULLv2i32_indexed;
590 llvm_unreachable("Unrecognized intrinsic.");
592 ReplaceNode(N, CurDAG->getMachineNode(SMULLOpc, dl, N->getValueType(0), Ops));
596 /// Instructions that accept extend modifiers like UXTW expect the register
597 /// being extended to be a GPR32, but the incoming DAG might be acting on a
598 /// GPR64 (either via SEXT_INREG or AND). Extract the appropriate low bits if
599 /// this is the case.
600 static SDValue narrowIfNeeded(SelectionDAG *CurDAG, SDValue N) {
601 if (N.getValueType() == MVT::i32)
605 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32);
606 MachineSDNode *Node = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
607 dl, MVT::i32, N, SubReg);
608 return SDValue(Node, 0);
612 /// SelectArithExtendedRegister - Select a "extended register" operand. This
613 /// operand folds in an extend followed by an optional left shift.
614 bool AArch64DAGToDAGISel::SelectArithExtendedRegister(SDValue N, SDValue &Reg,
616 unsigned ShiftVal = 0;
617 AArch64_AM::ShiftExtendType Ext;
619 if (N.getOpcode() == ISD::SHL) {
620 ConstantSDNode *CSD = dyn_cast<ConstantSDNode>(N.getOperand(1));
623 ShiftVal = CSD->getZExtValue();
627 Ext = getExtendTypeForNode(N.getOperand(0));
628 if (Ext == AArch64_AM::InvalidShiftExtend)
631 Reg = N.getOperand(0).getOperand(0);
633 Ext = getExtendTypeForNode(N);
634 if (Ext == AArch64_AM::InvalidShiftExtend)
637 Reg = N.getOperand(0);
639 // Don't match if free 32-bit -> 64-bit zext can be used instead.
640 if (Ext == AArch64_AM::UXTW &&
641 Reg->getValueType(0).getSizeInBits() == 32 && isDef32(*Reg.getNode()))
645 // AArch64 mandates that the RHS of the operation must use the smallest
646 // register class that could contain the size being extended from. Thus,
647 // if we're folding a (sext i8), we need the RHS to be a GPR32, even though
648 // there might not be an actual 32-bit value in the program. We can
649 // (harmlessly) synthesize one by injected an EXTRACT_SUBREG here.
650 assert(Ext != AArch64_AM::UXTX && Ext != AArch64_AM::SXTX);
651 Reg = narrowIfNeeded(CurDAG, Reg);
652 Shift = CurDAG->getTargetConstant(getArithExtendImm(Ext, ShiftVal), SDLoc(N),
654 return isWorthFolding(N);
657 /// If there's a use of this ADDlow that's not itself a load/store then we'll
658 /// need to create a real ADD instruction from it anyway and there's no point in
659 /// folding it into the mem op. Theoretically, it shouldn't matter, but there's
660 /// a single pseudo-instruction for an ADRP/ADD pair so over-aggressive folding
661 /// leads to duplicated ADRP instructions.
662 static bool isWorthFoldingADDlow(SDValue N) {
663 for (auto Use : N->uses()) {
664 if (Use->getOpcode() != ISD::LOAD && Use->getOpcode() != ISD::STORE &&
665 Use->getOpcode() != ISD::ATOMIC_LOAD &&
666 Use->getOpcode() != ISD::ATOMIC_STORE)
669 // ldar and stlr have much more restrictive addressing modes (just a
671 if (isStrongerThanMonotonic(cast<MemSDNode>(Use)->getOrdering()))
678 /// SelectAddrModeIndexed7S - Select a "register plus scaled signed 7-bit
679 /// immediate" address. The "Size" argument is the size in bytes of the memory
680 /// reference, which determines the scale.
681 bool AArch64DAGToDAGISel::SelectAddrModeIndexed7S(SDValue N, unsigned Size,
685 const DataLayout &DL = CurDAG->getDataLayout();
686 const TargetLowering *TLI = getTargetLowering();
687 if (N.getOpcode() == ISD::FrameIndex) {
688 int FI = cast<FrameIndexSDNode>(N)->getIndex();
689 Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy(DL));
690 OffImm = CurDAG->getTargetConstant(0, dl, MVT::i64);
694 // As opposed to the (12-bit) Indexed addressing mode below, the 7-bit signed
695 // selected here doesn't support labels/immediates, only base+offset.
697 if (CurDAG->isBaseWithConstantOffset(N)) {
698 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
699 int64_t RHSC = RHS->getSExtValue();
700 unsigned Scale = Log2_32(Size);
701 if ((RHSC & (Size - 1)) == 0 && RHSC >= -(0x40 << Scale) &&
702 RHSC < (0x40 << Scale)) {
703 Base = N.getOperand(0);
704 if (Base.getOpcode() == ISD::FrameIndex) {
705 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
706 Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy(DL));
708 OffImm = CurDAG->getTargetConstant(RHSC >> Scale, dl, MVT::i64);
714 // Base only. The address will be materialized into a register before
715 // the memory is accessed.
716 // add x0, Xbase, #offset
719 OffImm = CurDAG->getTargetConstant(0, dl, MVT::i64);
723 /// SelectAddrModeIndexed - Select a "register plus scaled unsigned 12-bit
724 /// immediate" address. The "Size" argument is the size in bytes of the memory
725 /// reference, which determines the scale.
726 bool AArch64DAGToDAGISel::SelectAddrModeIndexed(SDValue N, unsigned Size,
727 SDValue &Base, SDValue &OffImm) {
729 const DataLayout &DL = CurDAG->getDataLayout();
730 const TargetLowering *TLI = getTargetLowering();
731 if (N.getOpcode() == ISD::FrameIndex) {
732 int FI = cast<FrameIndexSDNode>(N)->getIndex();
733 Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy(DL));
734 OffImm = CurDAG->getTargetConstant(0, dl, MVT::i64);
738 if (N.getOpcode() == AArch64ISD::ADDlow && isWorthFoldingADDlow(N)) {
739 GlobalAddressSDNode *GAN =
740 dyn_cast<GlobalAddressSDNode>(N.getOperand(1).getNode());
741 Base = N.getOperand(0);
742 OffImm = N.getOperand(1);
746 const GlobalValue *GV = GAN->getGlobal();
747 unsigned Alignment = GV->getAlignment();
748 Type *Ty = GV->getValueType();
749 if (Alignment == 0 && Ty->isSized())
750 Alignment = DL.getABITypeAlignment(Ty);
752 if (Alignment >= Size)
756 if (CurDAG->isBaseWithConstantOffset(N)) {
757 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
758 int64_t RHSC = (int64_t)RHS->getZExtValue();
759 unsigned Scale = Log2_32(Size);
760 if ((RHSC & (Size - 1)) == 0 && RHSC >= 0 && RHSC < (0x1000 << Scale)) {
761 Base = N.getOperand(0);
762 if (Base.getOpcode() == ISD::FrameIndex) {
763 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
764 Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy(DL));
766 OffImm = CurDAG->getTargetConstant(RHSC >> Scale, dl, MVT::i64);
772 // Before falling back to our general case, check if the unscaled
773 // instructions can handle this. If so, that's preferable.
774 if (SelectAddrModeUnscaled(N, Size, Base, OffImm))
777 // Base only. The address will be materialized into a register before
778 // the memory is accessed.
779 // add x0, Xbase, #offset
782 OffImm = CurDAG->getTargetConstant(0, dl, MVT::i64);
786 /// SelectAddrModeUnscaled - Select a "register plus unscaled signed 9-bit
787 /// immediate" address. This should only match when there is an offset that
788 /// is not valid for a scaled immediate addressing mode. The "Size" argument
789 /// is the size in bytes of the memory reference, which is needed here to know
790 /// what is valid for a scaled immediate.
791 bool AArch64DAGToDAGISel::SelectAddrModeUnscaled(SDValue N, unsigned Size,
794 if (!CurDAG->isBaseWithConstantOffset(N))
796 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
797 int64_t RHSC = RHS->getSExtValue();
798 // If the offset is valid as a scaled immediate, don't match here.
799 if ((RHSC & (Size - 1)) == 0 && RHSC >= 0 &&
800 RHSC < (0x1000 << Log2_32(Size)))
802 if (RHSC >= -256 && RHSC < 256) {
803 Base = N.getOperand(0);
804 if (Base.getOpcode() == ISD::FrameIndex) {
805 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
806 const TargetLowering *TLI = getTargetLowering();
807 Base = CurDAG->getTargetFrameIndex(
808 FI, TLI->getPointerTy(CurDAG->getDataLayout()));
810 OffImm = CurDAG->getTargetConstant(RHSC, SDLoc(N), MVT::i64);
817 static SDValue Widen(SelectionDAG *CurDAG, SDValue N) {
819 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32);
820 SDValue ImpDef = SDValue(
821 CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, MVT::i64), 0);
822 MachineSDNode *Node = CurDAG->getMachineNode(
823 TargetOpcode::INSERT_SUBREG, dl, MVT::i64, ImpDef, N, SubReg);
824 return SDValue(Node, 0);
827 /// \brief Check if the given SHL node (\p N), can be used to form an
828 /// extended register for an addressing mode.
829 bool AArch64DAGToDAGISel::SelectExtendedSHL(SDValue N, unsigned Size,
830 bool WantExtend, SDValue &Offset,
831 SDValue &SignExtend) {
832 assert(N.getOpcode() == ISD::SHL && "Invalid opcode.");
833 ConstantSDNode *CSD = dyn_cast<ConstantSDNode>(N.getOperand(1));
834 if (!CSD || (CSD->getZExtValue() & 0x7) != CSD->getZExtValue())
839 AArch64_AM::ShiftExtendType Ext =
840 getExtendTypeForNode(N.getOperand(0), true);
841 if (Ext == AArch64_AM::InvalidShiftExtend)
844 Offset = narrowIfNeeded(CurDAG, N.getOperand(0).getOperand(0));
845 SignExtend = CurDAG->getTargetConstant(Ext == AArch64_AM::SXTW, dl,
848 Offset = N.getOperand(0);
849 SignExtend = CurDAG->getTargetConstant(0, dl, MVT::i32);
852 unsigned LegalShiftVal = Log2_32(Size);
853 unsigned ShiftVal = CSD->getZExtValue();
855 if (ShiftVal != 0 && ShiftVal != LegalShiftVal)
858 return isWorthFolding(N);
861 bool AArch64DAGToDAGISel::SelectAddrModeWRO(SDValue N, unsigned Size,
862 SDValue &Base, SDValue &Offset,
865 if (N.getOpcode() != ISD::ADD)
867 SDValue LHS = N.getOperand(0);
868 SDValue RHS = N.getOperand(1);
871 // We don't want to match immediate adds here, because they are better lowered
872 // to the register-immediate addressing modes.
873 if (isa<ConstantSDNode>(LHS) || isa<ConstantSDNode>(RHS))
876 // Check if this particular node is reused in any non-memory related
877 // operation. If yes, do not try to fold this node into the address
878 // computation, since the computation will be kept.
879 const SDNode *Node = N.getNode();
880 for (SDNode *UI : Node->uses()) {
881 if (!isa<MemSDNode>(*UI))
885 // Remember if it is worth folding N when it produces extended register.
886 bool IsExtendedRegisterWorthFolding = isWorthFolding(N);
888 // Try to match a shifted extend on the RHS.
889 if (IsExtendedRegisterWorthFolding && RHS.getOpcode() == ISD::SHL &&
890 SelectExtendedSHL(RHS, Size, true, Offset, SignExtend)) {
892 DoShift = CurDAG->getTargetConstant(true, dl, MVT::i32);
896 // Try to match a shifted extend on the LHS.
897 if (IsExtendedRegisterWorthFolding && LHS.getOpcode() == ISD::SHL &&
898 SelectExtendedSHL(LHS, Size, true, Offset, SignExtend)) {
900 DoShift = CurDAG->getTargetConstant(true, dl, MVT::i32);
904 // There was no shift, whatever else we find.
905 DoShift = CurDAG->getTargetConstant(false, dl, MVT::i32);
907 AArch64_AM::ShiftExtendType Ext = AArch64_AM::InvalidShiftExtend;
908 // Try to match an unshifted extend on the LHS.
909 if (IsExtendedRegisterWorthFolding &&
910 (Ext = getExtendTypeForNode(LHS, true)) !=
911 AArch64_AM::InvalidShiftExtend) {
913 Offset = narrowIfNeeded(CurDAG, LHS.getOperand(0));
914 SignExtend = CurDAG->getTargetConstant(Ext == AArch64_AM::SXTW, dl,
916 if (isWorthFolding(LHS))
920 // Try to match an unshifted extend on the RHS.
921 if (IsExtendedRegisterWorthFolding &&
922 (Ext = getExtendTypeForNode(RHS, true)) !=
923 AArch64_AM::InvalidShiftExtend) {
925 Offset = narrowIfNeeded(CurDAG, RHS.getOperand(0));
926 SignExtend = CurDAG->getTargetConstant(Ext == AArch64_AM::SXTW, dl,
928 if (isWorthFolding(RHS))
935 // Check if the given immediate is preferred by ADD. If an immediate can be
936 // encoded in an ADD, or it can be encoded in an "ADD LSL #12" and can not be
937 // encoded by one MOVZ, return true.
938 static bool isPreferredADD(int64_t ImmOff) {
939 // Constant in [0x0, 0xfff] can be encoded in ADD.
940 if ((ImmOff & 0xfffffffffffff000LL) == 0x0LL)
942 // Check if it can be encoded in an "ADD LSL #12".
943 if ((ImmOff & 0xffffffffff000fffLL) == 0x0LL)
944 // As a single MOVZ is faster than a "ADD of LSL #12", ignore such constant.
945 return (ImmOff & 0xffffffffff00ffffLL) != 0x0LL &&
946 (ImmOff & 0xffffffffffff0fffLL) != 0x0LL;
950 bool AArch64DAGToDAGISel::SelectAddrModeXRO(SDValue N, unsigned Size,
951 SDValue &Base, SDValue &Offset,
954 if (N.getOpcode() != ISD::ADD)
956 SDValue LHS = N.getOperand(0);
957 SDValue RHS = N.getOperand(1);
960 // Check if this particular node is reused in any non-memory related
961 // operation. If yes, do not try to fold this node into the address
962 // computation, since the computation will be kept.
963 const SDNode *Node = N.getNode();
964 for (SDNode *UI : Node->uses()) {
965 if (!isa<MemSDNode>(*UI))
969 // Watch out if RHS is a wide immediate, it can not be selected into
970 // [BaseReg+Imm] addressing mode. Also it may not be able to be encoded into
971 // ADD/SUB. Instead it will use [BaseReg + 0] address mode and generate
972 // instructions like:
973 // MOV X0, WideImmediate
974 // ADD X1, BaseReg, X0
976 // For such situation, using [BaseReg, XReg] addressing mode can save one
978 // MOV X0, WideImmediate
979 // LDR X2, [BaseReg, X0]
980 if (isa<ConstantSDNode>(RHS)) {
981 int64_t ImmOff = (int64_t)cast<ConstantSDNode>(RHS)->getZExtValue();
982 unsigned Scale = Log2_32(Size);
983 // Skip the immediate can be selected by load/store addressing mode.
984 // Also skip the immediate can be encoded by a single ADD (SUB is also
985 // checked by using -ImmOff).
986 if ((ImmOff % Size == 0 && ImmOff >= 0 && ImmOff < (0x1000 << Scale)) ||
987 isPreferredADD(ImmOff) || isPreferredADD(-ImmOff))
990 SDValue Ops[] = { RHS };
992 CurDAG->getMachineNode(AArch64::MOVi64imm, DL, MVT::i64, Ops);
993 SDValue MOVIV = SDValue(MOVI, 0);
994 // This ADD of two X register will be selected into [Reg+Reg] mode.
995 N = CurDAG->getNode(ISD::ADD, DL, MVT::i64, LHS, MOVIV);
998 // Remember if it is worth folding N when it produces extended register.
999 bool IsExtendedRegisterWorthFolding = isWorthFolding(N);
1001 // Try to match a shifted extend on the RHS.
1002 if (IsExtendedRegisterWorthFolding && RHS.getOpcode() == ISD::SHL &&
1003 SelectExtendedSHL(RHS, Size, false, Offset, SignExtend)) {
1005 DoShift = CurDAG->getTargetConstant(true, DL, MVT::i32);
1009 // Try to match a shifted extend on the LHS.
1010 if (IsExtendedRegisterWorthFolding && LHS.getOpcode() == ISD::SHL &&
1011 SelectExtendedSHL(LHS, Size, false, Offset, SignExtend)) {
1013 DoShift = CurDAG->getTargetConstant(true, DL, MVT::i32);
1017 // Match any non-shifted, non-extend, non-immediate add expression.
1020 SignExtend = CurDAG->getTargetConstant(false, DL, MVT::i32);
1021 DoShift = CurDAG->getTargetConstant(false, DL, MVT::i32);
1022 // Reg1 + Reg2 is free: no check needed.
1026 SDValue AArch64DAGToDAGISel::createDTuple(ArrayRef<SDValue> Regs) {
1027 static const unsigned RegClassIDs[] = {
1028 AArch64::DDRegClassID, AArch64::DDDRegClassID, AArch64::DDDDRegClassID};
1029 static const unsigned SubRegs[] = {AArch64::dsub0, AArch64::dsub1,
1030 AArch64::dsub2, AArch64::dsub3};
1032 return createTuple(Regs, RegClassIDs, SubRegs);
1035 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) {
1036 static const unsigned RegClassIDs[] = {
1037 AArch64::QQRegClassID, AArch64::QQQRegClassID, AArch64::QQQQRegClassID};
1038 static const unsigned SubRegs[] = {AArch64::qsub0, AArch64::qsub1,
1039 AArch64::qsub2, AArch64::qsub3};
1041 return createTuple(Regs, RegClassIDs, SubRegs);
1044 SDValue AArch64DAGToDAGISel::createTuple(ArrayRef<SDValue> Regs,
1045 const unsigned RegClassIDs[],
1046 const unsigned SubRegs[]) {
1047 // There's no special register-class for a vector-list of 1 element: it's just
1049 if (Regs.size() == 1)
1052 assert(Regs.size() >= 2 && Regs.size() <= 4);
1056 SmallVector<SDValue, 4> Ops;
1058 // First operand of REG_SEQUENCE is the desired RegClass.
1060 CurDAG->getTargetConstant(RegClassIDs[Regs.size() - 2], DL, MVT::i32));
1062 // Then we get pairs of source & subregister-position for the components.
1063 for (unsigned i = 0; i < Regs.size(); ++i) {
1064 Ops.push_back(Regs[i]);
1065 Ops.push_back(CurDAG->getTargetConstant(SubRegs[i], DL, MVT::i32));
1069 CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL, MVT::Untyped, Ops);
1070 return SDValue(N, 0);
1073 void AArch64DAGToDAGISel::SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc,
1076 EVT VT = N->getValueType(0);
1078 unsigned ExtOff = isExt;
1080 // Form a REG_SEQUENCE to force register allocation.
1081 unsigned Vec0Off = ExtOff + 1;
1082 SmallVector<SDValue, 4> Regs(N->op_begin() + Vec0Off,
1083 N->op_begin() + Vec0Off + NumVecs);
1084 SDValue RegSeq = createQTuple(Regs);
1086 SmallVector<SDValue, 6> Ops;
1088 Ops.push_back(N->getOperand(1));
1089 Ops.push_back(RegSeq);
1090 Ops.push_back(N->getOperand(NumVecs + ExtOff + 1));
1091 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, VT, Ops));
1094 bool AArch64DAGToDAGISel::tryIndexedLoad(SDNode *N) {
1095 LoadSDNode *LD = cast<LoadSDNode>(N);
1096 if (LD->isUnindexed())
1098 EVT VT = LD->getMemoryVT();
1099 EVT DstVT = N->getValueType(0);
1100 ISD::MemIndexedMode AM = LD->getAddressingMode();
1101 bool IsPre = AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
1103 // We're not doing validity checking here. That was done when checking
1104 // if we should mark the load as indexed or not. We're just selecting
1105 // the right instruction.
1106 unsigned Opcode = 0;
1108 ISD::LoadExtType ExtType = LD->getExtensionType();
1109 bool InsertTo64 = false;
1111 Opcode = IsPre ? AArch64::LDRXpre : AArch64::LDRXpost;
1112 else if (VT == MVT::i32) {
1113 if (ExtType == ISD::NON_EXTLOAD)
1114 Opcode = IsPre ? AArch64::LDRWpre : AArch64::LDRWpost;
1115 else if (ExtType == ISD::SEXTLOAD)
1116 Opcode = IsPre ? AArch64::LDRSWpre : AArch64::LDRSWpost;
1118 Opcode = IsPre ? AArch64::LDRWpre : AArch64::LDRWpost;
1120 // The result of the load is only i32. It's the subreg_to_reg that makes
1124 } else if (VT == MVT::i16) {
1125 if (ExtType == ISD::SEXTLOAD) {
1126 if (DstVT == MVT::i64)
1127 Opcode = IsPre ? AArch64::LDRSHXpre : AArch64::LDRSHXpost;
1129 Opcode = IsPre ? AArch64::LDRSHWpre : AArch64::LDRSHWpost;
1131 Opcode = IsPre ? AArch64::LDRHHpre : AArch64::LDRHHpost;
1132 InsertTo64 = DstVT == MVT::i64;
1133 // The result of the load is only i32. It's the subreg_to_reg that makes
1137 } else if (VT == MVT::i8) {
1138 if (ExtType == ISD::SEXTLOAD) {
1139 if (DstVT == MVT::i64)
1140 Opcode = IsPre ? AArch64::LDRSBXpre : AArch64::LDRSBXpost;
1142 Opcode = IsPre ? AArch64::LDRSBWpre : AArch64::LDRSBWpost;
1144 Opcode = IsPre ? AArch64::LDRBBpre : AArch64::LDRBBpost;
1145 InsertTo64 = DstVT == MVT::i64;
1146 // The result of the load is only i32. It's the subreg_to_reg that makes
1150 } else if (VT == MVT::f16) {
1151 Opcode = IsPre ? AArch64::LDRHpre : AArch64::LDRHpost;
1152 } else if (VT == MVT::f32) {
1153 Opcode = IsPre ? AArch64::LDRSpre : AArch64::LDRSpost;
1154 } else if (VT == MVT::f64 || VT.is64BitVector()) {
1155 Opcode = IsPre ? AArch64::LDRDpre : AArch64::LDRDpost;
1156 } else if (VT.is128BitVector()) {
1157 Opcode = IsPre ? AArch64::LDRQpre : AArch64::LDRQpost;
1160 SDValue Chain = LD->getChain();
1161 SDValue Base = LD->getBasePtr();
1162 ConstantSDNode *OffsetOp = cast<ConstantSDNode>(LD->getOffset());
1163 int OffsetVal = (int)OffsetOp->getZExtValue();
1165 SDValue Offset = CurDAG->getTargetConstant(OffsetVal, dl, MVT::i64);
1166 SDValue Ops[] = { Base, Offset, Chain };
1167 SDNode *Res = CurDAG->getMachineNode(Opcode, dl, MVT::i64, DstVT,
1169 // Either way, we're replacing the node, so tell the caller that.
1170 SDValue LoadedVal = SDValue(Res, 1);
1172 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32);
1174 SDValue(CurDAG->getMachineNode(
1175 AArch64::SUBREG_TO_REG, dl, MVT::i64,
1176 CurDAG->getTargetConstant(0, dl, MVT::i64), LoadedVal,
1181 ReplaceUses(SDValue(N, 0), LoadedVal);
1182 ReplaceUses(SDValue(N, 1), SDValue(Res, 0));
1183 ReplaceUses(SDValue(N, 2), SDValue(Res, 2));
1184 CurDAG->RemoveDeadNode(N);
1188 void AArch64DAGToDAGISel::SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
1189 unsigned SubRegIdx) {
1191 EVT VT = N->getValueType(0);
1192 SDValue Chain = N->getOperand(0);
1194 SDValue Ops[] = {N->getOperand(2), // Mem operand;
1197 const EVT ResTys[] = {MVT::Untyped, MVT::Other};
1199 SDNode *Ld = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
1200 SDValue SuperReg = SDValue(Ld, 0);
1201 for (unsigned i = 0; i < NumVecs; ++i)
1202 ReplaceUses(SDValue(N, i),
1203 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg));
1205 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1));
1207 // Transfer memoperands.
1208 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1209 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1210 cast<MachineSDNode>(Ld)->setMemRefs(MemOp, MemOp + 1);
1212 CurDAG->RemoveDeadNode(N);
1215 void AArch64DAGToDAGISel::SelectPostLoad(SDNode *N, unsigned NumVecs,
1216 unsigned Opc, unsigned SubRegIdx) {
1218 EVT VT = N->getValueType(0);
1219 SDValue Chain = N->getOperand(0);
1221 SDValue Ops[] = {N->getOperand(1), // Mem operand
1222 N->getOperand(2), // Incremental
1225 const EVT ResTys[] = {MVT::i64, // Type of the write back register
1226 MVT::Untyped, MVT::Other};
1228 SDNode *Ld = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
1230 // Update uses of write back register
1231 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0));
1233 // Update uses of vector list
1234 SDValue SuperReg = SDValue(Ld, 1);
1236 ReplaceUses(SDValue(N, 0), SuperReg);
1238 for (unsigned i = 0; i < NumVecs; ++i)
1239 ReplaceUses(SDValue(N, i),
1240 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg));
1243 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(Ld, 2));
1244 CurDAG->RemoveDeadNode(N);
1247 void AArch64DAGToDAGISel::SelectStore(SDNode *N, unsigned NumVecs,
1250 EVT VT = N->getOperand(2)->getValueType(0);
1252 // Form a REG_SEQUENCE to force register allocation.
1253 bool Is128Bit = VT.getSizeInBits() == 128;
1254 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
1255 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs);
1257 SDValue Ops[] = {RegSeq, N->getOperand(NumVecs + 2), N->getOperand(0)};
1258 SDNode *St = CurDAG->getMachineNode(Opc, dl, N->getValueType(0), Ops);
1260 // Transfer memoperands.
1261 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1262 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1263 cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1);
1268 void AArch64DAGToDAGISel::SelectPostStore(SDNode *N, unsigned NumVecs,
1271 EVT VT = N->getOperand(2)->getValueType(0);
1272 const EVT ResTys[] = {MVT::i64, // Type of the write back register
1273 MVT::Other}; // Type for the Chain
1275 // Form a REG_SEQUENCE to force register allocation.
1276 bool Is128Bit = VT.getSizeInBits() == 128;
1277 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);
1278 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs);
1280 SDValue Ops[] = {RegSeq,
1281 N->getOperand(NumVecs + 1), // base register
1282 N->getOperand(NumVecs + 2), // Incremental
1283 N->getOperand(0)}; // Chain
1284 SDNode *St = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
1290 /// WidenVector - Given a value in the V64 register class, produce the
1291 /// equivalent value in the V128 register class.
1296 WidenVector(SelectionDAG &DAG) : DAG(DAG) {}
1298 SDValue operator()(SDValue V64Reg) {
1299 EVT VT = V64Reg.getValueType();
1300 unsigned NarrowSize = VT.getVectorNumElements();
1301 MVT EltTy = VT.getVectorElementType().getSimpleVT();
1302 MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize);
1306 SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, WideTy), 0);
1307 return DAG.getTargetInsertSubreg(AArch64::dsub, DL, WideTy, Undef, V64Reg);
1312 /// NarrowVector - Given a value in the V128 register class, produce the
1313 /// equivalent value in the V64 register class.
1314 static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) {
1315 EVT VT = V128Reg.getValueType();
1316 unsigned WideSize = VT.getVectorNumElements();
1317 MVT EltTy = VT.getVectorElementType().getSimpleVT();
1318 MVT NarrowTy = MVT::getVectorVT(EltTy, WideSize / 2);
1320 return DAG.getTargetExtractSubreg(AArch64::dsub, SDLoc(V128Reg), NarrowTy,
1324 void AArch64DAGToDAGISel::SelectLoadLane(SDNode *N, unsigned NumVecs,
1327 EVT VT = N->getValueType(0);
1328 bool Narrow = VT.getSizeInBits() == 64;
1330 // Form a REG_SEQUENCE to force register allocation.
1331 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
1334 transform(Regs, Regs.begin(),
1335 WidenVector(*CurDAG));
1337 SDValue RegSeq = createQTuple(Regs);
1339 const EVT ResTys[] = {MVT::Untyped, MVT::Other};
1342 cast<ConstantSDNode>(N->getOperand(NumVecs + 2))->getZExtValue();
1344 SDValue Ops[] = {RegSeq, CurDAG->getTargetConstant(LaneNo, dl, MVT::i64),
1345 N->getOperand(NumVecs + 3), N->getOperand(0)};
1346 SDNode *Ld = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
1347 SDValue SuperReg = SDValue(Ld, 0);
1349 EVT WideVT = RegSeq.getOperand(1)->getValueType(0);
1350 static const unsigned QSubs[] = { AArch64::qsub0, AArch64::qsub1,
1351 AArch64::qsub2, AArch64::qsub3 };
1352 for (unsigned i = 0; i < NumVecs; ++i) {
1353 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT, SuperReg);
1355 NV = NarrowVector(NV, *CurDAG);
1356 ReplaceUses(SDValue(N, i), NV);
1359 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1));
1360 CurDAG->RemoveDeadNode(N);
1363 void AArch64DAGToDAGISel::SelectPostLoadLane(SDNode *N, unsigned NumVecs,
1366 EVT VT = N->getValueType(0);
1367 bool Narrow = VT.getSizeInBits() == 64;
1369 // Form a REG_SEQUENCE to force register allocation.
1370 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);
1373 transform(Regs, Regs.begin(),
1374 WidenVector(*CurDAG));
1376 SDValue RegSeq = createQTuple(Regs);
1378 const EVT ResTys[] = {MVT::i64, // Type of the write back register
1379 RegSeq->getValueType(0), MVT::Other};
1382 cast<ConstantSDNode>(N->getOperand(NumVecs + 1))->getZExtValue();
1384 SDValue Ops[] = {RegSeq,
1385 CurDAG->getTargetConstant(LaneNo, dl,
1386 MVT::i64), // Lane Number
1387 N->getOperand(NumVecs + 2), // Base register
1388 N->getOperand(NumVecs + 3), // Incremental
1390 SDNode *Ld = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
1392 // Update uses of the write back register
1393 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0));
1395 // Update uses of the vector list
1396 SDValue SuperReg = SDValue(Ld, 1);
1398 ReplaceUses(SDValue(N, 0),
1399 Narrow ? NarrowVector(SuperReg, *CurDAG) : SuperReg);
1401 EVT WideVT = RegSeq.getOperand(1)->getValueType(0);
1402 static const unsigned QSubs[] = { AArch64::qsub0, AArch64::qsub1,
1403 AArch64::qsub2, AArch64::qsub3 };
1404 for (unsigned i = 0; i < NumVecs; ++i) {
1405 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT,
1408 NV = NarrowVector(NV, *CurDAG);
1409 ReplaceUses(SDValue(N, i), NV);
1414 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(Ld, 2));
1415 CurDAG->RemoveDeadNode(N);
1418 void AArch64DAGToDAGISel::SelectStoreLane(SDNode *N, unsigned NumVecs,
1421 EVT VT = N->getOperand(2)->getValueType(0);
1422 bool Narrow = VT.getSizeInBits() == 64;
1424 // Form a REG_SEQUENCE to force register allocation.
1425 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
1428 transform(Regs, Regs.begin(),
1429 WidenVector(*CurDAG));
1431 SDValue RegSeq = createQTuple(Regs);
1434 cast<ConstantSDNode>(N->getOperand(NumVecs + 2))->getZExtValue();
1436 SDValue Ops[] = {RegSeq, CurDAG->getTargetConstant(LaneNo, dl, MVT::i64),
1437 N->getOperand(NumVecs + 3), N->getOperand(0)};
1438 SDNode *St = CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops);
1440 // Transfer memoperands.
1441 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1442 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1443 cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1);
1448 void AArch64DAGToDAGISel::SelectPostStoreLane(SDNode *N, unsigned NumVecs,
1451 EVT VT = N->getOperand(2)->getValueType(0);
1452 bool Narrow = VT.getSizeInBits() == 64;
1454 // Form a REG_SEQUENCE to force register allocation.
1455 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);
1458 transform(Regs, Regs.begin(),
1459 WidenVector(*CurDAG));
1461 SDValue RegSeq = createQTuple(Regs);
1463 const EVT ResTys[] = {MVT::i64, // Type of the write back register
1467 cast<ConstantSDNode>(N->getOperand(NumVecs + 1))->getZExtValue();
1469 SDValue Ops[] = {RegSeq, CurDAG->getTargetConstant(LaneNo, dl, MVT::i64),
1470 N->getOperand(NumVecs + 2), // Base Register
1471 N->getOperand(NumVecs + 3), // Incremental
1473 SDNode *St = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
1475 // Transfer memoperands.
1476 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1477 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1478 cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1);
1483 static bool isBitfieldExtractOpFromAnd(SelectionDAG *CurDAG, SDNode *N,
1484 unsigned &Opc, SDValue &Opd0,
1485 unsigned &LSB, unsigned &MSB,
1486 unsigned NumberOfIgnoredLowBits,
1487 bool BiggerPattern) {
1488 assert(N->getOpcode() == ISD::AND &&
1489 "N must be a AND operation to call this function");
1491 EVT VT = N->getValueType(0);
1493 // Here we can test the type of VT and return false when the type does not
1494 // match, but since it is done prior to that call in the current context
1495 // we turned that into an assert to avoid redundant code.
1496 assert((VT == MVT::i32 || VT == MVT::i64) &&
1497 "Type checking must have been done before calling this function");
1499 // FIXME: simplify-demanded-bits in DAGCombine will probably have
1500 // changed the AND node to a 32-bit mask operation. We'll have to
1501 // undo that as part of the transform here if we want to catch all
1502 // the opportunities.
1503 // Currently the NumberOfIgnoredLowBits argument helps to recover
1504 // form these situations when matching bigger pattern (bitfield insert).
1506 // For unsigned extracts, check for a shift right and mask
1507 uint64_t AndImm = 0;
1508 if (!isOpcWithIntImmediate(N, ISD::AND, AndImm))
1511 const SDNode *Op0 = N->getOperand(0).getNode();
1513 // Because of simplify-demanded-bits in DAGCombine, the mask may have been
1514 // simplified. Try to undo that
1515 AndImm |= (1 << NumberOfIgnoredLowBits) - 1;
1517 // The immediate is a mask of the low bits iff imm & (imm+1) == 0
1518 if (AndImm & (AndImm + 1))
1521 bool ClampMSB = false;
1522 uint64_t SrlImm = 0;
1523 // Handle the SRL + ANY_EXTEND case.
1524 if (VT == MVT::i64 && Op0->getOpcode() == ISD::ANY_EXTEND &&
1525 isOpcWithIntImmediate(Op0->getOperand(0).getNode(), ISD::SRL, SrlImm)) {
1526 // Extend the incoming operand of the SRL to 64-bit.
1527 Opd0 = Widen(CurDAG, Op0->getOperand(0).getOperand(0));
1528 // Make sure to clamp the MSB so that we preserve the semantics of the
1529 // original operations.
1531 } else if (VT == MVT::i32 && Op0->getOpcode() == ISD::TRUNCATE &&
1532 isOpcWithIntImmediate(Op0->getOperand(0).getNode(), ISD::SRL,
1534 // If the shift result was truncated, we can still combine them.
1535 Opd0 = Op0->getOperand(0).getOperand(0);
1537 // Use the type of SRL node.
1538 VT = Opd0->getValueType(0);
1539 } else if (isOpcWithIntImmediate(Op0, ISD::SRL, SrlImm)) {
1540 Opd0 = Op0->getOperand(0);
1541 } else if (BiggerPattern) {
1542 // Let's pretend a 0 shift right has been performed.
1543 // The resulting code will be at least as good as the original one
1544 // plus it may expose more opportunities for bitfield insert pattern.
1545 // FIXME: Currently we limit this to the bigger pattern, because
1546 // some optimizations expect AND and not UBFM.
1547 Opd0 = N->getOperand(0);
1551 // Bail out on large immediates. This happens when no proper
1552 // combining/constant folding was performed.
1553 if (!BiggerPattern && (SrlImm <= 0 || SrlImm >= VT.getSizeInBits())) {
1555 << ": Found large shift immediate, this should not happen\n"));
1560 MSB = SrlImm + (VT == MVT::i32 ? countTrailingOnes<uint32_t>(AndImm)
1561 : countTrailingOnes<uint64_t>(AndImm)) -
1564 // Since we're moving the extend before the right shift operation, we need
1565 // to clamp the MSB to make sure we don't shift in undefined bits instead of
1566 // the zeros which would get shifted in with the original right shift
1568 MSB = MSB > 31 ? 31 : MSB;
1570 Opc = VT == MVT::i32 ? AArch64::UBFMWri : AArch64::UBFMXri;
1574 static bool isBitfieldExtractOpFromSExtInReg(SDNode *N, unsigned &Opc,
1575 SDValue &Opd0, unsigned &Immr,
1577 assert(N->getOpcode() == ISD::SIGN_EXTEND_INREG);
1579 EVT VT = N->getValueType(0);
1580 unsigned BitWidth = VT.getSizeInBits();
1581 assert((VT == MVT::i32 || VT == MVT::i64) &&
1582 "Type checking must have been done before calling this function");
1584 SDValue Op = N->getOperand(0);
1585 if (Op->getOpcode() == ISD::TRUNCATE) {
1586 Op = Op->getOperand(0);
1587 VT = Op->getValueType(0);
1588 BitWidth = VT.getSizeInBits();
1592 if (!isOpcWithIntImmediate(Op.getNode(), ISD::SRL, ShiftImm) &&
1593 !isOpcWithIntImmediate(Op.getNode(), ISD::SRA, ShiftImm))
1596 unsigned Width = cast<VTSDNode>(N->getOperand(1))->getVT().getSizeInBits();
1597 if (ShiftImm + Width > BitWidth)
1600 Opc = (VT == MVT::i32) ? AArch64::SBFMWri : AArch64::SBFMXri;
1601 Opd0 = Op.getOperand(0);
1603 Imms = ShiftImm + Width - 1;
1607 static bool isSeveralBitsExtractOpFromShr(SDNode *N, unsigned &Opc,
1608 SDValue &Opd0, unsigned &LSB,
1610 // We are looking for the following pattern which basically extracts several
1611 // continuous bits from the source value and places it from the LSB of the
1612 // destination value, all other bits of the destination value or set to zero:
1614 // Value2 = AND Value, MaskImm
1615 // SRL Value2, ShiftImm
1617 // with MaskImm >> ShiftImm to search for the bit width.
1619 // This gets selected into a single UBFM:
1621 // UBFM Value, ShiftImm, BitWide + SrlImm -1
1624 if (N->getOpcode() != ISD::SRL)
1627 uint64_t AndMask = 0;
1628 if (!isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, AndMask))
1631 Opd0 = N->getOperand(0).getOperand(0);
1633 uint64_t SrlImm = 0;
1634 if (!isIntImmediate(N->getOperand(1), SrlImm))
1637 // Check whether we really have several bits extract here.
1638 unsigned BitWide = 64 - countLeadingOnes(~(AndMask >> SrlImm));
1639 if (BitWide && isMask_64(AndMask >> SrlImm)) {
1640 if (N->getValueType(0) == MVT::i32)
1641 Opc = AArch64::UBFMWri;
1643 Opc = AArch64::UBFMXri;
1646 MSB = BitWide + SrlImm - 1;
1653 static bool isBitfieldExtractOpFromShr(SDNode *N, unsigned &Opc, SDValue &Opd0,
1654 unsigned &Immr, unsigned &Imms,
1655 bool BiggerPattern) {
1656 assert((N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL) &&
1657 "N must be a SHR/SRA operation to call this function");
1659 EVT VT = N->getValueType(0);
1661 // Here we can test the type of VT and return false when the type does not
1662 // match, but since it is done prior to that call in the current context
1663 // we turned that into an assert to avoid redundant code.
1664 assert((VT == MVT::i32 || VT == MVT::i64) &&
1665 "Type checking must have been done before calling this function");
1667 // Check for AND + SRL doing several bits extract.
1668 if (isSeveralBitsExtractOpFromShr(N, Opc, Opd0, Immr, Imms))
1671 // We're looking for a shift of a shift.
1672 uint64_t ShlImm = 0;
1673 uint64_t TruncBits = 0;
1674 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, ShlImm)) {
1675 Opd0 = N->getOperand(0).getOperand(0);
1676 } else if (VT == MVT::i32 && N->getOpcode() == ISD::SRL &&
1677 N->getOperand(0).getNode()->getOpcode() == ISD::TRUNCATE) {
1678 // We are looking for a shift of truncate. Truncate from i64 to i32 could
1679 // be considered as setting high 32 bits as zero. Our strategy here is to
1680 // always generate 64bit UBFM. This consistency will help the CSE pass
1681 // later find more redundancy.
1682 Opd0 = N->getOperand(0).getOperand(0);
1683 TruncBits = Opd0->getValueType(0).getSizeInBits() - VT.getSizeInBits();
1684 VT = Opd0->getValueType(0);
1685 assert(VT == MVT::i64 && "the promoted type should be i64");
1686 } else if (BiggerPattern) {
1687 // Let's pretend a 0 shift left has been performed.
1688 // FIXME: Currently we limit this to the bigger pattern case,
1689 // because some optimizations expect AND and not UBFM
1690 Opd0 = N->getOperand(0);
1694 // Missing combines/constant folding may have left us with strange
1696 if (ShlImm >= VT.getSizeInBits()) {
1698 << ": Found large shift immediate, this should not happen\n"));
1702 uint64_t SrlImm = 0;
1703 if (!isIntImmediate(N->getOperand(1), SrlImm))
1706 assert(SrlImm > 0 && SrlImm < VT.getSizeInBits() &&
1707 "bad amount in shift node!");
1708 int immr = SrlImm - ShlImm;
1709 Immr = immr < 0 ? immr + VT.getSizeInBits() : immr;
1710 Imms = VT.getSizeInBits() - ShlImm - TruncBits - 1;
1711 // SRA requires a signed extraction
1713 Opc = N->getOpcode() == ISD::SRA ? AArch64::SBFMWri : AArch64::UBFMWri;
1715 Opc = N->getOpcode() == ISD::SRA ? AArch64::SBFMXri : AArch64::UBFMXri;
1719 bool AArch64DAGToDAGISel::tryBitfieldExtractOpFromSExt(SDNode *N) {
1720 assert(N->getOpcode() == ISD::SIGN_EXTEND);
1722 EVT VT = N->getValueType(0);
1723 EVT NarrowVT = N->getOperand(0)->getValueType(0);
1724 if (VT != MVT::i64 || NarrowVT != MVT::i32)
1728 SDValue Op = N->getOperand(0);
1729 if (!isOpcWithIntImmediate(Op.getNode(), ISD::SRA, ShiftImm))
1733 // Extend the incoming operand of the shift to 64-bits.
1734 SDValue Opd0 = Widen(CurDAG, Op.getOperand(0));
1735 unsigned Immr = ShiftImm;
1736 unsigned Imms = NarrowVT.getSizeInBits() - 1;
1737 SDValue Ops[] = {Opd0, CurDAG->getTargetConstant(Immr, dl, VT),
1738 CurDAG->getTargetConstant(Imms, dl, VT)};
1739 CurDAG->SelectNodeTo(N, AArch64::SBFMXri, VT, Ops);
1743 static bool isBitfieldExtractOp(SelectionDAG *CurDAG, SDNode *N, unsigned &Opc,
1744 SDValue &Opd0, unsigned &Immr, unsigned &Imms,
1745 unsigned NumberOfIgnoredLowBits = 0,
1746 bool BiggerPattern = false) {
1747 if (N->getValueType(0) != MVT::i32 && N->getValueType(0) != MVT::i64)
1750 switch (N->getOpcode()) {
1752 if (!N->isMachineOpcode())
1756 return isBitfieldExtractOpFromAnd(CurDAG, N, Opc, Opd0, Immr, Imms,
1757 NumberOfIgnoredLowBits, BiggerPattern);
1760 return isBitfieldExtractOpFromShr(N, Opc, Opd0, Immr, Imms, BiggerPattern);
1762 case ISD::SIGN_EXTEND_INREG:
1763 return isBitfieldExtractOpFromSExtInReg(N, Opc, Opd0, Immr, Imms);
1766 unsigned NOpc = N->getMachineOpcode();
1770 case AArch64::SBFMWri:
1771 case AArch64::UBFMWri:
1772 case AArch64::SBFMXri:
1773 case AArch64::UBFMXri:
1775 Opd0 = N->getOperand(0);
1776 Immr = cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
1777 Imms = cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
1784 bool AArch64DAGToDAGISel::tryBitfieldExtractOp(SDNode *N) {
1785 unsigned Opc, Immr, Imms;
1787 if (!isBitfieldExtractOp(CurDAG, N, Opc, Opd0, Immr, Imms))
1790 EVT VT = N->getValueType(0);
1793 // If the bit extract operation is 64bit but the original type is 32bit, we
1794 // need to add one EXTRACT_SUBREG.
1795 if ((Opc == AArch64::SBFMXri || Opc == AArch64::UBFMXri) && VT == MVT::i32) {
1796 SDValue Ops64[] = {Opd0, CurDAG->getTargetConstant(Immr, dl, MVT::i64),
1797 CurDAG->getTargetConstant(Imms, dl, MVT::i64)};
1799 SDNode *BFM = CurDAG->getMachineNode(Opc, dl, MVT::i64, Ops64);
1800 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32);
1801 ReplaceNode(N, CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl,
1802 MVT::i32, SDValue(BFM, 0), SubReg));
1806 SDValue Ops[] = {Opd0, CurDAG->getTargetConstant(Immr, dl, VT),
1807 CurDAG->getTargetConstant(Imms, dl, VT)};
1808 CurDAG->SelectNodeTo(N, Opc, VT, Ops);
1812 /// Does DstMask form a complementary pair with the mask provided by
1813 /// BitsToBeInserted, suitable for use in a BFI instruction. Roughly speaking,
1814 /// this asks whether DstMask zeroes precisely those bits that will be set by
1816 static bool isBitfieldDstMask(uint64_t DstMask, const APInt &BitsToBeInserted,
1817 unsigned NumberOfIgnoredHighBits, EVT VT) {
1818 assert((VT == MVT::i32 || VT == MVT::i64) &&
1819 "i32 or i64 mask type expected!");
1820 unsigned BitWidth = VT.getSizeInBits() - NumberOfIgnoredHighBits;
1822 APInt SignificantDstMask = APInt(BitWidth, DstMask);
1823 APInt SignificantBitsToBeInserted = BitsToBeInserted.zextOrTrunc(BitWidth);
1825 return (SignificantDstMask & SignificantBitsToBeInserted) == 0 &&
1826 (SignificantDstMask | SignificantBitsToBeInserted).isAllOnesValue();
1829 // Look for bits that will be useful for later uses.
1830 // A bit is consider useless as soon as it is dropped and never used
1831 // before it as been dropped.
1832 // E.g., looking for useful bit of x
1835 // After #1, x useful bits are 0x7, then the useful bits of x, live through
1837 // After #2, the useful bits of x are 0x4.
1838 // However, if x is used on an unpredicatable instruction, then all its bits
1844 static void getUsefulBits(SDValue Op, APInt &UsefulBits, unsigned Depth = 0);
1846 static void getUsefulBitsFromAndWithImmediate(SDValue Op, APInt &UsefulBits,
1849 cast<const ConstantSDNode>(Op.getOperand(1).getNode())->getZExtValue();
1850 Imm = AArch64_AM::decodeLogicalImmediate(Imm, UsefulBits.getBitWidth());
1851 UsefulBits &= APInt(UsefulBits.getBitWidth(), Imm);
1852 getUsefulBits(Op, UsefulBits, Depth + 1);
1855 static void getUsefulBitsFromBitfieldMoveOpd(SDValue Op, APInt &UsefulBits,
1856 uint64_t Imm, uint64_t MSB,
1858 // inherit the bitwidth value
1859 APInt OpUsefulBits(UsefulBits);
1863 OpUsefulBits <<= MSB - Imm + 1;
1865 // The interesting part will be in the lower part of the result
1866 getUsefulBits(Op, OpUsefulBits, Depth + 1);
1867 // The interesting part was starting at Imm in the argument
1868 OpUsefulBits <<= Imm;
1870 OpUsefulBits <<= MSB + 1;
1872 // The interesting part will be shifted in the result
1873 OpUsefulBits <<= OpUsefulBits.getBitWidth() - Imm;
1874 getUsefulBits(Op, OpUsefulBits, Depth + 1);
1875 // The interesting part was at zero in the argument
1876 OpUsefulBits.lshrInPlace(OpUsefulBits.getBitWidth() - Imm);
1879 UsefulBits &= OpUsefulBits;
1882 static void getUsefulBitsFromUBFM(SDValue Op, APInt &UsefulBits,
1885 cast<const ConstantSDNode>(Op.getOperand(1).getNode())->getZExtValue();
1887 cast<const ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue();
1889 getUsefulBitsFromBitfieldMoveOpd(Op, UsefulBits, Imm, MSB, Depth);
1892 static void getUsefulBitsFromOrWithShiftedReg(SDValue Op, APInt &UsefulBits,
1894 uint64_t ShiftTypeAndValue =
1895 cast<const ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue();
1896 APInt Mask(UsefulBits);
1897 Mask.clearAllBits();
1900 if (AArch64_AM::getShiftType(ShiftTypeAndValue) == AArch64_AM::LSL) {
1902 uint64_t ShiftAmt = AArch64_AM::getShiftValue(ShiftTypeAndValue);
1904 getUsefulBits(Op, Mask, Depth + 1);
1905 Mask.lshrInPlace(ShiftAmt);
1906 } else if (AArch64_AM::getShiftType(ShiftTypeAndValue) == AArch64_AM::LSR) {
1908 // We do not handle AArch64_AM::ASR, because the sign will change the
1909 // number of useful bits
1910 uint64_t ShiftAmt = AArch64_AM::getShiftValue(ShiftTypeAndValue);
1911 Mask.lshrInPlace(ShiftAmt);
1912 getUsefulBits(Op, Mask, Depth + 1);
1920 static void getUsefulBitsFromBFM(SDValue Op, SDValue Orig, APInt &UsefulBits,
1923 cast<const ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue();
1925 cast<const ConstantSDNode>(Op.getOperand(3).getNode())->getZExtValue();
1927 APInt OpUsefulBits(UsefulBits);
1930 APInt ResultUsefulBits(UsefulBits.getBitWidth(), 0);
1931 ResultUsefulBits.flipAllBits();
1932 APInt Mask(UsefulBits.getBitWidth(), 0);
1934 getUsefulBits(Op, ResultUsefulBits, Depth + 1);
1937 // The instruction is a BFXIL.
1938 uint64_t Width = MSB - Imm + 1;
1941 OpUsefulBits <<= Width;
1944 if (Op.getOperand(1) == Orig) {
1945 // Copy the low bits from the result to bits starting from LSB.
1946 Mask = ResultUsefulBits & OpUsefulBits;
1950 if (Op.getOperand(0) == Orig)
1951 // Bits starting from LSB in the input contribute to the result.
1952 Mask |= (ResultUsefulBits & ~OpUsefulBits);
1954 // The instruction is a BFI.
1955 uint64_t Width = MSB + 1;
1956 uint64_t LSB = UsefulBits.getBitWidth() - Imm;
1958 OpUsefulBits <<= Width;
1960 OpUsefulBits <<= LSB;
1962 if (Op.getOperand(1) == Orig) {
1963 // Copy the bits from the result to the zero bits.
1964 Mask = ResultUsefulBits & OpUsefulBits;
1965 Mask.lshrInPlace(LSB);
1968 if (Op.getOperand(0) == Orig)
1969 Mask |= (ResultUsefulBits & ~OpUsefulBits);
1975 static void getUsefulBitsForUse(SDNode *UserNode, APInt &UsefulBits,
1976 SDValue Orig, unsigned Depth) {
1978 // Users of this node should have already been instruction selected
1979 // FIXME: Can we turn that into an assert?
1980 if (!UserNode->isMachineOpcode())
1983 switch (UserNode->getMachineOpcode()) {
1986 case AArch64::ANDSWri:
1987 case AArch64::ANDSXri:
1988 case AArch64::ANDWri:
1989 case AArch64::ANDXri:
1990 // We increment Depth only when we call the getUsefulBits
1991 return getUsefulBitsFromAndWithImmediate(SDValue(UserNode, 0), UsefulBits,
1993 case AArch64::UBFMWri:
1994 case AArch64::UBFMXri:
1995 return getUsefulBitsFromUBFM(SDValue(UserNode, 0), UsefulBits, Depth);
1997 case AArch64::ORRWrs:
1998 case AArch64::ORRXrs:
1999 if (UserNode->getOperand(1) != Orig)
2001 return getUsefulBitsFromOrWithShiftedReg(SDValue(UserNode, 0), UsefulBits,
2003 case AArch64::BFMWri:
2004 case AArch64::BFMXri:
2005 return getUsefulBitsFromBFM(SDValue(UserNode, 0), Orig, UsefulBits, Depth);
2007 case AArch64::STRBBui:
2008 case AArch64::STURBBi:
2009 if (UserNode->getOperand(0) != Orig)
2011 UsefulBits &= APInt(UsefulBits.getBitWidth(), 0xff);
2014 case AArch64::STRHHui:
2015 case AArch64::STURHHi:
2016 if (UserNode->getOperand(0) != Orig)
2018 UsefulBits &= APInt(UsefulBits.getBitWidth(), 0xffff);
2023 static void getUsefulBits(SDValue Op, APInt &UsefulBits, unsigned Depth) {
2026 // Initialize UsefulBits
2028 unsigned Bitwidth = Op.getScalarValueSizeInBits();
2029 // At the beginning, assume every produced bits is useful
2030 UsefulBits = APInt(Bitwidth, 0);
2031 UsefulBits.flipAllBits();
2033 APInt UsersUsefulBits(UsefulBits.getBitWidth(), 0);
2035 for (SDNode *Node : Op.getNode()->uses()) {
2036 // A use cannot produce useful bits
2037 APInt UsefulBitsForUse = APInt(UsefulBits);
2038 getUsefulBitsForUse(Node, UsefulBitsForUse, Op, Depth);
2039 UsersUsefulBits |= UsefulBitsForUse;
2041 // UsefulBits contains the produced bits that are meaningful for the
2042 // current definition, thus a user cannot make a bit meaningful at
2044 UsefulBits &= UsersUsefulBits;
2047 /// Create a machine node performing a notional SHL of Op by ShlAmount. If
2048 /// ShlAmount is negative, do a (logical) right-shift instead. If ShlAmount is
2049 /// 0, return Op unchanged.
2050 static SDValue getLeftShift(SelectionDAG *CurDAG, SDValue Op, int ShlAmount) {
2054 EVT VT = Op.getValueType();
2056 unsigned BitWidth = VT.getSizeInBits();
2057 unsigned UBFMOpc = BitWidth == 32 ? AArch64::UBFMWri : AArch64::UBFMXri;
2060 if (ShlAmount > 0) {
2061 // LSL wD, wN, #Amt == UBFM wD, wN, #32-Amt, #31-Amt
2062 ShiftNode = CurDAG->getMachineNode(
2063 UBFMOpc, dl, VT, Op,
2064 CurDAG->getTargetConstant(BitWidth - ShlAmount, dl, VT),
2065 CurDAG->getTargetConstant(BitWidth - 1 - ShlAmount, dl, VT));
2067 // LSR wD, wN, #Amt == UBFM wD, wN, #Amt, #32-1
2068 assert(ShlAmount < 0 && "expected right shift");
2069 int ShrAmount = -ShlAmount;
2070 ShiftNode = CurDAG->getMachineNode(
2071 UBFMOpc, dl, VT, Op, CurDAG->getTargetConstant(ShrAmount, dl, VT),
2072 CurDAG->getTargetConstant(BitWidth - 1, dl, VT));
2075 return SDValue(ShiftNode, 0);
2078 /// Does this tree qualify as an attempt to move a bitfield into position,
2079 /// essentially "(and (shl VAL, N), Mask)".
2080 static bool isBitfieldPositioningOp(SelectionDAG *CurDAG, SDValue Op,
2082 SDValue &Src, int &ShiftAmount,
2084 EVT VT = Op.getValueType();
2085 unsigned BitWidth = VT.getSizeInBits();
2087 assert(BitWidth == 32 || BitWidth == 64);
2090 CurDAG->computeKnownBits(Op, Known);
2092 // Non-zero in the sense that they're not provably zero, which is the key
2093 // point if we want to use this value
2094 uint64_t NonZeroBits = (~Known.Zero).getZExtValue();
2096 // Discard a constant AND mask if present. It's safe because the node will
2097 // already have been factored into the computeKnownBits calculation above.
2099 if (isOpcWithIntImmediate(Op.getNode(), ISD::AND, AndImm)) {
2100 assert((~APInt(BitWidth, AndImm) & ~Known.Zero) == 0);
2101 Op = Op.getOperand(0);
2104 // Don't match if the SHL has more than one use, since then we'll end up
2105 // generating SHL+UBFIZ instead of just keeping SHL+AND.
2106 if (!BiggerPattern && !Op.hasOneUse())
2110 if (!isOpcWithIntImmediate(Op.getNode(), ISD::SHL, ShlImm))
2112 Op = Op.getOperand(0);
2114 if (!isShiftedMask_64(NonZeroBits))
2117 ShiftAmount = countTrailingZeros(NonZeroBits);
2118 MaskWidth = countTrailingOnes(NonZeroBits >> ShiftAmount);
2120 // BFI encompasses sufficiently many nodes that it's worth inserting an extra
2121 // LSL/LSR if the mask in NonZeroBits doesn't quite match up with the ISD::SHL
2122 // amount. BiggerPattern is true when this pattern is being matched for BFI,
2123 // BiggerPattern is false when this pattern is being matched for UBFIZ, in
2124 // which case it is not profitable to insert an extra shift.
2125 if (ShlImm - ShiftAmount != 0 && !BiggerPattern)
2127 Src = getLeftShift(CurDAG, Op, ShlImm - ShiftAmount);
2132 static bool isShiftedMask(uint64_t Mask, EVT VT) {
2133 assert(VT == MVT::i32 || VT == MVT::i64);
2135 return isShiftedMask_32(Mask);
2136 return isShiftedMask_64(Mask);
2139 // Generate a BFI/BFXIL from 'or (and X, MaskImm), OrImm' iff the value being
2140 // inserted only sets known zero bits.
2141 static bool tryBitfieldInsertOpFromOrAndImm(SDNode *N, SelectionDAG *CurDAG) {
2142 assert(N->getOpcode() == ISD::OR && "Expect a OR operation");
2144 EVT VT = N->getValueType(0);
2145 if (VT != MVT::i32 && VT != MVT::i64)
2148 unsigned BitWidth = VT.getSizeInBits();
2151 if (!isOpcWithIntImmediate(N, ISD::OR, OrImm))
2154 // Skip this transformation if the ORR immediate can be encoded in the ORR.
2155 // Otherwise, we'll trade an AND+ORR for ORR+BFI/BFXIL, which is most likely
2156 // performance neutral.
2157 if (AArch64_AM::isLogicalImmediate(OrImm, BitWidth))
2161 SDValue And = N->getOperand(0);
2162 // Must be a single use AND with an immediate operand.
2163 if (!And.hasOneUse() ||
2164 !isOpcWithIntImmediate(And.getNode(), ISD::AND, MaskImm))
2167 // Compute the Known Zero for the AND as this allows us to catch more general
2168 // cases than just looking for AND with imm.
2170 CurDAG->computeKnownBits(And, Known);
2172 // Non-zero in the sense that they're not provably zero, which is the key
2173 // point if we want to use this value.
2174 uint64_t NotKnownZero = (~Known.Zero).getZExtValue();
2176 // The KnownZero mask must be a shifted mask (e.g., 1110..011, 11100..00).
2177 if (!isShiftedMask(Known.Zero.getZExtValue(), VT))
2180 // The bits being inserted must only set those bits that are known to be zero.
2181 if ((OrImm & NotKnownZero) != 0) {
2182 // FIXME: It's okay if the OrImm sets NotKnownZero bits to 1, but we don't
2183 // currently handle this case.
2187 // BFI/BFXIL dst, src, #lsb, #width.
2188 int LSB = countTrailingOnes(NotKnownZero);
2189 int Width = BitWidth - APInt(BitWidth, NotKnownZero).countPopulation();
2191 // BFI/BFXIL is an alias of BFM, so translate to BFM operands.
2192 unsigned ImmR = (BitWidth - LSB) % BitWidth;
2193 unsigned ImmS = Width - 1;
2195 // If we're creating a BFI instruction avoid cases where we need more
2196 // instructions to materialize the BFI constant as compared to the original
2197 // ORR. A BFXIL will use the same constant as the original ORR, so the code
2198 // should be no worse in this case.
2199 bool IsBFI = LSB != 0;
2200 uint64_t BFIImm = OrImm >> LSB;
2201 if (IsBFI && !AArch64_AM::isLogicalImmediate(BFIImm, BitWidth)) {
2202 // We have a BFI instruction and we know the constant can't be materialized
2203 // with a ORR-immediate with the zero register.
2204 unsigned OrChunks = 0, BFIChunks = 0;
2205 for (unsigned Shift = 0; Shift < BitWidth; Shift += 16) {
2206 if (((OrImm >> Shift) & 0xFFFF) != 0)
2208 if (((BFIImm >> Shift) & 0xFFFF) != 0)
2211 if (BFIChunks > OrChunks)
2215 // Materialize the constant to be inserted.
2217 unsigned MOVIOpc = VT == MVT::i32 ? AArch64::MOVi32imm : AArch64::MOVi64imm;
2218 SDNode *MOVI = CurDAG->getMachineNode(
2219 MOVIOpc, DL, VT, CurDAG->getTargetConstant(BFIImm, DL, VT));
2221 // Create the BFI/BFXIL instruction.
2222 SDValue Ops[] = {And.getOperand(0), SDValue(MOVI, 0),
2223 CurDAG->getTargetConstant(ImmR, DL, VT),
2224 CurDAG->getTargetConstant(ImmS, DL, VT)};
2225 unsigned Opc = (VT == MVT::i32) ? AArch64::BFMWri : AArch64::BFMXri;
2226 CurDAG->SelectNodeTo(N, Opc, VT, Ops);
2230 static bool tryBitfieldInsertOpFromOr(SDNode *N, const APInt &UsefulBits,
2231 SelectionDAG *CurDAG) {
2232 assert(N->getOpcode() == ISD::OR && "Expect a OR operation");
2234 EVT VT = N->getValueType(0);
2235 if (VT != MVT::i32 && VT != MVT::i64)
2238 unsigned BitWidth = VT.getSizeInBits();
2240 // Because of simplify-demanded-bits in DAGCombine, involved masks may not
2241 // have the expected shape. Try to undo that.
2243 unsigned NumberOfIgnoredLowBits = UsefulBits.countTrailingZeros();
2244 unsigned NumberOfIgnoredHighBits = UsefulBits.countLeadingZeros();
2246 // Given a OR operation, check if we have the following pattern
2247 // ubfm c, b, imm, imm2 (or something that does the same jobs, see
2248 // isBitfieldExtractOp)
2249 // d = e & mask2 ; where mask is a binary sequence of 1..10..0 and
2250 // countTrailingZeros(mask2) == imm2 - imm + 1
2252 // if yes, replace the OR instruction with:
2253 // f = BFM Opd0, Opd1, LSB, MSB ; where LSB = imm, and MSB = imm2
2255 // OR is commutative, check all combinations of operand order and values of
2256 // BiggerPattern, i.e.
2257 // Opd0, Opd1, BiggerPattern=false
2258 // Opd1, Opd0, BiggerPattern=false
2259 // Opd0, Opd1, BiggerPattern=true
2260 // Opd1, Opd0, BiggerPattern=true
2261 // Several of these combinations may match, so check with BiggerPattern=false
2262 // first since that will produce better results by matching more instructions
2263 // and/or inserting fewer extra instructions.
2264 for (int I = 0; I < 4; ++I) {
2267 unsigned ImmR, ImmS;
2268 bool BiggerPattern = I / 2;
2269 SDValue OrOpd0Val = N->getOperand(I % 2);
2270 SDNode *OrOpd0 = OrOpd0Val.getNode();
2271 SDValue OrOpd1Val = N->getOperand((I + 1) % 2);
2272 SDNode *OrOpd1 = OrOpd1Val.getNode();
2276 if (isBitfieldExtractOp(CurDAG, OrOpd0, BFXOpc, Src, ImmR, ImmS,
2277 NumberOfIgnoredLowBits, BiggerPattern)) {
2278 // Check that the returned opcode is compatible with the pattern,
2279 // i.e., same type and zero extended (U and not S)
2280 if ((BFXOpc != AArch64::UBFMXri && VT == MVT::i64) ||
2281 (BFXOpc != AArch64::UBFMWri && VT == MVT::i32))
2284 // Compute the width of the bitfield insertion
2286 Width = ImmS - ImmR + 1;
2287 // FIXME: This constraint is to catch bitfield insertion we may
2288 // want to widen the pattern if we want to grab general bitfied
2293 // If the mask on the insertee is correct, we have a BFXIL operation. We
2294 // can share the ImmR and ImmS values from the already-computed UBFM.
2295 } else if (isBitfieldPositioningOp(CurDAG, OrOpd0Val,
2297 Src, DstLSB, Width)) {
2298 ImmR = (BitWidth - DstLSB) % BitWidth;
2303 // Check the second part of the pattern
2304 EVT VT = OrOpd1->getValueType(0);
2305 assert((VT == MVT::i32 || VT == MVT::i64) && "unexpected OR operand");
2307 // Compute the Known Zero for the candidate of the first operand.
2308 // This allows to catch more general case than just looking for
2309 // AND with imm. Indeed, simplify-demanded-bits may have removed
2310 // the AND instruction because it proves it was useless.
2312 CurDAG->computeKnownBits(OrOpd1Val, Known);
2314 // Check if there is enough room for the second operand to appear
2316 APInt BitsToBeInserted =
2317 APInt::getBitsSet(Known.getBitWidth(), DstLSB, DstLSB + Width);
2319 if ((BitsToBeInserted & ~Known.Zero) != 0)
2322 // Set the first operand
2324 if (isOpcWithIntImmediate(OrOpd1, ISD::AND, Imm) &&
2325 isBitfieldDstMask(Imm, BitsToBeInserted, NumberOfIgnoredHighBits, VT))
2326 // In that case, we can eliminate the AND
2327 Dst = OrOpd1->getOperand(0);
2329 // Maybe the AND has been removed by simplify-demanded-bits
2330 // or is useful because it discards more bits
2335 SDValue Ops[] = {Dst, Src, CurDAG->getTargetConstant(ImmR, DL, VT),
2336 CurDAG->getTargetConstant(ImmS, DL, VT)};
2337 unsigned Opc = (VT == MVT::i32) ? AArch64::BFMWri : AArch64::BFMXri;
2338 CurDAG->SelectNodeTo(N, Opc, VT, Ops);
2342 // Generate a BFXIL from 'or (and X, Mask0Imm), (and Y, Mask1Imm)' iff
2343 // Mask0Imm and ~Mask1Imm are equivalent and one of the MaskImms is a shifted
2344 // mask (e.g., 0x000ffff0).
2345 uint64_t Mask0Imm, Mask1Imm;
2346 SDValue And0 = N->getOperand(0);
2347 SDValue And1 = N->getOperand(1);
2348 if (And0.hasOneUse() && And1.hasOneUse() &&
2349 isOpcWithIntImmediate(And0.getNode(), ISD::AND, Mask0Imm) &&
2350 isOpcWithIntImmediate(And1.getNode(), ISD::AND, Mask1Imm) &&
2351 APInt(BitWidth, Mask0Imm) == ~APInt(BitWidth, Mask1Imm) &&
2352 (isShiftedMask(Mask0Imm, VT) || isShiftedMask(Mask1Imm, VT))) {
2354 // ORR is commutative, so canonicalize to the form 'or (and X, Mask0Imm),
2355 // (and Y, Mask1Imm)' where Mask1Imm is the shifted mask masking off the
2356 // bits to be inserted.
2357 if (isShiftedMask(Mask0Imm, VT)) {
2358 std::swap(And0, And1);
2359 std::swap(Mask0Imm, Mask1Imm);
2362 SDValue Src = And1->getOperand(0);
2363 SDValue Dst = And0->getOperand(0);
2364 unsigned LSB = countTrailingZeros(Mask1Imm);
2365 int Width = BitWidth - APInt(BitWidth, Mask0Imm).countPopulation();
2367 // The BFXIL inserts the low-order bits from a source register, so right
2368 // shift the needed bits into place.
2370 unsigned ShiftOpc = (VT == MVT::i32) ? AArch64::UBFMWri : AArch64::UBFMXri;
2371 SDNode *LSR = CurDAG->getMachineNode(
2372 ShiftOpc, DL, VT, Src, CurDAG->getTargetConstant(LSB, DL, VT),
2373 CurDAG->getTargetConstant(BitWidth - 1, DL, VT));
2375 // BFXIL is an alias of BFM, so translate to BFM operands.
2376 unsigned ImmR = (BitWidth - LSB) % BitWidth;
2377 unsigned ImmS = Width - 1;
2379 // Create the BFXIL instruction.
2380 SDValue Ops[] = {Dst, SDValue(LSR, 0),
2381 CurDAG->getTargetConstant(ImmR, DL, VT),
2382 CurDAG->getTargetConstant(ImmS, DL, VT)};
2383 unsigned Opc = (VT == MVT::i32) ? AArch64::BFMWri : AArch64::BFMXri;
2384 CurDAG->SelectNodeTo(N, Opc, VT, Ops);
2391 bool AArch64DAGToDAGISel::tryBitfieldInsertOp(SDNode *N) {
2392 if (N->getOpcode() != ISD::OR)
2396 getUsefulBits(SDValue(N, 0), NUsefulBits);
2398 // If all bits are not useful, just return UNDEF.
2400 CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF, N->getValueType(0));
2404 if (tryBitfieldInsertOpFromOr(N, NUsefulBits, CurDAG))
2407 return tryBitfieldInsertOpFromOrAndImm(N, CurDAG);
2410 /// SelectBitfieldInsertInZeroOp - Match a UBFIZ instruction that is the
2411 /// equivalent of a left shift by a constant amount followed by an and masking
2412 /// out a contiguous set of bits.
2413 bool AArch64DAGToDAGISel::tryBitfieldInsertInZeroOp(SDNode *N) {
2414 if (N->getOpcode() != ISD::AND)
2417 EVT VT = N->getValueType(0);
2418 if (VT != MVT::i32 && VT != MVT::i64)
2423 if (!isBitfieldPositioningOp(CurDAG, SDValue(N, 0), /*BiggerPattern=*/false,
2424 Op0, DstLSB, Width))
2427 // ImmR is the rotate right amount.
2428 unsigned ImmR = (VT.getSizeInBits() - DstLSB) % VT.getSizeInBits();
2429 // ImmS is the most significant bit of the source to be moved.
2430 unsigned ImmS = Width - 1;
2433 SDValue Ops[] = {Op0, CurDAG->getTargetConstant(ImmR, DL, VT),
2434 CurDAG->getTargetConstant(ImmS, DL, VT)};
2435 unsigned Opc = (VT == MVT::i32) ? AArch64::UBFMWri : AArch64::UBFMXri;
2436 CurDAG->SelectNodeTo(N, Opc, VT, Ops);
2441 AArch64DAGToDAGISel::SelectCVTFixedPosOperand(SDValue N, SDValue &FixedPos,
2442 unsigned RegWidth) {
2444 if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N))
2445 FVal = CN->getValueAPF();
2446 else if (LoadSDNode *LN = dyn_cast<LoadSDNode>(N)) {
2447 // Some otherwise illegal constants are allowed in this case.
2448 if (LN->getOperand(1).getOpcode() != AArch64ISD::ADDlow ||
2449 !isa<ConstantPoolSDNode>(LN->getOperand(1)->getOperand(1)))
2452 ConstantPoolSDNode *CN =
2453 dyn_cast<ConstantPoolSDNode>(LN->getOperand(1)->getOperand(1));
2454 FVal = cast<ConstantFP>(CN->getConstVal())->getValueAPF();
2458 // An FCVT[SU] instruction performs: convertToInt(Val * 2^fbits) where fbits
2459 // is between 1 and 32 for a destination w-register, or 1 and 64 for an
2462 // By this stage, we've detected (fp_to_[su]int (fmul Val, THIS_NODE)) so we
2463 // want THIS_NODE to be 2^fbits. This is much easier to deal with using
2467 // fbits is between 1 and 64 in the worst-case, which means the fmul
2468 // could have 2^64 as an actual operand. Need 65 bits of precision.
2469 APSInt IntVal(65, true);
2470 FVal.convertToInteger(IntVal, APFloat::rmTowardZero, &IsExact);
2472 // N.b. isPowerOf2 also checks for > 0.
2473 if (!IsExact || !IntVal.isPowerOf2()) return false;
2474 unsigned FBits = IntVal.logBase2();
2476 // Checks above should have guaranteed that we haven't lost information in
2477 // finding FBits, but it must still be in range.
2478 if (FBits == 0 || FBits > RegWidth) return false;
2480 FixedPos = CurDAG->getTargetConstant(FBits, SDLoc(N), MVT::i32);
2484 // Inspects a register string of the form o0:op1:CRn:CRm:op2 gets the fields
2485 // of the string and obtains the integer values from them and combines these
2486 // into a single value to be used in the MRS/MSR instruction.
2487 static int getIntOperandFromRegisterString(StringRef RegString) {
2488 SmallVector<StringRef, 5> Fields;
2489 RegString.split(Fields, ':');
2491 if (Fields.size() == 1)
2494 assert(Fields.size() == 5
2495 && "Invalid number of fields in read register string");
2497 SmallVector<int, 5> Ops;
2498 bool AllIntFields = true;
2500 for (StringRef Field : Fields) {
2502 AllIntFields &= !Field.getAsInteger(10, IntField);
2503 Ops.push_back(IntField);
2506 assert(AllIntFields &&
2507 "Unexpected non-integer value in special register string.");
2509 // Need to combine the integer fields of the string into a single value
2510 // based on the bit encoding of MRS/MSR instruction.
2511 return (Ops[0] << 14) | (Ops[1] << 11) | (Ops[2] << 7) |
2512 (Ops[3] << 3) | (Ops[4]);
2515 // Lower the read_register intrinsic to an MRS instruction node if the special
2516 // register string argument is either of the form detailed in the ALCE (the
2517 // form described in getIntOperandsFromRegsterString) or is a named register
2518 // known by the MRS SysReg mapper.
2519 bool AArch64DAGToDAGISel::tryReadRegister(SDNode *N) {
2520 const MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(N->getOperand(1));
2521 const MDString *RegString = dyn_cast<MDString>(MD->getMD()->getOperand(0));
2524 int Reg = getIntOperandFromRegisterString(RegString->getString());
2526 ReplaceNode(N, CurDAG->getMachineNode(
2527 AArch64::MRS, DL, N->getSimpleValueType(0), MVT::Other,
2528 CurDAG->getTargetConstant(Reg, DL, MVT::i32),
2533 // Use the sysreg mapper to map the remaining possible strings to the
2534 // value for the register to be used for the instruction operand.
2535 auto TheReg = AArch64SysReg::lookupSysRegByName(RegString->getString());
2536 if (TheReg && TheReg->Readable &&
2537 TheReg->haveFeatures(Subtarget->getFeatureBits()))
2538 Reg = TheReg->Encoding;
2540 Reg = AArch64SysReg::parseGenericRegister(RegString->getString());
2543 ReplaceNode(N, CurDAG->getMachineNode(
2544 AArch64::MRS, DL, N->getSimpleValueType(0), MVT::Other,
2545 CurDAG->getTargetConstant(Reg, DL, MVT::i32),
2553 // Lower the write_register intrinsic to an MSR instruction node if the special
2554 // register string argument is either of the form detailed in the ALCE (the
2555 // form described in getIntOperandsFromRegsterString) or is a named register
2556 // known by the MSR SysReg mapper.
2557 bool AArch64DAGToDAGISel::tryWriteRegister(SDNode *N) {
2558 const MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(N->getOperand(1));
2559 const MDString *RegString = dyn_cast<MDString>(MD->getMD()->getOperand(0));
2562 int Reg = getIntOperandFromRegisterString(RegString->getString());
2565 N, CurDAG->getMachineNode(AArch64::MSR, DL, MVT::Other,
2566 CurDAG->getTargetConstant(Reg, DL, MVT::i32),
2567 N->getOperand(2), N->getOperand(0)));
2571 // Check if the register was one of those allowed as the pstatefield value in
2572 // the MSR (immediate) instruction. To accept the values allowed in the
2573 // pstatefield for the MSR (immediate) instruction, we also require that an
2574 // immediate value has been provided as an argument, we know that this is
2575 // the case as it has been ensured by semantic checking.
2576 auto PMapper = AArch64PState::lookupPStateByName(RegString->getString());
2578 assert (isa<ConstantSDNode>(N->getOperand(2))
2579 && "Expected a constant integer expression.");
2580 unsigned Reg = PMapper->Encoding;
2581 uint64_t Immed = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
2583 if (Reg == AArch64PState::PAN || Reg == AArch64PState::UAO) {
2584 assert(Immed < 2 && "Bad imm");
2585 State = AArch64::MSRpstateImm1;
2587 assert(Immed < 16 && "Bad imm");
2588 State = AArch64::MSRpstateImm4;
2590 ReplaceNode(N, CurDAG->getMachineNode(
2591 State, DL, MVT::Other,
2592 CurDAG->getTargetConstant(Reg, DL, MVT::i32),
2593 CurDAG->getTargetConstant(Immed, DL, MVT::i16),
2598 // Use the sysreg mapper to attempt to map the remaining possible strings
2599 // to the value for the register to be used for the MSR (register)
2600 // instruction operand.
2601 auto TheReg = AArch64SysReg::lookupSysRegByName(RegString->getString());
2602 if (TheReg && TheReg->Writeable &&
2603 TheReg->haveFeatures(Subtarget->getFeatureBits()))
2604 Reg = TheReg->Encoding;
2606 Reg = AArch64SysReg::parseGenericRegister(RegString->getString());
2608 ReplaceNode(N, CurDAG->getMachineNode(
2609 AArch64::MSR, DL, MVT::Other,
2610 CurDAG->getTargetConstant(Reg, DL, MVT::i32),
2611 N->getOperand(2), N->getOperand(0)));
2618 /// We've got special pseudo-instructions for these
2619 bool AArch64DAGToDAGISel::SelectCMP_SWAP(SDNode *N) {
2621 EVT MemTy = cast<MemSDNode>(N)->getMemoryVT();
2623 // Leave IR for LSE if subtarget supports it.
2624 if (Subtarget->hasLSE()) return false;
2626 if (MemTy == MVT::i8)
2627 Opcode = AArch64::CMP_SWAP_8;
2628 else if (MemTy == MVT::i16)
2629 Opcode = AArch64::CMP_SWAP_16;
2630 else if (MemTy == MVT::i32)
2631 Opcode = AArch64::CMP_SWAP_32;
2632 else if (MemTy == MVT::i64)
2633 Opcode = AArch64::CMP_SWAP_64;
2635 llvm_unreachable("Unknown AtomicCmpSwap type");
2637 MVT RegTy = MemTy == MVT::i64 ? MVT::i64 : MVT::i32;
2638 SDValue Ops[] = {N->getOperand(1), N->getOperand(2), N->getOperand(3),
2640 SDNode *CmpSwap = CurDAG->getMachineNode(
2642 CurDAG->getVTList(RegTy, MVT::i32, MVT::Other), Ops);
2644 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2645 MemOp[0] = cast<MemSDNode>(N)->getMemOperand();
2646 cast<MachineSDNode>(CmpSwap)->setMemRefs(MemOp, MemOp + 1);
2648 ReplaceUses(SDValue(N, 0), SDValue(CmpSwap, 0));
2649 ReplaceUses(SDValue(N, 1), SDValue(CmpSwap, 2));
2650 CurDAG->RemoveDeadNode(N);
2655 void AArch64DAGToDAGISel::Select(SDNode *Node) {
2656 // Dump information about the Node being selected
2657 DEBUG(errs() << "Selecting: ");
2658 DEBUG(Node->dump(CurDAG));
2659 DEBUG(errs() << "\n");
2661 // If we have a custom node, we already have selected!
2662 if (Node->isMachineOpcode()) {
2663 DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
2664 Node->setNodeId(-1);
2668 // Few custom selection stuff.
2669 EVT VT = Node->getValueType(0);
2671 switch (Node->getOpcode()) {
2675 case ISD::ATOMIC_CMP_SWAP:
2676 if (SelectCMP_SWAP(Node))
2680 case ISD::READ_REGISTER:
2681 if (tryReadRegister(Node))
2685 case ISD::WRITE_REGISTER:
2686 if (tryWriteRegister(Node))
2691 if (tryMLAV64LaneV128(Node))
2696 // Try to select as an indexed load. Fall through to normal processing
2698 if (tryIndexedLoad(Node))
2706 case ISD::SIGN_EXTEND_INREG:
2707 if (tryBitfieldExtractOp(Node))
2709 if (tryBitfieldInsertInZeroOp(Node))
2713 case ISD::SIGN_EXTEND:
2714 if (tryBitfieldExtractOpFromSExt(Node))
2719 if (tryBitfieldInsertOp(Node))
2723 case ISD::EXTRACT_VECTOR_ELT: {
2724 // Extracting lane zero is a special case where we can just use a plain
2725 // EXTRACT_SUBREG instruction, which will become FMOV. This is easier for
2726 // the rest of the compiler, especially the register allocator and copyi
2727 // propagation, to reason about, so is preferred when it's possible to
2729 ConstantSDNode *LaneNode = cast<ConstantSDNode>(Node->getOperand(1));
2730 // Bail and use the default Select() for non-zero lanes.
2731 if (LaneNode->getZExtValue() != 0)
2733 // If the element type is not the same as the result type, likewise
2734 // bail and use the default Select(), as there's more to do than just
2735 // a cross-class COPY. This catches extracts of i8 and i16 elements
2736 // since they will need an explicit zext.
2737 if (VT != Node->getOperand(0).getValueType().getVectorElementType())
2740 switch (Node->getOperand(0)
2742 .getVectorElementType()
2745 llvm_unreachable("Unexpected vector element type!");
2747 SubReg = AArch64::dsub;
2750 SubReg = AArch64::ssub;
2753 SubReg = AArch64::hsub;
2756 llvm_unreachable("unexpected zext-requiring extract element!");
2758 SDValue Extract = CurDAG->getTargetExtractSubreg(SubReg, SDLoc(Node), VT,
2759 Node->getOperand(0));
2760 DEBUG(dbgs() << "ISEL: Custom selection!\n=> ");
2761 DEBUG(Extract->dumpr(CurDAG));
2762 DEBUG(dbgs() << "\n");
2763 ReplaceNode(Node, Extract.getNode());
2766 case ISD::Constant: {
2767 // Materialize zero constants as copies from WZR/XZR. This allows
2768 // the coalescer to propagate these into other instructions.
2769 ConstantSDNode *ConstNode = cast<ConstantSDNode>(Node);
2770 if (ConstNode->isNullValue()) {
2771 if (VT == MVT::i32) {
2772 SDValue New = CurDAG->getCopyFromReg(
2773 CurDAG->getEntryNode(), SDLoc(Node), AArch64::WZR, MVT::i32);
2774 ReplaceNode(Node, New.getNode());
2776 } else if (VT == MVT::i64) {
2777 SDValue New = CurDAG->getCopyFromReg(
2778 CurDAG->getEntryNode(), SDLoc(Node), AArch64::XZR, MVT::i64);
2779 ReplaceNode(Node, New.getNode());
2786 case ISD::FrameIndex: {
2787 // Selects to ADDXri FI, 0 which in turn will become ADDXri SP, imm.
2788 int FI = cast<FrameIndexSDNode>(Node)->getIndex();
2789 unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0);
2790 const TargetLowering *TLI = getTargetLowering();
2791 SDValue TFI = CurDAG->getTargetFrameIndex(
2792 FI, TLI->getPointerTy(CurDAG->getDataLayout()));
2794 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, DL, MVT::i32),
2795 CurDAG->getTargetConstant(Shifter, DL, MVT::i32) };
2796 CurDAG->SelectNodeTo(Node, AArch64::ADDXri, MVT::i64, Ops);
2799 case ISD::INTRINSIC_W_CHAIN: {
2800 unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
2804 case Intrinsic::aarch64_ldaxp:
2805 case Intrinsic::aarch64_ldxp: {
2807 IntNo == Intrinsic::aarch64_ldaxp ? AArch64::LDAXPX : AArch64::LDXPX;
2808 SDValue MemAddr = Node->getOperand(2);
2810 SDValue Chain = Node->getOperand(0);
2812 SDNode *Ld = CurDAG->getMachineNode(Op, DL, MVT::i64, MVT::i64,
2813 MVT::Other, MemAddr, Chain);
2815 // Transfer memoperands.
2816 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2817 MemOp[0] = cast<MemIntrinsicSDNode>(Node)->getMemOperand();
2818 cast<MachineSDNode>(Ld)->setMemRefs(MemOp, MemOp + 1);
2819 ReplaceNode(Node, Ld);
2822 case Intrinsic::aarch64_stlxp:
2823 case Intrinsic::aarch64_stxp: {
2825 IntNo == Intrinsic::aarch64_stlxp ? AArch64::STLXPX : AArch64::STXPX;
2827 SDValue Chain = Node->getOperand(0);
2828 SDValue ValLo = Node->getOperand(2);
2829 SDValue ValHi = Node->getOperand(3);
2830 SDValue MemAddr = Node->getOperand(4);
2832 // Place arguments in the right order.
2833 SDValue Ops[] = {ValLo, ValHi, MemAddr, Chain};
2835 SDNode *St = CurDAG->getMachineNode(Op, DL, MVT::i32, MVT::Other, Ops);
2836 // Transfer memoperands.
2837 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2838 MemOp[0] = cast<MemIntrinsicSDNode>(Node)->getMemOperand();
2839 cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1);
2841 ReplaceNode(Node, St);
2844 case Intrinsic::aarch64_neon_ld1x2:
2845 if (VT == MVT::v8i8) {
2846 SelectLoad(Node, 2, AArch64::LD1Twov8b, AArch64::dsub0);
2848 } else if (VT == MVT::v16i8) {
2849 SelectLoad(Node, 2, AArch64::LD1Twov16b, AArch64::qsub0);
2851 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
2852 SelectLoad(Node, 2, AArch64::LD1Twov4h, AArch64::dsub0);
2854 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
2855 SelectLoad(Node, 2, AArch64::LD1Twov8h, AArch64::qsub0);
2857 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
2858 SelectLoad(Node, 2, AArch64::LD1Twov2s, AArch64::dsub0);
2860 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
2861 SelectLoad(Node, 2, AArch64::LD1Twov4s, AArch64::qsub0);
2863 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
2864 SelectLoad(Node, 2, AArch64::LD1Twov1d, AArch64::dsub0);
2866 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
2867 SelectLoad(Node, 2, AArch64::LD1Twov2d, AArch64::qsub0);
2871 case Intrinsic::aarch64_neon_ld1x3:
2872 if (VT == MVT::v8i8) {
2873 SelectLoad(Node, 3, AArch64::LD1Threev8b, AArch64::dsub0);
2875 } else if (VT == MVT::v16i8) {
2876 SelectLoad(Node, 3, AArch64::LD1Threev16b, AArch64::qsub0);
2878 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
2879 SelectLoad(Node, 3, AArch64::LD1Threev4h, AArch64::dsub0);
2881 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
2882 SelectLoad(Node, 3, AArch64::LD1Threev8h, AArch64::qsub0);
2884 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
2885 SelectLoad(Node, 3, AArch64::LD1Threev2s, AArch64::dsub0);
2887 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
2888 SelectLoad(Node, 3, AArch64::LD1Threev4s, AArch64::qsub0);
2890 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
2891 SelectLoad(Node, 3, AArch64::LD1Threev1d, AArch64::dsub0);
2893 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
2894 SelectLoad(Node, 3, AArch64::LD1Threev2d, AArch64::qsub0);
2898 case Intrinsic::aarch64_neon_ld1x4:
2899 if (VT == MVT::v8i8) {
2900 SelectLoad(Node, 4, AArch64::LD1Fourv8b, AArch64::dsub0);
2902 } else if (VT == MVT::v16i8) {
2903 SelectLoad(Node, 4, AArch64::LD1Fourv16b, AArch64::qsub0);
2905 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
2906 SelectLoad(Node, 4, AArch64::LD1Fourv4h, AArch64::dsub0);
2908 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
2909 SelectLoad(Node, 4, AArch64::LD1Fourv8h, AArch64::qsub0);
2911 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
2912 SelectLoad(Node, 4, AArch64::LD1Fourv2s, AArch64::dsub0);
2914 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
2915 SelectLoad(Node, 4, AArch64::LD1Fourv4s, AArch64::qsub0);
2917 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
2918 SelectLoad(Node, 4, AArch64::LD1Fourv1d, AArch64::dsub0);
2920 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
2921 SelectLoad(Node, 4, AArch64::LD1Fourv2d, AArch64::qsub0);
2925 case Intrinsic::aarch64_neon_ld2:
2926 if (VT == MVT::v8i8) {
2927 SelectLoad(Node, 2, AArch64::LD2Twov8b, AArch64::dsub0);
2929 } else if (VT == MVT::v16i8) {
2930 SelectLoad(Node, 2, AArch64::LD2Twov16b, AArch64::qsub0);
2932 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
2933 SelectLoad(Node, 2, AArch64::LD2Twov4h, AArch64::dsub0);
2935 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
2936 SelectLoad(Node, 2, AArch64::LD2Twov8h, AArch64::qsub0);
2938 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
2939 SelectLoad(Node, 2, AArch64::LD2Twov2s, AArch64::dsub0);
2941 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
2942 SelectLoad(Node, 2, AArch64::LD2Twov4s, AArch64::qsub0);
2944 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
2945 SelectLoad(Node, 2, AArch64::LD1Twov1d, AArch64::dsub0);
2947 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
2948 SelectLoad(Node, 2, AArch64::LD2Twov2d, AArch64::qsub0);
2952 case Intrinsic::aarch64_neon_ld3:
2953 if (VT == MVT::v8i8) {
2954 SelectLoad(Node, 3, AArch64::LD3Threev8b, AArch64::dsub0);
2956 } else if (VT == MVT::v16i8) {
2957 SelectLoad(Node, 3, AArch64::LD3Threev16b, AArch64::qsub0);
2959 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
2960 SelectLoad(Node, 3, AArch64::LD3Threev4h, AArch64::dsub0);
2962 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
2963 SelectLoad(Node, 3, AArch64::LD3Threev8h, AArch64::qsub0);
2965 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
2966 SelectLoad(Node, 3, AArch64::LD3Threev2s, AArch64::dsub0);
2968 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
2969 SelectLoad(Node, 3, AArch64::LD3Threev4s, AArch64::qsub0);
2971 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
2972 SelectLoad(Node, 3, AArch64::LD1Threev1d, AArch64::dsub0);
2974 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
2975 SelectLoad(Node, 3, AArch64::LD3Threev2d, AArch64::qsub0);
2979 case Intrinsic::aarch64_neon_ld4:
2980 if (VT == MVT::v8i8) {
2981 SelectLoad(Node, 4, AArch64::LD4Fourv8b, AArch64::dsub0);
2983 } else if (VT == MVT::v16i8) {
2984 SelectLoad(Node, 4, AArch64::LD4Fourv16b, AArch64::qsub0);
2986 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
2987 SelectLoad(Node, 4, AArch64::LD4Fourv4h, AArch64::dsub0);
2989 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
2990 SelectLoad(Node, 4, AArch64::LD4Fourv8h, AArch64::qsub0);
2992 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
2993 SelectLoad(Node, 4, AArch64::LD4Fourv2s, AArch64::dsub0);
2995 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
2996 SelectLoad(Node, 4, AArch64::LD4Fourv4s, AArch64::qsub0);
2998 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
2999 SelectLoad(Node, 4, AArch64::LD1Fourv1d, AArch64::dsub0);
3001 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3002 SelectLoad(Node, 4, AArch64::LD4Fourv2d, AArch64::qsub0);
3006 case Intrinsic::aarch64_neon_ld2r:
3007 if (VT == MVT::v8i8) {
3008 SelectLoad(Node, 2, AArch64::LD2Rv8b, AArch64::dsub0);
3010 } else if (VT == MVT::v16i8) {
3011 SelectLoad(Node, 2, AArch64::LD2Rv16b, AArch64::qsub0);
3013 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3014 SelectLoad(Node, 2, AArch64::LD2Rv4h, AArch64::dsub0);
3016 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3017 SelectLoad(Node, 2, AArch64::LD2Rv8h, AArch64::qsub0);
3019 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3020 SelectLoad(Node, 2, AArch64::LD2Rv2s, AArch64::dsub0);
3022 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3023 SelectLoad(Node, 2, AArch64::LD2Rv4s, AArch64::qsub0);
3025 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3026 SelectLoad(Node, 2, AArch64::LD2Rv1d, AArch64::dsub0);
3028 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3029 SelectLoad(Node, 2, AArch64::LD2Rv2d, AArch64::qsub0);
3033 case Intrinsic::aarch64_neon_ld3r:
3034 if (VT == MVT::v8i8) {
3035 SelectLoad(Node, 3, AArch64::LD3Rv8b, AArch64::dsub0);
3037 } else if (VT == MVT::v16i8) {
3038 SelectLoad(Node, 3, AArch64::LD3Rv16b, AArch64::qsub0);
3040 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3041 SelectLoad(Node, 3, AArch64::LD3Rv4h, AArch64::dsub0);
3043 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3044 SelectLoad(Node, 3, AArch64::LD3Rv8h, AArch64::qsub0);
3046 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3047 SelectLoad(Node, 3, AArch64::LD3Rv2s, AArch64::dsub0);
3049 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3050 SelectLoad(Node, 3, AArch64::LD3Rv4s, AArch64::qsub0);
3052 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3053 SelectLoad(Node, 3, AArch64::LD3Rv1d, AArch64::dsub0);
3055 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3056 SelectLoad(Node, 3, AArch64::LD3Rv2d, AArch64::qsub0);
3060 case Intrinsic::aarch64_neon_ld4r:
3061 if (VT == MVT::v8i8) {
3062 SelectLoad(Node, 4, AArch64::LD4Rv8b, AArch64::dsub0);
3064 } else if (VT == MVT::v16i8) {
3065 SelectLoad(Node, 4, AArch64::LD4Rv16b, AArch64::qsub0);
3067 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3068 SelectLoad(Node, 4, AArch64::LD4Rv4h, AArch64::dsub0);
3070 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3071 SelectLoad(Node, 4, AArch64::LD4Rv8h, AArch64::qsub0);
3073 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3074 SelectLoad(Node, 4, AArch64::LD4Rv2s, AArch64::dsub0);
3076 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3077 SelectLoad(Node, 4, AArch64::LD4Rv4s, AArch64::qsub0);
3079 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3080 SelectLoad(Node, 4, AArch64::LD4Rv1d, AArch64::dsub0);
3082 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3083 SelectLoad(Node, 4, AArch64::LD4Rv2d, AArch64::qsub0);
3087 case Intrinsic::aarch64_neon_ld2lane:
3088 if (VT == MVT::v16i8 || VT == MVT::v8i8) {
3089 SelectLoadLane(Node, 2, AArch64::LD2i8);
3091 } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
3093 SelectLoadLane(Node, 2, AArch64::LD2i16);
3095 } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
3097 SelectLoadLane(Node, 2, AArch64::LD2i32);
3099 } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
3101 SelectLoadLane(Node, 2, AArch64::LD2i64);
3105 case Intrinsic::aarch64_neon_ld3lane:
3106 if (VT == MVT::v16i8 || VT == MVT::v8i8) {
3107 SelectLoadLane(Node, 3, AArch64::LD3i8);
3109 } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
3111 SelectLoadLane(Node, 3, AArch64::LD3i16);
3113 } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
3115 SelectLoadLane(Node, 3, AArch64::LD3i32);
3117 } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
3119 SelectLoadLane(Node, 3, AArch64::LD3i64);
3123 case Intrinsic::aarch64_neon_ld4lane:
3124 if (VT == MVT::v16i8 || VT == MVT::v8i8) {
3125 SelectLoadLane(Node, 4, AArch64::LD4i8);
3127 } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
3129 SelectLoadLane(Node, 4, AArch64::LD4i16);
3131 } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
3133 SelectLoadLane(Node, 4, AArch64::LD4i32);
3135 } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
3137 SelectLoadLane(Node, 4, AArch64::LD4i64);
3143 case ISD::INTRINSIC_WO_CHAIN: {
3144 unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
3148 case Intrinsic::aarch64_neon_tbl2:
3149 SelectTable(Node, 2,
3150 VT == MVT::v8i8 ? AArch64::TBLv8i8Two : AArch64::TBLv16i8Two,
3153 case Intrinsic::aarch64_neon_tbl3:
3154 SelectTable(Node, 3, VT == MVT::v8i8 ? AArch64::TBLv8i8Three
3155 : AArch64::TBLv16i8Three,
3158 case Intrinsic::aarch64_neon_tbl4:
3159 SelectTable(Node, 4, VT == MVT::v8i8 ? AArch64::TBLv8i8Four
3160 : AArch64::TBLv16i8Four,
3163 case Intrinsic::aarch64_neon_tbx2:
3164 SelectTable(Node, 2,
3165 VT == MVT::v8i8 ? AArch64::TBXv8i8Two : AArch64::TBXv16i8Two,
3168 case Intrinsic::aarch64_neon_tbx3:
3169 SelectTable(Node, 3, VT == MVT::v8i8 ? AArch64::TBXv8i8Three
3170 : AArch64::TBXv16i8Three,
3173 case Intrinsic::aarch64_neon_tbx4:
3174 SelectTable(Node, 4, VT == MVT::v8i8 ? AArch64::TBXv8i8Four
3175 : AArch64::TBXv16i8Four,
3178 case Intrinsic::aarch64_neon_smull:
3179 case Intrinsic::aarch64_neon_umull:
3180 if (tryMULLV64LaneV128(IntNo, Node))
3186 case ISD::INTRINSIC_VOID: {
3187 unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
3188 if (Node->getNumOperands() >= 3)
3189 VT = Node->getOperand(2)->getValueType(0);
3193 case Intrinsic::aarch64_neon_st1x2: {
3194 if (VT == MVT::v8i8) {
3195 SelectStore(Node, 2, AArch64::ST1Twov8b);
3197 } else if (VT == MVT::v16i8) {
3198 SelectStore(Node, 2, AArch64::ST1Twov16b);
3200 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3201 SelectStore(Node, 2, AArch64::ST1Twov4h);
3203 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3204 SelectStore(Node, 2, AArch64::ST1Twov8h);
3206 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3207 SelectStore(Node, 2, AArch64::ST1Twov2s);
3209 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3210 SelectStore(Node, 2, AArch64::ST1Twov4s);
3212 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3213 SelectStore(Node, 2, AArch64::ST1Twov2d);
3215 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3216 SelectStore(Node, 2, AArch64::ST1Twov1d);
3221 case Intrinsic::aarch64_neon_st1x3: {
3222 if (VT == MVT::v8i8) {
3223 SelectStore(Node, 3, AArch64::ST1Threev8b);
3225 } else if (VT == MVT::v16i8) {
3226 SelectStore(Node, 3, AArch64::ST1Threev16b);
3228 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3229 SelectStore(Node, 3, AArch64::ST1Threev4h);
3231 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3232 SelectStore(Node, 3, AArch64::ST1Threev8h);
3234 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3235 SelectStore(Node, 3, AArch64::ST1Threev2s);
3237 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3238 SelectStore(Node, 3, AArch64::ST1Threev4s);
3240 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3241 SelectStore(Node, 3, AArch64::ST1Threev2d);
3243 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3244 SelectStore(Node, 3, AArch64::ST1Threev1d);
3249 case Intrinsic::aarch64_neon_st1x4: {
3250 if (VT == MVT::v8i8) {
3251 SelectStore(Node, 4, AArch64::ST1Fourv8b);
3253 } else if (VT == MVT::v16i8) {
3254 SelectStore(Node, 4, AArch64::ST1Fourv16b);
3256 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3257 SelectStore(Node, 4, AArch64::ST1Fourv4h);
3259 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3260 SelectStore(Node, 4, AArch64::ST1Fourv8h);
3262 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3263 SelectStore(Node, 4, AArch64::ST1Fourv2s);
3265 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3266 SelectStore(Node, 4, AArch64::ST1Fourv4s);
3268 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3269 SelectStore(Node, 4, AArch64::ST1Fourv2d);
3271 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3272 SelectStore(Node, 4, AArch64::ST1Fourv1d);
3277 case Intrinsic::aarch64_neon_st2: {
3278 if (VT == MVT::v8i8) {
3279 SelectStore(Node, 2, AArch64::ST2Twov8b);
3281 } else if (VT == MVT::v16i8) {
3282 SelectStore(Node, 2, AArch64::ST2Twov16b);
3284 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3285 SelectStore(Node, 2, AArch64::ST2Twov4h);
3287 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3288 SelectStore(Node, 2, AArch64::ST2Twov8h);
3290 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3291 SelectStore(Node, 2, AArch64::ST2Twov2s);
3293 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3294 SelectStore(Node, 2, AArch64::ST2Twov4s);
3296 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3297 SelectStore(Node, 2, AArch64::ST2Twov2d);
3299 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3300 SelectStore(Node, 2, AArch64::ST1Twov1d);
3305 case Intrinsic::aarch64_neon_st3: {
3306 if (VT == MVT::v8i8) {
3307 SelectStore(Node, 3, AArch64::ST3Threev8b);
3309 } else if (VT == MVT::v16i8) {
3310 SelectStore(Node, 3, AArch64::ST3Threev16b);
3312 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3313 SelectStore(Node, 3, AArch64::ST3Threev4h);
3315 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3316 SelectStore(Node, 3, AArch64::ST3Threev8h);
3318 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3319 SelectStore(Node, 3, AArch64::ST3Threev2s);
3321 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3322 SelectStore(Node, 3, AArch64::ST3Threev4s);
3324 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3325 SelectStore(Node, 3, AArch64::ST3Threev2d);
3327 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3328 SelectStore(Node, 3, AArch64::ST1Threev1d);
3333 case Intrinsic::aarch64_neon_st4: {
3334 if (VT == MVT::v8i8) {
3335 SelectStore(Node, 4, AArch64::ST4Fourv8b);
3337 } else if (VT == MVT::v16i8) {
3338 SelectStore(Node, 4, AArch64::ST4Fourv16b);
3340 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3341 SelectStore(Node, 4, AArch64::ST4Fourv4h);
3343 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3344 SelectStore(Node, 4, AArch64::ST4Fourv8h);
3346 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3347 SelectStore(Node, 4, AArch64::ST4Fourv2s);
3349 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3350 SelectStore(Node, 4, AArch64::ST4Fourv4s);
3352 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3353 SelectStore(Node, 4, AArch64::ST4Fourv2d);
3355 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3356 SelectStore(Node, 4, AArch64::ST1Fourv1d);
3361 case Intrinsic::aarch64_neon_st2lane: {
3362 if (VT == MVT::v16i8 || VT == MVT::v8i8) {
3363 SelectStoreLane(Node, 2, AArch64::ST2i8);
3365 } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
3367 SelectStoreLane(Node, 2, AArch64::ST2i16);
3369 } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
3371 SelectStoreLane(Node, 2, AArch64::ST2i32);
3373 } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
3375 SelectStoreLane(Node, 2, AArch64::ST2i64);
3380 case Intrinsic::aarch64_neon_st3lane: {
3381 if (VT == MVT::v16i8 || VT == MVT::v8i8) {
3382 SelectStoreLane(Node, 3, AArch64::ST3i8);
3384 } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
3386 SelectStoreLane(Node, 3, AArch64::ST3i16);
3388 } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
3390 SelectStoreLane(Node, 3, AArch64::ST3i32);
3392 } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
3394 SelectStoreLane(Node, 3, AArch64::ST3i64);
3399 case Intrinsic::aarch64_neon_st4lane: {
3400 if (VT == MVT::v16i8 || VT == MVT::v8i8) {
3401 SelectStoreLane(Node, 4, AArch64::ST4i8);
3403 } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
3405 SelectStoreLane(Node, 4, AArch64::ST4i16);
3407 } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
3409 SelectStoreLane(Node, 4, AArch64::ST4i32);
3411 } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
3413 SelectStoreLane(Node, 4, AArch64::ST4i64);
3421 case AArch64ISD::LD2post: {
3422 if (VT == MVT::v8i8) {
3423 SelectPostLoad(Node, 2, AArch64::LD2Twov8b_POST, AArch64::dsub0);
3425 } else if (VT == MVT::v16i8) {
3426 SelectPostLoad(Node, 2, AArch64::LD2Twov16b_POST, AArch64::qsub0);
3428 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3429 SelectPostLoad(Node, 2, AArch64::LD2Twov4h_POST, AArch64::dsub0);
3431 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3432 SelectPostLoad(Node, 2, AArch64::LD2Twov8h_POST, AArch64::qsub0);
3434 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3435 SelectPostLoad(Node, 2, AArch64::LD2Twov2s_POST, AArch64::dsub0);
3437 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3438 SelectPostLoad(Node, 2, AArch64::LD2Twov4s_POST, AArch64::qsub0);
3440 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3441 SelectPostLoad(Node, 2, AArch64::LD1Twov1d_POST, AArch64::dsub0);
3443 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3444 SelectPostLoad(Node, 2, AArch64::LD2Twov2d_POST, AArch64::qsub0);
3449 case AArch64ISD::LD3post: {
3450 if (VT == MVT::v8i8) {
3451 SelectPostLoad(Node, 3, AArch64::LD3Threev8b_POST, AArch64::dsub0);
3453 } else if (VT == MVT::v16i8) {
3454 SelectPostLoad(Node, 3, AArch64::LD3Threev16b_POST, AArch64::qsub0);
3456 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3457 SelectPostLoad(Node, 3, AArch64::LD3Threev4h_POST, AArch64::dsub0);
3459 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3460 SelectPostLoad(Node, 3, AArch64::LD3Threev8h_POST, AArch64::qsub0);
3462 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3463 SelectPostLoad(Node, 3, AArch64::LD3Threev2s_POST, AArch64::dsub0);
3465 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3466 SelectPostLoad(Node, 3, AArch64::LD3Threev4s_POST, AArch64::qsub0);
3468 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3469 SelectPostLoad(Node, 3, AArch64::LD1Threev1d_POST, AArch64::dsub0);
3471 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3472 SelectPostLoad(Node, 3, AArch64::LD3Threev2d_POST, AArch64::qsub0);
3477 case AArch64ISD::LD4post: {
3478 if (VT == MVT::v8i8) {
3479 SelectPostLoad(Node, 4, AArch64::LD4Fourv8b_POST, AArch64::dsub0);
3481 } else if (VT == MVT::v16i8) {
3482 SelectPostLoad(Node, 4, AArch64::LD4Fourv16b_POST, AArch64::qsub0);
3484 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3485 SelectPostLoad(Node, 4, AArch64::LD4Fourv4h_POST, AArch64::dsub0);
3487 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3488 SelectPostLoad(Node, 4, AArch64::LD4Fourv8h_POST, AArch64::qsub0);
3490 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3491 SelectPostLoad(Node, 4, AArch64::LD4Fourv2s_POST, AArch64::dsub0);
3493 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3494 SelectPostLoad(Node, 4, AArch64::LD4Fourv4s_POST, AArch64::qsub0);
3496 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3497 SelectPostLoad(Node, 4, AArch64::LD1Fourv1d_POST, AArch64::dsub0);
3499 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3500 SelectPostLoad(Node, 4, AArch64::LD4Fourv2d_POST, AArch64::qsub0);
3505 case AArch64ISD::LD1x2post: {
3506 if (VT == MVT::v8i8) {
3507 SelectPostLoad(Node, 2, AArch64::LD1Twov8b_POST, AArch64::dsub0);
3509 } else if (VT == MVT::v16i8) {
3510 SelectPostLoad(Node, 2, AArch64::LD1Twov16b_POST, AArch64::qsub0);
3512 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3513 SelectPostLoad(Node, 2, AArch64::LD1Twov4h_POST, AArch64::dsub0);
3515 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3516 SelectPostLoad(Node, 2, AArch64::LD1Twov8h_POST, AArch64::qsub0);
3518 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3519 SelectPostLoad(Node, 2, AArch64::LD1Twov2s_POST, AArch64::dsub0);
3521 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3522 SelectPostLoad(Node, 2, AArch64::LD1Twov4s_POST, AArch64::qsub0);
3524 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3525 SelectPostLoad(Node, 2, AArch64::LD1Twov1d_POST, AArch64::dsub0);
3527 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3528 SelectPostLoad(Node, 2, AArch64::LD1Twov2d_POST, AArch64::qsub0);
3533 case AArch64ISD::LD1x3post: {
3534 if (VT == MVT::v8i8) {
3535 SelectPostLoad(Node, 3, AArch64::LD1Threev8b_POST, AArch64::dsub0);
3537 } else if (VT == MVT::v16i8) {
3538 SelectPostLoad(Node, 3, AArch64::LD1Threev16b_POST, AArch64::qsub0);
3540 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3541 SelectPostLoad(Node, 3, AArch64::LD1Threev4h_POST, AArch64::dsub0);
3543 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3544 SelectPostLoad(Node, 3, AArch64::LD1Threev8h_POST, AArch64::qsub0);
3546 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3547 SelectPostLoad(Node, 3, AArch64::LD1Threev2s_POST, AArch64::dsub0);
3549 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3550 SelectPostLoad(Node, 3, AArch64::LD1Threev4s_POST, AArch64::qsub0);
3552 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3553 SelectPostLoad(Node, 3, AArch64::LD1Threev1d_POST, AArch64::dsub0);
3555 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3556 SelectPostLoad(Node, 3, AArch64::LD1Threev2d_POST, AArch64::qsub0);
3561 case AArch64ISD::LD1x4post: {
3562 if (VT == MVT::v8i8) {
3563 SelectPostLoad(Node, 4, AArch64::LD1Fourv8b_POST, AArch64::dsub0);
3565 } else if (VT == MVT::v16i8) {
3566 SelectPostLoad(Node, 4, AArch64::LD1Fourv16b_POST, AArch64::qsub0);
3568 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3569 SelectPostLoad(Node, 4, AArch64::LD1Fourv4h_POST, AArch64::dsub0);
3571 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3572 SelectPostLoad(Node, 4, AArch64::LD1Fourv8h_POST, AArch64::qsub0);
3574 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3575 SelectPostLoad(Node, 4, AArch64::LD1Fourv2s_POST, AArch64::dsub0);
3577 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3578 SelectPostLoad(Node, 4, AArch64::LD1Fourv4s_POST, AArch64::qsub0);
3580 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3581 SelectPostLoad(Node, 4, AArch64::LD1Fourv1d_POST, AArch64::dsub0);
3583 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3584 SelectPostLoad(Node, 4, AArch64::LD1Fourv2d_POST, AArch64::qsub0);
3589 case AArch64ISD::LD1DUPpost: {
3590 if (VT == MVT::v8i8) {
3591 SelectPostLoad(Node, 1, AArch64::LD1Rv8b_POST, AArch64::dsub0);
3593 } else if (VT == MVT::v16i8) {
3594 SelectPostLoad(Node, 1, AArch64::LD1Rv16b_POST, AArch64::qsub0);
3596 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3597 SelectPostLoad(Node, 1, AArch64::LD1Rv4h_POST, AArch64::dsub0);
3599 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3600 SelectPostLoad(Node, 1, AArch64::LD1Rv8h_POST, AArch64::qsub0);
3602 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3603 SelectPostLoad(Node, 1, AArch64::LD1Rv2s_POST, AArch64::dsub0);
3605 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3606 SelectPostLoad(Node, 1, AArch64::LD1Rv4s_POST, AArch64::qsub0);
3608 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3609 SelectPostLoad(Node, 1, AArch64::LD1Rv1d_POST, AArch64::dsub0);
3611 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3612 SelectPostLoad(Node, 1, AArch64::LD1Rv2d_POST, AArch64::qsub0);
3617 case AArch64ISD::LD2DUPpost: {
3618 if (VT == MVT::v8i8) {
3619 SelectPostLoad(Node, 2, AArch64::LD2Rv8b_POST, AArch64::dsub0);
3621 } else if (VT == MVT::v16i8) {
3622 SelectPostLoad(Node, 2, AArch64::LD2Rv16b_POST, AArch64::qsub0);
3624 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3625 SelectPostLoad(Node, 2, AArch64::LD2Rv4h_POST, AArch64::dsub0);
3627 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3628 SelectPostLoad(Node, 2, AArch64::LD2Rv8h_POST, AArch64::qsub0);
3630 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3631 SelectPostLoad(Node, 2, AArch64::LD2Rv2s_POST, AArch64::dsub0);
3633 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3634 SelectPostLoad(Node, 2, AArch64::LD2Rv4s_POST, AArch64::qsub0);
3636 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3637 SelectPostLoad(Node, 2, AArch64::LD2Rv1d_POST, AArch64::dsub0);
3639 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3640 SelectPostLoad(Node, 2, AArch64::LD2Rv2d_POST, AArch64::qsub0);
3645 case AArch64ISD::LD3DUPpost: {
3646 if (VT == MVT::v8i8) {
3647 SelectPostLoad(Node, 3, AArch64::LD3Rv8b_POST, AArch64::dsub0);
3649 } else if (VT == MVT::v16i8) {
3650 SelectPostLoad(Node, 3, AArch64::LD3Rv16b_POST, AArch64::qsub0);
3652 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3653 SelectPostLoad(Node, 3, AArch64::LD3Rv4h_POST, AArch64::dsub0);
3655 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3656 SelectPostLoad(Node, 3, AArch64::LD3Rv8h_POST, AArch64::qsub0);
3658 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3659 SelectPostLoad(Node, 3, AArch64::LD3Rv2s_POST, AArch64::dsub0);
3661 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3662 SelectPostLoad(Node, 3, AArch64::LD3Rv4s_POST, AArch64::qsub0);
3664 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3665 SelectPostLoad(Node, 3, AArch64::LD3Rv1d_POST, AArch64::dsub0);
3667 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3668 SelectPostLoad(Node, 3, AArch64::LD3Rv2d_POST, AArch64::qsub0);
3673 case AArch64ISD::LD4DUPpost: {
3674 if (VT == MVT::v8i8) {
3675 SelectPostLoad(Node, 4, AArch64::LD4Rv8b_POST, AArch64::dsub0);
3677 } else if (VT == MVT::v16i8) {
3678 SelectPostLoad(Node, 4, AArch64::LD4Rv16b_POST, AArch64::qsub0);
3680 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3681 SelectPostLoad(Node, 4, AArch64::LD4Rv4h_POST, AArch64::dsub0);
3683 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3684 SelectPostLoad(Node, 4, AArch64::LD4Rv8h_POST, AArch64::qsub0);
3686 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3687 SelectPostLoad(Node, 4, AArch64::LD4Rv2s_POST, AArch64::dsub0);
3689 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3690 SelectPostLoad(Node, 4, AArch64::LD4Rv4s_POST, AArch64::qsub0);
3692 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3693 SelectPostLoad(Node, 4, AArch64::LD4Rv1d_POST, AArch64::dsub0);
3695 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3696 SelectPostLoad(Node, 4, AArch64::LD4Rv2d_POST, AArch64::qsub0);
3701 case AArch64ISD::LD1LANEpost: {
3702 if (VT == MVT::v16i8 || VT == MVT::v8i8) {
3703 SelectPostLoadLane(Node, 1, AArch64::LD1i8_POST);
3705 } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
3707 SelectPostLoadLane(Node, 1, AArch64::LD1i16_POST);
3709 } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
3711 SelectPostLoadLane(Node, 1, AArch64::LD1i32_POST);
3713 } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
3715 SelectPostLoadLane(Node, 1, AArch64::LD1i64_POST);
3720 case AArch64ISD::LD2LANEpost: {
3721 if (VT == MVT::v16i8 || VT == MVT::v8i8) {
3722 SelectPostLoadLane(Node, 2, AArch64::LD2i8_POST);
3724 } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
3726 SelectPostLoadLane(Node, 2, AArch64::LD2i16_POST);
3728 } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
3730 SelectPostLoadLane(Node, 2, AArch64::LD2i32_POST);
3732 } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
3734 SelectPostLoadLane(Node, 2, AArch64::LD2i64_POST);
3739 case AArch64ISD::LD3LANEpost: {
3740 if (VT == MVT::v16i8 || VT == MVT::v8i8) {
3741 SelectPostLoadLane(Node, 3, AArch64::LD3i8_POST);
3743 } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
3745 SelectPostLoadLane(Node, 3, AArch64::LD3i16_POST);
3747 } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
3749 SelectPostLoadLane(Node, 3, AArch64::LD3i32_POST);
3751 } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
3753 SelectPostLoadLane(Node, 3, AArch64::LD3i64_POST);
3758 case AArch64ISD::LD4LANEpost: {
3759 if (VT == MVT::v16i8 || VT == MVT::v8i8) {
3760 SelectPostLoadLane(Node, 4, AArch64::LD4i8_POST);
3762 } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
3764 SelectPostLoadLane(Node, 4, AArch64::LD4i16_POST);
3766 } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
3768 SelectPostLoadLane(Node, 4, AArch64::LD4i32_POST);
3770 } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
3772 SelectPostLoadLane(Node, 4, AArch64::LD4i64_POST);
3777 case AArch64ISD::ST2post: {
3778 VT = Node->getOperand(1).getValueType();
3779 if (VT == MVT::v8i8) {
3780 SelectPostStore(Node, 2, AArch64::ST2Twov8b_POST);
3782 } else if (VT == MVT::v16i8) {
3783 SelectPostStore(Node, 2, AArch64::ST2Twov16b_POST);
3785 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3786 SelectPostStore(Node, 2, AArch64::ST2Twov4h_POST);
3788 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3789 SelectPostStore(Node, 2, AArch64::ST2Twov8h_POST);
3791 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3792 SelectPostStore(Node, 2, AArch64::ST2Twov2s_POST);
3794 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3795 SelectPostStore(Node, 2, AArch64::ST2Twov4s_POST);
3797 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3798 SelectPostStore(Node, 2, AArch64::ST2Twov2d_POST);
3800 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3801 SelectPostStore(Node, 2, AArch64::ST1Twov1d_POST);
3806 case AArch64ISD::ST3post: {
3807 VT = Node->getOperand(1).getValueType();
3808 if (VT == MVT::v8i8) {
3809 SelectPostStore(Node, 3, AArch64::ST3Threev8b_POST);
3811 } else if (VT == MVT::v16i8) {
3812 SelectPostStore(Node, 3, AArch64::ST3Threev16b_POST);
3814 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3815 SelectPostStore(Node, 3, AArch64::ST3Threev4h_POST);
3817 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3818 SelectPostStore(Node, 3, AArch64::ST3Threev8h_POST);
3820 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3821 SelectPostStore(Node, 3, AArch64::ST3Threev2s_POST);
3823 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3824 SelectPostStore(Node, 3, AArch64::ST3Threev4s_POST);
3826 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3827 SelectPostStore(Node, 3, AArch64::ST3Threev2d_POST);
3829 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3830 SelectPostStore(Node, 3, AArch64::ST1Threev1d_POST);
3835 case AArch64ISD::ST4post: {
3836 VT = Node->getOperand(1).getValueType();
3837 if (VT == MVT::v8i8) {
3838 SelectPostStore(Node, 4, AArch64::ST4Fourv8b_POST);
3840 } else if (VT == MVT::v16i8) {
3841 SelectPostStore(Node, 4, AArch64::ST4Fourv16b_POST);
3843 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3844 SelectPostStore(Node, 4, AArch64::ST4Fourv4h_POST);
3846 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3847 SelectPostStore(Node, 4, AArch64::ST4Fourv8h_POST);
3849 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3850 SelectPostStore(Node, 4, AArch64::ST4Fourv2s_POST);
3852 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3853 SelectPostStore(Node, 4, AArch64::ST4Fourv4s_POST);
3855 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3856 SelectPostStore(Node, 4, AArch64::ST4Fourv2d_POST);
3858 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3859 SelectPostStore(Node, 4, AArch64::ST1Fourv1d_POST);
3864 case AArch64ISD::ST1x2post: {
3865 VT = Node->getOperand(1).getValueType();
3866 if (VT == MVT::v8i8) {
3867 SelectPostStore(Node, 2, AArch64::ST1Twov8b_POST);
3869 } else if (VT == MVT::v16i8) {
3870 SelectPostStore(Node, 2, AArch64::ST1Twov16b_POST);
3872 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3873 SelectPostStore(Node, 2, AArch64::ST1Twov4h_POST);
3875 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3876 SelectPostStore(Node, 2, AArch64::ST1Twov8h_POST);
3878 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3879 SelectPostStore(Node, 2, AArch64::ST1Twov2s_POST);
3881 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3882 SelectPostStore(Node, 2, AArch64::ST1Twov4s_POST);
3884 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3885 SelectPostStore(Node, 2, AArch64::ST1Twov1d_POST);
3887 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3888 SelectPostStore(Node, 2, AArch64::ST1Twov2d_POST);
3893 case AArch64ISD::ST1x3post: {
3894 VT = Node->getOperand(1).getValueType();
3895 if (VT == MVT::v8i8) {
3896 SelectPostStore(Node, 3, AArch64::ST1Threev8b_POST);
3898 } else if (VT == MVT::v16i8) {
3899 SelectPostStore(Node, 3, AArch64::ST1Threev16b_POST);
3901 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3902 SelectPostStore(Node, 3, AArch64::ST1Threev4h_POST);
3904 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3905 SelectPostStore(Node, 3, AArch64::ST1Threev8h_POST);
3907 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3908 SelectPostStore(Node, 3, AArch64::ST1Threev2s_POST);
3910 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3911 SelectPostStore(Node, 3, AArch64::ST1Threev4s_POST);
3913 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3914 SelectPostStore(Node, 3, AArch64::ST1Threev1d_POST);
3916 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3917 SelectPostStore(Node, 3, AArch64::ST1Threev2d_POST);
3922 case AArch64ISD::ST1x4post: {
3923 VT = Node->getOperand(1).getValueType();
3924 if (VT == MVT::v8i8) {
3925 SelectPostStore(Node, 4, AArch64::ST1Fourv8b_POST);
3927 } else if (VT == MVT::v16i8) {
3928 SelectPostStore(Node, 4, AArch64::ST1Fourv16b_POST);
3930 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
3931 SelectPostStore(Node, 4, AArch64::ST1Fourv4h_POST);
3933 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
3934 SelectPostStore(Node, 4, AArch64::ST1Fourv8h_POST);
3936 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
3937 SelectPostStore(Node, 4, AArch64::ST1Fourv2s_POST);
3939 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3940 SelectPostStore(Node, 4, AArch64::ST1Fourv4s_POST);
3942 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
3943 SelectPostStore(Node, 4, AArch64::ST1Fourv1d_POST);
3945 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3946 SelectPostStore(Node, 4, AArch64::ST1Fourv2d_POST);
3951 case AArch64ISD::ST2LANEpost: {
3952 VT = Node->getOperand(1).getValueType();
3953 if (VT == MVT::v16i8 || VT == MVT::v8i8) {
3954 SelectPostStoreLane(Node, 2, AArch64::ST2i8_POST);
3956 } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
3958 SelectPostStoreLane(Node, 2, AArch64::ST2i16_POST);
3960 } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
3962 SelectPostStoreLane(Node, 2, AArch64::ST2i32_POST);
3964 } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
3966 SelectPostStoreLane(Node, 2, AArch64::ST2i64_POST);
3971 case AArch64ISD::ST3LANEpost: {
3972 VT = Node->getOperand(1).getValueType();
3973 if (VT == MVT::v16i8 || VT == MVT::v8i8) {
3974 SelectPostStoreLane(Node, 3, AArch64::ST3i8_POST);
3976 } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
3978 SelectPostStoreLane(Node, 3, AArch64::ST3i16_POST);
3980 } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
3982 SelectPostStoreLane(Node, 3, AArch64::ST3i32_POST);
3984 } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
3986 SelectPostStoreLane(Node, 3, AArch64::ST3i64_POST);
3991 case AArch64ISD::ST4LANEpost: {
3992 VT = Node->getOperand(1).getValueType();
3993 if (VT == MVT::v16i8 || VT == MVT::v8i8) {
3994 SelectPostStoreLane(Node, 4, AArch64::ST4i8_POST);
3996 } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
3998 SelectPostStoreLane(Node, 4, AArch64::ST4i16_POST);
4000 } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
4002 SelectPostStoreLane(Node, 4, AArch64::ST4i32_POST);
4004 } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
4006 SelectPostStoreLane(Node, 4, AArch64::ST4i64_POST);
4013 // Select the default instruction
4017 /// createAArch64ISelDag - This pass converts a legalized DAG into a
4018 /// AArch64-specific DAG, ready for instruction scheduling.
4019 FunctionPass *llvm::createAArch64ISelDag(AArch64TargetMachine &TM,
4020 CodeGenOpt::Level OptLevel) {
4021 return new AArch64DAGToDAGISel(TM, OptLevel);