1 //==-- AArch64ISelLowering.h - AArch64 DAG Lowering Interface ----*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that AArch64 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
16 #define LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/TargetLowering.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/IR/Instruction.h"
27 namespace AArch64ISD {
29 enum NodeType : unsigned {
30 FIRST_NUMBER = ISD::BUILTIN_OP_END,
31 WrapperLarge, // 4-instruction MOVZ/MOVK sequence for 64-bit addresses.
32 CALL, // Function call.
34 // Produces the full sequence of instructions for getting the thread pointer
35 // offset of a variable into X0, using the TLSDesc model.
37 ADRP, // Page address of a TargetGlobalAddress operand.
38 ADDlow, // Add the low 12 bits of a TargetGlobalAddress operand.
39 LOADgot, // Load from automatically generated descriptor (e.g. Global
40 // Offset Table, TLS record).
41 RET_FLAG, // Return with a flag operand. Operand 0 is the chain operand.
42 BRCOND, // Conditional branch instruction; "b.cond".
44 FCSEL, // Conditional move instruction.
45 CSINV, // Conditional select invert.
46 CSNEG, // Conditional select negate.
47 CSINC, // Conditional select increment.
49 // Pointer to the thread's local storage area. Materialised from TPIDR_EL0 on
53 SBC, // adc, sbc instructions
55 // Arithmetic instructions which write flags.
62 // Conditional compares. Operands: left,right,falsecc,cc,flags
67 // Floating point comparison
73 // Scalar-to-vector duplication
80 // Vector immedate moves
89 // Vector immediate ops
93 // Vector bit select: similar to ISD::VSELECT but not all bits within an
94 // element must be identical.
97 // Vector arithmetic negation
112 // Vector shift by scalar
117 // Vector shift by scalar (again)
124 // Vector comparisons
134 // Vector zero comparisons
146 // Vector across-lanes addition
147 // Only the lower result lane is defined.
151 // Vector across-lanes min/max
152 // Only the lower result lane is defined.
158 // Vector bitwise negation
161 // Vector bitwise selection
164 // Compare-and-branch
173 // Custom prefetch handling
176 // {s|u}int to FP within a FP register.
180 /// Natural vector cast. ISD::BITCAST is not natural in the big-endian
181 /// world w.r.t vectors; which causes additional REV instructions to be
182 /// generated to compensate for the byte-swapping. But sometimes we do
183 /// need to re-interpret the data in SIMD vector registers in big-endian
184 /// mode without emitting such REV instructions.
190 // Reciprocal estimates and steps.
194 // NEON Load/Store with post-increment base updates
195 LD2post = ISD::FIRST_TARGET_MEMORY_OPCODE,
220 } // end namespace AArch64ISD
224 // Any instruction that defines a 32-bit result zeros out the high half of the
225 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
226 // be copying from a truncate. But any other 32-bit operation will zero-extend
228 // FIXME: X86 also checks for CMOV here. Do we need something similar?
229 static inline bool isDef32(const SDNode &N) {
230 unsigned Opc = N.getOpcode();
231 return Opc != ISD::TRUNCATE && Opc != TargetOpcode::EXTRACT_SUBREG &&
232 Opc != ISD::CopyFromReg;
235 } // end anonymous namespace
237 class AArch64Subtarget;
238 class AArch64TargetMachine;
240 class AArch64TargetLowering : public TargetLowering {
242 explicit AArch64TargetLowering(const TargetMachine &TM,
243 const AArch64Subtarget &STI);
245 /// Selects the correct CCAssignFn for a given CallingConvention value.
246 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const;
248 /// Selects the correct CCAssignFn for a given CallingConvention value.
249 CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC) const;
251 /// Determine which of the bits specified in Mask are known to be either zero
252 /// or one and return them in the KnownZero/KnownOne bitsets.
253 void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
254 const APInt &DemandedElts,
255 const SelectionDAG &DAG,
256 unsigned Depth = 0) const override;
258 bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
259 TargetLoweringOpt &TLO) const override;
261 MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override;
263 /// Returns true if the target allows unaligned memory accesses of the
265 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace = 0,
267 bool *Fast = nullptr) const override;
269 /// Provide custom lowering hooks for some operations.
270 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
272 const char *getTargetNodeName(unsigned Opcode) const override;
274 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
276 /// Returns true if a cast between SrcAS and DestAS is a noop.
277 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
278 // Addrspacecasts are always noops.
282 /// This method returns a target specific FastISel object, or null if the
283 /// target does not support "fast" ISel.
284 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
285 const TargetLibraryInfo *libInfo) const override;
287 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
289 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
291 /// Return true if the given shuffle mask can be codegen'd directly, or if it
292 /// should be stack expanded.
293 bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
295 /// Return the ISD::SETCC ValueType.
296 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
297 EVT VT) const override;
299 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
301 MachineBasicBlock *EmitF128CSEL(MachineInstr &MI,
302 MachineBasicBlock *BB) const;
305 EmitInstrWithCustomInserter(MachineInstr &MI,
306 MachineBasicBlock *MBB) const override;
308 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
310 unsigned Intrinsic) const override;
312 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
313 bool isTruncateFree(EVT VT1, EVT VT2) const override;
315 bool isProfitableToHoist(Instruction *I) const override;
317 bool isZExtFree(Type *Ty1, Type *Ty2) const override;
318 bool isZExtFree(EVT VT1, EVT VT2) const override;
319 bool isZExtFree(SDValue Val, EVT VT2) const override;
321 bool hasPairedLoad(EVT LoadedType, unsigned &RequiredAligment) const override;
323 unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
325 bool lowerInterleavedLoad(LoadInst *LI,
326 ArrayRef<ShuffleVectorInst *> Shuffles,
327 ArrayRef<unsigned> Indices,
328 unsigned Factor) const override;
329 bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
330 unsigned Factor) const override;
332 bool isLegalAddImmediate(int64_t) const override;
333 bool isLegalICmpImmediate(int64_t) const override;
335 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
336 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
337 MachineFunction &MF) const override;
339 /// Return true if the addressing mode represented by AM is legal for this
340 /// target, for a load/store of the specified type.
341 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
343 Instruction *I = nullptr) const override;
345 /// \brief Return the cost of the scaling factor used in the addressing
346 /// mode represented by AM for this target, for a load/store
347 /// of the specified type.
348 /// If the AM is supported, the return value must be >= 0.
349 /// If the AM is not supported, it returns a negative value.
350 int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
351 unsigned AS) const override;
353 /// Return true if an FMA operation is faster than a pair of fmul and fadd
354 /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
355 /// returns true, otherwise fmuladd is expanded to fmul + fadd.
356 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
358 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
360 /// \brief Returns false if N is a bit extraction pattern of (X >> C) & Mask.
361 bool isDesirableToCommuteWithShift(const SDNode *N) const override;
363 /// \brief Returns true if it is beneficial to convert a load of a constant
364 /// to just the constant itself.
365 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
366 Type *Ty) const override;
368 Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
369 AtomicOrdering Ord) const override;
370 Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
371 Value *Addr, AtomicOrdering Ord) const override;
373 void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override;
375 TargetLoweringBase::AtomicExpansionKind
376 shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
377 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
378 TargetLoweringBase::AtomicExpansionKind
379 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
381 bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
383 bool useLoadStackGuardNode() const override;
384 TargetLoweringBase::LegalizeTypeAction
385 getPreferredVectorAction(EVT VT) const override;
387 /// If the target has a standard location for the stack protector cookie,
388 /// returns the address of that location. Otherwise, returns nullptr.
389 Value *getIRStackGuard(IRBuilder<> &IRB) const override;
391 /// If the target has a standard location for the unsafe stack pointer,
392 /// returns the address of that location. Otherwise, returns nullptr.
393 Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const override;
395 /// If a physical register, this returns the register that receives the
396 /// exception address on entry to an EH pad.
398 getExceptionPointerRegister(const Constant *PersonalityFn) const override {
399 // FIXME: This is a guess. Has this been defined yet?
403 /// If a physical register, this returns the register that receives the
404 /// exception typeid on entry to a landing pad.
406 getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
407 // FIXME: This is a guess. Has this been defined yet?
411 bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
413 bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
414 const SelectionDAG &DAG) const override {
415 // Do not merge to float value size (128 bytes) if no implicit
416 // float attribute is set.
418 bool NoFloat = DAG.getMachineFunction().getFunction().hasFnAttribute(
419 Attribute::NoImplicitFloat);
422 return (MemVT.getSizeInBits() <= 64);
426 bool isCheapToSpeculateCttz() const override {
430 bool isCheapToSpeculateCtlz() const override {
434 bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
436 bool hasAndNotCompare(SDValue) const override {
441 bool hasBitPreservingFPLogic(EVT VT) const override {
442 // FIXME: Is this always true? It should be true for vectors at least.
443 return VT == MVT::f32 || VT == MVT::f64;
446 bool supportSplitCSR(MachineFunction *MF) const override {
447 return MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
448 MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
450 void initializeSplitCSR(MachineBasicBlock *Entry) const override;
451 void insertCopiesSplitCSR(
452 MachineBasicBlock *Entry,
453 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
455 bool supportSwiftError() const override {
459 /// Returns the size of the platform's va_list object.
460 unsigned getVaListSizeInBits(const DataLayout &DL) const override;
462 /// Returns true if \p VecTy is a legal interleaved access type. This
463 /// function checks the vector element type and the overall width of the
465 bool isLegalInterleavedAccessType(VectorType *VecTy,
466 const DataLayout &DL) const;
468 /// Returns the number of interleaved accesses that will be generated when
469 /// lowering accesses of the given type.
470 unsigned getNumInterleavedAccesses(VectorType *VecTy,
471 const DataLayout &DL) const;
473 MachineMemOperand::Flags getMMOFlags(const Instruction &I) const override;
475 bool functionArgumentNeedsConsecutiveRegisters(Type *Ty,
476 CallingConv::ID CallConv,
477 bool isVarArg) const override;
479 bool isExtFreeImpl(const Instruction *Ext) const override;
481 /// Keep a pointer to the AArch64Subtarget around so that we can
482 /// make the right decision when generating code for different targets.
483 const AArch64Subtarget *Subtarget;
485 void addTypeForNEON(MVT VT, MVT PromotedBitwiseVT);
486 void addDRTypeForNEON(MVT VT);
487 void addQRTypeForNEON(MVT VT);
489 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
491 const SmallVectorImpl<ISD::InputArg> &Ins,
492 const SDLoc &DL, SelectionDAG &DAG,
493 SmallVectorImpl<SDValue> &InVals) const override;
495 SDValue LowerCall(CallLoweringInfo & /*CLI*/,
496 SmallVectorImpl<SDValue> &InVals) const override;
498 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
499 CallingConv::ID CallConv, bool isVarArg,
500 const SmallVectorImpl<ISD::InputArg> &Ins,
501 const SDLoc &DL, SelectionDAG &DAG,
502 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
503 SDValue ThisVal) const;
505 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
507 bool isEligibleForTailCallOptimization(
508 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
509 const SmallVectorImpl<ISD::OutputArg> &Outs,
510 const SmallVectorImpl<SDValue> &OutVals,
511 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
513 /// Finds the incoming stack arguments which overlap the given fixed stack
514 /// object and incorporates their load into the current chain. This prevents
515 /// an upcoming store from clobbering the stack argument before it's used.
516 SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG,
517 MachineFrameInfo &MFI, int ClobberedFI) const;
519 bool DoesCalleeRestoreStack(CallingConv::ID CallCC, bool TailCallOpt) const;
521 void saveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &DL,
522 SDValue &Chain) const;
524 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
526 const SmallVectorImpl<ISD::OutputArg> &Outs,
527 LLVMContext &Context) const override;
529 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
530 const SmallVectorImpl<ISD::OutputArg> &Outs,
531 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
532 SelectionDAG &DAG) const override;
534 SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
535 unsigned Flag) const;
536 SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
537 unsigned Flag) const;
538 SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
539 unsigned Flag) const;
540 SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
541 unsigned Flag) const;
542 template <class NodeTy>
543 SDValue getGOT(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
544 template <class NodeTy>
545 SDValue getAddrLarge(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
546 template <class NodeTy>
547 SDValue getAddr(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
548 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
549 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
550 SDValue LowerDarwinGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
551 SDValue LowerELFGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
552 SDValue LowerELFTLSDescCallSeq(SDValue SymAddr, const SDLoc &DL,
553 SelectionDAG &DAG) const;
554 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
555 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
556 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
557 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
558 SDValue LowerSELECT_CC(ISD::CondCode CC, SDValue LHS, SDValue RHS,
559 SDValue TVal, SDValue FVal, const SDLoc &dl,
560 SelectionDAG &DAG) const;
561 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
562 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
563 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
564 SDValue LowerAAPCS_VASTART(SDValue Op, SelectionDAG &DAG) const;
565 SDValue LowerDarwin_VASTART(SDValue Op, SelectionDAG &DAG) const;
566 SDValue LowerWin64_VASTART(SDValue Op, SelectionDAG &DAG) const;
567 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
568 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
569 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
570 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
571 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
572 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
573 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
574 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
575 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
576 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
577 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
578 SDValue LowerVectorSRA_SRL_SHL(SDValue Op, SelectionDAG &DAG) const;
579 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
580 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
581 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
582 SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
583 SDValue LowerF128Call(SDValue Op, SelectionDAG &DAG,
584 RTLIB::Libcall Call) const;
585 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
586 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
587 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
588 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
589 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
590 SDValue LowerVectorAND(SDValue Op, SelectionDAG &DAG) const;
591 SDValue LowerVectorOR(SDValue Op, SelectionDAG &DAG) const;
592 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
593 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
594 SDValue LowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
596 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
597 std::vector<SDNode *> *Created) const override;
598 SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
599 int &ExtraSteps, bool &UseOneConst,
600 bool Reciprocal) const override;
601 SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
602 int &ExtraSteps) const override;
603 unsigned combineRepeatedFPDivisors() const override;
605 ConstraintType getConstraintType(StringRef Constraint) const override;
606 unsigned getRegisterByName(const char* RegName, EVT VT,
607 SelectionDAG &DAG) const override;
609 /// Examine constraint string and operand type and determine a weight value.
610 /// The operand object must already have been set up with the operand type.
612 getSingleConstraintMatchWeight(AsmOperandInfo &info,
613 const char *constraint) const override;
615 std::pair<unsigned, const TargetRegisterClass *>
616 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
617 StringRef Constraint, MVT VT) const override;
619 const char *LowerXConstraint(EVT ConstraintVT) const override;
621 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
622 std::vector<SDValue> &Ops,
623 SelectionDAG &DAG) const override;
625 unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
626 if (ConstraintCode == "Q")
627 return InlineAsm::Constraint_Q;
628 // FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are
629 // followed by llvm_unreachable so we'll leave them unimplemented in
630 // the backend for now.
631 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
634 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
635 bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
636 bool getIndexedAddressParts(SDNode *Op, SDValue &Base, SDValue &Offset,
637 ISD::MemIndexedMode &AM, bool &IsInc,
638 SelectionDAG &DAG) const;
639 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
640 ISD::MemIndexedMode &AM,
641 SelectionDAG &DAG) const override;
642 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
643 SDValue &Offset, ISD::MemIndexedMode &AM,
644 SelectionDAG &DAG) const override;
646 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
647 SelectionDAG &DAG) const override;
649 bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override;
653 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
654 const TargetLibraryInfo *libInfo);
655 } // end namespace AArch64
657 } // end namespace llvm