1 //==-- AArch64ISelLowering.h - AArch64 DAG Lowering Interface ----*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that AArch64 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
16 #define LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/IR/CallingConv.h"
22 #include "llvm/IR/Instruction.h"
23 #include "llvm/Target/TargetLowering.h"
27 namespace AArch64ISD {
29 enum NodeType : unsigned {
30 FIRST_NUMBER = ISD::BUILTIN_OP_END,
31 WrapperLarge, // 4-instruction MOVZ/MOVK sequence for 64-bit addresses.
32 CALL, // Function call.
34 // Produces the full sequence of instructions for getting the thread pointer
35 // offset of a variable into X0, using the TLSDesc model.
37 ADRP, // Page address of a TargetGlobalAddress operand.
38 ADDlow, // Add the low 12 bits of a TargetGlobalAddress operand.
39 LOADgot, // Load from automatically generated descriptor (e.g. Global
40 // Offset Table, TLS record).
41 RET_FLAG, // Return with a flag operand. Operand 0 is the chain operand.
42 BRCOND, // Conditional branch instruction; "b.cond".
44 FCSEL, // Conditional move instruction.
45 CSINV, // Conditional select invert.
46 CSNEG, // Conditional select negate.
47 CSINC, // Conditional select increment.
49 // Pointer to the thread's local storage area. Materialised from TPIDR_EL0 on
53 SBC, // adc, sbc instructions
55 // Arithmetic instructions which write flags.
62 // Conditional compares. Operands: left,right,falsecc,cc,flags
67 // Floating point comparison
73 // Scalar-to-vector duplication
80 // Vector immedate moves
89 // Vector immediate ops
93 // Vector bit select: similar to ISD::VSELECT but not all bits within an
94 // element must be identical.
97 // Vector arithmetic negation
112 // Vector shift by scalar
117 // Vector shift by scalar (again)
124 // Vector comparisons
134 // Vector zero comparisons
146 // Vector across-lanes addition
147 // Only the lower result lane is defined.
151 // Vector across-lanes min/max
152 // Only the lower result lane is defined.
158 // Vector bitwise negation
161 // Vector bitwise selection
164 // Compare-and-branch
173 // Custom prefetch handling
176 // {s|u}int to FP within a FP register.
180 /// Natural vector cast. ISD::BITCAST is not natural in the big-endian
181 /// world w.r.t vectors; which causes additional REV instructions to be
182 /// generated to compensate for the byte-swapping. But sometimes we do
183 /// need to re-interpret the data in SIMD vector registers in big-endian
184 /// mode without emitting such REV instructions.
190 // Reciprocal estimates.
194 // NEON Load/Store with post-increment base updates
195 LD2post = ISD::FIRST_TARGET_MEMORY_OPCODE,
220 } // end namespace AArch64ISD
222 class AArch64Subtarget;
223 class AArch64TargetMachine;
225 class AArch64TargetLowering : public TargetLowering {
227 explicit AArch64TargetLowering(const TargetMachine &TM,
228 const AArch64Subtarget &STI);
230 /// Selects the correct CCAssignFn for a given CallingConvention value.
231 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const;
233 /// Determine which of the bits specified in Mask are known to be either zero
234 /// or one and return them in the KnownZero/KnownOne bitsets.
235 void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero,
236 APInt &KnownOne, const SelectionDAG &DAG,
237 unsigned Depth = 0) const override;
239 MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override;
241 /// Returns true if the target allows unaligned memory accesses of the
243 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace = 0,
245 bool *Fast = nullptr) const override;
247 /// Provide custom lowering hooks for some operations.
248 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
250 const char *getTargetNodeName(unsigned Opcode) const override;
252 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
254 /// Returns true if a cast between SrcAS and DestAS is a noop.
255 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
256 // Addrspacecasts are always noops.
260 /// This method returns a target specific FastISel object, or null if the
261 /// target does not support "fast" ISel.
262 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
263 const TargetLibraryInfo *libInfo) const override;
265 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
267 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
269 /// Return true if the given shuffle mask can be codegen'd directly, or if it
270 /// should be stack expanded.
271 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const override;
273 /// Return the ISD::SETCC ValueType.
274 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
275 EVT VT) const override;
277 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
279 MachineBasicBlock *EmitF128CSEL(MachineInstr &MI,
280 MachineBasicBlock *BB) const;
283 EmitInstrWithCustomInserter(MachineInstr &MI,
284 MachineBasicBlock *MBB) const override;
286 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
287 unsigned Intrinsic) const override;
289 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
290 bool isTruncateFree(EVT VT1, EVT VT2) const override;
292 bool isProfitableToHoist(Instruction *I) const override;
294 bool isZExtFree(Type *Ty1, Type *Ty2) const override;
295 bool isZExtFree(EVT VT1, EVT VT2) const override;
296 bool isZExtFree(SDValue Val, EVT VT2) const override;
298 bool hasPairedLoad(Type *LoadedType,
299 unsigned &RequiredAligment) const override;
300 bool hasPairedLoad(EVT LoadedType, unsigned &RequiredAligment) const override;
302 unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
304 bool lowerInterleavedLoad(LoadInst *LI,
305 ArrayRef<ShuffleVectorInst *> Shuffles,
306 ArrayRef<unsigned> Indices,
307 unsigned Factor) const override;
308 bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
309 unsigned Factor) const override;
311 bool isLegalAddImmediate(int64_t) const override;
312 bool isLegalICmpImmediate(int64_t) const override;
314 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
315 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
316 MachineFunction &MF) const override;
318 /// Return true if the addressing mode represented by AM is legal for this
319 /// target, for a load/store of the specified type.
320 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
321 unsigned AS) const override;
323 /// \brief Return the cost of the scaling factor used in the addressing
324 /// mode represented by AM for this target, for a load/store
325 /// of the specified type.
326 /// If the AM is supported, the return value must be >= 0.
327 /// If the AM is not supported, it returns a negative value.
328 int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
329 unsigned AS) const override;
331 /// Return true if an FMA operation is faster than a pair of fmul and fadd
332 /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
333 /// returns true, otherwise fmuladd is expanded to fmul + fadd.
334 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
336 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
338 /// \brief Returns false if N is a bit extraction pattern of (X >> C) & Mask.
339 bool isDesirableToCommuteWithShift(const SDNode *N) const override;
341 /// \brief Returns true if it is beneficial to convert a load of a constant
342 /// to just the constant itself.
343 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
344 Type *Ty) const override;
346 Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
347 AtomicOrdering Ord) const override;
348 Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
349 Value *Addr, AtomicOrdering Ord) const override;
351 void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override;
353 TargetLoweringBase::AtomicExpansionKind
354 shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
355 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
356 TargetLoweringBase::AtomicExpansionKind
357 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
359 bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
361 bool useLoadStackGuardNode() const override;
362 TargetLoweringBase::LegalizeTypeAction
363 getPreferredVectorAction(EVT VT) const override;
365 /// If the target has a standard location for the stack protector cookie,
366 /// returns the address of that location. Otherwise, returns nullptr.
367 Value *getIRStackGuard(IRBuilder<> &IRB) const override;
369 /// If the target has a standard location for the unsafe stack pointer,
370 /// returns the address of that location. Otherwise, returns nullptr.
371 Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const override;
373 /// If a physical register, this returns the register that receives the
374 /// exception address on entry to an EH pad.
376 getExceptionPointerRegister(const Constant *PersonalityFn) const override {
377 // FIXME: This is a guess. Has this been defined yet?
381 /// If a physical register, this returns the register that receives the
382 /// exception typeid on entry to a landing pad.
384 getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
385 // FIXME: This is a guess. Has this been defined yet?
389 bool isIntDivCheap(EVT VT, AttributeSet Attr) const override;
391 bool isCheapToSpeculateCttz() const override {
395 bool isCheapToSpeculateCtlz() const override {
399 bool hasBitPreservingFPLogic(EVT VT) const override {
400 // FIXME: Is this always true? It should be true for vectors at least.
401 return VT == MVT::f32 || VT == MVT::f64;
404 bool supportSplitCSR(MachineFunction *MF) const override {
405 return MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS &&
406 MF->getFunction()->hasFnAttribute(Attribute::NoUnwind);
408 void initializeSplitCSR(MachineBasicBlock *Entry) const override;
409 void insertCopiesSplitCSR(
410 MachineBasicBlock *Entry,
411 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
413 bool supportSwiftError() const override {
418 bool isExtFreeImpl(const Instruction *Ext) const override;
420 /// Keep a pointer to the AArch64Subtarget around so that we can
421 /// make the right decision when generating code for different targets.
422 const AArch64Subtarget *Subtarget;
424 void addTypeForNEON(MVT VT, MVT PromotedBitwiseVT);
425 void addDRTypeForNEON(MVT VT);
426 void addQRTypeForNEON(MVT VT);
428 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
430 const SmallVectorImpl<ISD::InputArg> &Ins,
431 const SDLoc &DL, SelectionDAG &DAG,
432 SmallVectorImpl<SDValue> &InVals) const override;
434 SDValue LowerCall(CallLoweringInfo & /*CLI*/,
435 SmallVectorImpl<SDValue> &InVals) const override;
437 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
438 CallingConv::ID CallConv, bool isVarArg,
439 const SmallVectorImpl<ISD::InputArg> &Ins,
440 const SDLoc &DL, SelectionDAG &DAG,
441 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
442 SDValue ThisVal) const;
444 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
446 bool isEligibleForTailCallOptimization(
447 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
448 const SmallVectorImpl<ISD::OutputArg> &Outs,
449 const SmallVectorImpl<SDValue> &OutVals,
450 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
452 /// Finds the incoming stack arguments which overlap the given fixed stack
453 /// object and incorporates their load into the current chain. This prevents
454 /// an upcoming store from clobbering the stack argument before it's used.
455 SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG,
456 MachineFrameInfo *MFI, int ClobberedFI) const;
458 bool DoesCalleeRestoreStack(CallingConv::ID CallCC, bool TailCallOpt) const;
460 bool IsTailCallConvention(CallingConv::ID CallCC) const;
462 void saveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &DL,
463 SDValue &Chain) const;
465 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
467 const SmallVectorImpl<ISD::OutputArg> &Outs,
468 LLVMContext &Context) const override;
470 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
471 const SmallVectorImpl<ISD::OutputArg> &Outs,
472 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
473 SelectionDAG &DAG) const override;
475 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
476 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
477 SDValue LowerDarwinGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
478 SDValue LowerELFGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
479 SDValue LowerELFTLSDescCallSeq(SDValue SymAddr, const SDLoc &DL,
480 SelectionDAG &DAG) const;
481 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
482 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
483 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
484 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
485 SDValue LowerSELECT_CC(ISD::CondCode CC, SDValue LHS, SDValue RHS,
486 SDValue TVal, SDValue FVal, const SDLoc &dl,
487 SelectionDAG &DAG) const;
488 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
489 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
490 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
491 SDValue LowerAAPCS_VASTART(SDValue Op, SelectionDAG &DAG) const;
492 SDValue LowerDarwin_VASTART(SDValue Op, SelectionDAG &DAG) const;
493 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
494 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
495 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
496 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
497 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
498 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
499 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
500 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
501 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
502 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
503 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
504 SDValue LowerVectorSRA_SRL_SHL(SDValue Op, SelectionDAG &DAG) const;
505 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
506 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
507 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
508 SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
509 SDValue LowerF128Call(SDValue Op, SelectionDAG &DAG,
510 RTLIB::Libcall Call) const;
511 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
512 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
513 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
514 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
515 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
516 SDValue LowerVectorAND(SDValue Op, SelectionDAG &DAG) const;
517 SDValue LowerVectorOR(SDValue Op, SelectionDAG &DAG) const;
518 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
519 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
521 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
522 std::vector<SDNode *> *Created) const override;
523 SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI,
524 unsigned &RefinementSteps,
525 bool &UseOneConstNR) const override;
526 SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI,
527 unsigned &RefinementSteps) const override;
528 unsigned combineRepeatedFPDivisors() const override;
530 ConstraintType getConstraintType(StringRef Constraint) const override;
531 unsigned getRegisterByName(const char* RegName, EVT VT,
532 SelectionDAG &DAG) const override;
534 /// Examine constraint string and operand type and determine a weight value.
535 /// The operand object must already have been set up with the operand type.
537 getSingleConstraintMatchWeight(AsmOperandInfo &info,
538 const char *constraint) const override;
540 std::pair<unsigned, const TargetRegisterClass *>
541 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
542 StringRef Constraint, MVT VT) const override;
544 const char *LowerXConstraint(EVT ConstraintVT) const override;
546 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
547 std::vector<SDValue> &Ops,
548 SelectionDAG &DAG) const override;
550 unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
551 if (ConstraintCode == "Q")
552 return InlineAsm::Constraint_Q;
553 // FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are
554 // followed by llvm_unreachable so we'll leave them unimplemented in
555 // the backend for now.
556 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
559 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
560 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
561 bool getIndexedAddressParts(SDNode *Op, SDValue &Base, SDValue &Offset,
562 ISD::MemIndexedMode &AM, bool &IsInc,
563 SelectionDAG &DAG) const;
564 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
565 ISD::MemIndexedMode &AM,
566 SelectionDAG &DAG) const override;
567 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
568 SDValue &Offset, ISD::MemIndexedMode &AM,
569 SelectionDAG &DAG) const override;
571 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
572 SelectionDAG &DAG) const override;
574 bool functionArgumentNeedsConsecutiveRegisters(Type *Ty,
575 CallingConv::ID CallConv,
576 bool isVarArg) const override;
578 bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override;
582 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
583 const TargetLibraryInfo *libInfo);
584 } // end namespace AArch64
586 } // end namespace llvm