1 //===- AArch64InstrInfo.h - AArch64 Instruction Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the AArch64 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
15 #define LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
18 #include "AArch64RegisterInfo.h"
19 #include "llvm/CodeGen/MachineCombinerPattern.h"
20 #include "llvm/Target/TargetInstrInfo.h"
22 #define GET_INSTRINFO_HEADER
23 #include "AArch64GenInstrInfo.inc"
27 class AArch64Subtarget;
28 class AArch64TargetMachine;
30 class AArch64InstrInfo final : public AArch64GenInstrInfo {
31 const AArch64RegisterInfo RI;
32 const AArch64Subtarget &Subtarget;
35 explicit AArch64InstrInfo(const AArch64Subtarget &STI);
37 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
38 /// such, whenever a client has an instance of instruction info, it should
39 /// always be able to get register info as well (through this method).
40 const AArch64RegisterInfo &getRegisterInfo() const { return RI; }
42 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
44 bool isAsCheapAsAMove(const MachineInstr &MI) const override;
46 bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
47 unsigned &DstReg, unsigned &SubIdx) const override;
50 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
51 AliasAnalysis *AA = nullptr) const override;
53 unsigned isLoadFromStackSlot(const MachineInstr &MI,
54 int &FrameIndex) const override;
55 unsigned isStoreToStackSlot(const MachineInstr &MI,
56 int &FrameIndex) const override;
58 /// Returns true if there is a shiftable register and that the shift value
60 bool hasShiftedReg(const MachineInstr &MI) const;
62 /// Returns true if there is an extendable register and that the extending
63 /// value is non-zero.
64 bool hasExtendedReg(const MachineInstr &MI) const;
66 /// \brief Does this instruction set its full destination register to zero?
67 bool isGPRZero(const MachineInstr &MI) const;
69 /// \brief Does this instruction rename a GPR without modifying bits?
70 bool isGPRCopy(const MachineInstr &MI) const;
72 /// \brief Does this instruction rename an FPR without modifying bits?
73 bool isFPRCopy(const MachineInstr &MI) const;
75 /// Return true if this is load/store scales or extends its register offset.
76 /// This refers to scaling a dynamic index as opposed to scaled immediates.
77 /// MI should be a memory op that allows scaled addressing.
78 bool isScaledAddr(const MachineInstr &MI) const;
80 /// Return true if pairing the given load or store is hinted to be
82 bool isLdStPairSuppressed(const MachineInstr &MI) const;
84 /// Return true if this is an unscaled load/store.
85 bool isUnscaledLdSt(unsigned Opc) const;
87 /// Return true if this is an unscaled load/store.
88 bool isUnscaledLdSt(MachineInstr &MI) const;
90 static bool isPairableLdStInst(const MachineInstr &MI) {
91 switch (MI.getOpcode()) {
94 // Scaled instructions.
100 case AArch64::LDRSui:
101 case AArch64::LDRDui:
102 case AArch64::LDRQui:
103 case AArch64::LDRXui:
104 case AArch64::LDRWui:
105 case AArch64::LDRSWui:
106 // Unscaled instructions.
107 case AArch64::STURSi:
108 case AArch64::STURDi:
109 case AArch64::STURQi:
110 case AArch64::STURWi:
111 case AArch64::STURXi:
112 case AArch64::LDURSi:
113 case AArch64::LDURDi:
114 case AArch64::LDURQi:
115 case AArch64::LDURWi:
116 case AArch64::LDURXi:
117 case AArch64::LDURSWi:
122 /// Return true if this is a load/store that can be potentially paired/merged.
123 bool isCandidateToMergeOrPair(MachineInstr &MI) const;
125 /// Hint that pairing the given load or store is unprofitable.
126 void suppressLdStPair(MachineInstr &MI) const;
128 bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg,
130 const TargetRegisterInfo *TRI) const override;
132 bool getMemOpBaseRegImmOfsWidth(MachineInstr &LdSt, unsigned &BaseReg,
133 int64_t &Offset, unsigned &Width,
134 const TargetRegisterInfo *TRI) const;
136 /// Return the immediate offset of the base register in a load/store \p LdSt.
137 MachineOperand &getMemOpBaseRegImmOfsOffsetOperand(MachineInstr &LdSt) const;
139 /// \brief Returns true if opcode \p Opc is a memory operation. If it is, set
140 /// \p Scale, \p Width, \p MinOffset, and \p MaxOffset accordingly.
142 /// For unscaled instructions, \p Scale is set to 1.
143 bool getMemOpInfo(unsigned Opcode, unsigned &Scale, unsigned &Width,
144 int64_t &MinOffset, int64_t &MaxOffset) const;
146 bool shouldClusterMemOps(MachineInstr &FirstLdSt, MachineInstr &SecondLdSt,
147 unsigned NumLoads) const override;
149 MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx,
150 uint64_t Offset, const MDNode *Var,
152 const DebugLoc &DL) const;
153 void copyPhysRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
154 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
155 bool KillSrc, unsigned Opcode,
156 llvm::ArrayRef<unsigned> Indices) const;
157 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
158 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
159 bool KillSrc) const override;
161 void storeRegToStackSlot(MachineBasicBlock &MBB,
162 MachineBasicBlock::iterator MBBI, unsigned SrcReg,
163 bool isKill, int FrameIndex,
164 const TargetRegisterClass *RC,
165 const TargetRegisterInfo *TRI) const override;
167 void loadRegFromStackSlot(MachineBasicBlock &MBB,
168 MachineBasicBlock::iterator MBBI, unsigned DestReg,
169 int FrameIndex, const TargetRegisterClass *RC,
170 const TargetRegisterInfo *TRI) const override;
172 // This tells target independent code that it is okay to pass instructions
173 // with subreg operands to foldMemoryOperandImpl.
174 bool isSubregFoldable() const override { return true; }
176 using TargetInstrInfo::foldMemoryOperandImpl;
178 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
179 ArrayRef<unsigned> Ops,
180 MachineBasicBlock::iterator InsertPt, int FrameIndex,
181 LiveIntervals *LIS = nullptr) const override;
183 /// \returns true if a branch from an instruction with opcode \p BranchOpc
184 /// bytes is capable of jumping to a position \p BrOffset bytes away.
185 bool isBranchOffsetInRange(unsigned BranchOpc,
186 int64_t BrOffset) const override;
188 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
190 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
191 MachineBasicBlock *&FBB,
192 SmallVectorImpl<MachineOperand> &Cond,
193 bool AllowModify = false) const override;
194 unsigned removeBranch(MachineBasicBlock &MBB,
195 int *BytesRemoved = nullptr) const override;
196 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
197 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
199 int *BytesAdded = nullptr) const override;
201 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
202 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
203 unsigned, unsigned, int &, int &, int &) const override;
204 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
205 const DebugLoc &DL, unsigned DstReg,
206 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
207 unsigned FalseReg) const override;
208 void getNoop(MCInst &NopInst) const override;
210 /// analyzeCompare - For a comparison instruction, return the source registers
211 /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
212 /// Return true if the comparison instruction can be analyzed.
213 bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
214 unsigned &SrcReg2, int &CmpMask,
215 int &CmpValue) const override;
216 /// optimizeCompareInstr - Convert the instruction supplying the argument to
217 /// the comparison into one that sets the zero bit in the flags register.
218 bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
219 unsigned SrcReg2, int CmpMask, int CmpValue,
220 const MachineRegisterInfo *MRI) const override;
221 bool optimizeCondBranch(MachineInstr &MI) const override;
223 /// Return true when a code sequence can improve throughput. It
224 /// should be called only for instructions in loops.
225 /// \param Pattern - combiner pattern
226 bool isThroughputPattern(MachineCombinerPattern Pattern) const override;
227 /// Return true when there is potentially a faster code sequence
228 /// for an instruction chain ending in <Root>. All potential patterns are
229 /// listed in the <Patterns> array.
230 bool getMachineCombinerPatterns(MachineInstr &Root,
231 SmallVectorImpl<MachineCombinerPattern> &Patterns)
233 /// Return true when Inst is associative and commutative so that it can be
235 bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
236 /// When getMachineCombinerPatterns() finds patterns, this function generates
237 /// the instructions that could replace the original code sequence
238 void genAlternativeCodeSequence(
239 MachineInstr &Root, MachineCombinerPattern Pattern,
240 SmallVectorImpl<MachineInstr *> &InsInstrs,
241 SmallVectorImpl<MachineInstr *> &DelInstrs,
242 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
243 /// AArch64 supports MachineCombiner.
244 bool useMachineCombiner() const override;
246 bool expandPostRAPseudo(MachineInstr &MI) const override;
248 std::pair<unsigned, unsigned>
249 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
250 ArrayRef<std::pair<unsigned, const char *>>
251 getSerializableDirectMachineOperandTargetFlags() const override;
252 ArrayRef<std::pair<unsigned, const char *>>
253 getSerializableBitmaskMachineOperandTargetFlags() const override;
255 bool isFunctionSafeToOutlineFrom(MachineFunction &MF) const override;
256 unsigned getOutliningBenefit(size_t SequenceSize, size_t Occurrences,
257 bool CanBeTailCall) const override;
258 AArch64GenInstrInfo::MachineOutlinerInstrType
259 getOutliningType(MachineInstr &MI) const override;
260 void insertOutlinerEpilogue(MachineBasicBlock &MBB,
262 bool IsTailCall) const override;
263 void insertOutlinerPrologue(MachineBasicBlock &MBB,
265 bool isTailCall) const override;
266 MachineBasicBlock::iterator
267 insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
268 MachineBasicBlock::iterator &It,
270 bool IsTailCall) const override;
271 /// Returns true if the instruction has a shift by immediate that can be
272 /// executed in one cycle less.
273 bool isFalkorShiftExtFast(const MachineInstr &MI) const;
276 /// \brief Sets the offsets on outlined instructions in \p MBB which use SP
277 /// so that they will be valid post-outlining.
279 /// \param MBB A \p MachineBasicBlock in an outlined function.
280 void fixupPostOutline(MachineBasicBlock &MBB) const;
282 void instantiateCondBranch(MachineBasicBlock &MBB, const DebugLoc &DL,
283 MachineBasicBlock *TBB,
284 ArrayRef<MachineOperand> Cond) const;
285 bool substituteCmpToZero(MachineInstr &CmpInstr, unsigned SrcReg,
286 const MachineRegisterInfo *MRI) const;
289 /// emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg
290 /// plus Offset. This is intended to be used from within the prolog/epilog
291 /// insertion (PEI) pass, where a virtual scratch register may be allocated
292 /// if necessary, to be replaced by the scavenger at the end of PEI.
293 void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
294 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
295 int Offset, const TargetInstrInfo *TII,
296 MachineInstr::MIFlag = MachineInstr::NoFlags,
297 bool SetNZCV = false);
299 /// rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the
300 /// FP. Return false if the offset could not be handled directly in MI, and
301 /// return the left-over portion by reference.
302 bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
303 unsigned FrameReg, int &Offset,
304 const AArch64InstrInfo *TII);
306 /// \brief Use to report the frame offset status in isAArch64FrameOffsetLegal.
307 enum AArch64FrameOffsetStatus {
308 AArch64FrameOffsetCannotUpdate = 0x0, ///< Offset cannot apply.
309 AArch64FrameOffsetIsLegal = 0x1, ///< Offset is legal.
310 AArch64FrameOffsetCanUpdate = 0x2 ///< Offset can apply, at least partly.
313 /// \brief Check if the @p Offset is a valid frame offset for @p MI.
314 /// The returned value reports the validity of the frame offset for @p MI.
315 /// It uses the values defined by AArch64FrameOffsetStatus for that.
316 /// If result == AArch64FrameOffsetCannotUpdate, @p MI cannot be updated to
318 /// If result & AArch64FrameOffsetIsLegal, @p Offset can completely be
319 /// rewriten in @p MI.
320 /// If result & AArch64FrameOffsetCanUpdate, @p Offset contains the
321 /// amount that is off the limit of the legal offset.
322 /// If set, @p OutUseUnscaledOp will contain the whether @p MI should be
323 /// turned into an unscaled operator, which opcode is in @p OutUnscaledOp.
324 /// If set, @p EmittableOffset contains the amount that can be set in @p MI
325 /// (possibly with @p OutUnscaledOp if OutUseUnscaledOp is true) and that
326 /// is a legal offset.
327 int isAArch64FrameOffsetLegal(const MachineInstr &MI, int &Offset,
328 bool *OutUseUnscaledOp = nullptr,
329 unsigned *OutUnscaledOp = nullptr,
330 int *EmittableOffset = nullptr);
332 static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; }
334 static inline bool isCondBranchOpcode(int Opc) {
351 static inline bool isIndirectBranchOpcode(int Opc) { return Opc == AArch64::BR; }
353 } // end namespace llvm