1 //===- AArch64InstrInfo.h - AArch64 Instruction Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the AArch64 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
15 #define LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
18 #include "AArch64RegisterInfo.h"
19 #include "llvm/CodeGen/MachineCombinerPattern.h"
20 #include "llvm/Target/TargetInstrInfo.h"
22 #define GET_INSTRINFO_HEADER
23 #include "AArch64GenInstrInfo.inc"
27 class AArch64Subtarget;
28 class AArch64TargetMachine;
30 class AArch64InstrInfo final : public AArch64GenInstrInfo {
31 const AArch64RegisterInfo RI;
32 const AArch64Subtarget &Subtarget;
35 explicit AArch64InstrInfo(const AArch64Subtarget &STI);
37 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
38 /// such, whenever a client has an instance of instruction info, it should
39 /// always be able to get register info as well (through this method).
40 const AArch64RegisterInfo &getRegisterInfo() const { return RI; }
42 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
44 bool isAsCheapAsAMove(const MachineInstr &MI) const override;
46 bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
47 unsigned &DstReg, unsigned &SubIdx) const override;
50 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
51 AliasAnalysis *AA = nullptr) const override;
53 unsigned isLoadFromStackSlot(const MachineInstr &MI,
54 int &FrameIndex) const override;
55 unsigned isStoreToStackSlot(const MachineInstr &MI,
56 int &FrameIndex) const override;
58 /// Returns true if there is a shiftable register and that the shift value
60 bool hasShiftedReg(const MachineInstr &MI) const;
62 /// Returns true if there is an extendable register and that the extending
63 /// value is non-zero.
64 bool hasExtendedReg(const MachineInstr &MI) const;
66 /// \brief Does this instruction set its full destination register to zero?
67 bool isGPRZero(const MachineInstr &MI) const;
69 /// \brief Does this instruction rename a GPR without modifying bits?
70 bool isGPRCopy(const MachineInstr &MI) const;
72 /// \brief Does this instruction rename an FPR without modifying bits?
73 bool isFPRCopy(const MachineInstr &MI) const;
75 /// Return true if this is load/store scales or extends its register offset.
76 /// This refers to scaling a dynamic index as opposed to scaled immediates.
77 /// MI should be a memory op that allows scaled addressing.
78 bool isScaledAddr(const MachineInstr &MI) const;
80 /// Return true if pairing the given load or store is hinted to be
82 bool isLdStPairSuppressed(const MachineInstr &MI) const;
84 /// Return true if this is an unscaled load/store.
85 bool isUnscaledLdSt(unsigned Opc) const;
87 /// Return true if this is an unscaled load/store.
88 bool isUnscaledLdSt(MachineInstr &MI) const;
90 static bool isPairableLdStInst(const MachineInstr &MI) {
91 switch (MI.getOpcode()) {
94 // Scaled instructions.
100 case AArch64::LDRSui:
101 case AArch64::LDRDui:
102 case AArch64::LDRQui:
103 case AArch64::LDRXui:
104 case AArch64::LDRWui:
105 case AArch64::LDRSWui:
106 // Unscaled instructions.
107 case AArch64::STURSi:
108 case AArch64::STURDi:
109 case AArch64::STURQi:
110 case AArch64::STURWi:
111 case AArch64::STURXi:
112 case AArch64::LDURSi:
113 case AArch64::LDURDi:
114 case AArch64::LDURQi:
115 case AArch64::LDURWi:
116 case AArch64::LDURXi:
117 case AArch64::LDURSWi:
122 /// Return true if this is a load/store that can be potentially paired/merged.
123 bool isCandidateToMergeOrPair(MachineInstr &MI) const;
125 /// Hint that pairing the given load or store is unprofitable.
126 void suppressLdStPair(MachineInstr &MI) const;
128 bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg,
130 const TargetRegisterInfo *TRI) const override;
132 bool getMemOpBaseRegImmOfsWidth(MachineInstr &LdSt, unsigned &BaseReg,
133 int64_t &Offset, unsigned &Width,
134 const TargetRegisterInfo *TRI) const;
136 bool shouldClusterMemOps(MachineInstr &FirstLdSt, MachineInstr &SecondLdSt,
137 unsigned NumLoads) const override;
139 bool shouldScheduleAdjacent(const MachineInstr &First,
140 const MachineInstr &Second) const override;
142 MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx,
143 uint64_t Offset, const MDNode *Var,
145 const DebugLoc &DL) const;
146 void copyPhysRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
147 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
148 bool KillSrc, unsigned Opcode,
149 llvm::ArrayRef<unsigned> Indices) const;
150 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
151 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
152 bool KillSrc) const override;
154 void storeRegToStackSlot(MachineBasicBlock &MBB,
155 MachineBasicBlock::iterator MBBI, unsigned SrcReg,
156 bool isKill, int FrameIndex,
157 const TargetRegisterClass *RC,
158 const TargetRegisterInfo *TRI) const override;
160 void loadRegFromStackSlot(MachineBasicBlock &MBB,
161 MachineBasicBlock::iterator MBBI, unsigned DestReg,
162 int FrameIndex, const TargetRegisterClass *RC,
163 const TargetRegisterInfo *TRI) const override;
165 // This tells target independent code that it is okay to pass instructions
166 // with subreg operands to foldMemoryOperandImpl.
167 bool isSubregFoldable() const override { return true; }
169 using TargetInstrInfo::foldMemoryOperandImpl;
171 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
172 ArrayRef<unsigned> Ops,
173 MachineBasicBlock::iterator InsertPt, int FrameIndex,
174 LiveIntervals *LIS = nullptr) const override;
176 /// \returns true if a branch from an instruction with opcode \p BranchOpc
177 /// bytes is capable of jumping to a position \p BrOffset bytes away.
178 bool isBranchOffsetInRange(unsigned BranchOpc,
179 int64_t BrOffset) const override;
181 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
183 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
184 MachineBasicBlock *&FBB,
185 SmallVectorImpl<MachineOperand> &Cond,
186 bool AllowModify = false) const override;
187 unsigned removeBranch(MachineBasicBlock &MBB,
188 int *BytesRemoved = nullptr) const override;
189 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
190 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
192 int *BytesAdded = nullptr) const override;
194 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
195 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
196 unsigned, unsigned, int &, int &, int &) const override;
197 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
198 const DebugLoc &DL, unsigned DstReg,
199 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
200 unsigned FalseReg) const override;
201 void getNoopForMachoTarget(MCInst &NopInst) const override;
203 /// analyzeCompare - For a comparison instruction, return the source registers
204 /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
205 /// Return true if the comparison instruction can be analyzed.
206 bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
207 unsigned &SrcReg2, int &CmpMask,
208 int &CmpValue) const override;
209 /// optimizeCompareInstr - Convert the instruction supplying the argument to
210 /// the comparison into one that sets the zero bit in the flags register.
211 bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
212 unsigned SrcReg2, int CmpMask, int CmpValue,
213 const MachineRegisterInfo *MRI) const override;
214 bool optimizeCondBranch(MachineInstr &MI) const override;
216 /// Return true when a code sequence can improve throughput. It
217 /// should be called only for instructions in loops.
218 /// \param Pattern - combiner pattern
219 bool isThroughputPattern(MachineCombinerPattern Pattern) const override;
220 /// Return true when there is potentially a faster code sequence
221 /// for an instruction chain ending in <Root>. All potential patterns are
222 /// listed in the <Patterns> array.
223 bool getMachineCombinerPatterns(MachineInstr &Root,
224 SmallVectorImpl<MachineCombinerPattern> &Patterns)
226 /// Return true when Inst is associative and commutative so that it can be
228 bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
229 /// When getMachineCombinerPatterns() finds patterns, this function generates
230 /// the instructions that could replace the original code sequence
231 void genAlternativeCodeSequence(
232 MachineInstr &Root, MachineCombinerPattern Pattern,
233 SmallVectorImpl<MachineInstr *> &InsInstrs,
234 SmallVectorImpl<MachineInstr *> &DelInstrs,
235 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
236 /// AArch64 supports MachineCombiner.
237 bool useMachineCombiner() const override;
239 bool expandPostRAPseudo(MachineInstr &MI) const override;
241 std::pair<unsigned, unsigned>
242 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
243 ArrayRef<std::pair<unsigned, const char *>>
244 getSerializableDirectMachineOperandTargetFlags() const override;
245 ArrayRef<std::pair<unsigned, const char *>>
246 getSerializableBitmaskMachineOperandTargetFlags() const override;
249 void instantiateCondBranch(MachineBasicBlock &MBB, const DebugLoc &DL,
250 MachineBasicBlock *TBB,
251 ArrayRef<MachineOperand> Cond) const;
252 bool substituteCmpToZero(MachineInstr &CmpInstr, unsigned SrcReg,
253 const MachineRegisterInfo *MRI) const;
256 /// emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg
257 /// plus Offset. This is intended to be used from within the prolog/epilog
258 /// insertion (PEI) pass, where a virtual scratch register may be allocated
259 /// if necessary, to be replaced by the scavenger at the end of PEI.
260 void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
261 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
262 int Offset, const TargetInstrInfo *TII,
263 MachineInstr::MIFlag = MachineInstr::NoFlags,
264 bool SetNZCV = false);
266 /// rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the
267 /// FP. Return false if the offset could not be handled directly in MI, and
268 /// return the left-over portion by reference.
269 bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
270 unsigned FrameReg, int &Offset,
271 const AArch64InstrInfo *TII);
273 /// \brief Use to report the frame offset status in isAArch64FrameOffsetLegal.
274 enum AArch64FrameOffsetStatus {
275 AArch64FrameOffsetCannotUpdate = 0x0, ///< Offset cannot apply.
276 AArch64FrameOffsetIsLegal = 0x1, ///< Offset is legal.
277 AArch64FrameOffsetCanUpdate = 0x2 ///< Offset can apply, at least partly.
280 /// \brief Check if the @p Offset is a valid frame offset for @p MI.
281 /// The returned value reports the validity of the frame offset for @p MI.
282 /// It uses the values defined by AArch64FrameOffsetStatus for that.
283 /// If result == AArch64FrameOffsetCannotUpdate, @p MI cannot be updated to
285 /// If result & AArch64FrameOffsetIsLegal, @p Offset can completely be
286 /// rewriten in @p MI.
287 /// If result & AArch64FrameOffsetCanUpdate, @p Offset contains the
288 /// amount that is off the limit of the legal offset.
289 /// If set, @p OutUseUnscaledOp will contain the whether @p MI should be
290 /// turned into an unscaled operator, which opcode is in @p OutUnscaledOp.
291 /// If set, @p EmittableOffset contains the amount that can be set in @p MI
292 /// (possibly with @p OutUnscaledOp if OutUseUnscaledOp is true) and that
293 /// is a legal offset.
294 int isAArch64FrameOffsetLegal(const MachineInstr &MI, int &Offset,
295 bool *OutUseUnscaledOp = nullptr,
296 unsigned *OutUnscaledOp = nullptr,
297 int *EmittableOffset = nullptr);
299 static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; }
301 static inline bool isCondBranchOpcode(int Opc) {
318 static inline bool isIndirectBranchOpcode(int Opc) { return Opc == AArch64::BR; }
320 } // end namespace llvm