1 //=- AArch64InstrInfo.td - Describe the AArch64 Instructions -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // AArch64 Instruction definitions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM Instruction Predicate Definitions.
17 def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">,
18 AssemblerPredicate<"HasV8_1aOps", "armv8.1a">;
19 def HasV8_2a : Predicate<"Subtarget->hasV8_2aOps()">,
20 AssemblerPredicate<"HasV8_2aOps", "armv8.2a">;
21 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
22 AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">;
23 def HasNEON : Predicate<"Subtarget->hasNEON()">,
24 AssemblerPredicate<"FeatureNEON", "neon">;
25 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
26 AssemblerPredicate<"FeatureCrypto", "crypto">;
27 def HasCRC : Predicate<"Subtarget->hasCRC()">,
28 AssemblerPredicate<"FeatureCRC", "crc">;
29 def HasLSE : Predicate<"Subtarget->hasLSE()">,
30 AssemblerPredicate<"FeatureLSE", "lse">;
31 def HasRAS : Predicate<"Subtarget->hasRAS()">,
32 AssemblerPredicate<"FeatureRAS", "ras">;
33 def HasRDM : Predicate<"Subtarget->hasRDM()">,
34 AssemblerPredicate<"FeatureRDM", "rdm">;
35 def HasPerfMon : Predicate<"Subtarget->hasPerfMon()">;
36 def HasFullFP16 : Predicate<"Subtarget->hasFullFP16()">,
37 AssemblerPredicate<"FeatureFullFP16", "fullfp16">;
38 def HasSPE : Predicate<"Subtarget->hasSPE()">,
39 AssemblerPredicate<"FeatureSPE", "spe">;
41 def IsLE : Predicate<"Subtarget->isLittleEndian()">;
42 def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
43 def UseAlternateSExtLoadCVTF32
44 : Predicate<"Subtarget->useAlternateSExtLoadCVTF32Pattern()">;
46 def UseNegativeImmediates
47 : Predicate<"false">, AssemblerPredicate<"!FeatureNoNegativeImmediates",
48 "NegativeImmediates">;
51 //===----------------------------------------------------------------------===//
52 // AArch64-specific DAG Nodes.
55 // SDTBinaryArithWithFlagsOut - RES1, FLAGS = op LHS, RHS
56 def SDTBinaryArithWithFlagsOut : SDTypeProfile<2, 2,
59 SDTCisInt<0>, SDTCisVT<1, i32>]>;
61 // SDTBinaryArithWithFlagsIn - RES1, FLAGS = op LHS, RHS, FLAGS
62 def SDTBinaryArithWithFlagsIn : SDTypeProfile<1, 3,
68 // SDTBinaryArithWithFlagsInOut - RES1, FLAGS = op LHS, RHS, FLAGS
69 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
76 def SDT_AArch64Brcond : SDTypeProfile<0, 3,
77 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>,
79 def SDT_AArch64cbz : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisVT<1, OtherVT>]>;
80 def SDT_AArch64tbz : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>,
81 SDTCisVT<2, OtherVT>]>;
84 def SDT_AArch64CSel : SDTypeProfile<1, 4,
89 def SDT_AArch64CCMP : SDTypeProfile<1, 5,
96 def SDT_AArch64FCCMP : SDTypeProfile<1, 5,
103 def SDT_AArch64FCmp : SDTypeProfile<0, 2,
105 SDTCisSameAs<0, 1>]>;
106 def SDT_AArch64Dup : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
107 def SDT_AArch64DupLane : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<2>]>;
108 def SDT_AArch64Zip : SDTypeProfile<1, 2, [SDTCisVec<0>,
110 SDTCisSameAs<0, 2>]>;
111 def SDT_AArch64MOVIedit : SDTypeProfile<1, 1, [SDTCisInt<1>]>;
112 def SDT_AArch64MOVIshift : SDTypeProfile<1, 2, [SDTCisInt<1>, SDTCisInt<2>]>;
113 def SDT_AArch64vecimm : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
114 SDTCisInt<2>, SDTCisInt<3>]>;
115 def SDT_AArch64UnaryVec: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
116 def SDT_AArch64ExtVec: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
117 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
118 def SDT_AArch64vshift : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>, SDTCisInt<2>]>;
120 def SDT_AArch64unvec : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
121 def SDT_AArch64fcmpz : SDTypeProfile<1, 1, []>;
122 def SDT_AArch64fcmp : SDTypeProfile<1, 2, [SDTCisSameAs<1,2>]>;
123 def SDT_AArch64binvec : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
125 def SDT_AArch64trivec : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
128 def SDT_AArch64TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>]>;
129 def SDT_AArch64PREFETCH : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<1>]>;
131 def SDT_AArch64ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>;
133 def SDT_AArch64TLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>,
136 // Generates the general dynamic sequences, i.e.
137 // adrp x0, :tlsdesc:var
138 // ldr x1, [x0, #:tlsdesc_lo12:var]
139 // add x0, x0, #:tlsdesc_lo12:var
143 // (the TPIDR_EL0 offset is put directly in X0, hence no "result" here)
144 // number of operands (the variable)
145 def SDT_AArch64TLSDescCallSeq : SDTypeProfile<0,1,
148 def SDT_AArch64WrapperLarge : SDTypeProfile<1, 4,
149 [SDTCisVT<0, i64>, SDTCisVT<1, i32>,
150 SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>,
151 SDTCisSameAs<1, 4>]>;
155 def AArch64adrp : SDNode<"AArch64ISD::ADRP", SDTIntUnaryOp, []>;
156 def AArch64addlow : SDNode<"AArch64ISD::ADDlow", SDTIntBinOp, []>;
157 def AArch64LOADgot : SDNode<"AArch64ISD::LOADgot", SDTIntUnaryOp>;
158 def AArch64callseq_start : SDNode<"ISD::CALLSEQ_START",
159 SDCallSeqStart<[ SDTCisVT<0, i32> ]>,
160 [SDNPHasChain, SDNPOutGlue]>;
161 def AArch64callseq_end : SDNode<"ISD::CALLSEQ_END",
162 SDCallSeqEnd<[ SDTCisVT<0, i32>,
164 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
165 def AArch64call : SDNode<"AArch64ISD::CALL",
166 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
167 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
169 def AArch64brcond : SDNode<"AArch64ISD::BRCOND", SDT_AArch64Brcond,
171 def AArch64cbz : SDNode<"AArch64ISD::CBZ", SDT_AArch64cbz,
173 def AArch64cbnz : SDNode<"AArch64ISD::CBNZ", SDT_AArch64cbz,
175 def AArch64tbz : SDNode<"AArch64ISD::TBZ", SDT_AArch64tbz,
177 def AArch64tbnz : SDNode<"AArch64ISD::TBNZ", SDT_AArch64tbz,
181 def AArch64csel : SDNode<"AArch64ISD::CSEL", SDT_AArch64CSel>;
182 def AArch64csinv : SDNode<"AArch64ISD::CSINV", SDT_AArch64CSel>;
183 def AArch64csneg : SDNode<"AArch64ISD::CSNEG", SDT_AArch64CSel>;
184 def AArch64csinc : SDNode<"AArch64ISD::CSINC", SDT_AArch64CSel>;
185 def AArch64retflag : SDNode<"AArch64ISD::RET_FLAG", SDTNone,
186 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
187 def AArch64adc : SDNode<"AArch64ISD::ADC", SDTBinaryArithWithFlagsIn >;
188 def AArch64sbc : SDNode<"AArch64ISD::SBC", SDTBinaryArithWithFlagsIn>;
189 def AArch64add_flag : SDNode<"AArch64ISD::ADDS", SDTBinaryArithWithFlagsOut,
191 def AArch64sub_flag : SDNode<"AArch64ISD::SUBS", SDTBinaryArithWithFlagsOut>;
192 def AArch64and_flag : SDNode<"AArch64ISD::ANDS", SDTBinaryArithWithFlagsOut,
194 def AArch64adc_flag : SDNode<"AArch64ISD::ADCS", SDTBinaryArithWithFlagsInOut>;
195 def AArch64sbc_flag : SDNode<"AArch64ISD::SBCS", SDTBinaryArithWithFlagsInOut>;
197 def AArch64ccmp : SDNode<"AArch64ISD::CCMP", SDT_AArch64CCMP>;
198 def AArch64ccmn : SDNode<"AArch64ISD::CCMN", SDT_AArch64CCMP>;
199 def AArch64fccmp : SDNode<"AArch64ISD::FCCMP", SDT_AArch64FCCMP>;
201 def AArch64threadpointer : SDNode<"AArch64ISD::THREAD_POINTER", SDTPtrLeaf>;
203 def AArch64fcmp : SDNode<"AArch64ISD::FCMP", SDT_AArch64FCmp>;
205 def AArch64dup : SDNode<"AArch64ISD::DUP", SDT_AArch64Dup>;
206 def AArch64duplane8 : SDNode<"AArch64ISD::DUPLANE8", SDT_AArch64DupLane>;
207 def AArch64duplane16 : SDNode<"AArch64ISD::DUPLANE16", SDT_AArch64DupLane>;
208 def AArch64duplane32 : SDNode<"AArch64ISD::DUPLANE32", SDT_AArch64DupLane>;
209 def AArch64duplane64 : SDNode<"AArch64ISD::DUPLANE64", SDT_AArch64DupLane>;
211 def AArch64zip1 : SDNode<"AArch64ISD::ZIP1", SDT_AArch64Zip>;
212 def AArch64zip2 : SDNode<"AArch64ISD::ZIP2", SDT_AArch64Zip>;
213 def AArch64uzp1 : SDNode<"AArch64ISD::UZP1", SDT_AArch64Zip>;
214 def AArch64uzp2 : SDNode<"AArch64ISD::UZP2", SDT_AArch64Zip>;
215 def AArch64trn1 : SDNode<"AArch64ISD::TRN1", SDT_AArch64Zip>;
216 def AArch64trn2 : SDNode<"AArch64ISD::TRN2", SDT_AArch64Zip>;
218 def AArch64movi_edit : SDNode<"AArch64ISD::MOVIedit", SDT_AArch64MOVIedit>;
219 def AArch64movi_shift : SDNode<"AArch64ISD::MOVIshift", SDT_AArch64MOVIshift>;
220 def AArch64movi_msl : SDNode<"AArch64ISD::MOVImsl", SDT_AArch64MOVIshift>;
221 def AArch64mvni_shift : SDNode<"AArch64ISD::MVNIshift", SDT_AArch64MOVIshift>;
222 def AArch64mvni_msl : SDNode<"AArch64ISD::MVNImsl", SDT_AArch64MOVIshift>;
223 def AArch64movi : SDNode<"AArch64ISD::MOVI", SDT_AArch64MOVIedit>;
224 def AArch64fmov : SDNode<"AArch64ISD::FMOV", SDT_AArch64MOVIedit>;
226 def AArch64rev16 : SDNode<"AArch64ISD::REV16", SDT_AArch64UnaryVec>;
227 def AArch64rev32 : SDNode<"AArch64ISD::REV32", SDT_AArch64UnaryVec>;
228 def AArch64rev64 : SDNode<"AArch64ISD::REV64", SDT_AArch64UnaryVec>;
229 def AArch64ext : SDNode<"AArch64ISD::EXT", SDT_AArch64ExtVec>;
231 def AArch64vashr : SDNode<"AArch64ISD::VASHR", SDT_AArch64vshift>;
232 def AArch64vlshr : SDNode<"AArch64ISD::VLSHR", SDT_AArch64vshift>;
233 def AArch64vshl : SDNode<"AArch64ISD::VSHL", SDT_AArch64vshift>;
234 def AArch64sqshli : SDNode<"AArch64ISD::SQSHL_I", SDT_AArch64vshift>;
235 def AArch64uqshli : SDNode<"AArch64ISD::UQSHL_I", SDT_AArch64vshift>;
236 def AArch64sqshlui : SDNode<"AArch64ISD::SQSHLU_I", SDT_AArch64vshift>;
237 def AArch64srshri : SDNode<"AArch64ISD::SRSHR_I", SDT_AArch64vshift>;
238 def AArch64urshri : SDNode<"AArch64ISD::URSHR_I", SDT_AArch64vshift>;
240 def AArch64not: SDNode<"AArch64ISD::NOT", SDT_AArch64unvec>;
241 def AArch64bit: SDNode<"AArch64ISD::BIT", SDT_AArch64trivec>;
242 def AArch64bsl: SDNode<"AArch64ISD::BSL", SDT_AArch64trivec>;
244 def AArch64cmeq: SDNode<"AArch64ISD::CMEQ", SDT_AArch64binvec>;
245 def AArch64cmge: SDNode<"AArch64ISD::CMGE", SDT_AArch64binvec>;
246 def AArch64cmgt: SDNode<"AArch64ISD::CMGT", SDT_AArch64binvec>;
247 def AArch64cmhi: SDNode<"AArch64ISD::CMHI", SDT_AArch64binvec>;
248 def AArch64cmhs: SDNode<"AArch64ISD::CMHS", SDT_AArch64binvec>;
250 def AArch64fcmeq: SDNode<"AArch64ISD::FCMEQ", SDT_AArch64fcmp>;
251 def AArch64fcmge: SDNode<"AArch64ISD::FCMGE", SDT_AArch64fcmp>;
252 def AArch64fcmgt: SDNode<"AArch64ISD::FCMGT", SDT_AArch64fcmp>;
254 def AArch64cmeqz: SDNode<"AArch64ISD::CMEQz", SDT_AArch64unvec>;
255 def AArch64cmgez: SDNode<"AArch64ISD::CMGEz", SDT_AArch64unvec>;
256 def AArch64cmgtz: SDNode<"AArch64ISD::CMGTz", SDT_AArch64unvec>;
257 def AArch64cmlez: SDNode<"AArch64ISD::CMLEz", SDT_AArch64unvec>;
258 def AArch64cmltz: SDNode<"AArch64ISD::CMLTz", SDT_AArch64unvec>;
259 def AArch64cmtst : PatFrag<(ops node:$LHS, node:$RHS),
260 (AArch64not (AArch64cmeqz (and node:$LHS, node:$RHS)))>;
262 def AArch64fcmeqz: SDNode<"AArch64ISD::FCMEQz", SDT_AArch64fcmpz>;
263 def AArch64fcmgez: SDNode<"AArch64ISD::FCMGEz", SDT_AArch64fcmpz>;
264 def AArch64fcmgtz: SDNode<"AArch64ISD::FCMGTz", SDT_AArch64fcmpz>;
265 def AArch64fcmlez: SDNode<"AArch64ISD::FCMLEz", SDT_AArch64fcmpz>;
266 def AArch64fcmltz: SDNode<"AArch64ISD::FCMLTz", SDT_AArch64fcmpz>;
268 def AArch64bici: SDNode<"AArch64ISD::BICi", SDT_AArch64vecimm>;
269 def AArch64orri: SDNode<"AArch64ISD::ORRi", SDT_AArch64vecimm>;
271 def AArch64neg : SDNode<"AArch64ISD::NEG", SDT_AArch64unvec>;
273 def AArch64tcret: SDNode<"AArch64ISD::TC_RETURN", SDT_AArch64TCRET,
274 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
276 def AArch64Prefetch : SDNode<"AArch64ISD::PREFETCH", SDT_AArch64PREFETCH,
277 [SDNPHasChain, SDNPSideEffect]>;
279 def AArch64sitof: SDNode<"AArch64ISD::SITOF", SDT_AArch64ITOF>;
280 def AArch64uitof: SDNode<"AArch64ISD::UITOF", SDT_AArch64ITOF>;
282 def AArch64tlsdesc_callseq : SDNode<"AArch64ISD::TLSDESC_CALLSEQ",
283 SDT_AArch64TLSDescCallSeq,
284 [SDNPInGlue, SDNPOutGlue, SDNPHasChain,
288 def AArch64WrapperLarge : SDNode<"AArch64ISD::WrapperLarge",
289 SDT_AArch64WrapperLarge>;
291 def AArch64NvCast : SDNode<"AArch64ISD::NVCAST", SDTUnaryOp>;
293 def SDT_AArch64mull : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
294 SDTCisSameAs<1, 2>]>;
295 def AArch64smull : SDNode<"AArch64ISD::SMULL", SDT_AArch64mull>;
296 def AArch64umull : SDNode<"AArch64ISD::UMULL", SDT_AArch64mull>;
298 def AArch64frecpe : SDNode<"AArch64ISD::FRECPE", SDTFPUnaryOp>;
299 def AArch64frecps : SDNode<"AArch64ISD::FRECPS", SDTFPBinOp>;
300 def AArch64frsqrte : SDNode<"AArch64ISD::FRSQRTE", SDTFPUnaryOp>;
301 def AArch64frsqrts : SDNode<"AArch64ISD::FRSQRTS", SDTFPBinOp>;
303 def AArch64saddv : SDNode<"AArch64ISD::SADDV", SDT_AArch64UnaryVec>;
304 def AArch64uaddv : SDNode<"AArch64ISD::UADDV", SDT_AArch64UnaryVec>;
305 def AArch64sminv : SDNode<"AArch64ISD::SMINV", SDT_AArch64UnaryVec>;
306 def AArch64uminv : SDNode<"AArch64ISD::UMINV", SDT_AArch64UnaryVec>;
307 def AArch64smaxv : SDNode<"AArch64ISD::SMAXV", SDT_AArch64UnaryVec>;
308 def AArch64umaxv : SDNode<"AArch64ISD::UMAXV", SDT_AArch64UnaryVec>;
310 //===----------------------------------------------------------------------===//
312 //===----------------------------------------------------------------------===//
314 // AArch64 Instruction Predicate Definitions.
315 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
316 def IsNotDarwin: Predicate<"!Subtarget->isTargetDarwin()">;
317 def ForCodeSize : Predicate<"ForCodeSize">;
318 def NotForCodeSize : Predicate<"!ForCodeSize">;
320 include "AArch64InstrFormats.td"
322 //===----------------------------------------------------------------------===//
324 //===----------------------------------------------------------------------===//
325 // Miscellaneous instructions.
326 //===----------------------------------------------------------------------===//
328 let Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1 in {
329 // We set Sched to empty list because we expect these instructions to simply get
330 // removed in most cases.
331 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
332 [(AArch64callseq_start timm:$amt)]>, Sched<[]>;
333 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
334 [(AArch64callseq_end timm:$amt1, timm:$amt2)]>,
336 } // Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1
338 let isReMaterializable = 1, isCodeGenOnly = 1 in {
339 // FIXME: The following pseudo instructions are only needed because remat
340 // cannot handle multiple instructions. When that changes, they can be
341 // removed, along with the AArch64Wrapper node.
343 let AddedComplexity = 10 in
344 def LOADgot : Pseudo<(outs GPR64:$dst), (ins i64imm:$addr),
345 [(set GPR64:$dst, (AArch64LOADgot tglobaladdr:$addr))]>,
348 // The MOVaddr instruction should match only when the add is not folded
349 // into a load or store address.
351 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
352 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaladdr:$hi),
353 tglobaladdr:$low))]>,
354 Sched<[WriteAdrAdr]>;
356 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
357 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tjumptable:$hi),
359 Sched<[WriteAdrAdr]>;
361 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
362 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tconstpool:$hi),
364 Sched<[WriteAdrAdr]>;
366 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
367 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tblockaddress:$hi),
368 tblockaddress:$low))]>,
369 Sched<[WriteAdrAdr]>;
371 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
372 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaltlsaddr:$hi),
373 tglobaltlsaddr:$low))]>,
374 Sched<[WriteAdrAdr]>;
376 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
377 [(set GPR64:$dst, (AArch64addlow (AArch64adrp texternalsym:$hi),
378 texternalsym:$low))]>,
379 Sched<[WriteAdrAdr]>;
381 } // isReMaterializable, isCodeGenOnly
383 def : Pat<(AArch64LOADgot tglobaltlsaddr:$addr),
384 (LOADgot tglobaltlsaddr:$addr)>;
386 def : Pat<(AArch64LOADgot texternalsym:$addr),
387 (LOADgot texternalsym:$addr)>;
389 def : Pat<(AArch64LOADgot tconstpool:$addr),
390 (LOADgot tconstpool:$addr)>;
392 //===----------------------------------------------------------------------===//
393 // System instructions.
394 //===----------------------------------------------------------------------===//
396 def HINT : HintI<"hint">;
397 def : InstAlias<"nop", (HINT 0b000)>;
398 def : InstAlias<"yield",(HINT 0b001)>;
399 def : InstAlias<"wfe", (HINT 0b010)>;
400 def : InstAlias<"wfi", (HINT 0b011)>;
401 def : InstAlias<"sev", (HINT 0b100)>;
402 def : InstAlias<"sevl", (HINT 0b101)>;
403 def : InstAlias<"esb", (HINT 0b10000)>, Requires<[HasRAS]>;
405 // v8.2a Statistical Profiling extension
406 def : InstAlias<"psb $op", (HINT psbhint_op:$op)>, Requires<[HasSPE]>;
408 // As far as LLVM is concerned this writes to the system's exclusive monitors.
409 let mayLoad = 1, mayStore = 1 in
410 def CLREX : CRmSystemI<imm0_15, 0b010, "clrex">;
412 // NOTE: ideally, this would have mayStore = 0, mayLoad = 0, but we cannot
413 // model patterns with sufficiently fine granularity.
414 let mayLoad = ?, mayStore = ? in {
415 def DMB : CRmSystemI<barrier_op, 0b101, "dmb",
416 [(int_aarch64_dmb (i32 imm32_0_15:$CRm))]>;
418 def DSB : CRmSystemI<barrier_op, 0b100, "dsb",
419 [(int_aarch64_dsb (i32 imm32_0_15:$CRm))]>;
421 def ISB : CRmSystemI<barrier_op, 0b110, "isb",
422 [(int_aarch64_isb (i32 imm32_0_15:$CRm))]>;
425 def : InstAlias<"clrex", (CLREX 0xf)>;
426 def : InstAlias<"isb", (ISB 0xf)>;
430 def MSRpstateImm1 : MSRpstateImm0_1;
431 def MSRpstateImm4 : MSRpstateImm0_15;
433 // The thread pointer (on Linux, at least, where this has been implemented) is
434 // TPIDR_EL0. Add pseudo op so we can mark it as not having any side effects.
435 let hasSideEffects = 0 in
436 def MOVbaseTLS : Pseudo<(outs GPR64:$dst), (ins),
437 [(set GPR64:$dst, AArch64threadpointer)]>, Sched<[]>;
439 // The cycle counter PMC register is PMCCNTR_EL0.
440 let Predicates = [HasPerfMon] in
441 def : Pat<(readcyclecounter), (MRS 0xdce8)>;
443 // Generic system instructions
444 def SYSxt : SystemXtI<0, "sys">;
445 def SYSLxt : SystemLXtI<1, "sysl">;
447 def : InstAlias<"sys $op1, $Cn, $Cm, $op2",
448 (SYSxt imm0_7:$op1, sys_cr_op:$Cn,
449 sys_cr_op:$Cm, imm0_7:$op2, XZR)>;
451 //===----------------------------------------------------------------------===//
452 // Move immediate instructions.
453 //===----------------------------------------------------------------------===//
455 defm MOVK : InsertImmediate<0b11, "movk">;
456 defm MOVN : MoveImmediate<0b00, "movn">;
458 let PostEncoderMethod = "fixMOVZ" in
459 defm MOVZ : MoveImmediate<0b10, "movz">;
461 // First group of aliases covers an implicit "lsl #0".
462 def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, imm0_65535:$imm, 0)>;
463 def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, imm0_65535:$imm, 0)>;
464 def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, imm0_65535:$imm, 0)>;
465 def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, imm0_65535:$imm, 0)>;
466 def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, imm0_65535:$imm, 0)>;
467 def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, imm0_65535:$imm, 0)>;
469 // Next, we have various ELF relocations with the ":XYZ_g0:sym" syntax.
470 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
471 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
472 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
473 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
475 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
476 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
477 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
478 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
480 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g3:$sym, 48)>;
481 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g2:$sym, 32)>;
482 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g1:$sym, 16)>;
483 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g0:$sym, 0)>;
485 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
486 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
488 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
489 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
491 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16)>;
492 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g0:$sym, 0)>;
494 // Final group of aliases covers true "mov $Rd, $imm" cases.
495 multiclass movw_mov_alias<string basename,Instruction INST, RegisterClass GPR,
496 int width, int shift> {
497 def _asmoperand : AsmOperandClass {
498 let Name = basename # width # "_lsl" # shift # "MovAlias";
499 let PredicateMethod = "is" # basename # "MovAlias<" # width # ", "
501 let RenderMethod = "add" # basename # "MovAliasOperands<" # shift # ">";
504 def _movimm : Operand<i32> {
505 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_asmoperand");
508 def : InstAlias<"mov $Rd, $imm",
509 (INST GPR:$Rd, !cast<Operand>(NAME # "_movimm"):$imm, shift)>;
512 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 0>;
513 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 16>;
515 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 0>;
516 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 16>;
517 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 32>;
518 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 48>;
520 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 0>;
521 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 16>;
523 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 0>;
524 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 16>;
525 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 32>;
526 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 48>;
528 let isReMaterializable = 1, isCodeGenOnly = 1, isMoveImm = 1,
529 isAsCheapAsAMove = 1 in {
530 // FIXME: The following pseudo instructions are only needed because remat
531 // cannot handle multiple instructions. When that changes, we can select
532 // directly to the real instructions and get rid of these pseudos.
535 : Pseudo<(outs GPR32:$dst), (ins i32imm:$src),
536 [(set GPR32:$dst, imm:$src)]>,
539 : Pseudo<(outs GPR64:$dst), (ins i64imm:$src),
540 [(set GPR64:$dst, imm:$src)]>,
542 } // isReMaterializable, isCodeGenOnly
544 // If possible, we want to use MOVi32imm even for 64-bit moves. This gives the
545 // eventual expansion code fewer bits to worry about getting right. Marshalling
546 // the types is a little tricky though:
547 def i64imm_32bit : ImmLeaf<i64, [{
548 return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);
551 def s64imm_32bit : ImmLeaf<i64, [{
552 int64_t Imm64 = static_cast<int64_t>(Imm);
553 return Imm64 >= std::numeric_limits<int32_t>::min() &&
554 Imm64 <= std::numeric_limits<int32_t>::max();
557 def trunc_imm : SDNodeXForm<imm, [{
558 return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i32);
561 def : Pat<(i64 i64imm_32bit:$src),
562 (SUBREG_TO_REG (i64 0), (MOVi32imm (trunc_imm imm:$src)), sub_32)>;
564 // Materialize FP constants via MOVi32imm/MOVi64imm (MachO large code model).
565 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
566 return CurDAG->getTargetConstant(
567 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i32);
570 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
571 return CurDAG->getTargetConstant(
572 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i64);
576 def : Pat<(f32 fpimm:$in),
577 (COPY_TO_REGCLASS (MOVi32imm (bitcast_fpimm_to_i32 f32:$in)), FPR32)>;
578 def : Pat<(f64 fpimm:$in),
579 (COPY_TO_REGCLASS (MOVi64imm (bitcast_fpimm_to_i64 f64:$in)), FPR64)>;
582 // Deal with the various forms of (ELF) large addressing with MOVZ/MOVK
584 def : Pat<(AArch64WrapperLarge tglobaladdr:$g3, tglobaladdr:$g2,
585 tglobaladdr:$g1, tglobaladdr:$g0),
586 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tglobaladdr:$g0, 0),
587 tglobaladdr:$g1, 16),
588 tglobaladdr:$g2, 32),
589 tglobaladdr:$g3, 48)>;
591 def : Pat<(AArch64WrapperLarge tblockaddress:$g3, tblockaddress:$g2,
592 tblockaddress:$g1, tblockaddress:$g0),
593 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tblockaddress:$g0, 0),
594 tblockaddress:$g1, 16),
595 tblockaddress:$g2, 32),
596 tblockaddress:$g3, 48)>;
598 def : Pat<(AArch64WrapperLarge tconstpool:$g3, tconstpool:$g2,
599 tconstpool:$g1, tconstpool:$g0),
600 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tconstpool:$g0, 0),
603 tconstpool:$g3, 48)>;
605 def : Pat<(AArch64WrapperLarge tjumptable:$g3, tjumptable:$g2,
606 tjumptable:$g1, tjumptable:$g0),
607 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tjumptable:$g0, 0),
610 tjumptable:$g3, 48)>;
613 //===----------------------------------------------------------------------===//
614 // Arithmetic instructions.
615 //===----------------------------------------------------------------------===//
617 // Add/subtract with carry.
618 defm ADC : AddSubCarry<0, "adc", "adcs", AArch64adc, AArch64adc_flag>;
619 defm SBC : AddSubCarry<1, "sbc", "sbcs", AArch64sbc, AArch64sbc_flag>;
621 def : InstAlias<"ngc $dst, $src", (SBCWr GPR32:$dst, WZR, GPR32:$src)>;
622 def : InstAlias<"ngc $dst, $src", (SBCXr GPR64:$dst, XZR, GPR64:$src)>;
623 def : InstAlias<"ngcs $dst, $src", (SBCSWr GPR32:$dst, WZR, GPR32:$src)>;
624 def : InstAlias<"ngcs $dst, $src", (SBCSXr GPR64:$dst, XZR, GPR64:$src)>;
627 defm ADD : AddSub<0, "add", "sub", add>;
628 defm SUB : AddSub<1, "sub", "add">;
630 def : InstAlias<"mov $dst, $src",
631 (ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0)>;
632 def : InstAlias<"mov $dst, $src",
633 (ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0)>;
634 def : InstAlias<"mov $dst, $src",
635 (ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0)>;
636 def : InstAlias<"mov $dst, $src",
637 (ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0)>;
639 defm ADDS : AddSubS<0, "adds", AArch64add_flag, "cmn", "subs", "cmp">;
640 defm SUBS : AddSubS<1, "subs", AArch64sub_flag, "cmp", "adds", "cmn">;
642 // Use SUBS instead of SUB to enable CSE between SUBS and SUB.
643 def : Pat<(sub GPR32sp:$Rn, addsub_shifted_imm32:$imm),
644 (SUBSWri GPR32sp:$Rn, addsub_shifted_imm32:$imm)>;
645 def : Pat<(sub GPR64sp:$Rn, addsub_shifted_imm64:$imm),
646 (SUBSXri GPR64sp:$Rn, addsub_shifted_imm64:$imm)>;
647 def : Pat<(sub GPR32:$Rn, GPR32:$Rm),
648 (SUBSWrr GPR32:$Rn, GPR32:$Rm)>;
649 def : Pat<(sub GPR64:$Rn, GPR64:$Rm),
650 (SUBSXrr GPR64:$Rn, GPR64:$Rm)>;
651 def : Pat<(sub GPR32:$Rn, arith_shifted_reg32:$Rm),
652 (SUBSWrs GPR32:$Rn, arith_shifted_reg32:$Rm)>;
653 def : Pat<(sub GPR64:$Rn, arith_shifted_reg64:$Rm),
654 (SUBSXrs GPR64:$Rn, arith_shifted_reg64:$Rm)>;
655 let AddedComplexity = 1 in {
656 def : Pat<(sub GPR32sp:$R2, arith_extended_reg32<i32>:$R3),
657 (SUBSWrx GPR32sp:$R2, arith_extended_reg32<i32>:$R3)>;
658 def : Pat<(sub GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3),
659 (SUBSXrx GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3)>;
662 // Because of the immediate format for add/sub-imm instructions, the
663 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
664 // These patterns capture that transformation.
665 let AddedComplexity = 1 in {
666 def : Pat<(add GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
667 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
668 def : Pat<(add GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
669 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
670 def : Pat<(sub GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
671 (ADDWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
672 def : Pat<(sub GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
673 (ADDXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
676 // Because of the immediate format for add/sub-imm instructions, the
677 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
678 // These patterns capture that transformation.
679 let AddedComplexity = 1 in {
680 def : Pat<(AArch64add_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
681 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
682 def : Pat<(AArch64add_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
683 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
684 def : Pat<(AArch64sub_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
685 (ADDSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
686 def : Pat<(AArch64sub_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
687 (ADDSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
690 def : InstAlias<"neg $dst, $src", (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
691 def : InstAlias<"neg $dst, $src", (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
692 def : InstAlias<"neg $dst, $src$shift",
693 (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
694 def : InstAlias<"neg $dst, $src$shift",
695 (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
697 def : InstAlias<"negs $dst, $src", (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
698 def : InstAlias<"negs $dst, $src", (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
699 def : InstAlias<"negs $dst, $src$shift",
700 (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
701 def : InstAlias<"negs $dst, $src$shift",
702 (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
705 // Unsigned/Signed divide
706 defm UDIV : Div<0, "udiv", udiv>;
707 defm SDIV : Div<1, "sdiv", sdiv>;
709 def : Pat<(int_aarch64_udiv GPR32:$Rn, GPR32:$Rm), (UDIVWr $Rn, $Rm)>;
710 def : Pat<(int_aarch64_udiv GPR64:$Rn, GPR64:$Rm), (UDIVXr $Rn, $Rm)>;
711 def : Pat<(int_aarch64_sdiv GPR32:$Rn, GPR32:$Rm), (SDIVWr $Rn, $Rm)>;
712 def : Pat<(int_aarch64_sdiv GPR64:$Rn, GPR64:$Rm), (SDIVXr $Rn, $Rm)>;
715 defm ASRV : Shift<0b10, "asr", sra>;
716 defm LSLV : Shift<0b00, "lsl", shl>;
717 defm LSRV : Shift<0b01, "lsr", srl>;
718 defm RORV : Shift<0b11, "ror", rotr>;
720 def : ShiftAlias<"asrv", ASRVWr, GPR32>;
721 def : ShiftAlias<"asrv", ASRVXr, GPR64>;
722 def : ShiftAlias<"lslv", LSLVWr, GPR32>;
723 def : ShiftAlias<"lslv", LSLVXr, GPR64>;
724 def : ShiftAlias<"lsrv", LSRVWr, GPR32>;
725 def : ShiftAlias<"lsrv", LSRVXr, GPR64>;
726 def : ShiftAlias<"rorv", RORVWr, GPR32>;
727 def : ShiftAlias<"rorv", RORVXr, GPR64>;
730 let AddedComplexity = 7 in {
731 defm MADD : MulAccum<0, "madd", add>;
732 defm MSUB : MulAccum<1, "msub", sub>;
734 def : Pat<(i32 (mul GPR32:$Rn, GPR32:$Rm)),
735 (MADDWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
736 def : Pat<(i64 (mul GPR64:$Rn, GPR64:$Rm)),
737 (MADDXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
739 def : Pat<(i32 (ineg (mul GPR32:$Rn, GPR32:$Rm))),
740 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
741 def : Pat<(i64 (ineg (mul GPR64:$Rn, GPR64:$Rm))),
742 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
743 def : Pat<(i32 (mul (ineg GPR32:$Rn), GPR32:$Rm)),
744 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
745 def : Pat<(i64 (mul (ineg GPR64:$Rn), GPR64:$Rm)),
746 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
747 } // AddedComplexity = 7
749 let AddedComplexity = 5 in {
750 def SMADDLrrr : WideMulAccum<0, 0b001, "smaddl", add, sext>;
751 def SMSUBLrrr : WideMulAccum<1, 0b001, "smsubl", sub, sext>;
752 def UMADDLrrr : WideMulAccum<0, 0b101, "umaddl", add, zext>;
753 def UMSUBLrrr : WideMulAccum<1, 0b101, "umsubl", sub, zext>;
755 def : Pat<(i64 (mul (sext GPR32:$Rn), (sext GPR32:$Rm))),
756 (SMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
757 def : Pat<(i64 (mul (zext GPR32:$Rn), (zext GPR32:$Rm))),
758 (UMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
760 def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (sext GPR32:$Rm)))),
761 (SMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
762 def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (zext GPR32:$Rm)))),
763 (UMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
765 def : Pat<(i64 (mul (sext GPR32:$Rn), (s64imm_32bit:$C))),
766 (SMADDLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), XZR)>;
767 def : Pat<(i64 (mul (zext GPR32:$Rn), (i64imm_32bit:$C))),
768 (UMADDLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), XZR)>;
769 def : Pat<(i64 (mul (sext_inreg GPR64:$Rn, i32), (s64imm_32bit:$C))),
770 (SMADDLrrr (i32 (EXTRACT_SUBREG GPR64:$Rn, sub_32)),
771 (MOVi32imm (trunc_imm imm:$C)), XZR)>;
773 def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (s64imm_32bit:$C)))),
774 (SMSUBLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), XZR)>;
775 def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (i64imm_32bit:$C)))),
776 (UMSUBLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), XZR)>;
777 def : Pat<(i64 (ineg (mul (sext_inreg GPR64:$Rn, i32), (s64imm_32bit:$C)))),
778 (SMSUBLrrr (i32 (EXTRACT_SUBREG GPR64:$Rn, sub_32)),
779 (MOVi32imm (trunc_imm imm:$C)), XZR)>;
781 def : Pat<(i64 (add (mul (sext GPR32:$Rn), (s64imm_32bit:$C)), GPR64:$Ra)),
782 (SMADDLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>;
783 def : Pat<(i64 (add (mul (zext GPR32:$Rn), (i64imm_32bit:$C)), GPR64:$Ra)),
784 (UMADDLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>;
785 def : Pat<(i64 (add (mul (sext_inreg GPR64:$Rn, i32), (s64imm_32bit:$C)),
787 (SMADDLrrr (i32 (EXTRACT_SUBREG GPR64:$Rn, sub_32)),
788 (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>;
790 def : Pat<(i64 (sub GPR64:$Ra, (mul (sext GPR32:$Rn), (s64imm_32bit:$C)))),
791 (SMSUBLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>;
792 def : Pat<(i64 (sub GPR64:$Ra, (mul (zext GPR32:$Rn), (i64imm_32bit:$C)))),
793 (UMSUBLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>;
794 def : Pat<(i64 (sub GPR64:$Ra, (mul (sext_inreg GPR64:$Rn, i32),
795 (s64imm_32bit:$C)))),
796 (SMSUBLrrr (i32 (EXTRACT_SUBREG GPR64:$Rn, sub_32)),
797 (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>;
798 } // AddedComplexity = 5
800 def : MulAccumWAlias<"mul", MADDWrrr>;
801 def : MulAccumXAlias<"mul", MADDXrrr>;
802 def : MulAccumWAlias<"mneg", MSUBWrrr>;
803 def : MulAccumXAlias<"mneg", MSUBXrrr>;
804 def : WideMulAccumAlias<"smull", SMADDLrrr>;
805 def : WideMulAccumAlias<"smnegl", SMSUBLrrr>;
806 def : WideMulAccumAlias<"umull", UMADDLrrr>;
807 def : WideMulAccumAlias<"umnegl", UMSUBLrrr>;
810 def SMULHrr : MulHi<0b010, "smulh", mulhs>;
811 def UMULHrr : MulHi<0b110, "umulh", mulhu>;
814 def CRC32Brr : BaseCRC32<0, 0b00, 0, GPR32, int_aarch64_crc32b, "crc32b">;
815 def CRC32Hrr : BaseCRC32<0, 0b01, 0, GPR32, int_aarch64_crc32h, "crc32h">;
816 def CRC32Wrr : BaseCRC32<0, 0b10, 0, GPR32, int_aarch64_crc32w, "crc32w">;
817 def CRC32Xrr : BaseCRC32<1, 0b11, 0, GPR64, int_aarch64_crc32x, "crc32x">;
819 def CRC32CBrr : BaseCRC32<0, 0b00, 1, GPR32, int_aarch64_crc32cb, "crc32cb">;
820 def CRC32CHrr : BaseCRC32<0, 0b01, 1, GPR32, int_aarch64_crc32ch, "crc32ch">;
821 def CRC32CWrr : BaseCRC32<0, 0b10, 1, GPR32, int_aarch64_crc32cw, "crc32cw">;
822 def CRC32CXrr : BaseCRC32<1, 0b11, 1, GPR64, int_aarch64_crc32cx, "crc32cx">;
825 defm CAS : CompareAndSwap<0, 0, "">;
826 defm CASA : CompareAndSwap<1, 0, "a">;
827 defm CASL : CompareAndSwap<0, 1, "l">;
828 defm CASAL : CompareAndSwap<1, 1, "al">;
831 defm CASP : CompareAndSwapPair<0, 0, "">;
832 defm CASPA : CompareAndSwapPair<1, 0, "a">;
833 defm CASPL : CompareAndSwapPair<0, 1, "l">;
834 defm CASPAL : CompareAndSwapPair<1, 1, "al">;
837 defm SWP : Swap<0, 0, "">;
838 defm SWPA : Swap<1, 0, "a">;
839 defm SWPL : Swap<0, 1, "l">;
840 defm SWPAL : Swap<1, 1, "al">;
842 // v8.1 atomic LD<OP>(register). Performs load and then ST<OP>(register)
843 defm LDADD : LDOPregister<0b000, "add", 0, 0, "">;
844 defm LDADDA : LDOPregister<0b000, "add", 1, 0, "a">;
845 defm LDADDL : LDOPregister<0b000, "add", 0, 1, "l">;
846 defm LDADDAL : LDOPregister<0b000, "add", 1, 1, "al">;
848 defm LDCLR : LDOPregister<0b001, "clr", 0, 0, "">;
849 defm LDCLRA : LDOPregister<0b001, "clr", 1, 0, "a">;
850 defm LDCLRL : LDOPregister<0b001, "clr", 0, 1, "l">;
851 defm LDCLRAL : LDOPregister<0b001, "clr", 1, 1, "al">;
853 defm LDEOR : LDOPregister<0b010, "eor", 0, 0, "">;
854 defm LDEORA : LDOPregister<0b010, "eor", 1, 0, "a">;
855 defm LDEORL : LDOPregister<0b010, "eor", 0, 1, "l">;
856 defm LDEORAL : LDOPregister<0b010, "eor", 1, 1, "al">;
858 defm LDSET : LDOPregister<0b011, "set", 0, 0, "">;
859 defm LDSETA : LDOPregister<0b011, "set", 1, 0, "a">;
860 defm LDSETL : LDOPregister<0b011, "set", 0, 1, "l">;
861 defm LDSETAL : LDOPregister<0b011, "set", 1, 1, "al">;
863 defm LDSMAX : LDOPregister<0b100, "smax", 0, 0, "">;
864 defm LDSMAXA : LDOPregister<0b100, "smax", 1, 0, "a">;
865 defm LDSMAXL : LDOPregister<0b100, "smax", 0, 1, "l">;
866 defm LDSMAXAL : LDOPregister<0b100, "smax", 1, 1, "al">;
868 defm LDSMIN : LDOPregister<0b101, "smin", 0, 0, "">;
869 defm LDSMINA : LDOPregister<0b101, "smin", 1, 0, "a">;
870 defm LDSMINL : LDOPregister<0b101, "smin", 0, 1, "l">;
871 defm LDSMINAL : LDOPregister<0b101, "smin", 1, 1, "al">;
873 defm LDUMAX : LDOPregister<0b110, "umax", 0, 0, "">;
874 defm LDUMAXA : LDOPregister<0b110, "umax", 1, 0, "a">;
875 defm LDUMAXL : LDOPregister<0b110, "umax", 0, 1, "l">;
876 defm LDUMAXAL : LDOPregister<0b110, "umax", 1, 1, "al">;
878 defm LDUMIN : LDOPregister<0b111, "umin", 0, 0, "">;
879 defm LDUMINA : LDOPregister<0b111, "umin", 1, 0, "a">;
880 defm LDUMINL : LDOPregister<0b111, "umin", 0, 1, "l">;
881 defm LDUMINAL : LDOPregister<0b111, "umin", 1, 1, "al">;
883 // v8.1 atomic ST<OP>(register) as aliases to "LD<OP>(register) when Rt=xZR"
884 defm : STOPregister<"stadd","LDADD">; // STADDx
885 defm : STOPregister<"stclr","LDCLR">; // STCLRx
886 defm : STOPregister<"steor","LDEOR">; // STEORx
887 defm : STOPregister<"stset","LDSET">; // STSETx
888 defm : STOPregister<"stsmax","LDSMAX">;// STSMAXx
889 defm : STOPregister<"stsmin","LDSMIN">;// STSMINx
890 defm : STOPregister<"stumax","LDUMAX">;// STUMAXx
891 defm : STOPregister<"stumin","LDUMIN">;// STUMINx
893 //===----------------------------------------------------------------------===//
894 // Logical instructions.
895 //===----------------------------------------------------------------------===//
898 defm ANDS : LogicalImmS<0b11, "ands", AArch64and_flag, "bics">;
899 defm AND : LogicalImm<0b00, "and", and, "bic">;
900 defm EOR : LogicalImm<0b10, "eor", xor, "eon">;
901 defm ORR : LogicalImm<0b01, "orr", or, "orn">;
903 // FIXME: these aliases *are* canonical sometimes (when movz can't be
904 // used). Actually, it seems to be working right now, but putting logical_immXX
905 // here is a bit dodgy on the AsmParser side too.
906 def : InstAlias<"mov $dst, $imm", (ORRWri GPR32sp:$dst, WZR,
907 logical_imm32:$imm), 0>;
908 def : InstAlias<"mov $dst, $imm", (ORRXri GPR64sp:$dst, XZR,
909 logical_imm64:$imm), 0>;
913 defm ANDS : LogicalRegS<0b11, 0, "ands", AArch64and_flag>;
914 defm BICS : LogicalRegS<0b11, 1, "bics",
915 BinOpFrag<(AArch64and_flag node:$LHS, (not node:$RHS))>>;
916 defm AND : LogicalReg<0b00, 0, "and", and>;
917 defm BIC : LogicalReg<0b00, 1, "bic",
918 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
919 defm EON : LogicalReg<0b10, 1, "eon",
920 BinOpFrag<(not (xor node:$LHS, node:$RHS))>>;
921 defm EOR : LogicalReg<0b10, 0, "eor", xor>;
922 defm ORN : LogicalReg<0b01, 1, "orn",
923 BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
924 defm ORR : LogicalReg<0b01, 0, "orr", or>;
926 def : InstAlias<"mov $dst, $src", (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0), 2>;
927 def : InstAlias<"mov $dst, $src", (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0), 2>;
929 def : InstAlias<"mvn $Wd, $Wm", (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0), 3>;
930 def : InstAlias<"mvn $Xd, $Xm", (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0), 3>;
932 def : InstAlias<"mvn $Wd, $Wm$sh",
933 (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh), 2>;
934 def : InstAlias<"mvn $Xd, $Xm$sh",
935 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh), 2>;
937 def : InstAlias<"tst $src1, $src2",
938 (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2), 2>;
939 def : InstAlias<"tst $src1, $src2",
940 (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2), 2>;
942 def : InstAlias<"tst $src1, $src2",
943 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0), 3>;
944 def : InstAlias<"tst $src1, $src2",
945 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0), 3>;
947 def : InstAlias<"tst $src1, $src2$sh",
948 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh), 2>;
949 def : InstAlias<"tst $src1, $src2$sh",
950 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh), 2>;
953 def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>;
954 def : Pat<(not GPR64:$Xm), (ORNXrr XZR, GPR64:$Xm)>;
957 //===----------------------------------------------------------------------===//
958 // One operand data processing instructions.
959 //===----------------------------------------------------------------------===//
961 defm CLS : OneOperandData<0b101, "cls">;
962 defm CLZ : OneOperandData<0b100, "clz", ctlz>;
963 defm RBIT : OneOperandData<0b000, "rbit", bitreverse>;
965 def REV16Wr : OneWRegData<0b001, "rev16",
966 UnOpFrag<(rotr (bswap node:$LHS), (i64 16))>>;
967 def REV16Xr : OneXRegData<0b001, "rev16", null_frag>;
969 def : Pat<(cttz GPR32:$Rn),
970 (CLZWr (RBITWr GPR32:$Rn))>;
971 def : Pat<(cttz GPR64:$Rn),
972 (CLZXr (RBITXr GPR64:$Rn))>;
973 def : Pat<(ctlz (or (shl (xor (sra GPR32:$Rn, (i64 31)), GPR32:$Rn), (i64 1)),
976 def : Pat<(ctlz (or (shl (xor (sra GPR64:$Rn, (i64 63)), GPR64:$Rn), (i64 1)),
980 // Unlike the other one operand instructions, the instructions with the "rev"
981 // mnemonic do *not* just different in the size bit, but actually use different
982 // opcode bits for the different sizes.
983 def REVWr : OneWRegData<0b010, "rev", bswap>;
984 def REVXr : OneXRegData<0b011, "rev", bswap>;
985 def REV32Xr : OneXRegData<0b010, "rev32",
986 UnOpFrag<(rotr (bswap node:$LHS), (i64 32))>>;
988 def : InstAlias<"rev64 $Rd, $Rn", (REVXr GPR64:$Rd, GPR64:$Rn), 0>;
990 // The bswap commutes with the rotr so we want a pattern for both possible
992 def : Pat<(bswap (rotr GPR32:$Rn, (i64 16))), (REV16Wr GPR32:$Rn)>;
993 def : Pat<(bswap (rotr GPR64:$Rn, (i64 32))), (REV32Xr GPR64:$Rn)>;
995 //===----------------------------------------------------------------------===//
996 // Bitfield immediate extraction instruction.
997 //===----------------------------------------------------------------------===//
998 let hasSideEffects = 0 in
999 defm EXTR : ExtractImm<"extr">;
1000 def : InstAlias<"ror $dst, $src, $shift",
1001 (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift)>;
1002 def : InstAlias<"ror $dst, $src, $shift",
1003 (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift)>;
1005 def : Pat<(rotr GPR32:$Rn, (i64 imm0_31:$imm)),
1006 (EXTRWrri GPR32:$Rn, GPR32:$Rn, imm0_31:$imm)>;
1007 def : Pat<(rotr GPR64:$Rn, (i64 imm0_63:$imm)),
1008 (EXTRXrri GPR64:$Rn, GPR64:$Rn, imm0_63:$imm)>;
1010 //===----------------------------------------------------------------------===//
1011 // Other bitfield immediate instructions.
1012 //===----------------------------------------------------------------------===//
1013 let hasSideEffects = 0 in {
1014 defm BFM : BitfieldImmWith2RegArgs<0b01, "bfm">;
1015 defm SBFM : BitfieldImm<0b00, "sbfm">;
1016 defm UBFM : BitfieldImm<0b10, "ubfm">;
1019 def i32shift_a : Operand<i64>, SDNodeXForm<imm, [{
1020 uint64_t enc = (32 - N->getZExtValue()) & 0x1f;
1021 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
1024 def i32shift_b : Operand<i64>, SDNodeXForm<imm, [{
1025 uint64_t enc = 31 - N->getZExtValue();
1026 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
1029 // min(7, 31 - shift_amt)
1030 def i32shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
1031 uint64_t enc = 31 - N->getZExtValue();
1032 enc = enc > 7 ? 7 : enc;
1033 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
1036 // min(15, 31 - shift_amt)
1037 def i32shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
1038 uint64_t enc = 31 - N->getZExtValue();
1039 enc = enc > 15 ? 15 : enc;
1040 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
1043 def i64shift_a : Operand<i64>, SDNodeXForm<imm, [{
1044 uint64_t enc = (64 - N->getZExtValue()) & 0x3f;
1045 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
1048 def i64shift_b : Operand<i64>, SDNodeXForm<imm, [{
1049 uint64_t enc = 63 - N->getZExtValue();
1050 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
1053 // min(7, 63 - shift_amt)
1054 def i64shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
1055 uint64_t enc = 63 - N->getZExtValue();
1056 enc = enc > 7 ? 7 : enc;
1057 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
1060 // min(15, 63 - shift_amt)
1061 def i64shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
1062 uint64_t enc = 63 - N->getZExtValue();
1063 enc = enc > 15 ? 15 : enc;
1064 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
1067 // min(31, 63 - shift_amt)
1068 def i64shift_sext_i32 : Operand<i64>, SDNodeXForm<imm, [{
1069 uint64_t enc = 63 - N->getZExtValue();
1070 enc = enc > 31 ? 31 : enc;
1071 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
1074 def : Pat<(shl GPR32:$Rn, (i64 imm0_31:$imm)),
1075 (UBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
1076 (i64 (i32shift_b imm0_31:$imm)))>;
1077 def : Pat<(shl GPR64:$Rn, (i64 imm0_63:$imm)),
1078 (UBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
1079 (i64 (i64shift_b imm0_63:$imm)))>;
1081 let AddedComplexity = 10 in {
1082 def : Pat<(sra GPR32:$Rn, (i64 imm0_31:$imm)),
1083 (SBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
1084 def : Pat<(sra GPR64:$Rn, (i64 imm0_63:$imm)),
1085 (SBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
1088 def : InstAlias<"asr $dst, $src, $shift",
1089 (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
1090 def : InstAlias<"asr $dst, $src, $shift",
1091 (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
1092 def : InstAlias<"sxtb $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
1093 def : InstAlias<"sxtb $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
1094 def : InstAlias<"sxth $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
1095 def : InstAlias<"sxth $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
1096 def : InstAlias<"sxtw $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
1098 def : Pat<(srl GPR32:$Rn, (i64 imm0_31:$imm)),
1099 (UBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
1100 def : Pat<(srl GPR64:$Rn, (i64 imm0_63:$imm)),
1101 (UBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
1103 def : InstAlias<"lsr $dst, $src, $shift",
1104 (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
1105 def : InstAlias<"lsr $dst, $src, $shift",
1106 (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
1107 def : InstAlias<"uxtb $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
1108 def : InstAlias<"uxtb $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
1109 def : InstAlias<"uxth $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
1110 def : InstAlias<"uxth $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
1111 def : InstAlias<"uxtw $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
1113 //===----------------------------------------------------------------------===//
1114 // Conditional comparison instructions.
1115 //===----------------------------------------------------------------------===//
1116 defm CCMN : CondComparison<0, "ccmn", AArch64ccmn>;
1117 defm CCMP : CondComparison<1, "ccmp", AArch64ccmp>;
1119 //===----------------------------------------------------------------------===//
1120 // Conditional select instructions.
1121 //===----------------------------------------------------------------------===//
1122 defm CSEL : CondSelect<0, 0b00, "csel">;
1124 def inc : PatFrag<(ops node:$in), (add node:$in, 1)>;
1125 defm CSINC : CondSelectOp<0, 0b01, "csinc", inc>;
1126 defm CSINV : CondSelectOp<1, 0b00, "csinv", not>;
1127 defm CSNEG : CondSelectOp<1, 0b01, "csneg", ineg>;
1129 def : Pat<(AArch64csinv GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
1130 (CSINVWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
1131 def : Pat<(AArch64csinv GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
1132 (CSINVXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
1133 def : Pat<(AArch64csneg GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
1134 (CSNEGWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
1135 def : Pat<(AArch64csneg GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
1136 (CSNEGXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
1137 def : Pat<(AArch64csinc GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
1138 (CSINCWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
1139 def : Pat<(AArch64csinc GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
1140 (CSINCXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
1142 def : Pat<(AArch64csel (i32 0), (i32 1), (i32 imm:$cc), NZCV),
1143 (CSINCWr WZR, WZR, (i32 imm:$cc))>;
1144 def : Pat<(AArch64csel (i64 0), (i64 1), (i32 imm:$cc), NZCV),
1145 (CSINCXr XZR, XZR, (i32 imm:$cc))>;
1146 def : Pat<(AArch64csel GPR32:$tval, (i32 1), (i32 imm:$cc), NZCV),
1147 (CSINCWr GPR32:$tval, WZR, (i32 imm:$cc))>;
1148 def : Pat<(AArch64csel GPR64:$tval, (i64 1), (i32 imm:$cc), NZCV),
1149 (CSINCXr GPR64:$tval, XZR, (i32 imm:$cc))>;
1150 def : Pat<(AArch64csel (i32 1), GPR32:$fval, (i32 imm:$cc), NZCV),
1151 (CSINCWr GPR32:$fval, WZR, (i32 (inv_cond_XFORM imm:$cc)))>;
1152 def : Pat<(AArch64csel (i64 1), GPR64:$fval, (i32 imm:$cc), NZCV),
1153 (CSINCXr GPR64:$fval, XZR, (i32 (inv_cond_XFORM imm:$cc)))>;
1154 def : Pat<(AArch64csel (i32 0), (i32 -1), (i32 imm:$cc), NZCV),
1155 (CSINVWr WZR, WZR, (i32 imm:$cc))>;
1156 def : Pat<(AArch64csel (i64 0), (i64 -1), (i32 imm:$cc), NZCV),
1157 (CSINVXr XZR, XZR, (i32 imm:$cc))>;
1158 def : Pat<(AArch64csel GPR32:$tval, (i32 -1), (i32 imm:$cc), NZCV),
1159 (CSINVWr GPR32:$tval, WZR, (i32 imm:$cc))>;
1160 def : Pat<(AArch64csel GPR64:$tval, (i64 -1), (i32 imm:$cc), NZCV),
1161 (CSINVXr GPR64:$tval, XZR, (i32 imm:$cc))>;
1162 def : Pat<(AArch64csel (i32 -1), GPR32:$fval, (i32 imm:$cc), NZCV),
1163 (CSINVWr GPR32:$fval, WZR, (i32 (inv_cond_XFORM imm:$cc)))>;
1164 def : Pat<(AArch64csel (i64 -1), GPR64:$fval, (i32 imm:$cc), NZCV),
1165 (CSINVXr GPR64:$fval, XZR, (i32 (inv_cond_XFORM imm:$cc)))>;
1167 // The inverse of the condition code from the alias instruction is what is used
1168 // in the aliased instruction. The parser all ready inverts the condition code
1169 // for these aliases.
1170 def : InstAlias<"cset $dst, $cc",
1171 (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
1172 def : InstAlias<"cset $dst, $cc",
1173 (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
1175 def : InstAlias<"csetm $dst, $cc",
1176 (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
1177 def : InstAlias<"csetm $dst, $cc",
1178 (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
1180 def : InstAlias<"cinc $dst, $src, $cc",
1181 (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
1182 def : InstAlias<"cinc $dst, $src, $cc",
1183 (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
1185 def : InstAlias<"cinv $dst, $src, $cc",
1186 (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
1187 def : InstAlias<"cinv $dst, $src, $cc",
1188 (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
1190 def : InstAlias<"cneg $dst, $src, $cc",
1191 (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
1192 def : InstAlias<"cneg $dst, $src, $cc",
1193 (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
1195 //===----------------------------------------------------------------------===//
1196 // PC-relative instructions.
1197 //===----------------------------------------------------------------------===//
1198 let isReMaterializable = 1 in {
1199 let hasSideEffects = 0, mayStore = 0, mayLoad = 0 in {
1200 def ADR : ADRI<0, "adr", adrlabel, []>;
1201 } // hasSideEffects = 0
1203 def ADRP : ADRI<1, "adrp", adrplabel,
1204 [(set GPR64:$Xd, (AArch64adrp tglobaladdr:$label))]>;
1205 } // isReMaterializable = 1
1207 // page address of a constant pool entry, block address
1208 def : Pat<(AArch64adrp tconstpool:$cp), (ADRP tconstpool:$cp)>;
1209 def : Pat<(AArch64adrp tblockaddress:$cp), (ADRP tblockaddress:$cp)>;
1211 //===----------------------------------------------------------------------===//
1212 // Unconditional branch (register) instructions.
1213 //===----------------------------------------------------------------------===//
1215 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1216 def RET : BranchReg<0b0010, "ret", []>;
1217 def DRPS : SpecialReturn<0b0101, "drps">;
1218 def ERET : SpecialReturn<0b0100, "eret">;
1219 } // isReturn = 1, isTerminator = 1, isBarrier = 1
1221 // Default to the LR register.
1222 def : InstAlias<"ret", (RET LR)>;
1224 let isCall = 1, Defs = [LR], Uses = [SP] in {
1225 def BLR : BranchReg<0b0001, "blr", [(AArch64call GPR64:$Rn)]>;
1228 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1229 def BR : BranchReg<0b0000, "br", [(brind GPR64:$Rn)]>;
1230 } // isBranch, isTerminator, isBarrier, isIndirectBranch
1232 // Create a separate pseudo-instruction for codegen to use so that we don't
1233 // flag lr as used in every function. It'll be restored before the RET by the
1234 // epilogue if it's legitimately used.
1235 def RET_ReallyLR : Pseudo<(outs), (ins), [(AArch64retflag)]>,
1236 Sched<[WriteBrReg]> {
1237 let isTerminator = 1;
1242 // This is a directive-like pseudo-instruction. The purpose is to insert an
1243 // R_AARCH64_TLSDESC_CALL relocation at the offset of the following instruction
1244 // (which in the usual case is a BLR).
1245 let hasSideEffects = 1 in
1246 def TLSDESCCALL : Pseudo<(outs), (ins i64imm:$sym), []>, Sched<[]> {
1247 let AsmString = ".tlsdesccall $sym";
1250 // FIXME: maybe the scratch register used shouldn't be fixed to X1?
1251 // FIXME: can "hasSideEffects be dropped?
1252 let isCall = 1, Defs = [LR, X0, X1], hasSideEffects = 1,
1253 isCodeGenOnly = 1 in
1255 : Pseudo<(outs), (ins i64imm:$sym),
1256 [(AArch64tlsdesc_callseq tglobaltlsaddr:$sym)]>,
1257 Sched<[WriteI, WriteLD, WriteI, WriteBrReg]>;
1258 def : Pat<(AArch64tlsdesc_callseq texternalsym:$sym),
1259 (TLSDESC_CALLSEQ texternalsym:$sym)>;
1261 //===----------------------------------------------------------------------===//
1262 // Conditional branch (immediate) instruction.
1263 //===----------------------------------------------------------------------===//
1264 def Bcc : BranchCond;
1266 //===----------------------------------------------------------------------===//
1267 // Compare-and-branch instructions.
1268 //===----------------------------------------------------------------------===//
1269 defm CBZ : CmpBranch<0, "cbz", AArch64cbz>;
1270 defm CBNZ : CmpBranch<1, "cbnz", AArch64cbnz>;
1272 //===----------------------------------------------------------------------===//
1273 // Test-bit-and-branch instructions.
1274 //===----------------------------------------------------------------------===//
1275 defm TBZ : TestBranch<0, "tbz", AArch64tbz>;
1276 defm TBNZ : TestBranch<1, "tbnz", AArch64tbnz>;
1278 //===----------------------------------------------------------------------===//
1279 // Unconditional branch (immediate) instructions.
1280 //===----------------------------------------------------------------------===//
1281 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
1282 def B : BranchImm<0, "b", [(br bb:$addr)]>;
1283 } // isBranch, isTerminator, isBarrier
1285 let isCall = 1, Defs = [LR], Uses = [SP] in {
1286 def BL : CallImm<1, "bl", [(AArch64call tglobaladdr:$addr)]>;
1288 def : Pat<(AArch64call texternalsym:$func), (BL texternalsym:$func)>;
1290 //===----------------------------------------------------------------------===//
1291 // Exception generation instructions.
1292 //===----------------------------------------------------------------------===//
1293 def BRK : ExceptionGeneration<0b001, 0b00, "brk">;
1294 def DCPS1 : ExceptionGeneration<0b101, 0b01, "dcps1">;
1295 def DCPS2 : ExceptionGeneration<0b101, 0b10, "dcps2">;
1296 def DCPS3 : ExceptionGeneration<0b101, 0b11, "dcps3">;
1297 def HLT : ExceptionGeneration<0b010, 0b00, "hlt">;
1298 def HVC : ExceptionGeneration<0b000, 0b10, "hvc">;
1299 def SMC : ExceptionGeneration<0b000, 0b11, "smc">;
1300 def SVC : ExceptionGeneration<0b000, 0b01, "svc">;
1302 // DCPSn defaults to an immediate operand of zero if unspecified.
1303 def : InstAlias<"dcps1", (DCPS1 0)>;
1304 def : InstAlias<"dcps2", (DCPS2 0)>;
1305 def : InstAlias<"dcps3", (DCPS3 0)>;
1307 //===----------------------------------------------------------------------===//
1308 // Load instructions.
1309 //===----------------------------------------------------------------------===//
1311 // Pair (indexed, offset)
1312 defm LDPW : LoadPairOffset<0b00, 0, GPR32, simm7s4, "ldp">;
1313 defm LDPX : LoadPairOffset<0b10, 0, GPR64, simm7s8, "ldp">;
1314 defm LDPS : LoadPairOffset<0b00, 1, FPR32, simm7s4, "ldp">;
1315 defm LDPD : LoadPairOffset<0b01, 1, FPR64, simm7s8, "ldp">;
1316 defm LDPQ : LoadPairOffset<0b10, 1, FPR128, simm7s16, "ldp">;
1318 defm LDPSW : LoadPairOffset<0b01, 0, GPR64, simm7s4, "ldpsw">;
1320 // Pair (pre-indexed)
1321 def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1322 def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1323 def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1324 def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1325 def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1327 def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1329 // Pair (post-indexed)
1330 def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1331 def LDPXpost : LoadPairPostIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1332 def LDPSpost : LoadPairPostIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1333 def LDPDpost : LoadPairPostIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1334 def LDPQpost : LoadPairPostIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1336 def LDPSWpost : LoadPairPostIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1339 // Pair (no allocate)
1340 defm LDNPW : LoadPairNoAlloc<0b00, 0, GPR32, simm7s4, "ldnp">;
1341 defm LDNPX : LoadPairNoAlloc<0b10, 0, GPR64, simm7s8, "ldnp">;
1342 defm LDNPS : LoadPairNoAlloc<0b00, 1, FPR32, simm7s4, "ldnp">;
1343 defm LDNPD : LoadPairNoAlloc<0b01, 1, FPR64, simm7s8, "ldnp">;
1344 defm LDNPQ : LoadPairNoAlloc<0b10, 1, FPR128, simm7s16, "ldnp">;
1347 // (register offset)
1351 defm LDRBB : Load8RO<0b00, 0, 0b01, GPR32, "ldrb", i32, zextloadi8>;
1352 defm LDRHH : Load16RO<0b01, 0, 0b01, GPR32, "ldrh", i32, zextloadi16>;
1353 defm LDRW : Load32RO<0b10, 0, 0b01, GPR32, "ldr", i32, load>;
1354 defm LDRX : Load64RO<0b11, 0, 0b01, GPR64, "ldr", i64, load>;
1357 defm LDRB : Load8RO<0b00, 1, 0b01, FPR8, "ldr", untyped, load>;
1358 defm LDRH : Load16RO<0b01, 1, 0b01, FPR16, "ldr", f16, load>;
1359 defm LDRS : Load32RO<0b10, 1, 0b01, FPR32, "ldr", f32, load>;
1360 defm LDRD : Load64RO<0b11, 1, 0b01, FPR64, "ldr", f64, load>;
1361 defm LDRQ : Load128RO<0b00, 1, 0b11, FPR128, "ldr", f128, load>;
1363 // Load sign-extended half-word
1364 defm LDRSHW : Load16RO<0b01, 0, 0b11, GPR32, "ldrsh", i32, sextloadi16>;
1365 defm LDRSHX : Load16RO<0b01, 0, 0b10, GPR64, "ldrsh", i64, sextloadi16>;
1367 // Load sign-extended byte
1368 defm LDRSBW : Load8RO<0b00, 0, 0b11, GPR32, "ldrsb", i32, sextloadi8>;
1369 defm LDRSBX : Load8RO<0b00, 0, 0b10, GPR64, "ldrsb", i64, sextloadi8>;
1371 // Load sign-extended word
1372 defm LDRSW : Load32RO<0b10, 0, 0b10, GPR64, "ldrsw", i64, sextloadi32>;
1375 defm PRFM : PrefetchRO<0b11, 0, 0b10, "prfm">;
1377 // For regular load, we do not have any alignment requirement.
1378 // Thus, it is safe to directly map the vector loads with interesting
1379 // addressing modes.
1380 // FIXME: We could do the same for bitconvert to floating point vectors.
1381 multiclass ScalToVecROLoadPat<ROAddrMode ro, SDPatternOperator loadop,
1382 ValueType ScalTy, ValueType VecTy,
1383 Instruction LOADW, Instruction LOADX,
1385 def : Pat<(VecTy (scalar_to_vector (ScalTy
1386 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset))))),
1387 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1388 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset),
1391 def : Pat<(VecTy (scalar_to_vector (ScalTy
1392 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset))))),
1393 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1394 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset),
1398 let AddedComplexity = 10 in {
1399 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v8i8, LDRBroW, LDRBroX, bsub>;
1400 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v16i8, LDRBroW, LDRBroX, bsub>;
1402 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v4i16, LDRHroW, LDRHroX, hsub>;
1403 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v8i16, LDRHroW, LDRHroX, hsub>;
1405 defm : ScalToVecROLoadPat<ro16, load, i32, v4f16, LDRHroW, LDRHroX, hsub>;
1406 defm : ScalToVecROLoadPat<ro16, load, i32, v8f16, LDRHroW, LDRHroX, hsub>;
1408 defm : ScalToVecROLoadPat<ro32, load, i32, v2i32, LDRSroW, LDRSroX, ssub>;
1409 defm : ScalToVecROLoadPat<ro32, load, i32, v4i32, LDRSroW, LDRSroX, ssub>;
1411 defm : ScalToVecROLoadPat<ro32, load, f32, v2f32, LDRSroW, LDRSroX, ssub>;
1412 defm : ScalToVecROLoadPat<ro32, load, f32, v4f32, LDRSroW, LDRSroX, ssub>;
1414 defm : ScalToVecROLoadPat<ro64, load, i64, v2i64, LDRDroW, LDRDroX, dsub>;
1416 defm : ScalToVecROLoadPat<ro64, load, f64, v2f64, LDRDroW, LDRDroX, dsub>;
1419 def : Pat <(v1i64 (scalar_to_vector (i64
1420 (load (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
1421 ro_Wextend64:$extend))))),
1422 (LDRDroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend)>;
1424 def : Pat <(v1i64 (scalar_to_vector (i64
1425 (load (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
1426 ro_Xextend64:$extend))))),
1427 (LDRDroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend)>;
1430 // Match all load 64 bits width whose type is compatible with FPR64
1431 multiclass VecROLoadPat<ROAddrMode ro, ValueType VecTy,
1432 Instruction LOADW, Instruction LOADX> {
1434 def : Pat<(VecTy (load (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1435 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1437 def : Pat<(VecTy (load (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1438 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1441 let AddedComplexity = 10 in {
1442 let Predicates = [IsLE] in {
1443 // We must do vector loads with LD1 in big-endian.
1444 defm : VecROLoadPat<ro64, v2i32, LDRDroW, LDRDroX>;
1445 defm : VecROLoadPat<ro64, v2f32, LDRDroW, LDRDroX>;
1446 defm : VecROLoadPat<ro64, v8i8, LDRDroW, LDRDroX>;
1447 defm : VecROLoadPat<ro64, v4i16, LDRDroW, LDRDroX>;
1448 defm : VecROLoadPat<ro64, v4f16, LDRDroW, LDRDroX>;
1451 defm : VecROLoadPat<ro64, v1i64, LDRDroW, LDRDroX>;
1452 defm : VecROLoadPat<ro64, v1f64, LDRDroW, LDRDroX>;
1454 // Match all load 128 bits width whose type is compatible with FPR128
1455 let Predicates = [IsLE] in {
1456 // We must do vector loads with LD1 in big-endian.
1457 defm : VecROLoadPat<ro128, v2i64, LDRQroW, LDRQroX>;
1458 defm : VecROLoadPat<ro128, v2f64, LDRQroW, LDRQroX>;
1459 defm : VecROLoadPat<ro128, v4i32, LDRQroW, LDRQroX>;
1460 defm : VecROLoadPat<ro128, v4f32, LDRQroW, LDRQroX>;
1461 defm : VecROLoadPat<ro128, v8i16, LDRQroW, LDRQroX>;
1462 defm : VecROLoadPat<ro128, v8f16, LDRQroW, LDRQroX>;
1463 defm : VecROLoadPat<ro128, v16i8, LDRQroW, LDRQroX>;
1465 } // AddedComplexity = 10
1468 multiclass ExtLoadTo64ROPat<ROAddrMode ro, SDPatternOperator loadop,
1469 Instruction INSTW, Instruction INSTX> {
1470 def : Pat<(i64 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1471 (SUBREG_TO_REG (i64 0),
1472 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend),
1475 def : Pat<(i64 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1476 (SUBREG_TO_REG (i64 0),
1477 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend),
1481 let AddedComplexity = 10 in {
1482 defm : ExtLoadTo64ROPat<ro8, zextloadi8, LDRBBroW, LDRBBroX>;
1483 defm : ExtLoadTo64ROPat<ro16, zextloadi16, LDRHHroW, LDRHHroX>;
1484 defm : ExtLoadTo64ROPat<ro32, zextloadi32, LDRWroW, LDRWroX>;
1486 // zextloadi1 -> zextloadi8
1487 defm : ExtLoadTo64ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>;
1489 // extload -> zextload
1490 defm : ExtLoadTo64ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>;
1491 defm : ExtLoadTo64ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>;
1492 defm : ExtLoadTo64ROPat<ro32, extloadi32, LDRWroW, LDRWroX>;
1494 // extloadi1 -> zextloadi8
1495 defm : ExtLoadTo64ROPat<ro8, extloadi1, LDRBBroW, LDRBBroX>;
1500 multiclass ExtLoadTo32ROPat<ROAddrMode ro, SDPatternOperator loadop,
1501 Instruction INSTW, Instruction INSTX> {
1502 def : Pat<(i32 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1503 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1505 def : Pat<(i32 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1506 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1510 let AddedComplexity = 10 in {
1511 // extload -> zextload
1512 defm : ExtLoadTo32ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>;
1513 defm : ExtLoadTo32ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>;
1514 defm : ExtLoadTo32ROPat<ro32, extloadi32, LDRWroW, LDRWroX>;
1516 // zextloadi1 -> zextloadi8
1517 defm : ExtLoadTo32ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>;
1521 // (unsigned immediate)
1523 defm LDRX : LoadUI<0b11, 0, 0b01, GPR64, uimm12s8, "ldr",
1525 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>;
1526 defm LDRW : LoadUI<0b10, 0, 0b01, GPR32, uimm12s4, "ldr",
1528 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;
1529 defm LDRB : LoadUI<0b00, 1, 0b01, FPR8, uimm12s1, "ldr",
1531 (load (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)))]>;
1532 defm LDRH : LoadUI<0b01, 1, 0b01, FPR16, uimm12s2, "ldr",
1533 [(set (f16 FPR16:$Rt),
1534 (load (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)))]>;
1535 defm LDRS : LoadUI<0b10, 1, 0b01, FPR32, uimm12s4, "ldr",
1536 [(set (f32 FPR32:$Rt),
1537 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;
1538 defm LDRD : LoadUI<0b11, 1, 0b01, FPR64, uimm12s8, "ldr",
1539 [(set (f64 FPR64:$Rt),
1540 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>;
1541 defm LDRQ : LoadUI<0b00, 1, 0b11, FPR128, uimm12s16, "ldr",
1542 [(set (f128 FPR128:$Rt),
1543 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)))]>;
1545 // For regular load, we do not have any alignment requirement.
1546 // Thus, it is safe to directly map the vector loads with interesting
1547 // addressing modes.
1548 // FIXME: We could do the same for bitconvert to floating point vectors.
1549 def : Pat <(v8i8 (scalar_to_vector (i32
1550 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
1551 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
1552 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>;
1553 def : Pat <(v16i8 (scalar_to_vector (i32
1554 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
1555 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1556 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>;
1557 def : Pat <(v4i16 (scalar_to_vector (i32
1558 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
1559 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
1560 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1561 def : Pat <(v8i16 (scalar_to_vector (i32
1562 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
1563 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1564 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1565 def : Pat <(v2i32 (scalar_to_vector (i32
1566 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
1567 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1568 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
1569 def : Pat <(v4i32 (scalar_to_vector (i32
1570 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
1571 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1572 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
1573 def : Pat <(v1i64 (scalar_to_vector (i64
1574 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))),
1575 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1576 def : Pat <(v2i64 (scalar_to_vector (i64
1577 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))),
1578 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
1579 (LDRDui GPR64sp:$Rn, uimm12s8:$offset), dsub)>;
1581 // Match all load 64 bits width whose type is compatible with FPR64
1582 let Predicates = [IsLE] in {
1583 // We must use LD1 to perform vector loads in big-endian.
1584 def : Pat<(v2f32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1585 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1586 def : Pat<(v8i8 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1587 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1588 def : Pat<(v4i16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1589 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1590 def : Pat<(v2i32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1591 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1592 def : Pat<(v4f16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1593 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1595 def : Pat<(v1f64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1596 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1597 def : Pat<(v1i64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1598 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1600 // Match all load 128 bits width whose type is compatible with FPR128
1601 let Predicates = [IsLE] in {
1602 // We must use LD1 to perform vector loads in big-endian.
1603 def : Pat<(v4f32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1604 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1605 def : Pat<(v2f64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1606 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1607 def : Pat<(v16i8 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1608 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1609 def : Pat<(v8i16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1610 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1611 def : Pat<(v4i32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1612 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1613 def : Pat<(v2i64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1614 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1615 def : Pat<(v8f16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1616 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1618 def : Pat<(f128 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1619 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1621 defm LDRHH : LoadUI<0b01, 0, 0b01, GPR32, uimm12s2, "ldrh",
1623 (zextloadi16 (am_indexed16 GPR64sp:$Rn,
1624 uimm12s2:$offset)))]>;
1625 defm LDRBB : LoadUI<0b00, 0, 0b01, GPR32, uimm12s1, "ldrb",
1627 (zextloadi8 (am_indexed8 GPR64sp:$Rn,
1628 uimm12s1:$offset)))]>;
1630 def : Pat<(i64 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1631 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1632 def : Pat<(i64 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1633 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1635 // zextloadi1 -> zextloadi8
1636 def : Pat<(i32 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1637 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1638 def : Pat<(i64 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1639 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1641 // extload -> zextload
1642 def : Pat<(i32 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1643 (LDRHHui GPR64sp:$Rn, uimm12s2:$offset)>;
1644 def : Pat<(i32 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1645 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1646 def : Pat<(i32 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1647 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1648 def : Pat<(i64 (extloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))),
1649 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;
1650 def : Pat<(i64 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1651 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1652 def : Pat<(i64 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1653 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1654 def : Pat<(i64 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1655 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1657 // load sign-extended half-word
1658 defm LDRSHW : LoadUI<0b01, 0, 0b11, GPR32, uimm12s2, "ldrsh",
1660 (sextloadi16 (am_indexed16 GPR64sp:$Rn,
1661 uimm12s2:$offset)))]>;
1662 defm LDRSHX : LoadUI<0b01, 0, 0b10, GPR64, uimm12s2, "ldrsh",
1664 (sextloadi16 (am_indexed16 GPR64sp:$Rn,
1665 uimm12s2:$offset)))]>;
1667 // load sign-extended byte
1668 defm LDRSBW : LoadUI<0b00, 0, 0b11, GPR32, uimm12s1, "ldrsb",
1670 (sextloadi8 (am_indexed8 GPR64sp:$Rn,
1671 uimm12s1:$offset)))]>;
1672 defm LDRSBX : LoadUI<0b00, 0, 0b10, GPR64, uimm12s1, "ldrsb",
1674 (sextloadi8 (am_indexed8 GPR64sp:$Rn,
1675 uimm12s1:$offset)))]>;
1677 // load sign-extended word
1678 defm LDRSW : LoadUI<0b10, 0, 0b10, GPR64, uimm12s4, "ldrsw",
1680 (sextloadi32 (am_indexed32 GPR64sp:$Rn,
1681 uimm12s4:$offset)))]>;
1683 // load zero-extended word
1684 def : Pat<(i64 (zextloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))),
1685 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;
1688 def PRFMui : PrefetchUI<0b11, 0, 0b10, "prfm",
1689 [(AArch64Prefetch imm:$Rt,
1690 (am_indexed64 GPR64sp:$Rn,
1691 uimm12s8:$offset))]>;
1693 def : InstAlias<"prfm $Rt, [$Rn]", (PRFMui prfop:$Rt, GPR64sp:$Rn, 0)>;
1697 def LDRWl : LoadLiteral<0b00, 0, GPR32, "ldr">;
1698 def LDRXl : LoadLiteral<0b01, 0, GPR64, "ldr">;
1699 def LDRSl : LoadLiteral<0b00, 1, FPR32, "ldr">;
1700 def LDRDl : LoadLiteral<0b01, 1, FPR64, "ldr">;
1701 def LDRQl : LoadLiteral<0b10, 1, FPR128, "ldr">;
1703 // load sign-extended word
1704 def LDRSWl : LoadLiteral<0b10, 0, GPR64, "ldrsw">;
1707 def PRFMl : PrefetchLiteral<0b11, 0, "prfm", []>;
1708 // [(AArch64Prefetch imm:$Rt, tglobaladdr:$label)]>;
1711 // (unscaled immediate)
1712 defm LDURX : LoadUnscaled<0b11, 0, 0b01, GPR64, "ldur",
1714 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;
1715 defm LDURW : LoadUnscaled<0b10, 0, 0b01, GPR32, "ldur",
1717 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1718 defm LDURB : LoadUnscaled<0b00, 1, 0b01, FPR8, "ldur",
1720 (load (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1721 defm LDURH : LoadUnscaled<0b01, 1, 0b01, FPR16, "ldur",
1723 (load (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1724 defm LDURS : LoadUnscaled<0b10, 1, 0b01, FPR32, "ldur",
1725 [(set (f32 FPR32:$Rt),
1726 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1727 defm LDURD : LoadUnscaled<0b11, 1, 0b01, FPR64, "ldur",
1728 [(set (f64 FPR64:$Rt),
1729 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;
1730 defm LDURQ : LoadUnscaled<0b00, 1, 0b11, FPR128, "ldur",
1731 [(set (f128 FPR128:$Rt),
1732 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset)))]>;
1735 : LoadUnscaled<0b01, 0, 0b01, GPR32, "ldurh",
1737 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1739 : LoadUnscaled<0b00, 0, 0b01, GPR32, "ldurb",
1741 (zextloadi8 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1743 // Match all load 64 bits width whose type is compatible with FPR64
1744 let Predicates = [IsLE] in {
1745 def : Pat<(v2f32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1746 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1747 def : Pat<(v2i32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1748 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1749 def : Pat<(v4i16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1750 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1751 def : Pat<(v8i8 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1752 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1753 def : Pat<(v4f16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1754 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1756 def : Pat<(v1f64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1757 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1758 def : Pat<(v1i64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1759 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1761 // Match all load 128 bits width whose type is compatible with FPR128
1762 let Predicates = [IsLE] in {
1763 def : Pat<(v2f64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1764 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1765 def : Pat<(v2i64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1766 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1767 def : Pat<(v4f32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1768 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1769 def : Pat<(v4i32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1770 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1771 def : Pat<(v8i16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1772 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1773 def : Pat<(v16i8 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1774 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1775 def : Pat<(v8f16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1776 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1780 def : Pat<(i32 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1781 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
1782 def : Pat<(i32 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1783 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1784 def : Pat<(i32 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1785 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1786 def : Pat<(i64 (extloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))),
1787 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1788 def : Pat<(i64 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1789 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1790 def : Pat<(i64 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1791 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1792 def : Pat<(i64 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1793 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1795 def : Pat<(i32 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1796 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
1797 def : Pat<(i32 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1798 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1799 def : Pat<(i32 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1800 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1801 def : Pat<(i64 (zextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))),
1802 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1803 def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1804 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1805 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1806 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1807 def : Pat<(i64 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1808 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1812 // LDR mnemonics fall back to LDUR for negative or unaligned offsets.
1814 // Define new assembler match classes as we want to only match these when
1815 // the don't otherwise match the scaled addressing mode for LDR/STR. Don't
1816 // associate a DiagnosticType either, as we want the diagnostic for the
1817 // canonical form (the scaled operand) to take precedence.
1818 class SImm9OffsetOperand<int Width> : AsmOperandClass {
1819 let Name = "SImm9OffsetFB" # Width;
1820 let PredicateMethod = "isSImm9OffsetFB<" # Width # ">";
1821 let RenderMethod = "addImmOperands";
1824 def SImm9OffsetFB8Operand : SImm9OffsetOperand<8>;
1825 def SImm9OffsetFB16Operand : SImm9OffsetOperand<16>;
1826 def SImm9OffsetFB32Operand : SImm9OffsetOperand<32>;
1827 def SImm9OffsetFB64Operand : SImm9OffsetOperand<64>;
1828 def SImm9OffsetFB128Operand : SImm9OffsetOperand<128>;
1830 def simm9_offset_fb8 : Operand<i64> {
1831 let ParserMatchClass = SImm9OffsetFB8Operand;
1833 def simm9_offset_fb16 : Operand<i64> {
1834 let ParserMatchClass = SImm9OffsetFB16Operand;
1836 def simm9_offset_fb32 : Operand<i64> {
1837 let ParserMatchClass = SImm9OffsetFB32Operand;
1839 def simm9_offset_fb64 : Operand<i64> {
1840 let ParserMatchClass = SImm9OffsetFB64Operand;
1842 def simm9_offset_fb128 : Operand<i64> {
1843 let ParserMatchClass = SImm9OffsetFB128Operand;
1846 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1847 (LDURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
1848 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1849 (LDURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1850 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1851 (LDURBi FPR8:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1852 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1853 (LDURHi FPR16:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1854 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1855 (LDURSi FPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1856 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1857 (LDURDi FPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
1858 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1859 (LDURQi FPR128:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;
1862 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1863 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1864 def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1865 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1867 // load sign-extended half-word
1869 : LoadUnscaled<0b01, 0, 0b11, GPR32, "ldursh",
1871 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1873 : LoadUnscaled<0b01, 0, 0b10, GPR64, "ldursh",
1875 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1877 // load sign-extended byte
1879 : LoadUnscaled<0b00, 0, 0b11, GPR32, "ldursb",
1881 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1883 : LoadUnscaled<0b00, 0, 0b10, GPR64, "ldursb",
1885 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1887 // load sign-extended word
1889 : LoadUnscaled<0b10, 0, 0b10, GPR64, "ldursw",
1891 (sextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1893 // zero and sign extending aliases from generic LDR* mnemonics to LDUR*.
1894 def : InstAlias<"ldrb $Rt, [$Rn, $offset]",
1895 (LDURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1896 def : InstAlias<"ldrh $Rt, [$Rn, $offset]",
1897 (LDURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1898 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",
1899 (LDURSBWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1900 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",
1901 (LDURSBXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1902 def : InstAlias<"ldrsh $Rt, [$Rn, $offset]",
1903 (LDURSHWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1904 def : InstAlias<"ldrsh $Rt, [$Rn, $offset]",
1905 (LDURSHXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1906 def : InstAlias<"ldrsw $Rt, [$Rn, $offset]",
1907 (LDURSWi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1910 defm PRFUM : PrefetchUnscaled<0b11, 0, 0b10, "prfum",
1911 [(AArch64Prefetch imm:$Rt,
1912 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
1915 // (unscaled immediate, unprivileged)
1916 defm LDTRX : LoadUnprivileged<0b11, 0, 0b01, GPR64, "ldtr">;
1917 defm LDTRW : LoadUnprivileged<0b10, 0, 0b01, GPR32, "ldtr">;
1919 defm LDTRH : LoadUnprivileged<0b01, 0, 0b01, GPR32, "ldtrh">;
1920 defm LDTRB : LoadUnprivileged<0b00, 0, 0b01, GPR32, "ldtrb">;
1922 // load sign-extended half-word
1923 defm LDTRSHW : LoadUnprivileged<0b01, 0, 0b11, GPR32, "ldtrsh">;
1924 defm LDTRSHX : LoadUnprivileged<0b01, 0, 0b10, GPR64, "ldtrsh">;
1926 // load sign-extended byte
1927 defm LDTRSBW : LoadUnprivileged<0b00, 0, 0b11, GPR32, "ldtrsb">;
1928 defm LDTRSBX : LoadUnprivileged<0b00, 0, 0b10, GPR64, "ldtrsb">;
1930 // load sign-extended word
1931 defm LDTRSW : LoadUnprivileged<0b10, 0, 0b10, GPR64, "ldtrsw">;
1934 // (immediate pre-indexed)
1935 def LDRWpre : LoadPreIdx<0b10, 0, 0b01, GPR32, "ldr">;
1936 def LDRXpre : LoadPreIdx<0b11, 0, 0b01, GPR64, "ldr">;
1937 def LDRBpre : LoadPreIdx<0b00, 1, 0b01, FPR8, "ldr">;
1938 def LDRHpre : LoadPreIdx<0b01, 1, 0b01, FPR16, "ldr">;
1939 def LDRSpre : LoadPreIdx<0b10, 1, 0b01, FPR32, "ldr">;
1940 def LDRDpre : LoadPreIdx<0b11, 1, 0b01, FPR64, "ldr">;
1941 def LDRQpre : LoadPreIdx<0b00, 1, 0b11, FPR128, "ldr">;
1943 // load sign-extended half-word
1944 def LDRSHWpre : LoadPreIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1945 def LDRSHXpre : LoadPreIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1947 // load sign-extended byte
1948 def LDRSBWpre : LoadPreIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1949 def LDRSBXpre : LoadPreIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1951 // load zero-extended byte
1952 def LDRBBpre : LoadPreIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1953 def LDRHHpre : LoadPreIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1955 // load sign-extended word
1956 def LDRSWpre : LoadPreIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1959 // (immediate post-indexed)
1960 def LDRWpost : LoadPostIdx<0b10, 0, 0b01, GPR32, "ldr">;
1961 def LDRXpost : LoadPostIdx<0b11, 0, 0b01, GPR64, "ldr">;
1962 def LDRBpost : LoadPostIdx<0b00, 1, 0b01, FPR8, "ldr">;
1963 def LDRHpost : LoadPostIdx<0b01, 1, 0b01, FPR16, "ldr">;
1964 def LDRSpost : LoadPostIdx<0b10, 1, 0b01, FPR32, "ldr">;
1965 def LDRDpost : LoadPostIdx<0b11, 1, 0b01, FPR64, "ldr">;
1966 def LDRQpost : LoadPostIdx<0b00, 1, 0b11, FPR128, "ldr">;
1968 // load sign-extended half-word
1969 def LDRSHWpost : LoadPostIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1970 def LDRSHXpost : LoadPostIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1972 // load sign-extended byte
1973 def LDRSBWpost : LoadPostIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1974 def LDRSBXpost : LoadPostIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1976 // load zero-extended byte
1977 def LDRBBpost : LoadPostIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1978 def LDRHHpost : LoadPostIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1980 // load sign-extended word
1981 def LDRSWpost : LoadPostIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1983 //===----------------------------------------------------------------------===//
1984 // Store instructions.
1985 //===----------------------------------------------------------------------===//
1987 // Pair (indexed, offset)
1988 // FIXME: Use dedicated range-checked addressing mode operand here.
1989 defm STPW : StorePairOffset<0b00, 0, GPR32, simm7s4, "stp">;
1990 defm STPX : StorePairOffset<0b10, 0, GPR64, simm7s8, "stp">;
1991 defm STPS : StorePairOffset<0b00, 1, FPR32, simm7s4, "stp">;
1992 defm STPD : StorePairOffset<0b01, 1, FPR64, simm7s8, "stp">;
1993 defm STPQ : StorePairOffset<0b10, 1, FPR128, simm7s16, "stp">;
1995 // Pair (pre-indexed)
1996 def STPWpre : StorePairPreIdx<0b00, 0, GPR32, simm7s4, "stp">;
1997 def STPXpre : StorePairPreIdx<0b10, 0, GPR64, simm7s8, "stp">;
1998 def STPSpre : StorePairPreIdx<0b00, 1, FPR32, simm7s4, "stp">;
1999 def STPDpre : StorePairPreIdx<0b01, 1, FPR64, simm7s8, "stp">;
2000 def STPQpre : StorePairPreIdx<0b10, 1, FPR128, simm7s16, "stp">;
2002 // Pair (pre-indexed)
2003 def STPWpost : StorePairPostIdx<0b00, 0, GPR32, simm7s4, "stp">;
2004 def STPXpost : StorePairPostIdx<0b10, 0, GPR64, simm7s8, "stp">;
2005 def STPSpost : StorePairPostIdx<0b00, 1, FPR32, simm7s4, "stp">;
2006 def STPDpost : StorePairPostIdx<0b01, 1, FPR64, simm7s8, "stp">;
2007 def STPQpost : StorePairPostIdx<0b10, 1, FPR128, simm7s16, "stp">;
2009 // Pair (no allocate)
2010 defm STNPW : StorePairNoAlloc<0b00, 0, GPR32, simm7s4, "stnp">;
2011 defm STNPX : StorePairNoAlloc<0b10, 0, GPR64, simm7s8, "stnp">;
2012 defm STNPS : StorePairNoAlloc<0b00, 1, FPR32, simm7s4, "stnp">;
2013 defm STNPD : StorePairNoAlloc<0b01, 1, FPR64, simm7s8, "stnp">;
2014 defm STNPQ : StorePairNoAlloc<0b10, 1, FPR128, simm7s16, "stnp">;
2017 // (Register offset)
2020 defm STRBB : Store8RO< 0b00, 0, 0b00, GPR32, "strb", i32, truncstorei8>;
2021 defm STRHH : Store16RO<0b01, 0, 0b00, GPR32, "strh", i32, truncstorei16>;
2022 defm STRW : Store32RO<0b10, 0, 0b00, GPR32, "str", i32, store>;
2023 defm STRX : Store64RO<0b11, 0, 0b00, GPR64, "str", i64, store>;
2027 defm STRB : Store8RO< 0b00, 1, 0b00, FPR8, "str", untyped, store>;
2028 defm STRH : Store16RO<0b01, 1, 0b00, FPR16, "str", f16, store>;
2029 defm STRS : Store32RO<0b10, 1, 0b00, FPR32, "str", f32, store>;
2030 defm STRD : Store64RO<0b11, 1, 0b00, FPR64, "str", f64, store>;
2031 defm STRQ : Store128RO<0b00, 1, 0b10, FPR128, "str", f128, store>;
2033 multiclass TruncStoreFrom64ROPat<ROAddrMode ro, SDPatternOperator storeop,
2034 Instruction STRW, Instruction STRX> {
2036 def : Pat<(storeop GPR64:$Rt,
2037 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
2038 (STRW (EXTRACT_SUBREG GPR64:$Rt, sub_32),
2039 GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
2041 def : Pat<(storeop GPR64:$Rt,
2042 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
2043 (STRX (EXTRACT_SUBREG GPR64:$Rt, sub_32),
2044 GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
2047 let AddedComplexity = 10 in {
2049 defm : TruncStoreFrom64ROPat<ro8, truncstorei8, STRBBroW, STRBBroX>;
2050 defm : TruncStoreFrom64ROPat<ro16, truncstorei16, STRHHroW, STRHHroX>;
2051 defm : TruncStoreFrom64ROPat<ro32, truncstorei32, STRWroW, STRWroX>;
2054 multiclass VecROStorePat<ROAddrMode ro, ValueType VecTy, RegisterClass FPR,
2055 Instruction STRW, Instruction STRX> {
2056 def : Pat<(store (VecTy FPR:$Rt),
2057 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
2058 (STRW FPR:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
2060 def : Pat<(store (VecTy FPR:$Rt),
2061 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
2062 (STRX FPR:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
2065 let AddedComplexity = 10 in {
2066 // Match all store 64 bits width whose type is compatible with FPR64
2067 let Predicates = [IsLE] in {
2068 // We must use ST1 to store vectors in big-endian.
2069 defm : VecROStorePat<ro64, v2i32, FPR64, STRDroW, STRDroX>;
2070 defm : VecROStorePat<ro64, v2f32, FPR64, STRDroW, STRDroX>;
2071 defm : VecROStorePat<ro64, v4i16, FPR64, STRDroW, STRDroX>;
2072 defm : VecROStorePat<ro64, v8i8, FPR64, STRDroW, STRDroX>;
2073 defm : VecROStorePat<ro64, v4f16, FPR64, STRDroW, STRDroX>;
2076 defm : VecROStorePat<ro64, v1i64, FPR64, STRDroW, STRDroX>;
2077 defm : VecROStorePat<ro64, v1f64, FPR64, STRDroW, STRDroX>;
2079 // Match all store 128 bits width whose type is compatible with FPR128
2080 let Predicates = [IsLE] in {
2081 // We must use ST1 to store vectors in big-endian.
2082 defm : VecROStorePat<ro128, v2i64, FPR128, STRQroW, STRQroX>;
2083 defm : VecROStorePat<ro128, v2f64, FPR128, STRQroW, STRQroX>;
2084 defm : VecROStorePat<ro128, v4i32, FPR128, STRQroW, STRQroX>;
2085 defm : VecROStorePat<ro128, v4f32, FPR128, STRQroW, STRQroX>;
2086 defm : VecROStorePat<ro128, v8i16, FPR128, STRQroW, STRQroX>;
2087 defm : VecROStorePat<ro128, v16i8, FPR128, STRQroW, STRQroX>;
2088 defm : VecROStorePat<ro128, v8f16, FPR128, STRQroW, STRQroX>;
2090 } // AddedComplexity = 10
2092 // Match stores from lane 0 to the appropriate subreg's store.
2093 multiclass VecROStoreLane0Pat<ROAddrMode ro, SDPatternOperator storeop,
2094 ValueType VecTy, ValueType STy,
2095 SubRegIndex SubRegIdx,
2096 Instruction STRW, Instruction STRX> {
2098 def : Pat<(storeop (STy (vector_extract (VecTy VecListOne128:$Vt), 0)),
2099 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
2100 (STRW (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx),
2101 GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
2103 def : Pat<(storeop (STy (vector_extract (VecTy VecListOne128:$Vt), 0)),
2104 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
2105 (STRX (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx),
2106 GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
2109 let AddedComplexity = 19 in {
2110 defm : VecROStoreLane0Pat<ro16, truncstorei16, v8i16, i32, hsub, STRHroW, STRHroX>;
2111 defm : VecROStoreLane0Pat<ro16, store , v8i16, i16, hsub, STRHroW, STRHroX>;
2112 defm : VecROStoreLane0Pat<ro32, truncstorei32, v4i32, i32, ssub, STRSroW, STRSroX>;
2113 defm : VecROStoreLane0Pat<ro32, store , v4i32, i32, ssub, STRSroW, STRSroX>;
2114 defm : VecROStoreLane0Pat<ro32, store , v4f32, f32, ssub, STRSroW, STRSroX>;
2115 defm : VecROStoreLane0Pat<ro64, store , v2i64, i64, dsub, STRDroW, STRDroX>;
2116 defm : VecROStoreLane0Pat<ro64, store , v2f64, f64, dsub, STRDroW, STRDroX>;
2120 // (unsigned immediate)
2121 defm STRX : StoreUI<0b11, 0, 0b00, GPR64, uimm12s8, "str",
2123 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>;
2124 defm STRW : StoreUI<0b10, 0, 0b00, GPR32, uimm12s4, "str",
2126 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>;
2127 defm STRB : StoreUI<0b00, 1, 0b00, FPR8, uimm12s1, "str",
2129 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))]>;
2130 defm STRH : StoreUI<0b01, 1, 0b00, FPR16, uimm12s2, "str",
2131 [(store (f16 FPR16:$Rt),
2132 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))]>;
2133 defm STRS : StoreUI<0b10, 1, 0b00, FPR32, uimm12s4, "str",
2134 [(store (f32 FPR32:$Rt),
2135 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>;
2136 defm STRD : StoreUI<0b11, 1, 0b00, FPR64, uimm12s8, "str",
2137 [(store (f64 FPR64:$Rt),
2138 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>;
2139 defm STRQ : StoreUI<0b00, 1, 0b10, FPR128, uimm12s16, "str", []>;
2141 defm STRHH : StoreUI<0b01, 0, 0b00, GPR32, uimm12s2, "strh",
2142 [(truncstorei16 GPR32:$Rt,
2143 (am_indexed16 GPR64sp:$Rn,
2144 uimm12s2:$offset))]>;
2145 defm STRBB : StoreUI<0b00, 0, 0b00, GPR32, uimm12s1, "strb",
2146 [(truncstorei8 GPR32:$Rt,
2147 (am_indexed8 GPR64sp:$Rn,
2148 uimm12s1:$offset))]>;
2150 // Match all store 64 bits width whose type is compatible with FPR64
2151 let AddedComplexity = 10 in {
2152 let Predicates = [IsLE] in {
2153 // We must use ST1 to store vectors in big-endian.
2154 def : Pat<(store (v2f32 FPR64:$Rt),
2155 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2156 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2157 def : Pat<(store (v8i8 FPR64:$Rt),
2158 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2159 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2160 def : Pat<(store (v4i16 FPR64:$Rt),
2161 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2162 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2163 def : Pat<(store (v2i32 FPR64:$Rt),
2164 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2165 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2166 def : Pat<(store (v4f16 FPR64:$Rt),
2167 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2168 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2170 def : Pat<(store (v1f64 FPR64:$Rt),
2171 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2172 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2173 def : Pat<(store (v1i64 FPR64:$Rt),
2174 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2175 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2177 // Match all store 128 bits width whose type is compatible with FPR128
2178 let Predicates = [IsLE] in {
2179 // We must use ST1 to store vectors in big-endian.
2180 def : Pat<(store (v4f32 FPR128:$Rt),
2181 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2182 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2183 def : Pat<(store (v2f64 FPR128:$Rt),
2184 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2185 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2186 def : Pat<(store (v16i8 FPR128:$Rt),
2187 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2188 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2189 def : Pat<(store (v8i16 FPR128:$Rt),
2190 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2191 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2192 def : Pat<(store (v4i32 FPR128:$Rt),
2193 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2194 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2195 def : Pat<(store (v2i64 FPR128:$Rt),
2196 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2197 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2198 def : Pat<(store (v8f16 FPR128:$Rt),
2199 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2200 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2202 def : Pat<(store (f128 FPR128:$Rt),
2203 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2204 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2207 def : Pat<(truncstorei32 GPR64:$Rt,
2208 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)),
2209 (STRWui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s4:$offset)>;
2210 def : Pat<(truncstorei16 GPR64:$Rt,
2211 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)),
2212 (STRHHui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s2:$offset)>;
2213 def : Pat<(truncstorei8 GPR64:$Rt, (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)),
2214 (STRBBui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s1:$offset)>;
2216 } // AddedComplexity = 10
2219 // (unscaled immediate)
2220 defm STURX : StoreUnscaled<0b11, 0, 0b00, GPR64, "stur",
2222 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
2223 defm STURW : StoreUnscaled<0b10, 0, 0b00, GPR32, "stur",
2225 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>;
2226 defm STURB : StoreUnscaled<0b00, 1, 0b00, FPR8, "stur",
2228 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
2229 defm STURH : StoreUnscaled<0b01, 1, 0b00, FPR16, "stur",
2230 [(store (f16 FPR16:$Rt),
2231 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>;
2232 defm STURS : StoreUnscaled<0b10, 1, 0b00, FPR32, "stur",
2233 [(store (f32 FPR32:$Rt),
2234 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>;
2235 defm STURD : StoreUnscaled<0b11, 1, 0b00, FPR64, "stur",
2236 [(store (f64 FPR64:$Rt),
2237 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
2238 defm STURQ : StoreUnscaled<0b00, 1, 0b10, FPR128, "stur",
2239 [(store (f128 FPR128:$Rt),
2240 (am_unscaled128 GPR64sp:$Rn, simm9:$offset))]>;
2241 defm STURHH : StoreUnscaled<0b01, 0, 0b00, GPR32, "sturh",
2242 [(truncstorei16 GPR32:$Rt,
2243 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>;
2244 defm STURBB : StoreUnscaled<0b00, 0, 0b00, GPR32, "sturb",
2245 [(truncstorei8 GPR32:$Rt,
2246 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
2248 // Match all store 64 bits width whose type is compatible with FPR64
2249 let Predicates = [IsLE] in {
2250 // We must use ST1 to store vectors in big-endian.
2251 def : Pat<(store (v2f32 FPR64:$Rt),
2252 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2253 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2254 def : Pat<(store (v8i8 FPR64:$Rt),
2255 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2256 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2257 def : Pat<(store (v4i16 FPR64:$Rt),
2258 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2259 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2260 def : Pat<(store (v2i32 FPR64:$Rt),
2261 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2262 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2263 def : Pat<(store (v4f16 FPR64:$Rt),
2264 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2265 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2267 def : Pat<(store (v1f64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2268 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2269 def : Pat<(store (v1i64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2270 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2272 // Match all store 128 bits width whose type is compatible with FPR128
2273 let Predicates = [IsLE] in {
2274 // We must use ST1 to store vectors in big-endian.
2275 def : Pat<(store (v4f32 FPR128:$Rt),
2276 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2277 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2278 def : Pat<(store (v2f64 FPR128:$Rt),
2279 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2280 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2281 def : Pat<(store (v16i8 FPR128:$Rt),
2282 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2283 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2284 def : Pat<(store (v8i16 FPR128:$Rt),
2285 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2286 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2287 def : Pat<(store (v4i32 FPR128:$Rt),
2288 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2289 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2290 def : Pat<(store (v2i64 FPR128:$Rt),
2291 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2292 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2293 def : Pat<(store (v2f64 FPR128:$Rt),
2294 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2295 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2296 def : Pat<(store (v8f16 FPR128:$Rt),
2297 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2298 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2301 // unscaled i64 truncating stores
2302 def : Pat<(truncstorei32 GPR64:$Rt, (am_unscaled32 GPR64sp:$Rn, simm9:$offset)),
2303 (STURWi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2304 def : Pat<(truncstorei16 GPR64:$Rt, (am_unscaled16 GPR64sp:$Rn, simm9:$offset)),
2305 (STURHHi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2306 def : Pat<(truncstorei8 GPR64:$Rt, (am_unscaled8 GPR64sp:$Rn, simm9:$offset)),
2307 (STURBBi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2310 // STR mnemonics fall back to STUR for negative or unaligned offsets.
2311 def : InstAlias<"str $Rt, [$Rn, $offset]",
2312 (STURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
2313 def : InstAlias<"str $Rt, [$Rn, $offset]",
2314 (STURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
2315 def : InstAlias<"str $Rt, [$Rn, $offset]",
2316 (STURBi FPR8:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2317 def : InstAlias<"str $Rt, [$Rn, $offset]",
2318 (STURHi FPR16:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2319 def : InstAlias<"str $Rt, [$Rn, $offset]",
2320 (STURSi FPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
2321 def : InstAlias<"str $Rt, [$Rn, $offset]",
2322 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
2323 def : InstAlias<"str $Rt, [$Rn, $offset]",
2324 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;
2326 def : InstAlias<"strb $Rt, [$Rn, $offset]",
2327 (STURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2328 def : InstAlias<"strh $Rt, [$Rn, $offset]",
2329 (STURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2332 // (unscaled immediate, unprivileged)
2333 defm STTRW : StoreUnprivileged<0b10, 0, 0b00, GPR32, "sttr">;
2334 defm STTRX : StoreUnprivileged<0b11, 0, 0b00, GPR64, "sttr">;
2336 defm STTRH : StoreUnprivileged<0b01, 0, 0b00, GPR32, "sttrh">;
2337 defm STTRB : StoreUnprivileged<0b00, 0, 0b00, GPR32, "sttrb">;
2340 // (immediate pre-indexed)
2341 def STRWpre : StorePreIdx<0b10, 0, 0b00, GPR32, "str", pre_store, i32>;
2342 def STRXpre : StorePreIdx<0b11, 0, 0b00, GPR64, "str", pre_store, i64>;
2343 def STRBpre : StorePreIdx<0b00, 1, 0b00, FPR8, "str", pre_store, untyped>;
2344 def STRHpre : StorePreIdx<0b01, 1, 0b00, FPR16, "str", pre_store, f16>;
2345 def STRSpre : StorePreIdx<0b10, 1, 0b00, FPR32, "str", pre_store, f32>;
2346 def STRDpre : StorePreIdx<0b11, 1, 0b00, FPR64, "str", pre_store, f64>;
2347 def STRQpre : StorePreIdx<0b00, 1, 0b10, FPR128, "str", pre_store, f128>;
2349 def STRBBpre : StorePreIdx<0b00, 0, 0b00, GPR32, "strb", pre_truncsti8, i32>;
2350 def STRHHpre : StorePreIdx<0b01, 0, 0b00, GPR32, "strh", pre_truncsti16, i32>;
2353 def : Pat<(pre_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2354 (STRWpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2356 def : Pat<(pre_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2357 (STRHHpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2359 def : Pat<(pre_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2360 (STRBBpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2363 def : Pat<(pre_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2364 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2365 def : Pat<(pre_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2366 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2367 def : Pat<(pre_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2368 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2369 def : Pat<(pre_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2370 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2371 def : Pat<(pre_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2372 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2373 def : Pat<(pre_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2374 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2375 def : Pat<(pre_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2376 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2378 def : Pat<(pre_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2379 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2380 def : Pat<(pre_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2381 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2382 def : Pat<(pre_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2383 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2384 def : Pat<(pre_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2385 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2386 def : Pat<(pre_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2387 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2388 def : Pat<(pre_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2389 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2390 def : Pat<(pre_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2391 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2394 // (immediate post-indexed)
2395 def STRWpost : StorePostIdx<0b10, 0, 0b00, GPR32, "str", post_store, i32>;
2396 def STRXpost : StorePostIdx<0b11, 0, 0b00, GPR64, "str", post_store, i64>;
2397 def STRBpost : StorePostIdx<0b00, 1, 0b00, FPR8, "str", post_store, untyped>;
2398 def STRHpost : StorePostIdx<0b01, 1, 0b00, FPR16, "str", post_store, f16>;
2399 def STRSpost : StorePostIdx<0b10, 1, 0b00, FPR32, "str", post_store, f32>;
2400 def STRDpost : StorePostIdx<0b11, 1, 0b00, FPR64, "str", post_store, f64>;
2401 def STRQpost : StorePostIdx<0b00, 1, 0b10, FPR128, "str", post_store, f128>;
2403 def STRBBpost : StorePostIdx<0b00, 0, 0b00, GPR32, "strb", post_truncsti8, i32>;
2404 def STRHHpost : StorePostIdx<0b01, 0, 0b00, GPR32, "strh", post_truncsti16, i32>;
2407 def : Pat<(post_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2408 (STRWpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2410 def : Pat<(post_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2411 (STRHHpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2413 def : Pat<(post_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2414 (STRBBpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2417 def : Pat<(post_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2418 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2419 def : Pat<(post_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2420 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2421 def : Pat<(post_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2422 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2423 def : Pat<(post_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2424 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2425 def : Pat<(post_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2426 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2427 def : Pat<(post_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2428 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2429 def : Pat<(post_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2430 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2432 def : Pat<(post_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2433 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2434 def : Pat<(post_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2435 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2436 def : Pat<(post_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2437 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2438 def : Pat<(post_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2439 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2440 def : Pat<(post_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2441 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2442 def : Pat<(post_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2443 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2444 def : Pat<(post_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2445 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2447 //===----------------------------------------------------------------------===//
2448 // Load/store exclusive instructions.
2449 //===----------------------------------------------------------------------===//
2451 def LDARW : LoadAcquire <0b10, 1, 1, 0, 1, GPR32, "ldar">;
2452 def LDARX : LoadAcquire <0b11, 1, 1, 0, 1, GPR64, "ldar">;
2453 def LDARB : LoadAcquire <0b00, 1, 1, 0, 1, GPR32, "ldarb">;
2454 def LDARH : LoadAcquire <0b01, 1, 1, 0, 1, GPR32, "ldarh">;
2456 def LDAXRW : LoadExclusive <0b10, 0, 1, 0, 1, GPR32, "ldaxr">;
2457 def LDAXRX : LoadExclusive <0b11, 0, 1, 0, 1, GPR64, "ldaxr">;
2458 def LDAXRB : LoadExclusive <0b00, 0, 1, 0, 1, GPR32, "ldaxrb">;
2459 def LDAXRH : LoadExclusive <0b01, 0, 1, 0, 1, GPR32, "ldaxrh">;
2461 def LDXRW : LoadExclusive <0b10, 0, 1, 0, 0, GPR32, "ldxr">;
2462 def LDXRX : LoadExclusive <0b11, 0, 1, 0, 0, GPR64, "ldxr">;
2463 def LDXRB : LoadExclusive <0b00, 0, 1, 0, 0, GPR32, "ldxrb">;
2464 def LDXRH : LoadExclusive <0b01, 0, 1, 0, 0, GPR32, "ldxrh">;
2466 def STLRW : StoreRelease <0b10, 1, 0, 0, 1, GPR32, "stlr">;
2467 def STLRX : StoreRelease <0b11, 1, 0, 0, 1, GPR64, "stlr">;
2468 def STLRB : StoreRelease <0b00, 1, 0, 0, 1, GPR32, "stlrb">;
2469 def STLRH : StoreRelease <0b01, 1, 0, 0, 1, GPR32, "stlrh">;
2471 def STLXRW : StoreExclusive<0b10, 0, 0, 0, 1, GPR32, "stlxr">;
2472 def STLXRX : StoreExclusive<0b11, 0, 0, 0, 1, GPR64, "stlxr">;
2473 def STLXRB : StoreExclusive<0b00, 0, 0, 0, 1, GPR32, "stlxrb">;
2474 def STLXRH : StoreExclusive<0b01, 0, 0, 0, 1, GPR32, "stlxrh">;
2476 def STXRW : StoreExclusive<0b10, 0, 0, 0, 0, GPR32, "stxr">;
2477 def STXRX : StoreExclusive<0b11, 0, 0, 0, 0, GPR64, "stxr">;
2478 def STXRB : StoreExclusive<0b00, 0, 0, 0, 0, GPR32, "stxrb">;
2479 def STXRH : StoreExclusive<0b01, 0, 0, 0, 0, GPR32, "stxrh">;
2481 def LDAXPW : LoadExclusivePair<0b10, 0, 1, 1, 1, GPR32, "ldaxp">;
2482 def LDAXPX : LoadExclusivePair<0b11, 0, 1, 1, 1, GPR64, "ldaxp">;
2484 def LDXPW : LoadExclusivePair<0b10, 0, 1, 1, 0, GPR32, "ldxp">;
2485 def LDXPX : LoadExclusivePair<0b11, 0, 1, 1, 0, GPR64, "ldxp">;
2487 def STLXPW : StoreExclusivePair<0b10, 0, 0, 1, 1, GPR32, "stlxp">;
2488 def STLXPX : StoreExclusivePair<0b11, 0, 0, 1, 1, GPR64, "stlxp">;
2490 def STXPW : StoreExclusivePair<0b10, 0, 0, 1, 0, GPR32, "stxp">;
2491 def STXPX : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">;
2493 let Predicates = [HasV8_1a] in {
2494 // v8.1a "Limited Order Region" extension load-acquire instructions
2495 def LDLARW : LoadAcquire <0b10, 1, 1, 0, 0, GPR32, "ldlar">;
2496 def LDLARX : LoadAcquire <0b11, 1, 1, 0, 0, GPR64, "ldlar">;
2497 def LDLARB : LoadAcquire <0b00, 1, 1, 0, 0, GPR32, "ldlarb">;
2498 def LDLARH : LoadAcquire <0b01, 1, 1, 0, 0, GPR32, "ldlarh">;
2500 // v8.1a "Limited Order Region" extension store-release instructions
2501 def STLLRW : StoreRelease <0b10, 1, 0, 0, 0, GPR32, "stllr">;
2502 def STLLRX : StoreRelease <0b11, 1, 0, 0, 0, GPR64, "stllr">;
2503 def STLLRB : StoreRelease <0b00, 1, 0, 0, 0, GPR32, "stllrb">;
2504 def STLLRH : StoreRelease <0b01, 1, 0, 0, 0, GPR32, "stllrh">;
2507 //===----------------------------------------------------------------------===//
2508 // Scaled floating point to integer conversion instructions.
2509 //===----------------------------------------------------------------------===//
2511 defm FCVTAS : FPToIntegerUnscaled<0b00, 0b100, "fcvtas", int_aarch64_neon_fcvtas>;
2512 defm FCVTAU : FPToIntegerUnscaled<0b00, 0b101, "fcvtau", int_aarch64_neon_fcvtau>;
2513 defm FCVTMS : FPToIntegerUnscaled<0b10, 0b000, "fcvtms", int_aarch64_neon_fcvtms>;
2514 defm FCVTMU : FPToIntegerUnscaled<0b10, 0b001, "fcvtmu", int_aarch64_neon_fcvtmu>;
2515 defm FCVTNS : FPToIntegerUnscaled<0b00, 0b000, "fcvtns", int_aarch64_neon_fcvtns>;
2516 defm FCVTNU : FPToIntegerUnscaled<0b00, 0b001, "fcvtnu", int_aarch64_neon_fcvtnu>;
2517 defm FCVTPS : FPToIntegerUnscaled<0b01, 0b000, "fcvtps", int_aarch64_neon_fcvtps>;
2518 defm FCVTPU : FPToIntegerUnscaled<0b01, 0b001, "fcvtpu", int_aarch64_neon_fcvtpu>;
2519 defm FCVTZS : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2520 defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2521 defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2522 defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2524 multiclass FPToIntegerIntPats<Intrinsic round, string INST> {
2525 def : Pat<(i32 (round f16:$Rn)), (!cast<Instruction>(INST # UWHr) $Rn)>;
2526 def : Pat<(i64 (round f16:$Rn)), (!cast<Instruction>(INST # UXHr) $Rn)>;
2527 def : Pat<(i32 (round f32:$Rn)), (!cast<Instruction>(INST # UWSr) $Rn)>;
2528 def : Pat<(i64 (round f32:$Rn)), (!cast<Instruction>(INST # UXSr) $Rn)>;
2529 def : Pat<(i32 (round f64:$Rn)), (!cast<Instruction>(INST # UWDr) $Rn)>;
2530 def : Pat<(i64 (round f64:$Rn)), (!cast<Instruction>(INST # UXDr) $Rn)>;
2532 def : Pat<(i32 (round (fmul f16:$Rn, fixedpoint_f16_i32:$scale))),
2533 (!cast<Instruction>(INST # SWHri) $Rn, $scale)>;
2534 def : Pat<(i64 (round (fmul f16:$Rn, fixedpoint_f16_i64:$scale))),
2535 (!cast<Instruction>(INST # SXHri) $Rn, $scale)>;
2536 def : Pat<(i32 (round (fmul f32:$Rn, fixedpoint_f32_i32:$scale))),
2537 (!cast<Instruction>(INST # SWSri) $Rn, $scale)>;
2538 def : Pat<(i64 (round (fmul f32:$Rn, fixedpoint_f32_i64:$scale))),
2539 (!cast<Instruction>(INST # SXSri) $Rn, $scale)>;
2540 def : Pat<(i32 (round (fmul f64:$Rn, fixedpoint_f64_i32:$scale))),
2541 (!cast<Instruction>(INST # SWDri) $Rn, $scale)>;
2542 def : Pat<(i64 (round (fmul f64:$Rn, fixedpoint_f64_i64:$scale))),
2543 (!cast<Instruction>(INST # SXDri) $Rn, $scale)>;
2546 defm : FPToIntegerIntPats<int_aarch64_neon_fcvtzs, "FCVTZS">;
2547 defm : FPToIntegerIntPats<int_aarch64_neon_fcvtzu, "FCVTZU">;
2549 multiclass FPToIntegerPats<SDNode to_int, SDNode round, string INST> {
2550 def : Pat<(i32 (to_int (round f32:$Rn))),
2551 (!cast<Instruction>(INST # UWSr) f32:$Rn)>;
2552 def : Pat<(i64 (to_int (round f32:$Rn))),
2553 (!cast<Instruction>(INST # UXSr) f32:$Rn)>;
2554 def : Pat<(i32 (to_int (round f64:$Rn))),
2555 (!cast<Instruction>(INST # UWDr) f64:$Rn)>;
2556 def : Pat<(i64 (to_int (round f64:$Rn))),
2557 (!cast<Instruction>(INST # UXDr) f64:$Rn)>;
2560 defm : FPToIntegerPats<fp_to_sint, fceil, "FCVTPS">;
2561 defm : FPToIntegerPats<fp_to_uint, fceil, "FCVTPU">;
2562 defm : FPToIntegerPats<fp_to_sint, ffloor, "FCVTMS">;
2563 defm : FPToIntegerPats<fp_to_uint, ffloor, "FCVTMU">;
2564 defm : FPToIntegerPats<fp_to_sint, ftrunc, "FCVTZS">;
2565 defm : FPToIntegerPats<fp_to_uint, ftrunc, "FCVTZU">;
2566 defm : FPToIntegerPats<fp_to_sint, fround, "FCVTAS">;
2567 defm : FPToIntegerPats<fp_to_uint, fround, "FCVTAU">;
2569 //===----------------------------------------------------------------------===//
2570 // Scaled integer to floating point conversion instructions.
2571 //===----------------------------------------------------------------------===//
2573 defm SCVTF : IntegerToFP<0, "scvtf", sint_to_fp>;
2574 defm UCVTF : IntegerToFP<1, "ucvtf", uint_to_fp>;
2576 //===----------------------------------------------------------------------===//
2577 // Unscaled integer to floating point conversion instruction.
2578 //===----------------------------------------------------------------------===//
2580 defm FMOV : UnscaledConversion<"fmov">;
2582 // Add pseudo ops for FMOV 0 so we can mark them as isReMaterializable
2583 let isReMaterializable = 1, isCodeGenOnly = 1, isAsCheapAsAMove = 1 in {
2584 def FMOVS0 : Pseudo<(outs FPR32:$Rd), (ins), [(set f32:$Rd, (fpimm0))]>,
2586 def FMOVD0 : Pseudo<(outs FPR64:$Rd), (ins), [(set f64:$Rd, (fpimm0))]>,
2590 //===----------------------------------------------------------------------===//
2591 // Floating point conversion instruction.
2592 //===----------------------------------------------------------------------===//
2594 defm FCVT : FPConversion<"fcvt">;
2596 //===----------------------------------------------------------------------===//
2597 // Floating point single operand instructions.
2598 //===----------------------------------------------------------------------===//
2600 defm FABS : SingleOperandFPData<0b0001, "fabs", fabs>;
2601 defm FMOV : SingleOperandFPData<0b0000, "fmov">;
2602 defm FNEG : SingleOperandFPData<0b0010, "fneg", fneg>;
2603 defm FRINTA : SingleOperandFPData<0b1100, "frinta", fround>;
2604 defm FRINTI : SingleOperandFPData<0b1111, "frinti", fnearbyint>;
2605 defm FRINTM : SingleOperandFPData<0b1010, "frintm", ffloor>;
2606 defm FRINTN : SingleOperandFPData<0b1000, "frintn", int_aarch64_neon_frintn>;
2607 defm FRINTP : SingleOperandFPData<0b1001, "frintp", fceil>;
2609 def : Pat<(v1f64 (int_aarch64_neon_frintn (v1f64 FPR64:$Rn))),
2610 (FRINTNDr FPR64:$Rn)>;
2612 defm FRINTX : SingleOperandFPData<0b1110, "frintx", frint>;
2613 defm FRINTZ : SingleOperandFPData<0b1011, "frintz", ftrunc>;
2615 let SchedRW = [WriteFDiv] in {
2616 defm FSQRT : SingleOperandFPData<0b0011, "fsqrt", fsqrt>;
2619 //===----------------------------------------------------------------------===//
2620 // Floating point two operand instructions.
2621 //===----------------------------------------------------------------------===//
2623 defm FADD : TwoOperandFPData<0b0010, "fadd", fadd>;
2624 let SchedRW = [WriteFDiv] in {
2625 defm FDIV : TwoOperandFPData<0b0001, "fdiv", fdiv>;
2627 defm FMAXNM : TwoOperandFPData<0b0110, "fmaxnm", fmaxnum>;
2628 defm FMAX : TwoOperandFPData<0b0100, "fmax", fmaxnan>;
2629 defm FMINNM : TwoOperandFPData<0b0111, "fminnm", fminnum>;
2630 defm FMIN : TwoOperandFPData<0b0101, "fmin", fminnan>;
2631 let SchedRW = [WriteFMul] in {
2632 defm FMUL : TwoOperandFPData<0b0000, "fmul", fmul>;
2633 defm FNMUL : TwoOperandFPDataNeg<0b1000, "fnmul", fmul>;
2635 defm FSUB : TwoOperandFPData<0b0011, "fsub", fsub>;
2637 def : Pat<(v1f64 (fmaxnan (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2638 (FMAXDrr FPR64:$Rn, FPR64:$Rm)>;
2639 def : Pat<(v1f64 (fminnan (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2640 (FMINDrr FPR64:$Rn, FPR64:$Rm)>;
2641 def : Pat<(v1f64 (fmaxnum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2642 (FMAXNMDrr FPR64:$Rn, FPR64:$Rm)>;
2643 def : Pat<(v1f64 (fminnum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2644 (FMINNMDrr FPR64:$Rn, FPR64:$Rm)>;
2646 //===----------------------------------------------------------------------===//
2647 // Floating point three operand instructions.
2648 //===----------------------------------------------------------------------===//
2650 defm FMADD : ThreeOperandFPData<0, 0, "fmadd", fma>;
2651 defm FMSUB : ThreeOperandFPData<0, 1, "fmsub",
2652 TriOpFrag<(fma node:$LHS, (fneg node:$MHS), node:$RHS)> >;
2653 defm FNMADD : ThreeOperandFPData<1, 0, "fnmadd",
2654 TriOpFrag<(fneg (fma node:$LHS, node:$MHS, node:$RHS))> >;
2655 defm FNMSUB : ThreeOperandFPData<1, 1, "fnmsub",
2656 TriOpFrag<(fma node:$LHS, node:$MHS, (fneg node:$RHS))> >;
2658 // The following def pats catch the case where the LHS of an FMA is negated.
2659 // The TriOpFrag above catches the case where the middle operand is negated.
2661 // N.b. FMSUB etc have the accumulator at the *end* of (outs), unlike
2662 // the NEON variant.
2663 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, FPR32:$Ra)),
2664 (FMSUBSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2666 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, FPR64:$Ra)),
2667 (FMSUBDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2669 // We handled -(a + b*c) for FNMADD above, now it's time for "(-a) + (-b)*c" and
2671 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, (fneg FPR32:$Ra))),
2672 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2674 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, (fneg FPR64:$Ra))),
2675 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2677 def : Pat<(f32 (fma FPR32:$Rn, (fneg FPR32:$Rm), (fneg FPR32:$Ra))),
2678 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2680 def : Pat<(f64 (fma FPR64:$Rn, (fneg FPR64:$Rm), (fneg FPR64:$Ra))),
2681 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2683 //===----------------------------------------------------------------------===//
2684 // Floating point comparison instructions.
2685 //===----------------------------------------------------------------------===//
2687 defm FCMPE : FPComparison<1, "fcmpe">;
2688 defm FCMP : FPComparison<0, "fcmp", AArch64fcmp>;
2690 //===----------------------------------------------------------------------===//
2691 // Floating point conditional comparison instructions.
2692 //===----------------------------------------------------------------------===//
2694 defm FCCMPE : FPCondComparison<1, "fccmpe">;
2695 defm FCCMP : FPCondComparison<0, "fccmp", AArch64fccmp>;
2697 //===----------------------------------------------------------------------===//
2698 // Floating point conditional select instruction.
2699 //===----------------------------------------------------------------------===//
2701 defm FCSEL : FPCondSelect<"fcsel">;
2703 // CSEL instructions providing f128 types need to be handled by a
2704 // pseudo-instruction since the eventual code will need to introduce basic
2705 // blocks and control flow.
2706 def F128CSEL : Pseudo<(outs FPR128:$Rd),
2707 (ins FPR128:$Rn, FPR128:$Rm, ccode:$cond),
2708 [(set (f128 FPR128:$Rd),
2709 (AArch64csel FPR128:$Rn, FPR128:$Rm,
2710 (i32 imm:$cond), NZCV))]> {
2712 let usesCustomInserter = 1;
2713 let hasNoSchedulingInfo = 1;
2717 //===----------------------------------------------------------------------===//
2718 // Floating point immediate move.
2719 //===----------------------------------------------------------------------===//
2721 let isReMaterializable = 1 in {
2722 defm FMOV : FPMoveImmediate<"fmov">;
2725 //===----------------------------------------------------------------------===//
2726 // Advanced SIMD two vector instructions.
2727 //===----------------------------------------------------------------------===//
2729 defm UABDL : SIMDLongThreeVectorBHSabdl<1, 0b0111, "uabdl",
2730 int_aarch64_neon_uabd>;
2731 // Match UABDL in log2-shuffle patterns.
2732 def : Pat<(xor (v8i16 (AArch64vashr v8i16:$src, (i32 15))),
2733 (v8i16 (add (sub (zext (v8i8 V64:$opA)),
2734 (zext (v8i8 V64:$opB))),
2735 (AArch64vashr v8i16:$src, (i32 15))))),
2736 (UABDLv8i8_v8i16 V64:$opA, V64:$opB)>;
2737 def : Pat<(xor (v8i16 (AArch64vashr v8i16:$src, (i32 15))),
2738 (v8i16 (add (sub (zext (extract_high_v16i8 V128:$opA)),
2739 (zext (extract_high_v16i8 V128:$opB))),
2740 (AArch64vashr v8i16:$src, (i32 15))))),
2741 (UABDLv16i8_v8i16 V128:$opA, V128:$opB)>;
2742 def : Pat<(xor (v4i32 (AArch64vashr v4i32:$src, (i32 31))),
2743 (v4i32 (add (sub (zext (v4i16 V64:$opA)),
2744 (zext (v4i16 V64:$opB))),
2745 (AArch64vashr v4i32:$src, (i32 31))))),
2746 (UABDLv4i16_v4i32 V64:$opA, V64:$opB)>;
2747 def : Pat<(xor (v4i32 (AArch64vashr v4i32:$src, (i32 31))),
2748 (v4i32 (add (sub (zext (extract_high_v8i16 V128:$opA)),
2749 (zext (extract_high_v8i16 V128:$opB))),
2750 (AArch64vashr v4i32:$src, (i32 31))))),
2751 (UABDLv8i16_v4i32 V128:$opA, V128:$opB)>;
2752 def : Pat<(xor (v2i64 (AArch64vashr v2i64:$src, (i32 63))),
2753 (v2i64 (add (sub (zext (v2i32 V64:$opA)),
2754 (zext (v2i32 V64:$opB))),
2755 (AArch64vashr v2i64:$src, (i32 63))))),
2756 (UABDLv2i32_v2i64 V64:$opA, V64:$opB)>;
2757 def : Pat<(xor (v2i64 (AArch64vashr v2i64:$src, (i32 63))),
2758 (v2i64 (add (sub (zext (extract_high_v4i32 V128:$opA)),
2759 (zext (extract_high_v4i32 V128:$opB))),
2760 (AArch64vashr v2i64:$src, (i32 63))))),
2761 (UABDLv4i32_v2i64 V128:$opA, V128:$opB)>;
2763 defm ABS : SIMDTwoVectorBHSD<0, 0b01011, "abs", int_aarch64_neon_abs>;
2764 def : Pat<(xor (v8i8 (AArch64vashr V64:$src, (i32 7))),
2765 (v8i8 (add V64:$src, (AArch64vashr V64:$src, (i32 7))))),
2766 (ABSv8i8 V64:$src)>;
2767 def : Pat<(xor (v4i16 (AArch64vashr V64:$src, (i32 15))),
2768 (v4i16 (add V64:$src, (AArch64vashr V64:$src, (i32 15))))),
2769 (ABSv4i16 V64:$src)>;
2770 def : Pat<(xor (v2i32 (AArch64vashr V64:$src, (i32 31))),
2771 (v2i32 (add V64:$src, (AArch64vashr V64:$src, (i32 31))))),
2772 (ABSv2i32 V64:$src)>;
2773 def : Pat<(xor (v16i8 (AArch64vashr V128:$src, (i32 7))),
2774 (v16i8 (add V128:$src, (AArch64vashr V128:$src, (i32 7))))),
2775 (ABSv16i8 V128:$src)>;
2776 def : Pat<(xor (v8i16 (AArch64vashr V128:$src, (i32 15))),
2777 (v8i16 (add V128:$src, (AArch64vashr V128:$src, (i32 15))))),
2778 (ABSv8i16 V128:$src)>;
2779 def : Pat<(xor (v4i32 (AArch64vashr V128:$src, (i32 31))),
2780 (v4i32 (add V128:$src, (AArch64vashr V128:$src, (i32 31))))),
2781 (ABSv4i32 V128:$src)>;
2782 def : Pat<(xor (v2i64 (AArch64vashr V128:$src, (i32 63))),
2783 (v2i64 (add V128:$src, (AArch64vashr V128:$src, (i32 63))))),
2784 (ABSv2i64 V128:$src)>;
2786 defm CLS : SIMDTwoVectorBHS<0, 0b00100, "cls", int_aarch64_neon_cls>;
2787 defm CLZ : SIMDTwoVectorBHS<1, 0b00100, "clz", ctlz>;
2788 defm CMEQ : SIMDCmpTwoVector<0, 0b01001, "cmeq", AArch64cmeqz>;
2789 defm CMGE : SIMDCmpTwoVector<1, 0b01000, "cmge", AArch64cmgez>;
2790 defm CMGT : SIMDCmpTwoVector<0, 0b01000, "cmgt", AArch64cmgtz>;
2791 defm CMLE : SIMDCmpTwoVector<1, 0b01001, "cmle", AArch64cmlez>;
2792 defm CMLT : SIMDCmpTwoVector<0, 0b01010, "cmlt", AArch64cmltz>;
2793 defm CNT : SIMDTwoVectorB<0, 0b00, 0b00101, "cnt", ctpop>;
2794 defm FABS : SIMDTwoVectorFP<0, 1, 0b01111, "fabs", fabs>;
2796 defm FCMEQ : SIMDFPCmpTwoVector<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>;
2797 defm FCMGE : SIMDFPCmpTwoVector<1, 1, 0b01100, "fcmge", AArch64fcmgez>;
2798 defm FCMGT : SIMDFPCmpTwoVector<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>;
2799 defm FCMLE : SIMDFPCmpTwoVector<1, 1, 0b01101, "fcmle", AArch64fcmlez>;
2800 defm FCMLT : SIMDFPCmpTwoVector<0, 1, 0b01110, "fcmlt", AArch64fcmltz>;
2801 defm FCVTAS : SIMDTwoVectorFPToInt<0,0,0b11100, "fcvtas",int_aarch64_neon_fcvtas>;
2802 defm FCVTAU : SIMDTwoVectorFPToInt<1,0,0b11100, "fcvtau",int_aarch64_neon_fcvtau>;
2803 defm FCVTL : SIMDFPWidenTwoVector<0, 0, 0b10111, "fcvtl">;
2804 def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (v4i16 V64:$Rn))),
2805 (FCVTLv4i16 V64:$Rn)>;
2806 def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (extract_subvector (v8i16 V128:$Rn),
2808 (FCVTLv8i16 V128:$Rn)>;
2809 def : Pat<(v2f64 (fpextend (v2f32 V64:$Rn))), (FCVTLv2i32 V64:$Rn)>;
2810 def : Pat<(v2f64 (fpextend (v2f32 (extract_subvector (v4f32 V128:$Rn),
2812 (FCVTLv4i32 V128:$Rn)>;
2814 def : Pat<(v4f32 (fpextend (v4f16 V64:$Rn))), (FCVTLv4i16 V64:$Rn)>;
2815 def : Pat<(v4f32 (fpextend (v4f16 (extract_subvector (v8f16 V128:$Rn),
2817 (FCVTLv8i16 V128:$Rn)>;
2819 defm FCVTMS : SIMDTwoVectorFPToInt<0,0,0b11011, "fcvtms",int_aarch64_neon_fcvtms>;
2820 defm FCVTMU : SIMDTwoVectorFPToInt<1,0,0b11011, "fcvtmu",int_aarch64_neon_fcvtmu>;
2821 defm FCVTNS : SIMDTwoVectorFPToInt<0,0,0b11010, "fcvtns",int_aarch64_neon_fcvtns>;
2822 defm FCVTNU : SIMDTwoVectorFPToInt<1,0,0b11010, "fcvtnu",int_aarch64_neon_fcvtnu>;
2823 defm FCVTN : SIMDFPNarrowTwoVector<0, 0, 0b10110, "fcvtn">;
2824 def : Pat<(v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn))),
2825 (FCVTNv4i16 V128:$Rn)>;
2826 def : Pat<(concat_vectors V64:$Rd,
2827 (v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn)))),
2828 (FCVTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2829 def : Pat<(v2f32 (fpround (v2f64 V128:$Rn))), (FCVTNv2i32 V128:$Rn)>;
2830 def : Pat<(v4f16 (fpround (v4f32 V128:$Rn))), (FCVTNv4i16 V128:$Rn)>;
2831 def : Pat<(concat_vectors V64:$Rd, (v2f32 (fpround (v2f64 V128:$Rn)))),
2832 (FCVTNv4i32 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2833 defm FCVTPS : SIMDTwoVectorFPToInt<0,1,0b11010, "fcvtps",int_aarch64_neon_fcvtps>;
2834 defm FCVTPU : SIMDTwoVectorFPToInt<1,1,0b11010, "fcvtpu",int_aarch64_neon_fcvtpu>;
2835 defm FCVTXN : SIMDFPInexactCvtTwoVector<1, 0, 0b10110, "fcvtxn",
2836 int_aarch64_neon_fcvtxn>;
2837 defm FCVTZS : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs", fp_to_sint>;
2838 defm FCVTZU : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu", fp_to_uint>;
2840 def : Pat<(v4i16 (int_aarch64_neon_fcvtzs v4f16:$Rn)), (FCVTZSv4f16 $Rn)>;
2841 def : Pat<(v8i16 (int_aarch64_neon_fcvtzs v8f16:$Rn)), (FCVTZSv8f16 $Rn)>;
2842 def : Pat<(v2i32 (int_aarch64_neon_fcvtzs v2f32:$Rn)), (FCVTZSv2f32 $Rn)>;
2843 def : Pat<(v4i32 (int_aarch64_neon_fcvtzs v4f32:$Rn)), (FCVTZSv4f32 $Rn)>;
2844 def : Pat<(v2i64 (int_aarch64_neon_fcvtzs v2f64:$Rn)), (FCVTZSv2f64 $Rn)>;
2846 def : Pat<(v4i16 (int_aarch64_neon_fcvtzu v4f16:$Rn)), (FCVTZUv4f16 $Rn)>;
2847 def : Pat<(v8i16 (int_aarch64_neon_fcvtzu v8f16:$Rn)), (FCVTZUv8f16 $Rn)>;
2848 def : Pat<(v2i32 (int_aarch64_neon_fcvtzu v2f32:$Rn)), (FCVTZUv2f32 $Rn)>;
2849 def : Pat<(v4i32 (int_aarch64_neon_fcvtzu v4f32:$Rn)), (FCVTZUv4f32 $Rn)>;
2850 def : Pat<(v2i64 (int_aarch64_neon_fcvtzu v2f64:$Rn)), (FCVTZUv2f64 $Rn)>;
2852 defm FNEG : SIMDTwoVectorFP<1, 1, 0b01111, "fneg", fneg>;
2853 defm FRECPE : SIMDTwoVectorFP<0, 1, 0b11101, "frecpe", int_aarch64_neon_frecpe>;
2854 defm FRINTA : SIMDTwoVectorFP<1, 0, 0b11000, "frinta", fround>;
2855 defm FRINTI : SIMDTwoVectorFP<1, 1, 0b11001, "frinti", fnearbyint>;
2856 defm FRINTM : SIMDTwoVectorFP<0, 0, 0b11001, "frintm", ffloor>;
2857 defm FRINTN : SIMDTwoVectorFP<0, 0, 0b11000, "frintn", int_aarch64_neon_frintn>;
2858 defm FRINTP : SIMDTwoVectorFP<0, 1, 0b11000, "frintp", fceil>;
2859 defm FRINTX : SIMDTwoVectorFP<1, 0, 0b11001, "frintx", frint>;
2860 defm FRINTZ : SIMDTwoVectorFP<0, 1, 0b11001, "frintz", ftrunc>;
2861 defm FRSQRTE: SIMDTwoVectorFP<1, 1, 0b11101, "frsqrte", int_aarch64_neon_frsqrte>;
2862 defm FSQRT : SIMDTwoVectorFP<1, 1, 0b11111, "fsqrt", fsqrt>;
2863 defm NEG : SIMDTwoVectorBHSD<1, 0b01011, "neg",
2864 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
2865 defm NOT : SIMDTwoVectorB<1, 0b00, 0b00101, "not", vnot>;
2866 // Aliases for MVN -> NOT.
2867 def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}",
2868 (NOTv8i8 V64:$Vd, V64:$Vn)>;
2869 def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}",
2870 (NOTv16i8 V128:$Vd, V128:$Vn)>;
2872 def : Pat<(AArch64neg (v8i8 V64:$Rn)), (NEGv8i8 V64:$Rn)>;
2873 def : Pat<(AArch64neg (v16i8 V128:$Rn)), (NEGv16i8 V128:$Rn)>;
2874 def : Pat<(AArch64neg (v4i16 V64:$Rn)), (NEGv4i16 V64:$Rn)>;
2875 def : Pat<(AArch64neg (v8i16 V128:$Rn)), (NEGv8i16 V128:$Rn)>;
2876 def : Pat<(AArch64neg (v2i32 V64:$Rn)), (NEGv2i32 V64:$Rn)>;
2877 def : Pat<(AArch64neg (v4i32 V128:$Rn)), (NEGv4i32 V128:$Rn)>;
2878 def : Pat<(AArch64neg (v2i64 V128:$Rn)), (NEGv2i64 V128:$Rn)>;
2880 def : Pat<(AArch64not (v8i8 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2881 def : Pat<(AArch64not (v16i8 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2882 def : Pat<(AArch64not (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2883 def : Pat<(AArch64not (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2884 def : Pat<(AArch64not (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2885 def : Pat<(AArch64not (v1i64 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2886 def : Pat<(AArch64not (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2887 def : Pat<(AArch64not (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2889 def : Pat<(vnot (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2890 def : Pat<(vnot (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2891 def : Pat<(vnot (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2892 def : Pat<(vnot (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2893 def : Pat<(vnot (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2895 defm RBIT : SIMDTwoVectorB<1, 0b01, 0b00101, "rbit", int_aarch64_neon_rbit>;
2896 defm REV16 : SIMDTwoVectorB<0, 0b00, 0b00001, "rev16", AArch64rev16>;
2897 defm REV32 : SIMDTwoVectorBH<1, 0b00000, "rev32", AArch64rev32>;
2898 defm REV64 : SIMDTwoVectorBHS<0, 0b00000, "rev64", AArch64rev64>;
2899 defm SADALP : SIMDLongTwoVectorTied<0, 0b00110, "sadalp",
2900 BinOpFrag<(add node:$LHS, (int_aarch64_neon_saddlp node:$RHS))> >;
2901 defm SADDLP : SIMDLongTwoVector<0, 0b00010, "saddlp", int_aarch64_neon_saddlp>;
2902 defm SCVTF : SIMDTwoVectorIntToFP<0, 0, 0b11101, "scvtf", sint_to_fp>;
2903 defm SHLL : SIMDVectorLShiftLongBySizeBHS;
2904 defm SQABS : SIMDTwoVectorBHSD<0, 0b00111, "sqabs", int_aarch64_neon_sqabs>;
2905 defm SQNEG : SIMDTwoVectorBHSD<1, 0b00111, "sqneg", int_aarch64_neon_sqneg>;
2906 defm SQXTN : SIMDMixedTwoVector<0, 0b10100, "sqxtn", int_aarch64_neon_sqxtn>;
2907 defm SQXTUN : SIMDMixedTwoVector<1, 0b10010, "sqxtun", int_aarch64_neon_sqxtun>;
2908 defm SUQADD : SIMDTwoVectorBHSDTied<0, 0b00011, "suqadd",int_aarch64_neon_suqadd>;
2909 defm UADALP : SIMDLongTwoVectorTied<1, 0b00110, "uadalp",
2910 BinOpFrag<(add node:$LHS, (int_aarch64_neon_uaddlp node:$RHS))> >;
2911 defm UADDLP : SIMDLongTwoVector<1, 0b00010, "uaddlp",
2912 int_aarch64_neon_uaddlp>;
2913 defm UCVTF : SIMDTwoVectorIntToFP<1, 0, 0b11101, "ucvtf", uint_to_fp>;
2914 defm UQXTN : SIMDMixedTwoVector<1, 0b10100, "uqxtn", int_aarch64_neon_uqxtn>;
2915 defm URECPE : SIMDTwoVectorS<0, 1, 0b11100, "urecpe", int_aarch64_neon_urecpe>;
2916 defm URSQRTE: SIMDTwoVectorS<1, 1, 0b11100, "ursqrte", int_aarch64_neon_ursqrte>;
2917 defm USQADD : SIMDTwoVectorBHSDTied<1, 0b00011, "usqadd",int_aarch64_neon_usqadd>;
2918 defm XTN : SIMDMixedTwoVector<0, 0b10010, "xtn", trunc>;
2920 def : Pat<(v4f16 (AArch64rev32 V64:$Rn)), (REV32v4i16 V64:$Rn)>;
2921 def : Pat<(v4f16 (AArch64rev64 V64:$Rn)), (REV64v4i16 V64:$Rn)>;
2922 def : Pat<(v8f16 (AArch64rev32 V128:$Rn)), (REV32v8i16 V128:$Rn)>;
2923 def : Pat<(v8f16 (AArch64rev64 V128:$Rn)), (REV64v8i16 V128:$Rn)>;
2924 def : Pat<(v2f32 (AArch64rev64 V64:$Rn)), (REV64v2i32 V64:$Rn)>;
2925 def : Pat<(v4f32 (AArch64rev64 V128:$Rn)), (REV64v4i32 V128:$Rn)>;
2927 // Patterns for vector long shift (by element width). These need to match all
2928 // three of zext, sext and anyext so it's easier to pull the patterns out of the
2930 multiclass SIMDVectorLShiftLongBySizeBHSPats<SDPatternOperator ext> {
2931 def : Pat<(AArch64vshl (v8i16 (ext (v8i8 V64:$Rn))), (i32 8)),
2932 (SHLLv8i8 V64:$Rn)>;
2933 def : Pat<(AArch64vshl (v8i16 (ext (extract_high_v16i8 V128:$Rn))), (i32 8)),
2934 (SHLLv16i8 V128:$Rn)>;
2935 def : Pat<(AArch64vshl (v4i32 (ext (v4i16 V64:$Rn))), (i32 16)),
2936 (SHLLv4i16 V64:$Rn)>;
2937 def : Pat<(AArch64vshl (v4i32 (ext (extract_high_v8i16 V128:$Rn))), (i32 16)),
2938 (SHLLv8i16 V128:$Rn)>;
2939 def : Pat<(AArch64vshl (v2i64 (ext (v2i32 V64:$Rn))), (i32 32)),
2940 (SHLLv2i32 V64:$Rn)>;
2941 def : Pat<(AArch64vshl (v2i64 (ext (extract_high_v4i32 V128:$Rn))), (i32 32)),
2942 (SHLLv4i32 V128:$Rn)>;
2945 defm : SIMDVectorLShiftLongBySizeBHSPats<anyext>;
2946 defm : SIMDVectorLShiftLongBySizeBHSPats<zext>;
2947 defm : SIMDVectorLShiftLongBySizeBHSPats<sext>;
2949 //===----------------------------------------------------------------------===//
2950 // Advanced SIMD three vector instructions.
2951 //===----------------------------------------------------------------------===//
2953 defm ADD : SIMDThreeSameVector<0, 0b10000, "add", add>;
2954 defm ADDP : SIMDThreeSameVector<0, 0b10111, "addp", int_aarch64_neon_addp>;
2955 defm CMEQ : SIMDThreeSameVector<1, 0b10001, "cmeq", AArch64cmeq>;
2956 defm CMGE : SIMDThreeSameVector<0, 0b00111, "cmge", AArch64cmge>;
2957 defm CMGT : SIMDThreeSameVector<0, 0b00110, "cmgt", AArch64cmgt>;
2958 defm CMHI : SIMDThreeSameVector<1, 0b00110, "cmhi", AArch64cmhi>;
2959 defm CMHS : SIMDThreeSameVector<1, 0b00111, "cmhs", AArch64cmhs>;
2960 defm CMTST : SIMDThreeSameVector<0, 0b10001, "cmtst", AArch64cmtst>;
2961 defm FABD : SIMDThreeSameVectorFP<1,1,0b010,"fabd", int_aarch64_neon_fabd>;
2962 defm FACGE : SIMDThreeSameVectorFPCmp<1,0,0b101,"facge",int_aarch64_neon_facge>;
2963 defm FACGT : SIMDThreeSameVectorFPCmp<1,1,0b101,"facgt",int_aarch64_neon_facgt>;
2964 defm FADDP : SIMDThreeSameVectorFP<1,0,0b010,"faddp",int_aarch64_neon_addp>;
2965 defm FADD : SIMDThreeSameVectorFP<0,0,0b010,"fadd", fadd>;
2966 defm FCMEQ : SIMDThreeSameVectorFPCmp<0, 0, 0b100, "fcmeq", AArch64fcmeq>;
2967 defm FCMGE : SIMDThreeSameVectorFPCmp<1, 0, 0b100, "fcmge", AArch64fcmge>;
2968 defm FCMGT : SIMDThreeSameVectorFPCmp<1, 1, 0b100, "fcmgt", AArch64fcmgt>;
2969 defm FDIV : SIMDThreeSameVectorFP<1,0,0b111,"fdiv", fdiv>;
2970 defm FMAXNMP : SIMDThreeSameVectorFP<1,0,0b000,"fmaxnmp", int_aarch64_neon_fmaxnmp>;
2971 defm FMAXNM : SIMDThreeSameVectorFP<0,0,0b000,"fmaxnm", fmaxnum>;
2972 defm FMAXP : SIMDThreeSameVectorFP<1,0,0b110,"fmaxp", int_aarch64_neon_fmaxp>;
2973 defm FMAX : SIMDThreeSameVectorFP<0,0,0b110,"fmax", fmaxnan>;
2974 defm FMINNMP : SIMDThreeSameVectorFP<1,1,0b000,"fminnmp", int_aarch64_neon_fminnmp>;
2975 defm FMINNM : SIMDThreeSameVectorFP<0,1,0b000,"fminnm", fminnum>;
2976 defm FMINP : SIMDThreeSameVectorFP<1,1,0b110,"fminp", int_aarch64_neon_fminp>;
2977 defm FMIN : SIMDThreeSameVectorFP<0,1,0b110,"fmin", fminnan>;
2979 // NOTE: The operands of the PatFrag are reordered on FMLA/FMLS because the
2980 // instruction expects the addend first, while the fma intrinsic puts it last.
2981 defm FMLA : SIMDThreeSameVectorFPTied<0, 0, 0b001, "fmla",
2982 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
2983 defm FMLS : SIMDThreeSameVectorFPTied<0, 1, 0b001, "fmls",
2984 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
2986 // The following def pats catch the case where the LHS of an FMA is negated.
2987 // The TriOpFrag above catches the case where the middle operand is negated.
2988 def : Pat<(v2f32 (fma (fneg V64:$Rn), V64:$Rm, V64:$Rd)),
2989 (FMLSv2f32 V64:$Rd, V64:$Rn, V64:$Rm)>;
2991 def : Pat<(v4f32 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2992 (FMLSv4f32 V128:$Rd, V128:$Rn, V128:$Rm)>;
2994 def : Pat<(v2f64 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2995 (FMLSv2f64 V128:$Rd, V128:$Rn, V128:$Rm)>;
2997 defm FMULX : SIMDThreeSameVectorFP<0,0,0b011,"fmulx", int_aarch64_neon_fmulx>;
2998 defm FMUL : SIMDThreeSameVectorFP<1,0,0b011,"fmul", fmul>;
2999 defm FRECPS : SIMDThreeSameVectorFP<0,0,0b111,"frecps", int_aarch64_neon_frecps>;
3000 defm FRSQRTS : SIMDThreeSameVectorFP<0,1,0b111,"frsqrts", int_aarch64_neon_frsqrts>;
3001 defm FSUB : SIMDThreeSameVectorFP<0,1,0b010,"fsub", fsub>;
3002 defm MLA : SIMDThreeSameVectorBHSTied<0, 0b10010, "mla",
3003 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))> >;
3004 defm MLS : SIMDThreeSameVectorBHSTied<1, 0b10010, "mls",
3005 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))> >;
3006 defm MUL : SIMDThreeSameVectorBHS<0, 0b10011, "mul", mul>;
3007 defm PMUL : SIMDThreeSameVectorB<1, 0b10011, "pmul", int_aarch64_neon_pmul>;
3008 defm SABA : SIMDThreeSameVectorBHSTied<0, 0b01111, "saba",
3009 TriOpFrag<(add node:$LHS, (int_aarch64_neon_sabd node:$MHS, node:$RHS))> >;
3010 defm SABD : SIMDThreeSameVectorBHS<0,0b01110,"sabd", int_aarch64_neon_sabd>;
3011 defm SHADD : SIMDThreeSameVectorBHS<0,0b00000,"shadd", int_aarch64_neon_shadd>;
3012 defm SHSUB : SIMDThreeSameVectorBHS<0,0b00100,"shsub", int_aarch64_neon_shsub>;
3013 defm SMAXP : SIMDThreeSameVectorBHS<0,0b10100,"smaxp", int_aarch64_neon_smaxp>;
3014 defm SMAX : SIMDThreeSameVectorBHS<0,0b01100,"smax", smax>;
3015 defm SMINP : SIMDThreeSameVectorBHS<0,0b10101,"sminp", int_aarch64_neon_sminp>;
3016 defm SMIN : SIMDThreeSameVectorBHS<0,0b01101,"smin", smin>;
3017 defm SQADD : SIMDThreeSameVector<0,0b00001,"sqadd", int_aarch64_neon_sqadd>;
3018 defm SQDMULH : SIMDThreeSameVectorHS<0,0b10110,"sqdmulh",int_aarch64_neon_sqdmulh>;
3019 defm SQRDMULH : SIMDThreeSameVectorHS<1,0b10110,"sqrdmulh",int_aarch64_neon_sqrdmulh>;
3020 defm SQRSHL : SIMDThreeSameVector<0,0b01011,"sqrshl", int_aarch64_neon_sqrshl>;
3021 defm SQSHL : SIMDThreeSameVector<0,0b01001,"sqshl", int_aarch64_neon_sqshl>;
3022 defm SQSUB : SIMDThreeSameVector<0,0b00101,"sqsub", int_aarch64_neon_sqsub>;
3023 defm SRHADD : SIMDThreeSameVectorBHS<0,0b00010,"srhadd",int_aarch64_neon_srhadd>;
3024 defm SRSHL : SIMDThreeSameVector<0,0b01010,"srshl", int_aarch64_neon_srshl>;
3025 defm SSHL : SIMDThreeSameVector<0,0b01000,"sshl", int_aarch64_neon_sshl>;
3026 defm SUB : SIMDThreeSameVector<1,0b10000,"sub", sub>;
3027 defm UABA : SIMDThreeSameVectorBHSTied<1, 0b01111, "uaba",
3028 TriOpFrag<(add node:$LHS, (int_aarch64_neon_uabd node:$MHS, node:$RHS))> >;
3029 defm UABD : SIMDThreeSameVectorBHS<1,0b01110,"uabd", int_aarch64_neon_uabd>;
3030 defm UHADD : SIMDThreeSameVectorBHS<1,0b00000,"uhadd", int_aarch64_neon_uhadd>;
3031 defm UHSUB : SIMDThreeSameVectorBHS<1,0b00100,"uhsub", int_aarch64_neon_uhsub>;
3032 defm UMAXP : SIMDThreeSameVectorBHS<1,0b10100,"umaxp", int_aarch64_neon_umaxp>;
3033 defm UMAX : SIMDThreeSameVectorBHS<1,0b01100,"umax", umax>;
3034 defm UMINP : SIMDThreeSameVectorBHS<1,0b10101,"uminp", int_aarch64_neon_uminp>;
3035 defm UMIN : SIMDThreeSameVectorBHS<1,0b01101,"umin", umin>;
3036 defm UQADD : SIMDThreeSameVector<1,0b00001,"uqadd", int_aarch64_neon_uqadd>;
3037 defm UQRSHL : SIMDThreeSameVector<1,0b01011,"uqrshl", int_aarch64_neon_uqrshl>;
3038 defm UQSHL : SIMDThreeSameVector<1,0b01001,"uqshl", int_aarch64_neon_uqshl>;
3039 defm UQSUB : SIMDThreeSameVector<1,0b00101,"uqsub", int_aarch64_neon_uqsub>;
3040 defm URHADD : SIMDThreeSameVectorBHS<1,0b00010,"urhadd", int_aarch64_neon_urhadd>;
3041 defm URSHL : SIMDThreeSameVector<1,0b01010,"urshl", int_aarch64_neon_urshl>;
3042 defm USHL : SIMDThreeSameVector<1,0b01000,"ushl", int_aarch64_neon_ushl>;
3043 defm SQRDMLAH : SIMDThreeSameVectorSQRDMLxHTiedHS<1,0b10000,"sqrdmlah",
3044 int_aarch64_neon_sqadd>;
3045 defm SQRDMLSH : SIMDThreeSameVectorSQRDMLxHTiedHS<1,0b10001,"sqrdmlsh",
3046 int_aarch64_neon_sqsub>;
3048 defm AND : SIMDLogicalThreeVector<0, 0b00, "and", and>;
3049 defm BIC : SIMDLogicalThreeVector<0, 0b01, "bic",
3050 BinOpFrag<(and node:$LHS, (vnot node:$RHS))> >;
3051 defm BIF : SIMDLogicalThreeVector<1, 0b11, "bif">;
3052 defm BIT : SIMDLogicalThreeVectorTied<1, 0b10, "bit", AArch64bit>;
3053 defm BSL : SIMDLogicalThreeVectorTied<1, 0b01, "bsl",
3054 TriOpFrag<(or (and node:$LHS, node:$MHS), (and (vnot node:$LHS), node:$RHS))>>;
3055 defm EOR : SIMDLogicalThreeVector<1, 0b00, "eor", xor>;
3056 defm ORN : SIMDLogicalThreeVector<0, 0b11, "orn",
3057 BinOpFrag<(or node:$LHS, (vnot node:$RHS))> >;
3058 defm ORR : SIMDLogicalThreeVector<0, 0b10, "orr", or>;
3061 def : Pat<(AArch64bsl (v8i8 V64:$Rd), V64:$Rn, V64:$Rm),
3062 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
3063 def : Pat<(AArch64bsl (v4i16 V64:$Rd), V64:$Rn, V64:$Rm),
3064 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
3065 def : Pat<(AArch64bsl (v2i32 V64:$Rd), V64:$Rn, V64:$Rm),
3066 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
3067 def : Pat<(AArch64bsl (v1i64 V64:$Rd), V64:$Rn, V64:$Rm),
3068 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
3070 def : Pat<(AArch64bsl (v16i8 V128:$Rd), V128:$Rn, V128:$Rm),
3071 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
3072 def : Pat<(AArch64bsl (v8i16 V128:$Rd), V128:$Rn, V128:$Rm),
3073 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
3074 def : Pat<(AArch64bsl (v4i32 V128:$Rd), V128:$Rn, V128:$Rm),
3075 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
3076 def : Pat<(AArch64bsl (v2i64 V128:$Rd), V128:$Rn, V128:$Rm),
3077 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
3079 def : InstAlias<"mov{\t$dst.16b, $src.16b|.16b\t$dst, $src}",
3080 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 1>;
3081 def : InstAlias<"mov{\t$dst.8h, $src.8h|.8h\t$dst, $src}",
3082 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
3083 def : InstAlias<"mov{\t$dst.4s, $src.4s|.4s\t$dst, $src}",
3084 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
3085 def : InstAlias<"mov{\t$dst.2d, $src.2d|.2d\t$dst, $src}",
3086 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
3088 def : InstAlias<"mov{\t$dst.8b, $src.8b|.8b\t$dst, $src}",
3089 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 1>;
3090 def : InstAlias<"mov{\t$dst.4h, $src.4h|.4h\t$dst, $src}",
3091 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
3092 def : InstAlias<"mov{\t$dst.2s, $src.2s|.2s\t$dst, $src}",
3093 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
3094 def : InstAlias<"mov{\t$dst.1d, $src.1d|.1d\t$dst, $src}",
3095 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
3097 def : InstAlias<"{cmls\t$dst.8b, $src1.8b, $src2.8b" #
3098 "|cmls.8b\t$dst, $src1, $src2}",
3099 (CMHSv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
3100 def : InstAlias<"{cmls\t$dst.16b, $src1.16b, $src2.16b" #
3101 "|cmls.16b\t$dst, $src1, $src2}",
3102 (CMHSv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
3103 def : InstAlias<"{cmls\t$dst.4h, $src1.4h, $src2.4h" #
3104 "|cmls.4h\t$dst, $src1, $src2}",
3105 (CMHSv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
3106 def : InstAlias<"{cmls\t$dst.8h, $src1.8h, $src2.8h" #
3107 "|cmls.8h\t$dst, $src1, $src2}",
3108 (CMHSv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
3109 def : InstAlias<"{cmls\t$dst.2s, $src1.2s, $src2.2s" #
3110 "|cmls.2s\t$dst, $src1, $src2}",
3111 (CMHSv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
3112 def : InstAlias<"{cmls\t$dst.4s, $src1.4s, $src2.4s" #
3113 "|cmls.4s\t$dst, $src1, $src2}",
3114 (CMHSv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
3115 def : InstAlias<"{cmls\t$dst.2d, $src1.2d, $src2.2d" #
3116 "|cmls.2d\t$dst, $src1, $src2}",
3117 (CMHSv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
3119 def : InstAlias<"{cmlo\t$dst.8b, $src1.8b, $src2.8b" #
3120 "|cmlo.8b\t$dst, $src1, $src2}",
3121 (CMHIv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
3122 def : InstAlias<"{cmlo\t$dst.16b, $src1.16b, $src2.16b" #
3123 "|cmlo.16b\t$dst, $src1, $src2}",
3124 (CMHIv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
3125 def : InstAlias<"{cmlo\t$dst.4h, $src1.4h, $src2.4h" #
3126 "|cmlo.4h\t$dst, $src1, $src2}",
3127 (CMHIv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
3128 def : InstAlias<"{cmlo\t$dst.8h, $src1.8h, $src2.8h" #
3129 "|cmlo.8h\t$dst, $src1, $src2}",
3130 (CMHIv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
3131 def : InstAlias<"{cmlo\t$dst.2s, $src1.2s, $src2.2s" #
3132 "|cmlo.2s\t$dst, $src1, $src2}",
3133 (CMHIv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
3134 def : InstAlias<"{cmlo\t$dst.4s, $src1.4s, $src2.4s" #
3135 "|cmlo.4s\t$dst, $src1, $src2}",
3136 (CMHIv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
3137 def : InstAlias<"{cmlo\t$dst.2d, $src1.2d, $src2.2d" #
3138 "|cmlo.2d\t$dst, $src1, $src2}",
3139 (CMHIv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
3141 def : InstAlias<"{cmle\t$dst.8b, $src1.8b, $src2.8b" #
3142 "|cmle.8b\t$dst, $src1, $src2}",
3143 (CMGEv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
3144 def : InstAlias<"{cmle\t$dst.16b, $src1.16b, $src2.16b" #
3145 "|cmle.16b\t$dst, $src1, $src2}",
3146 (CMGEv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
3147 def : InstAlias<"{cmle\t$dst.4h, $src1.4h, $src2.4h" #
3148 "|cmle.4h\t$dst, $src1, $src2}",
3149 (CMGEv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
3150 def : InstAlias<"{cmle\t$dst.8h, $src1.8h, $src2.8h" #
3151 "|cmle.8h\t$dst, $src1, $src2}",
3152 (CMGEv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
3153 def : InstAlias<"{cmle\t$dst.2s, $src1.2s, $src2.2s" #
3154 "|cmle.2s\t$dst, $src1, $src2}",
3155 (CMGEv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
3156 def : InstAlias<"{cmle\t$dst.4s, $src1.4s, $src2.4s" #
3157 "|cmle.4s\t$dst, $src1, $src2}",
3158 (CMGEv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
3159 def : InstAlias<"{cmle\t$dst.2d, $src1.2d, $src2.2d" #
3160 "|cmle.2d\t$dst, $src1, $src2}",
3161 (CMGEv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
3163 def : InstAlias<"{cmlt\t$dst.8b, $src1.8b, $src2.8b" #
3164 "|cmlt.8b\t$dst, $src1, $src2}",
3165 (CMGTv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
3166 def : InstAlias<"{cmlt\t$dst.16b, $src1.16b, $src2.16b" #
3167 "|cmlt.16b\t$dst, $src1, $src2}",
3168 (CMGTv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
3169 def : InstAlias<"{cmlt\t$dst.4h, $src1.4h, $src2.4h" #
3170 "|cmlt.4h\t$dst, $src1, $src2}",
3171 (CMGTv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
3172 def : InstAlias<"{cmlt\t$dst.8h, $src1.8h, $src2.8h" #
3173 "|cmlt.8h\t$dst, $src1, $src2}",
3174 (CMGTv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
3175 def : InstAlias<"{cmlt\t$dst.2s, $src1.2s, $src2.2s" #
3176 "|cmlt.2s\t$dst, $src1, $src2}",
3177 (CMGTv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
3178 def : InstAlias<"{cmlt\t$dst.4s, $src1.4s, $src2.4s" #
3179 "|cmlt.4s\t$dst, $src1, $src2}",
3180 (CMGTv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
3181 def : InstAlias<"{cmlt\t$dst.2d, $src1.2d, $src2.2d" #
3182 "|cmlt.2d\t$dst, $src1, $src2}",
3183 (CMGTv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
3185 let Predicates = [HasNEON, HasFullFP16] in {
3186 def : InstAlias<"{fcmle\t$dst.4h, $src1.4h, $src2.4h" #
3187 "|fcmle.4h\t$dst, $src1, $src2}",
3188 (FCMGEv4f16 V64:$dst, V64:$src2, V64:$src1), 0>;
3189 def : InstAlias<"{fcmle\t$dst.8h, $src1.8h, $src2.8h" #
3190 "|fcmle.8h\t$dst, $src1, $src2}",
3191 (FCMGEv8f16 V128:$dst, V128:$src2, V128:$src1), 0>;
3193 def : InstAlias<"{fcmle\t$dst.2s, $src1.2s, $src2.2s" #
3194 "|fcmle.2s\t$dst, $src1, $src2}",
3195 (FCMGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
3196 def : InstAlias<"{fcmle\t$dst.4s, $src1.4s, $src2.4s" #
3197 "|fcmle.4s\t$dst, $src1, $src2}",
3198 (FCMGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
3199 def : InstAlias<"{fcmle\t$dst.2d, $src1.2d, $src2.2d" #
3200 "|fcmle.2d\t$dst, $src1, $src2}",
3201 (FCMGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
3203 let Predicates = [HasNEON, HasFullFP16] in {
3204 def : InstAlias<"{fcmlt\t$dst.4h, $src1.4h, $src2.4h" #
3205 "|fcmlt.4h\t$dst, $src1, $src2}",
3206 (FCMGTv4f16 V64:$dst, V64:$src2, V64:$src1), 0>;
3207 def : InstAlias<"{fcmlt\t$dst.8h, $src1.8h, $src2.8h" #
3208 "|fcmlt.8h\t$dst, $src1, $src2}",
3209 (FCMGTv8f16 V128:$dst, V128:$src2, V128:$src1), 0>;
3211 def : InstAlias<"{fcmlt\t$dst.2s, $src1.2s, $src2.2s" #
3212 "|fcmlt.2s\t$dst, $src1, $src2}",
3213 (FCMGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
3214 def : InstAlias<"{fcmlt\t$dst.4s, $src1.4s, $src2.4s" #
3215 "|fcmlt.4s\t$dst, $src1, $src2}",
3216 (FCMGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
3217 def : InstAlias<"{fcmlt\t$dst.2d, $src1.2d, $src2.2d" #
3218 "|fcmlt.2d\t$dst, $src1, $src2}",
3219 (FCMGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
3221 let Predicates = [HasNEON, HasFullFP16] in {
3222 def : InstAlias<"{facle\t$dst.4h, $src1.4h, $src2.4h" #
3223 "|facle.4h\t$dst, $src1, $src2}",
3224 (FACGEv4f16 V64:$dst, V64:$src2, V64:$src1), 0>;
3225 def : InstAlias<"{facle\t$dst.8h, $src1.8h, $src2.8h" #
3226 "|facle.8h\t$dst, $src1, $src2}",
3227 (FACGEv8f16 V128:$dst, V128:$src2, V128:$src1), 0>;
3229 def : InstAlias<"{facle\t$dst.2s, $src1.2s, $src2.2s" #
3230 "|facle.2s\t$dst, $src1, $src2}",
3231 (FACGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
3232 def : InstAlias<"{facle\t$dst.4s, $src1.4s, $src2.4s" #
3233 "|facle.4s\t$dst, $src1, $src2}",
3234 (FACGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
3235 def : InstAlias<"{facle\t$dst.2d, $src1.2d, $src2.2d" #
3236 "|facle.2d\t$dst, $src1, $src2}",
3237 (FACGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
3239 let Predicates = [HasNEON, HasFullFP16] in {
3240 def : InstAlias<"{faclt\t$dst.4h, $src1.4h, $src2.4h" #
3241 "|faclt.4h\t$dst, $src1, $src2}",
3242 (FACGTv4f16 V64:$dst, V64:$src2, V64:$src1), 0>;
3243 def : InstAlias<"{faclt\t$dst.8h, $src1.8h, $src2.8h" #
3244 "|faclt.8h\t$dst, $src1, $src2}",
3245 (FACGTv8f16 V128:$dst, V128:$src2, V128:$src1), 0>;
3247 def : InstAlias<"{faclt\t$dst.2s, $src1.2s, $src2.2s" #
3248 "|faclt.2s\t$dst, $src1, $src2}",
3249 (FACGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
3250 def : InstAlias<"{faclt\t$dst.4s, $src1.4s, $src2.4s" #
3251 "|faclt.4s\t$dst, $src1, $src2}",
3252 (FACGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
3253 def : InstAlias<"{faclt\t$dst.2d, $src1.2d, $src2.2d" #
3254 "|faclt.2d\t$dst, $src1, $src2}",
3255 (FACGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
3257 //===----------------------------------------------------------------------===//
3258 // Advanced SIMD three scalar instructions.
3259 //===----------------------------------------------------------------------===//
3261 defm ADD : SIMDThreeScalarD<0, 0b10000, "add", add>;
3262 defm CMEQ : SIMDThreeScalarD<1, 0b10001, "cmeq", AArch64cmeq>;
3263 defm CMGE : SIMDThreeScalarD<0, 0b00111, "cmge", AArch64cmge>;
3264 defm CMGT : SIMDThreeScalarD<0, 0b00110, "cmgt", AArch64cmgt>;
3265 defm CMHI : SIMDThreeScalarD<1, 0b00110, "cmhi", AArch64cmhi>;
3266 defm CMHS : SIMDThreeScalarD<1, 0b00111, "cmhs", AArch64cmhs>;
3267 defm CMTST : SIMDThreeScalarD<0, 0b10001, "cmtst", AArch64cmtst>;
3268 defm FABD : SIMDFPThreeScalar<1, 1, 0b010, "fabd", int_aarch64_sisd_fabd>;
3269 def : Pat<(v1f64 (int_aarch64_neon_fabd (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
3270 (FABD64 FPR64:$Rn, FPR64:$Rm)>;
3271 defm FACGE : SIMDThreeScalarFPCmp<1, 0, 0b101, "facge",
3272 int_aarch64_neon_facge>;
3273 defm FACGT : SIMDThreeScalarFPCmp<1, 1, 0b101, "facgt",
3274 int_aarch64_neon_facgt>;
3275 defm FCMEQ : SIMDThreeScalarFPCmp<0, 0, 0b100, "fcmeq", AArch64fcmeq>;
3276 defm FCMGE : SIMDThreeScalarFPCmp<1, 0, 0b100, "fcmge", AArch64fcmge>;
3277 defm FCMGT : SIMDThreeScalarFPCmp<1, 1, 0b100, "fcmgt", AArch64fcmgt>;
3278 defm FMULX : SIMDFPThreeScalar<0, 0, 0b011, "fmulx", int_aarch64_neon_fmulx>;
3279 defm FRECPS : SIMDFPThreeScalar<0, 0, 0b111, "frecps", int_aarch64_neon_frecps>;
3280 defm FRSQRTS : SIMDFPThreeScalar<0, 1, 0b111, "frsqrts", int_aarch64_neon_frsqrts>;
3281 defm SQADD : SIMDThreeScalarBHSD<0, 0b00001, "sqadd", int_aarch64_neon_sqadd>;
3282 defm SQDMULH : SIMDThreeScalarHS< 0, 0b10110, "sqdmulh", int_aarch64_neon_sqdmulh>;
3283 defm SQRDMULH : SIMDThreeScalarHS< 1, 0b10110, "sqrdmulh", int_aarch64_neon_sqrdmulh>;
3284 defm SQRSHL : SIMDThreeScalarBHSD<0, 0b01011, "sqrshl",int_aarch64_neon_sqrshl>;
3285 defm SQSHL : SIMDThreeScalarBHSD<0, 0b01001, "sqshl", int_aarch64_neon_sqshl>;
3286 defm SQSUB : SIMDThreeScalarBHSD<0, 0b00101, "sqsub", int_aarch64_neon_sqsub>;
3287 defm SRSHL : SIMDThreeScalarD< 0, 0b01010, "srshl", int_aarch64_neon_srshl>;
3288 defm SSHL : SIMDThreeScalarD< 0, 0b01000, "sshl", int_aarch64_neon_sshl>;
3289 defm SUB : SIMDThreeScalarD< 1, 0b10000, "sub", sub>;
3290 defm UQADD : SIMDThreeScalarBHSD<1, 0b00001, "uqadd", int_aarch64_neon_uqadd>;
3291 defm UQRSHL : SIMDThreeScalarBHSD<1, 0b01011, "uqrshl",int_aarch64_neon_uqrshl>;
3292 defm UQSHL : SIMDThreeScalarBHSD<1, 0b01001, "uqshl", int_aarch64_neon_uqshl>;
3293 defm UQSUB : SIMDThreeScalarBHSD<1, 0b00101, "uqsub", int_aarch64_neon_uqsub>;
3294 defm URSHL : SIMDThreeScalarD< 1, 0b01010, "urshl", int_aarch64_neon_urshl>;
3295 defm USHL : SIMDThreeScalarD< 1, 0b01000, "ushl", int_aarch64_neon_ushl>;
3296 let Predicates = [HasRDM] in {
3297 defm SQRDMLAH : SIMDThreeScalarHSTied<1, 0, 0b10000, "sqrdmlah">;
3298 defm SQRDMLSH : SIMDThreeScalarHSTied<1, 0, 0b10001, "sqrdmlsh">;
3299 def : Pat<(i32 (int_aarch64_neon_sqadd
3301 (i32 (int_aarch64_neon_sqrdmulh (i32 FPR32:$Rn),
3302 (i32 FPR32:$Rm))))),
3303 (SQRDMLAHv1i32 FPR32:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3304 def : Pat<(i32 (int_aarch64_neon_sqsub
3306 (i32 (int_aarch64_neon_sqrdmulh (i32 FPR32:$Rn),
3307 (i32 FPR32:$Rm))))),
3308 (SQRDMLSHv1i32 FPR32:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3311 def : InstAlias<"cmls $dst, $src1, $src2",
3312 (CMHSv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3313 def : InstAlias<"cmle $dst, $src1, $src2",
3314 (CMGEv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3315 def : InstAlias<"cmlo $dst, $src1, $src2",
3316 (CMHIv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3317 def : InstAlias<"cmlt $dst, $src1, $src2",
3318 (CMGTv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3319 def : InstAlias<"fcmle $dst, $src1, $src2",
3320 (FCMGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3321 def : InstAlias<"fcmle $dst, $src1, $src2",
3322 (FCMGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3323 def : InstAlias<"fcmlt $dst, $src1, $src2",
3324 (FCMGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3325 def : InstAlias<"fcmlt $dst, $src1, $src2",
3326 (FCMGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3327 def : InstAlias<"facle $dst, $src1, $src2",
3328 (FACGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3329 def : InstAlias<"facle $dst, $src1, $src2",
3330 (FACGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3331 def : InstAlias<"faclt $dst, $src1, $src2",
3332 (FACGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3333 def : InstAlias<"faclt $dst, $src1, $src2",
3334 (FACGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3336 //===----------------------------------------------------------------------===//
3337 // Advanced SIMD three scalar instructions (mixed operands).
3338 //===----------------------------------------------------------------------===//
3339 defm SQDMULL : SIMDThreeScalarMixedHS<0, 0b11010, "sqdmull",
3340 int_aarch64_neon_sqdmulls_scalar>;
3341 defm SQDMLAL : SIMDThreeScalarMixedTiedHS<0, 0b10010, "sqdmlal">;
3342 defm SQDMLSL : SIMDThreeScalarMixedTiedHS<0, 0b10110, "sqdmlsl">;
3344 def : Pat<(i64 (int_aarch64_neon_sqadd (i64 FPR64:$Rd),
3345 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
3346 (i32 FPR32:$Rm))))),
3347 (SQDMLALi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3348 def : Pat<(i64 (int_aarch64_neon_sqsub (i64 FPR64:$Rd),
3349 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
3350 (i32 FPR32:$Rm))))),
3351 (SQDMLSLi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3353 //===----------------------------------------------------------------------===//
3354 // Advanced SIMD two scalar instructions.
3355 //===----------------------------------------------------------------------===//
3357 defm ABS : SIMDTwoScalarD< 0, 0b01011, "abs", int_aarch64_neon_abs>;
3358 defm CMEQ : SIMDCmpTwoScalarD< 0, 0b01001, "cmeq", AArch64cmeqz>;
3359 defm CMGE : SIMDCmpTwoScalarD< 1, 0b01000, "cmge", AArch64cmgez>;
3360 defm CMGT : SIMDCmpTwoScalarD< 0, 0b01000, "cmgt", AArch64cmgtz>;
3361 defm CMLE : SIMDCmpTwoScalarD< 1, 0b01001, "cmle", AArch64cmlez>;
3362 defm CMLT : SIMDCmpTwoScalarD< 0, 0b01010, "cmlt", AArch64cmltz>;
3363 defm FCMEQ : SIMDFPCmpTwoScalar<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>;
3364 defm FCMGE : SIMDFPCmpTwoScalar<1, 1, 0b01100, "fcmge", AArch64fcmgez>;
3365 defm FCMGT : SIMDFPCmpTwoScalar<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>;
3366 defm FCMLE : SIMDFPCmpTwoScalar<1, 1, 0b01101, "fcmle", AArch64fcmlez>;
3367 defm FCMLT : SIMDFPCmpTwoScalar<0, 1, 0b01110, "fcmlt", AArch64fcmltz>;
3368 defm FCVTAS : SIMDFPTwoScalar< 0, 0, 0b11100, "fcvtas">;
3369 defm FCVTAU : SIMDFPTwoScalar< 1, 0, 0b11100, "fcvtau">;
3370 defm FCVTMS : SIMDFPTwoScalar< 0, 0, 0b11011, "fcvtms">;
3371 defm FCVTMU : SIMDFPTwoScalar< 1, 0, 0b11011, "fcvtmu">;
3372 defm FCVTNS : SIMDFPTwoScalar< 0, 0, 0b11010, "fcvtns">;
3373 defm FCVTNU : SIMDFPTwoScalar< 1, 0, 0b11010, "fcvtnu">;
3374 defm FCVTPS : SIMDFPTwoScalar< 0, 1, 0b11010, "fcvtps">;
3375 defm FCVTPU : SIMDFPTwoScalar< 1, 1, 0b11010, "fcvtpu">;
3376 def FCVTXNv1i64 : SIMDInexactCvtTwoScalar<0b10110, "fcvtxn">;
3377 defm FCVTZS : SIMDFPTwoScalar< 0, 1, 0b11011, "fcvtzs">;
3378 defm FCVTZU : SIMDFPTwoScalar< 1, 1, 0b11011, "fcvtzu">;
3379 defm FRECPE : SIMDFPTwoScalar< 0, 1, 0b11101, "frecpe">;
3380 defm FRECPX : SIMDFPTwoScalar< 0, 1, 0b11111, "frecpx">;
3381 defm FRSQRTE : SIMDFPTwoScalar< 1, 1, 0b11101, "frsqrte">;
3382 defm NEG : SIMDTwoScalarD< 1, 0b01011, "neg",
3383 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
3384 defm SCVTF : SIMDFPTwoScalarCVT< 0, 0, 0b11101, "scvtf", AArch64sitof>;
3385 defm SQABS : SIMDTwoScalarBHSD< 0, 0b00111, "sqabs", int_aarch64_neon_sqabs>;
3386 defm SQNEG : SIMDTwoScalarBHSD< 1, 0b00111, "sqneg", int_aarch64_neon_sqneg>;
3387 defm SQXTN : SIMDTwoScalarMixedBHS< 0, 0b10100, "sqxtn", int_aarch64_neon_scalar_sqxtn>;
3388 defm SQXTUN : SIMDTwoScalarMixedBHS< 1, 0b10010, "sqxtun", int_aarch64_neon_scalar_sqxtun>;
3389 defm SUQADD : SIMDTwoScalarBHSDTied< 0, 0b00011, "suqadd",
3390 int_aarch64_neon_suqadd>;
3391 defm UCVTF : SIMDFPTwoScalarCVT< 1, 0, 0b11101, "ucvtf", AArch64uitof>;
3392 defm UQXTN : SIMDTwoScalarMixedBHS<1, 0b10100, "uqxtn", int_aarch64_neon_scalar_uqxtn>;
3393 defm USQADD : SIMDTwoScalarBHSDTied< 1, 0b00011, "usqadd",
3394 int_aarch64_neon_usqadd>;
3396 def : Pat<(AArch64neg (v1i64 V64:$Rn)), (NEGv1i64 V64:$Rn)>;
3398 def : Pat<(v1i64 (int_aarch64_neon_fcvtas (v1f64 FPR64:$Rn))),
3399 (FCVTASv1i64 FPR64:$Rn)>;
3400 def : Pat<(v1i64 (int_aarch64_neon_fcvtau (v1f64 FPR64:$Rn))),
3401 (FCVTAUv1i64 FPR64:$Rn)>;
3402 def : Pat<(v1i64 (int_aarch64_neon_fcvtms (v1f64 FPR64:$Rn))),
3403 (FCVTMSv1i64 FPR64:$Rn)>;
3404 def : Pat<(v1i64 (int_aarch64_neon_fcvtmu (v1f64 FPR64:$Rn))),
3405 (FCVTMUv1i64 FPR64:$Rn)>;
3406 def : Pat<(v1i64 (int_aarch64_neon_fcvtns (v1f64 FPR64:$Rn))),
3407 (FCVTNSv1i64 FPR64:$Rn)>;
3408 def : Pat<(v1i64 (int_aarch64_neon_fcvtnu (v1f64 FPR64:$Rn))),
3409 (FCVTNUv1i64 FPR64:$Rn)>;
3410 def : Pat<(v1i64 (int_aarch64_neon_fcvtps (v1f64 FPR64:$Rn))),
3411 (FCVTPSv1i64 FPR64:$Rn)>;
3412 def : Pat<(v1i64 (int_aarch64_neon_fcvtpu (v1f64 FPR64:$Rn))),
3413 (FCVTPUv1i64 FPR64:$Rn)>;
3415 def : Pat<(f32 (int_aarch64_neon_frecpe (f32 FPR32:$Rn))),
3416 (FRECPEv1i32 FPR32:$Rn)>;
3417 def : Pat<(f64 (int_aarch64_neon_frecpe (f64 FPR64:$Rn))),
3418 (FRECPEv1i64 FPR64:$Rn)>;
3419 def : Pat<(v1f64 (int_aarch64_neon_frecpe (v1f64 FPR64:$Rn))),
3420 (FRECPEv1i64 FPR64:$Rn)>;
3422 def : Pat<(f32 (AArch64frecpe (f32 FPR32:$Rn))),
3423 (FRECPEv1i32 FPR32:$Rn)>;
3424 def : Pat<(v2f32 (AArch64frecpe (v2f32 V64:$Rn))),
3425 (FRECPEv2f32 V64:$Rn)>;
3426 def : Pat<(v4f32 (AArch64frecpe (v4f32 FPR128:$Rn))),
3427 (FRECPEv4f32 FPR128:$Rn)>;
3428 def : Pat<(f64 (AArch64frecpe (f64 FPR64:$Rn))),
3429 (FRECPEv1i64 FPR64:$Rn)>;
3430 def : Pat<(v1f64 (AArch64frecpe (v1f64 FPR64:$Rn))),
3431 (FRECPEv1i64 FPR64:$Rn)>;
3432 def : Pat<(v2f64 (AArch64frecpe (v2f64 FPR128:$Rn))),
3433 (FRECPEv2f64 FPR128:$Rn)>;
3435 def : Pat<(f32 (AArch64frecps (f32 FPR32:$Rn), (f32 FPR32:$Rm))),
3436 (FRECPS32 FPR32:$Rn, FPR32:$Rm)>;
3437 def : Pat<(v2f32 (AArch64frecps (v2f32 V64:$Rn), (v2f32 V64:$Rm))),
3438 (FRECPSv2f32 V64:$Rn, V64:$Rm)>;
3439 def : Pat<(v4f32 (AArch64frecps (v4f32 FPR128:$Rn), (v4f32 FPR128:$Rm))),
3440 (FRECPSv4f32 FPR128:$Rn, FPR128:$Rm)>;
3441 def : Pat<(f64 (AArch64frecps (f64 FPR64:$Rn), (f64 FPR64:$Rm))),
3442 (FRECPS64 FPR64:$Rn, FPR64:$Rm)>;
3443 def : Pat<(v2f64 (AArch64frecps (v2f64 FPR128:$Rn), (v2f64 FPR128:$Rm))),
3444 (FRECPSv2f64 FPR128:$Rn, FPR128:$Rm)>;
3446 def : Pat<(f32 (int_aarch64_neon_frecpx (f32 FPR32:$Rn))),
3447 (FRECPXv1i32 FPR32:$Rn)>;
3448 def : Pat<(f64 (int_aarch64_neon_frecpx (f64 FPR64:$Rn))),
3449 (FRECPXv1i64 FPR64:$Rn)>;
3451 def : Pat<(f32 (int_aarch64_neon_frsqrte (f32 FPR32:$Rn))),
3452 (FRSQRTEv1i32 FPR32:$Rn)>;
3453 def : Pat<(f64 (int_aarch64_neon_frsqrte (f64 FPR64:$Rn))),
3454 (FRSQRTEv1i64 FPR64:$Rn)>;
3455 def : Pat<(v1f64 (int_aarch64_neon_frsqrte (v1f64 FPR64:$Rn))),
3456 (FRSQRTEv1i64 FPR64:$Rn)>;
3458 def : Pat<(f32 (AArch64frsqrte (f32 FPR32:$Rn))),
3459 (FRSQRTEv1i32 FPR32:$Rn)>;
3460 def : Pat<(v2f32 (AArch64frsqrte (v2f32 V64:$Rn))),
3461 (FRSQRTEv2f32 V64:$Rn)>;
3462 def : Pat<(v4f32 (AArch64frsqrte (v4f32 FPR128:$Rn))),
3463 (FRSQRTEv4f32 FPR128:$Rn)>;
3464 def : Pat<(f64 (AArch64frsqrte (f64 FPR64:$Rn))),
3465 (FRSQRTEv1i64 FPR64:$Rn)>;
3466 def : Pat<(v1f64 (AArch64frsqrte (v1f64 FPR64:$Rn))),
3467 (FRSQRTEv1i64 FPR64:$Rn)>;
3468 def : Pat<(v2f64 (AArch64frsqrte (v2f64 FPR128:$Rn))),
3469 (FRSQRTEv2f64 FPR128:$Rn)>;
3471 def : Pat<(f32 (AArch64frsqrts (f32 FPR32:$Rn), (f32 FPR32:$Rm))),
3472 (FRSQRTS32 FPR32:$Rn, FPR32:$Rm)>;
3473 def : Pat<(v2f32 (AArch64frsqrts (v2f32 V64:$Rn), (v2f32 V64:$Rm))),
3474 (FRSQRTSv2f32 V64:$Rn, V64:$Rm)>;
3475 def : Pat<(v4f32 (AArch64frsqrts (v4f32 FPR128:$Rn), (v4f32 FPR128:$Rm))),
3476 (FRSQRTSv4f32 FPR128:$Rn, FPR128:$Rm)>;
3477 def : Pat<(f64 (AArch64frsqrts (f64 FPR64:$Rn), (f64 FPR64:$Rm))),
3478 (FRSQRTS64 FPR64:$Rn, FPR64:$Rm)>;
3479 def : Pat<(v2f64 (AArch64frsqrts (v2f64 FPR128:$Rn), (v2f64 FPR128:$Rm))),
3480 (FRSQRTSv2f64 FPR128:$Rn, FPR128:$Rm)>;
3482 // If an integer is about to be converted to a floating point value,
3483 // just load it on the floating point unit.
3484 // Here are the patterns for 8 and 16-bits to float.
3486 multiclass UIntToFPROLoadPat<ValueType DstTy, ValueType SrcTy,
3487 SDPatternOperator loadop, Instruction UCVTF,
3488 ROAddrMode ro, Instruction LDRW, Instruction LDRX,
3490 def : Pat<(DstTy (uint_to_fp (SrcTy
3491 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm,
3492 ro.Wext:$extend))))),
3493 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
3494 (LDRW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend),
3497 def : Pat<(DstTy (uint_to_fp (SrcTy
3498 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm,
3499 ro.Wext:$extend))))),
3500 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
3501 (LDRX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend),
3505 defm : UIntToFPROLoadPat<f32, i32, zextloadi8,
3506 UCVTFv1i32, ro8, LDRBroW, LDRBroX, bsub>;
3507 def : Pat <(f32 (uint_to_fp (i32
3508 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
3509 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3510 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>;
3511 def : Pat <(f32 (uint_to_fp (i32
3512 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),
3513 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3514 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>;
3515 // 16-bits -> float.
3516 defm : UIntToFPROLoadPat<f32, i32, zextloadi16,
3517 UCVTFv1i32, ro16, LDRHroW, LDRHroX, hsub>;
3518 def : Pat <(f32 (uint_to_fp (i32
3519 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
3520 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3521 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
3522 def : Pat <(f32 (uint_to_fp (i32
3523 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),
3524 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3525 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;
3526 // 32-bits are handled in target specific dag combine:
3527 // performIntToFpCombine.
3528 // 64-bits integer to 32-bits floating point, not possible with
3529 // UCVTF on floating point registers (both source and destination
3530 // must have the same size).
3532 // Here are the patterns for 8, 16, 32, and 64-bits to double.
3533 // 8-bits -> double.
3534 defm : UIntToFPROLoadPat<f64, i32, zextloadi8,
3535 UCVTFv1i64, ro8, LDRBroW, LDRBroX, bsub>;
3536 def : Pat <(f64 (uint_to_fp (i32
3537 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
3538 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3539 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>;
3540 def : Pat <(f64 (uint_to_fp (i32
3541 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),
3542 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3543 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>;
3544 // 16-bits -> double.
3545 defm : UIntToFPROLoadPat<f64, i32, zextloadi16,
3546 UCVTFv1i64, ro16, LDRHroW, LDRHroX, hsub>;
3547 def : Pat <(f64 (uint_to_fp (i32
3548 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
3549 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3550 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
3551 def : Pat <(f64 (uint_to_fp (i32
3552 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),
3553 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3554 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;
3555 // 32-bits -> double.
3556 defm : UIntToFPROLoadPat<f64, i32, load,
3557 UCVTFv1i64, ro32, LDRSroW, LDRSroX, ssub>;
3558 def : Pat <(f64 (uint_to_fp (i32
3559 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
3560 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3561 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub))>;
3562 def : Pat <(f64 (uint_to_fp (i32
3563 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset))))),
3564 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3565 (LDURSi GPR64sp:$Rn, simm9:$offset), ssub))>;
3566 // 64-bits -> double are handled in target specific dag combine:
3567 // performIntToFpCombine.
3569 //===----------------------------------------------------------------------===//
3570 // Advanced SIMD three different-sized vector instructions.
3571 //===----------------------------------------------------------------------===//
3573 defm ADDHN : SIMDNarrowThreeVectorBHS<0,0b0100,"addhn", int_aarch64_neon_addhn>;
3574 defm SUBHN : SIMDNarrowThreeVectorBHS<0,0b0110,"subhn", int_aarch64_neon_subhn>;
3575 defm RADDHN : SIMDNarrowThreeVectorBHS<1,0b0100,"raddhn",int_aarch64_neon_raddhn>;
3576 defm RSUBHN : SIMDNarrowThreeVectorBHS<1,0b0110,"rsubhn",int_aarch64_neon_rsubhn>;
3577 defm PMULL : SIMDDifferentThreeVectorBD<0,0b1110,"pmull",int_aarch64_neon_pmull>;
3578 defm SABAL : SIMDLongThreeVectorTiedBHSabal<0,0b0101,"sabal",
3579 int_aarch64_neon_sabd>;
3580 defm SABDL : SIMDLongThreeVectorBHSabdl<0, 0b0111, "sabdl",
3581 int_aarch64_neon_sabd>;
3582 defm SADDL : SIMDLongThreeVectorBHS< 0, 0b0000, "saddl",
3583 BinOpFrag<(add (sext node:$LHS), (sext node:$RHS))>>;
3584 defm SADDW : SIMDWideThreeVectorBHS< 0, 0b0001, "saddw",
3585 BinOpFrag<(add node:$LHS, (sext node:$RHS))>>;
3586 defm SMLAL : SIMDLongThreeVectorTiedBHS<0, 0b1000, "smlal",
3587 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
3588 defm SMLSL : SIMDLongThreeVectorTiedBHS<0, 0b1010, "smlsl",
3589 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
3590 defm SMULL : SIMDLongThreeVectorBHS<0, 0b1100, "smull", int_aarch64_neon_smull>;
3591 defm SQDMLAL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1001, "sqdmlal",
3592 int_aarch64_neon_sqadd>;
3593 defm SQDMLSL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1011, "sqdmlsl",
3594 int_aarch64_neon_sqsub>;
3595 defm SQDMULL : SIMDLongThreeVectorHS<0, 0b1101, "sqdmull",
3596 int_aarch64_neon_sqdmull>;
3597 defm SSUBL : SIMDLongThreeVectorBHS<0, 0b0010, "ssubl",
3598 BinOpFrag<(sub (sext node:$LHS), (sext node:$RHS))>>;
3599 defm SSUBW : SIMDWideThreeVectorBHS<0, 0b0011, "ssubw",
3600 BinOpFrag<(sub node:$LHS, (sext node:$RHS))>>;
3601 defm UABAL : SIMDLongThreeVectorTiedBHSabal<1, 0b0101, "uabal",
3602 int_aarch64_neon_uabd>;
3603 defm UADDL : SIMDLongThreeVectorBHS<1, 0b0000, "uaddl",
3604 BinOpFrag<(add (zext node:$LHS), (zext node:$RHS))>>;
3605 defm UADDW : SIMDWideThreeVectorBHS<1, 0b0001, "uaddw",
3606 BinOpFrag<(add node:$LHS, (zext node:$RHS))>>;
3607 defm UMLAL : SIMDLongThreeVectorTiedBHS<1, 0b1000, "umlal",
3608 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
3609 defm UMLSL : SIMDLongThreeVectorTiedBHS<1, 0b1010, "umlsl",
3610 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
3611 defm UMULL : SIMDLongThreeVectorBHS<1, 0b1100, "umull", int_aarch64_neon_umull>;
3612 defm USUBL : SIMDLongThreeVectorBHS<1, 0b0010, "usubl",
3613 BinOpFrag<(sub (zext node:$LHS), (zext node:$RHS))>>;
3614 defm USUBW : SIMDWideThreeVectorBHS< 1, 0b0011, "usubw",
3615 BinOpFrag<(sub node:$LHS, (zext node:$RHS))>>;
3617 // Additional patterns for SMULL and UMULL
3618 multiclass Neon_mul_widen_patterns<SDPatternOperator opnode,
3619 Instruction INST8B, Instruction INST4H, Instruction INST2S> {
3620 def : Pat<(v8i16 (opnode (v8i8 V64:$Rn), (v8i8 V64:$Rm))),
3621 (INST8B V64:$Rn, V64:$Rm)>;
3622 def : Pat<(v4i32 (opnode (v4i16 V64:$Rn), (v4i16 V64:$Rm))),
3623 (INST4H V64:$Rn, V64:$Rm)>;
3624 def : Pat<(v2i64 (opnode (v2i32 V64:$Rn), (v2i32 V64:$Rm))),
3625 (INST2S V64:$Rn, V64:$Rm)>;
3628 defm : Neon_mul_widen_patterns<AArch64smull, SMULLv8i8_v8i16,
3629 SMULLv4i16_v4i32, SMULLv2i32_v2i64>;
3630 defm : Neon_mul_widen_patterns<AArch64umull, UMULLv8i8_v8i16,
3631 UMULLv4i16_v4i32, UMULLv2i32_v2i64>;
3633 // Additional patterns for SMLAL/SMLSL and UMLAL/UMLSL
3634 multiclass Neon_mulacc_widen_patterns<SDPatternOperator opnode,
3635 Instruction INST8B, Instruction INST4H, Instruction INST2S> {
3636 def : Pat<(v8i16 (opnode (v8i16 V128:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm))),
3637 (INST8B V128:$Rd, V64:$Rn, V64:$Rm)>;
3638 def : Pat<(v4i32 (opnode (v4i32 V128:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm))),
3639 (INST4H V128:$Rd, V64:$Rn, V64:$Rm)>;
3640 def : Pat<(v2i64 (opnode (v2i64 V128:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm))),
3641 (INST2S V128:$Rd, V64:$Rn, V64:$Rm)>;
3644 defm : Neon_mulacc_widen_patterns<
3645 TriOpFrag<(add node:$LHS, (AArch64smull node:$MHS, node:$RHS))>,
3646 SMLALv8i8_v8i16, SMLALv4i16_v4i32, SMLALv2i32_v2i64>;
3647 defm : Neon_mulacc_widen_patterns<
3648 TriOpFrag<(add node:$LHS, (AArch64umull node:$MHS, node:$RHS))>,
3649 UMLALv8i8_v8i16, UMLALv4i16_v4i32, UMLALv2i32_v2i64>;
3650 defm : Neon_mulacc_widen_patterns<
3651 TriOpFrag<(sub node:$LHS, (AArch64smull node:$MHS, node:$RHS))>,
3652 SMLSLv8i8_v8i16, SMLSLv4i16_v4i32, SMLSLv2i32_v2i64>;
3653 defm : Neon_mulacc_widen_patterns<
3654 TriOpFrag<(sub node:$LHS, (AArch64umull node:$MHS, node:$RHS))>,
3655 UMLSLv8i8_v8i16, UMLSLv4i16_v4i32, UMLSLv2i32_v2i64>;
3657 // Patterns for 64-bit pmull
3658 def : Pat<(int_aarch64_neon_pmull64 V64:$Rn, V64:$Rm),
3659 (PMULLv1i64 V64:$Rn, V64:$Rm)>;
3660 def : Pat<(int_aarch64_neon_pmull64 (extractelt (v2i64 V128:$Rn), (i64 1)),
3661 (extractelt (v2i64 V128:$Rm), (i64 1))),
3662 (PMULLv2i64 V128:$Rn, V128:$Rm)>;
3664 // CodeGen patterns for addhn and subhn instructions, which can actually be
3665 // written in LLVM IR without too much difficulty.
3668 def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm), (i32 8))))),
3669 (ADDHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
3670 def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3672 (ADDHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
3673 def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3675 (ADDHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
3676 def : Pat<(concat_vectors (v8i8 V64:$Rd),
3677 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3679 (ADDHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3680 V128:$Rn, V128:$Rm)>;
3681 def : Pat<(concat_vectors (v4i16 V64:$Rd),
3682 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3684 (ADDHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3685 V128:$Rn, V128:$Rm)>;
3686 def : Pat<(concat_vectors (v2i32 V64:$Rd),
3687 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3689 (ADDHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3690 V128:$Rn, V128:$Rm)>;
3693 def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm), (i32 8))))),
3694 (SUBHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
3695 def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3697 (SUBHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
3698 def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3700 (SUBHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
3701 def : Pat<(concat_vectors (v8i8 V64:$Rd),
3702 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3704 (SUBHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3705 V128:$Rn, V128:$Rm)>;
3706 def : Pat<(concat_vectors (v4i16 V64:$Rd),
3707 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3709 (SUBHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3710 V128:$Rn, V128:$Rm)>;
3711 def : Pat<(concat_vectors (v2i32 V64:$Rd),
3712 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3714 (SUBHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3715 V128:$Rn, V128:$Rm)>;
3717 //----------------------------------------------------------------------------
3718 // AdvSIMD bitwise extract from vector instruction.
3719 //----------------------------------------------------------------------------
3721 defm EXT : SIMDBitwiseExtract<"ext">;
3723 def : Pat<(v4i16 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3724 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3725 def : Pat<(v8i16 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3726 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3727 def : Pat<(v2i32 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3728 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3729 def : Pat<(v2f32 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3730 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3731 def : Pat<(v4i32 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3732 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3733 def : Pat<(v4f32 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3734 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3735 def : Pat<(v2i64 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3736 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3737 def : Pat<(v2f64 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3738 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3739 def : Pat<(v4f16 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3740 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3741 def : Pat<(v8f16 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3742 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3744 // We use EXT to handle extract_subvector to copy the upper 64-bits of a
3746 def : Pat<(v8i8 (extract_subvector V128:$Rn, (i64 8))),
3747 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3748 def : Pat<(v4i16 (extract_subvector V128:$Rn, (i64 4))),
3749 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3750 def : Pat<(v2i32 (extract_subvector V128:$Rn, (i64 2))),
3751 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3752 def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 1))),
3753 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3754 def : Pat<(v4f16 (extract_subvector V128:$Rn, (i64 4))),
3755 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3756 def : Pat<(v2f32 (extract_subvector V128:$Rn, (i64 2))),
3757 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3758 def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 1))),
3759 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3762 //----------------------------------------------------------------------------
3763 // AdvSIMD zip vector
3764 //----------------------------------------------------------------------------
3766 defm TRN1 : SIMDZipVector<0b010, "trn1", AArch64trn1>;
3767 defm TRN2 : SIMDZipVector<0b110, "trn2", AArch64trn2>;
3768 defm UZP1 : SIMDZipVector<0b001, "uzp1", AArch64uzp1>;
3769 defm UZP2 : SIMDZipVector<0b101, "uzp2", AArch64uzp2>;
3770 defm ZIP1 : SIMDZipVector<0b011, "zip1", AArch64zip1>;
3771 defm ZIP2 : SIMDZipVector<0b111, "zip2", AArch64zip2>;
3773 //----------------------------------------------------------------------------
3774 // AdvSIMD TBL/TBX instructions
3775 //----------------------------------------------------------------------------
3777 defm TBL : SIMDTableLookup< 0, "tbl">;
3778 defm TBX : SIMDTableLookupTied<1, "tbx">;
3780 def : Pat<(v8i8 (int_aarch64_neon_tbl1 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
3781 (TBLv8i8One VecListOne128:$Rn, V64:$Ri)>;
3782 def : Pat<(v16i8 (int_aarch64_neon_tbl1 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
3783 (TBLv16i8One V128:$Ri, V128:$Rn)>;
3785 def : Pat<(v8i8 (int_aarch64_neon_tbx1 (v8i8 V64:$Rd),
3786 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
3787 (TBXv8i8One V64:$Rd, VecListOne128:$Rn, V64:$Ri)>;
3788 def : Pat<(v16i8 (int_aarch64_neon_tbx1 (v16i8 V128:$Rd),
3789 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
3790 (TBXv16i8One V128:$Rd, V128:$Ri, V128:$Rn)>;
3793 //----------------------------------------------------------------------------
3794 // AdvSIMD scalar CPY instruction
3795 //----------------------------------------------------------------------------
3797 defm CPY : SIMDScalarCPY<"cpy">;
3799 //----------------------------------------------------------------------------
3800 // AdvSIMD scalar pairwise instructions
3801 //----------------------------------------------------------------------------
3803 defm ADDP : SIMDPairwiseScalarD<0, 0b11011, "addp">;
3804 defm FADDP : SIMDFPPairwiseScalar<0, 0b01101, "faddp">;
3805 defm FMAXNMP : SIMDFPPairwiseScalar<0, 0b01100, "fmaxnmp">;
3806 defm FMAXP : SIMDFPPairwiseScalar<0, 0b01111, "fmaxp">;
3807 defm FMINNMP : SIMDFPPairwiseScalar<1, 0b01100, "fminnmp">;
3808 defm FMINP : SIMDFPPairwiseScalar<1, 0b01111, "fminp">;
3809 def : Pat<(v2i64 (AArch64saddv V128:$Rn)),
3810 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), (ADDPv2i64p V128:$Rn), dsub)>;
3811 def : Pat<(v2i64 (AArch64uaddv V128:$Rn)),
3812 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), (ADDPv2i64p V128:$Rn), dsub)>;
3813 def : Pat<(f32 (int_aarch64_neon_faddv (v2f32 V64:$Rn))),
3814 (FADDPv2i32p V64:$Rn)>;
3815 def : Pat<(f32 (int_aarch64_neon_faddv (v4f32 V128:$Rn))),
3816 (FADDPv2i32p (EXTRACT_SUBREG (FADDPv4f32 V128:$Rn, V128:$Rn), dsub))>;
3817 def : Pat<(f64 (int_aarch64_neon_faddv (v2f64 V128:$Rn))),
3818 (FADDPv2i64p V128:$Rn)>;
3819 def : Pat<(f32 (int_aarch64_neon_fmaxnmv (v2f32 V64:$Rn))),
3820 (FMAXNMPv2i32p V64:$Rn)>;
3821 def : Pat<(f64 (int_aarch64_neon_fmaxnmv (v2f64 V128:$Rn))),
3822 (FMAXNMPv2i64p V128:$Rn)>;
3823 def : Pat<(f32 (int_aarch64_neon_fmaxv (v2f32 V64:$Rn))),
3824 (FMAXPv2i32p V64:$Rn)>;
3825 def : Pat<(f64 (int_aarch64_neon_fmaxv (v2f64 V128:$Rn))),
3826 (FMAXPv2i64p V128:$Rn)>;
3827 def : Pat<(f32 (int_aarch64_neon_fminnmv (v2f32 V64:$Rn))),
3828 (FMINNMPv2i32p V64:$Rn)>;
3829 def : Pat<(f64 (int_aarch64_neon_fminnmv (v2f64 V128:$Rn))),
3830 (FMINNMPv2i64p V128:$Rn)>;
3831 def : Pat<(f32 (int_aarch64_neon_fminv (v2f32 V64:$Rn))),
3832 (FMINPv2i32p V64:$Rn)>;
3833 def : Pat<(f64 (int_aarch64_neon_fminv (v2f64 V128:$Rn))),
3834 (FMINPv2i64p V128:$Rn)>;
3836 //----------------------------------------------------------------------------
3837 // AdvSIMD INS/DUP instructions
3838 //----------------------------------------------------------------------------
3840 def DUPv8i8gpr : SIMDDupFromMain<0, {?,?,?,?,1}, ".8b", v8i8, V64, GPR32>;
3841 def DUPv16i8gpr : SIMDDupFromMain<1, {?,?,?,?,1}, ".16b", v16i8, V128, GPR32>;
3842 def DUPv4i16gpr : SIMDDupFromMain<0, {?,?,?,1,0}, ".4h", v4i16, V64, GPR32>;
3843 def DUPv8i16gpr : SIMDDupFromMain<1, {?,?,?,1,0}, ".8h", v8i16, V128, GPR32>;
3844 def DUPv2i32gpr : SIMDDupFromMain<0, {?,?,1,0,0}, ".2s", v2i32, V64, GPR32>;
3845 def DUPv4i32gpr : SIMDDupFromMain<1, {?,?,1,0,0}, ".4s", v4i32, V128, GPR32>;
3846 def DUPv2i64gpr : SIMDDupFromMain<1, {?,1,0,0,0}, ".2d", v2i64, V128, GPR64>;
3848 def DUPv2i64lane : SIMDDup64FromElement;
3849 def DUPv2i32lane : SIMDDup32FromElement<0, ".2s", v2i32, V64>;
3850 def DUPv4i32lane : SIMDDup32FromElement<1, ".4s", v4i32, V128>;
3851 def DUPv4i16lane : SIMDDup16FromElement<0, ".4h", v4i16, V64>;
3852 def DUPv8i16lane : SIMDDup16FromElement<1, ".8h", v8i16, V128>;
3853 def DUPv8i8lane : SIMDDup8FromElement <0, ".8b", v8i8, V64>;
3854 def DUPv16i8lane : SIMDDup8FromElement <1, ".16b", v16i8, V128>;
3856 def : Pat<(v2f32 (AArch64dup (f32 FPR32:$Rn))),
3857 (v2f32 (DUPv2i32lane
3858 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3860 def : Pat<(v4f32 (AArch64dup (f32 FPR32:$Rn))),
3861 (v4f32 (DUPv4i32lane
3862 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3864 def : Pat<(v2f64 (AArch64dup (f64 FPR64:$Rn))),
3865 (v2f64 (DUPv2i64lane
3866 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rn, dsub),
3868 def : Pat<(v4f16 (AArch64dup (f16 FPR16:$Rn))),
3869 (v4f16 (DUPv4i16lane
3870 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub),
3872 def : Pat<(v8f16 (AArch64dup (f16 FPR16:$Rn))),
3873 (v8f16 (DUPv8i16lane
3874 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub),
3877 def : Pat<(v4f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)),
3878 (DUPv4i16lane V128:$Rn, VectorIndexH:$imm)>;
3879 def : Pat<(v8f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)),
3880 (DUPv8i16lane V128:$Rn, VectorIndexH:$imm)>;
3882 def : Pat<(v2f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3883 (DUPv2i32lane V128:$Rn, VectorIndexS:$imm)>;
3884 def : Pat<(v4f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3885 (DUPv4i32lane V128:$Rn, VectorIndexS:$imm)>;
3886 def : Pat<(v2f64 (AArch64duplane64 (v2f64 V128:$Rn), VectorIndexD:$imm)),
3887 (DUPv2i64lane V128:$Rn, VectorIndexD:$imm)>;
3889 // If there's an (AArch64dup (vector_extract ...) ...), we can use a duplane
3890 // instruction even if the types don't match: we just have to remap the lane
3891 // carefully. N.b. this trick only applies to truncations.
3892 def VecIndex_x2 : SDNodeXForm<imm, [{
3893 return CurDAG->getTargetConstant(2 * N->getZExtValue(), SDLoc(N), MVT::i64);
3895 def VecIndex_x4 : SDNodeXForm<imm, [{
3896 return CurDAG->getTargetConstant(4 * N->getZExtValue(), SDLoc(N), MVT::i64);
3898 def VecIndex_x8 : SDNodeXForm<imm, [{
3899 return CurDAG->getTargetConstant(8 * N->getZExtValue(), SDLoc(N), MVT::i64);
3902 multiclass DUPWithTruncPats<ValueType ResVT, ValueType Src64VT,
3903 ValueType Src128VT, ValueType ScalVT,
3904 Instruction DUP, SDNodeXForm IdxXFORM> {
3905 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src128VT V128:$Rn),
3907 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3909 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src64VT V64:$Rn),
3911 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3914 defm : DUPWithTruncPats<v8i8, v4i16, v8i16, i32, DUPv8i8lane, VecIndex_x2>;
3915 defm : DUPWithTruncPats<v8i8, v2i32, v4i32, i32, DUPv8i8lane, VecIndex_x4>;
3916 defm : DUPWithTruncPats<v4i16, v2i32, v4i32, i32, DUPv4i16lane, VecIndex_x2>;
3918 defm : DUPWithTruncPats<v16i8, v4i16, v8i16, i32, DUPv16i8lane, VecIndex_x2>;
3919 defm : DUPWithTruncPats<v16i8, v2i32, v4i32, i32, DUPv16i8lane, VecIndex_x4>;
3920 defm : DUPWithTruncPats<v8i16, v2i32, v4i32, i32, DUPv8i16lane, VecIndex_x2>;
3922 multiclass DUPWithTrunci64Pats<ValueType ResVT, Instruction DUP,
3923 SDNodeXForm IdxXFORM> {
3924 def : Pat<(ResVT (AArch64dup (i32 (trunc (extractelt (v2i64 V128:$Rn),
3926 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3928 def : Pat<(ResVT (AArch64dup (i32 (trunc (extractelt (v1i64 V64:$Rn),
3930 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3933 defm : DUPWithTrunci64Pats<v8i8, DUPv8i8lane, VecIndex_x8>;
3934 defm : DUPWithTrunci64Pats<v4i16, DUPv4i16lane, VecIndex_x4>;
3935 defm : DUPWithTrunci64Pats<v2i32, DUPv2i32lane, VecIndex_x2>;
3937 defm : DUPWithTrunci64Pats<v16i8, DUPv16i8lane, VecIndex_x8>;
3938 defm : DUPWithTrunci64Pats<v8i16, DUPv8i16lane, VecIndex_x4>;
3939 defm : DUPWithTrunci64Pats<v4i32, DUPv4i32lane, VecIndex_x2>;
3941 // SMOV and UMOV definitions, with some extra patterns for convenience
3945 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3946 (i32 (SMOVvi8to32 V128:$Rn, VectorIndexB:$idx))>;
3947 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3948 (i64 (SMOVvi8to64 V128:$Rn, VectorIndexB:$idx))>;
3949 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3950 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3951 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3952 (i64 (SMOVvi16to64 V128:$Rn, VectorIndexH:$idx))>;
3953 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3954 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3955 def : Pat<(sext (i32 (vector_extract (v4i32 V128:$Rn), VectorIndexS:$idx))),
3956 (i64 (SMOVvi32to64 V128:$Rn, VectorIndexS:$idx))>;
3958 def : Pat<(sext_inreg (i64 (anyext (i32 (vector_extract (v16i8 V128:$Rn),
3959 VectorIndexB:$idx)))), i8),
3960 (i64 (SMOVvi8to64 V128:$Rn, VectorIndexB:$idx))>;
3961 def : Pat<(sext_inreg (i64 (anyext (i32 (vector_extract (v8i16 V128:$Rn),
3962 VectorIndexH:$idx)))), i16),
3963 (i64 (SMOVvi16to64 V128:$Rn, VectorIndexH:$idx))>;
3965 // Extracting i8 or i16 elements will have the zero-extend transformed to
3966 // an 'and' mask by type legalization since neither i8 nor i16 are legal types
3967 // for AArch64. Match these patterns here since UMOV already zeroes out the high
3968 // bits of the destination register.
3969 def : Pat<(and (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx),
3971 (i32 (UMOVvi8 V128:$Rn, VectorIndexB:$idx))>;
3972 def : Pat<(and (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),
3974 (i32 (UMOVvi16 V128:$Rn, VectorIndexH:$idx))>;
3978 def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)),
3979 (SUBREG_TO_REG (i32 0),
3980 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3981 def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)),
3982 (SUBREG_TO_REG (i32 0),
3983 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3985 def : Pat<(v8i16 (scalar_to_vector GPR32:$Rn)),
3986 (SUBREG_TO_REG (i32 0),
3987 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3988 def : Pat<(v4i16 (scalar_to_vector GPR32:$Rn)),
3989 (SUBREG_TO_REG (i32 0),
3990 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3992 def : Pat<(v2i32 (scalar_to_vector (i32 FPR32:$Rn))),
3993 (v2i32 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
3994 (i32 FPR32:$Rn), ssub))>;
3995 def : Pat<(v4i32 (scalar_to_vector (i32 FPR32:$Rn))),
3996 (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3997 (i32 FPR32:$Rn), ssub))>;
3998 def : Pat<(v2i64 (scalar_to_vector (i64 FPR64:$Rn))),
3999 (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
4000 (i64 FPR64:$Rn), dsub))>;
4002 def : Pat<(v4f16 (scalar_to_vector (f16 FPR16:$Rn))),
4003 (INSERT_SUBREG (v4f16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>;
4004 def : Pat<(v8f16 (scalar_to_vector (f16 FPR16:$Rn))),
4005 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>;
4007 def : Pat<(v4f32 (scalar_to_vector (f32 FPR32:$Rn))),
4008 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
4009 def : Pat<(v2f32 (scalar_to_vector (f32 FPR32:$Rn))),
4010 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
4011 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$Rn))),
4012 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rn, dsub)>;
4014 def : Pat<(v4f16 (vector_insert (v4f16 V64:$Rn),
4015 (f16 FPR16:$Rm), (i64 VectorIndexS:$imm))),
4018 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), V64:$Rn, dsub)),
4020 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)),
4024 def : Pat<(v8f16 (vector_insert (v8f16 V128:$Rn),
4025 (f16 FPR16:$Rm), (i64 VectorIndexH:$imm))),
4027 V128:$Rn, VectorIndexH:$imm,
4028 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)),
4031 def : Pat<(v2f32 (vector_insert (v2f32 V64:$Rn),
4032 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
4035 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), V64:$Rn, dsub)),
4037 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
4040 def : Pat<(v4f32 (vector_insert (v4f32 V128:$Rn),
4041 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
4043 V128:$Rn, VectorIndexS:$imm,
4044 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
4046 def : Pat<(v2f64 (vector_insert (v2f64 V128:$Rn),
4047 (f64 FPR64:$Rm), (i64 VectorIndexD:$imm))),
4049 V128:$Rn, VectorIndexD:$imm,
4050 (v2f64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rm, dsub)),
4053 // Copy an element at a constant index in one vector into a constant indexed
4054 // element of another.
4055 // FIXME refactor to a shared class/dev parameterized on vector type, vector
4056 // index type and INS extension
4057 def : Pat<(v16i8 (int_aarch64_neon_vcopy_lane
4058 (v16i8 V128:$Vd), VectorIndexB:$idx, (v16i8 V128:$Vs),
4059 VectorIndexB:$idx2)),
4061 V128:$Vd, VectorIndexB:$idx, V128:$Vs, VectorIndexB:$idx2)
4063 def : Pat<(v8i16 (int_aarch64_neon_vcopy_lane
4064 (v8i16 V128:$Vd), VectorIndexH:$idx, (v8i16 V128:$Vs),
4065 VectorIndexH:$idx2)),
4067 V128:$Vd, VectorIndexH:$idx, V128:$Vs, VectorIndexH:$idx2)
4069 def : Pat<(v4i32 (int_aarch64_neon_vcopy_lane
4070 (v4i32 V128:$Vd), VectorIndexS:$idx, (v4i32 V128:$Vs),
4071 VectorIndexS:$idx2)),
4073 V128:$Vd, VectorIndexS:$idx, V128:$Vs, VectorIndexS:$idx2)
4075 def : Pat<(v2i64 (int_aarch64_neon_vcopy_lane
4076 (v2i64 V128:$Vd), VectorIndexD:$idx, (v2i64 V128:$Vs),
4077 VectorIndexD:$idx2)),
4079 V128:$Vd, VectorIndexD:$idx, V128:$Vs, VectorIndexD:$idx2)
4082 multiclass Neon_INS_elt_pattern<ValueType VT128, ValueType VT64,
4083 ValueType VTScal, Instruction INS> {
4084 def : Pat<(VT128 (vector_insert V128:$src,
4085 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
4087 (INS V128:$src, imm:$Immd, V128:$Rn, imm:$Immn)>;
4089 def : Pat<(VT128 (vector_insert V128:$src,
4090 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
4092 (INS V128:$src, imm:$Immd,
4093 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn)>;
4095 def : Pat<(VT64 (vector_insert V64:$src,
4096 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
4098 (EXTRACT_SUBREG (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub),
4099 imm:$Immd, V128:$Rn, imm:$Immn),
4102 def : Pat<(VT64 (vector_insert V64:$src,
4103 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
4106 (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), imm:$Immd,
4107 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn),
4111 defm : Neon_INS_elt_pattern<v8f16, v4f16, f16, INSvi16lane>;
4112 defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, INSvi32lane>;
4113 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, INSvi64lane>;
4116 // Floating point vector extractions are codegen'd as either a sequence of
4117 // subregister extractions, or a MOV (aka CPY here, alias for DUP) if
4118 // the lane number is anything other than zero.
4119 def : Pat<(vector_extract (v2f64 V128:$Rn), 0),
4120 (f64 (EXTRACT_SUBREG V128:$Rn, dsub))>;
4121 def : Pat<(vector_extract (v4f32 V128:$Rn), 0),
4122 (f32 (EXTRACT_SUBREG V128:$Rn, ssub))>;
4123 def : Pat<(vector_extract (v8f16 V128:$Rn), 0),
4124 (f16 (EXTRACT_SUBREG V128:$Rn, hsub))>;
4126 def : Pat<(vector_extract (v2f64 V128:$Rn), VectorIndexD:$idx),
4127 (f64 (CPYi64 V128:$Rn, VectorIndexD:$idx))>;
4128 def : Pat<(vector_extract (v4f32 V128:$Rn), VectorIndexS:$idx),
4129 (f32 (CPYi32 V128:$Rn, VectorIndexS:$idx))>;
4130 def : Pat<(vector_extract (v8f16 V128:$Rn), VectorIndexH:$idx),
4131 (f16 (CPYi16 V128:$Rn, VectorIndexH:$idx))>;
4133 // All concat_vectors operations are canonicalised to act on i64 vectors for
4134 // AArch64. In the general case we need an instruction, which had just as well be
4136 class ConcatPat<ValueType DstTy, ValueType SrcTy>
4137 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rd), V64:$Rn)),
4138 (INSvi64lane (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 1,
4139 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub), 0)>;
4141 def : ConcatPat<v2i64, v1i64>;
4142 def : ConcatPat<v2f64, v1f64>;
4143 def : ConcatPat<v4i32, v2i32>;
4144 def : ConcatPat<v4f32, v2f32>;
4145 def : ConcatPat<v8i16, v4i16>;
4146 def : ConcatPat<v8f16, v4f16>;
4147 def : ConcatPat<v16i8, v8i8>;
4149 // If the high lanes are undef, though, we can just ignore them:
4150 class ConcatUndefPat<ValueType DstTy, ValueType SrcTy>
4151 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rn), undef)),
4152 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub)>;
4154 def : ConcatUndefPat<v2i64, v1i64>;
4155 def : ConcatUndefPat<v2f64, v1f64>;
4156 def : ConcatUndefPat<v4i32, v2i32>;
4157 def : ConcatUndefPat<v4f32, v2f32>;
4158 def : ConcatUndefPat<v8i16, v4i16>;
4159 def : ConcatUndefPat<v16i8, v8i8>;
4161 //----------------------------------------------------------------------------
4162 // AdvSIMD across lanes instructions
4163 //----------------------------------------------------------------------------
4165 defm ADDV : SIMDAcrossLanesBHS<0, 0b11011, "addv">;
4166 defm SMAXV : SIMDAcrossLanesBHS<0, 0b01010, "smaxv">;
4167 defm SMINV : SIMDAcrossLanesBHS<0, 0b11010, "sminv">;
4168 defm UMAXV : SIMDAcrossLanesBHS<1, 0b01010, "umaxv">;
4169 defm UMINV : SIMDAcrossLanesBHS<1, 0b11010, "uminv">;
4170 defm SADDLV : SIMDAcrossLanesHSD<0, 0b00011, "saddlv">;
4171 defm UADDLV : SIMDAcrossLanesHSD<1, 0b00011, "uaddlv">;
4172 defm FMAXNMV : SIMDFPAcrossLanes<0b01100, 0, "fmaxnmv", int_aarch64_neon_fmaxnmv>;
4173 defm FMAXV : SIMDFPAcrossLanes<0b01111, 0, "fmaxv", int_aarch64_neon_fmaxv>;
4174 defm FMINNMV : SIMDFPAcrossLanes<0b01100, 1, "fminnmv", int_aarch64_neon_fminnmv>;
4175 defm FMINV : SIMDFPAcrossLanes<0b01111, 1, "fminv", int_aarch64_neon_fminv>;
4177 // Patterns for across-vector intrinsics, that have a node equivalent, that
4178 // returns a vector (with only the low lane defined) instead of a scalar.
4179 // In effect, opNode is the same as (scalar_to_vector (IntNode)).
4180 multiclass SIMDAcrossLanesIntrinsic<string baseOpc,
4181 SDPatternOperator opNode> {
4182 // If a lane instruction caught the vector_extract around opNode, we can
4183 // directly match the latter to the instruction.
4184 def : Pat<(v8i8 (opNode V64:$Rn)),
4185 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
4186 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub)>;
4187 def : Pat<(v16i8 (opNode V128:$Rn)),
4188 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4189 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub)>;
4190 def : Pat<(v4i16 (opNode V64:$Rn)),
4191 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
4192 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub)>;
4193 def : Pat<(v8i16 (opNode V128:$Rn)),
4194 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
4195 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub)>;
4196 def : Pat<(v4i32 (opNode V128:$Rn)),
4197 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
4198 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub)>;
4201 // If none did, fallback to the explicit patterns, consuming the vector_extract.
4202 def : Pat<(i32 (vector_extract (insert_subvector undef, (v8i8 (opNode V64:$Rn)),
4203 (i32 0)), (i64 0))),
4204 (EXTRACT_SUBREG (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
4205 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn),
4207 def : Pat<(i32 (vector_extract (v16i8 (opNode V128:$Rn)), (i64 0))),
4208 (EXTRACT_SUBREG (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4209 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn),
4211 def : Pat<(i32 (vector_extract (insert_subvector undef,
4212 (v4i16 (opNode V64:$Rn)), (i32 0)), (i64 0))),
4213 (EXTRACT_SUBREG (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
4214 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn),
4216 def : Pat<(i32 (vector_extract (v8i16 (opNode V128:$Rn)), (i64 0))),
4217 (EXTRACT_SUBREG (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
4218 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn),
4220 def : Pat<(i32 (vector_extract (v4i32 (opNode V128:$Rn)), (i64 0))),
4221 (EXTRACT_SUBREG (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
4222 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn),
4227 multiclass SIMDAcrossLanesSignedIntrinsic<string baseOpc,
4228 SDPatternOperator opNode>
4229 : SIMDAcrossLanesIntrinsic<baseOpc, opNode> {
4230 // If there is a sign extension after this intrinsic, consume it as smov already
4232 def : Pat<(i32 (sext_inreg (i32 (vector_extract (insert_subvector undef,
4233 (opNode (v8i8 V64:$Rn)), (i32 0)), (i64 0))), i8)),
4235 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4236 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
4238 def : Pat<(i32 (sext_inreg (i32 (vector_extract
4239 (opNode (v16i8 V128:$Rn)), (i64 0))), i8)),
4241 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4242 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
4244 def : Pat<(i32 (sext_inreg (i32 (vector_extract (insert_subvector undef,
4245 (opNode (v4i16 V64:$Rn)), (i32 0)), (i64 0))), i16)),
4247 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4248 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
4250 def : Pat<(i32 (sext_inreg (i32 (vector_extract
4251 (opNode (v8i16 V128:$Rn)), (i64 0))), i16)),
4253 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4254 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
4258 multiclass SIMDAcrossLanesUnsignedIntrinsic<string baseOpc,
4259 SDPatternOperator opNode>
4260 : SIMDAcrossLanesIntrinsic<baseOpc, opNode> {
4261 // If there is a masking operation keeping only what has been actually
4262 // generated, consume it.
4263 def : Pat<(i32 (and (i32 (vector_extract (insert_subvector undef,
4264 (opNode (v8i8 V64:$Rn)), (i32 0)), (i64 0))), maski8_or_more)),
4265 (i32 (EXTRACT_SUBREG
4266 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4267 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
4269 def : Pat<(i32 (and (i32 (vector_extract (opNode (v16i8 V128:$Rn)), (i64 0))),
4271 (i32 (EXTRACT_SUBREG
4272 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4273 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
4275 def : Pat<(i32 (and (i32 (vector_extract (insert_subvector undef,
4276 (opNode (v4i16 V64:$Rn)), (i32 0)), (i64 0))), maski16_or_more)),
4277 (i32 (EXTRACT_SUBREG
4278 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4279 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
4281 def : Pat<(i32 (and (i32 (vector_extract (opNode (v8i16 V128:$Rn)), (i64 0))),
4283 (i32 (EXTRACT_SUBREG
4284 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4285 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
4289 defm : SIMDAcrossLanesSignedIntrinsic<"ADDV", AArch64saddv>;
4290 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
4291 def : Pat<(v2i32 (AArch64saddv (v2i32 V64:$Rn))),
4292 (ADDPv2i32 V64:$Rn, V64:$Rn)>;
4294 defm : SIMDAcrossLanesUnsignedIntrinsic<"ADDV", AArch64uaddv>;
4295 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
4296 def : Pat<(v2i32 (AArch64uaddv (v2i32 V64:$Rn))),
4297 (ADDPv2i32 V64:$Rn, V64:$Rn)>;
4299 defm : SIMDAcrossLanesSignedIntrinsic<"SMAXV", AArch64smaxv>;
4300 def : Pat<(v2i32 (AArch64smaxv (v2i32 V64:$Rn))),
4301 (SMAXPv2i32 V64:$Rn, V64:$Rn)>;
4303 defm : SIMDAcrossLanesSignedIntrinsic<"SMINV", AArch64sminv>;
4304 def : Pat<(v2i32 (AArch64sminv (v2i32 V64:$Rn))),
4305 (SMINPv2i32 V64:$Rn, V64:$Rn)>;
4307 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMAXV", AArch64umaxv>;
4308 def : Pat<(v2i32 (AArch64umaxv (v2i32 V64:$Rn))),
4309 (UMAXPv2i32 V64:$Rn, V64:$Rn)>;
4311 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMINV", AArch64uminv>;
4312 def : Pat<(v2i32 (AArch64uminv (v2i32 V64:$Rn))),
4313 (UMINPv2i32 V64:$Rn, V64:$Rn)>;
4315 multiclass SIMDAcrossLanesSignedLongIntrinsic<string baseOpc, Intrinsic intOp> {
4316 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
4318 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4319 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
4321 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
4323 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4324 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
4327 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
4328 (i32 (EXTRACT_SUBREG
4329 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4330 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
4332 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
4333 (i32 (EXTRACT_SUBREG
4334 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4335 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
4338 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
4339 (i64 (EXTRACT_SUBREG
4340 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4341 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
4345 multiclass SIMDAcrossLanesUnsignedLongIntrinsic<string baseOpc,
4347 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
4348 (i32 (EXTRACT_SUBREG
4349 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4350 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
4352 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
4353 (i32 (EXTRACT_SUBREG
4354 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4355 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
4358 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
4359 (i32 (EXTRACT_SUBREG
4360 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4361 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
4363 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
4364 (i32 (EXTRACT_SUBREG
4365 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4366 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
4369 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
4370 (i64 (EXTRACT_SUBREG
4371 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4372 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
4376 defm : SIMDAcrossLanesSignedLongIntrinsic<"SADDLV", int_aarch64_neon_saddlv>;
4377 defm : SIMDAcrossLanesUnsignedLongIntrinsic<"UADDLV", int_aarch64_neon_uaddlv>;
4379 // The vaddlv_s32 intrinsic gets mapped to SADDLP.
4380 def : Pat<(i64 (int_aarch64_neon_saddlv (v2i32 V64:$Rn))),
4381 (i64 (EXTRACT_SUBREG
4382 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4383 (SADDLPv2i32_v1i64 V64:$Rn), dsub),
4385 // The vaddlv_u32 intrinsic gets mapped to UADDLP.
4386 def : Pat<(i64 (int_aarch64_neon_uaddlv (v2i32 V64:$Rn))),
4387 (i64 (EXTRACT_SUBREG
4388 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4389 (UADDLPv2i32_v1i64 V64:$Rn), dsub),
4392 //------------------------------------------------------------------------------
4393 // AdvSIMD modified immediate instructions
4394 //------------------------------------------------------------------------------
4397 defm BIC : SIMDModifiedImmVectorShiftTied<1, 0b11, 0b01, "bic", AArch64bici>;
4399 defm ORR : SIMDModifiedImmVectorShiftTied<0, 0b11, 0b01, "orr", AArch64orri>;
4401 def : InstAlias<"bic $Vd.4h, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0)>;
4402 def : InstAlias<"bic $Vd.8h, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>;
4403 def : InstAlias<"bic $Vd.2s, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0)>;
4404 def : InstAlias<"bic $Vd.4s, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0)>;
4406 def : InstAlias<"bic.4h $Vd, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4407 def : InstAlias<"bic.8h $Vd, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4408 def : InstAlias<"bic.2s $Vd, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4409 def : InstAlias<"bic.4s $Vd, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4411 def : InstAlias<"orr $Vd.4h, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0)>;
4412 def : InstAlias<"orr $Vd.8h, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0)>;
4413 def : InstAlias<"orr $Vd.2s, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0)>;
4414 def : InstAlias<"orr $Vd.4s, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>;
4416 def : InstAlias<"orr.4h $Vd, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4417 def : InstAlias<"orr.8h $Vd, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4418 def : InstAlias<"orr.2s $Vd, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4419 def : InstAlias<"orr.4s $Vd, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4422 def FMOVv2f64_ns : SIMDModifiedImmVectorNoShift<1, 1, 0, 0b1111, V128, fpimm8,
4424 [(set (v2f64 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4425 def FMOVv2f32_ns : SIMDModifiedImmVectorNoShift<0, 0, 0, 0b1111, V64, fpimm8,
4427 [(set (v2f32 V64:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4428 def FMOVv4f32_ns : SIMDModifiedImmVectorNoShift<1, 0, 0, 0b1111, V128, fpimm8,
4430 [(set (v4f32 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4431 let Predicates = [HasNEON, HasFullFP16] in {
4432 def FMOVv4f16_ns : SIMDModifiedImmVectorNoShift<0, 0, 1, 0b1111, V64, fpimm8,
4434 [(set (v4f16 V64:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4435 def FMOVv8f16_ns : SIMDModifiedImmVectorNoShift<1, 0, 1, 0b1111, V128, fpimm8,
4437 [(set (v8f16 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4438 } // Predicates = [HasNEON, HasFullFP16]
4442 // EDIT byte mask: scalar
4443 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
4444 def MOVID : SIMDModifiedImmScalarNoShift<0, 1, 0b1110, "movi",
4445 [(set FPR64:$Rd, simdimmtype10:$imm8)]>;
4446 // The movi_edit node has the immediate value already encoded, so we use
4447 // a plain imm0_255 here.
4448 def : Pat<(f64 (AArch64movi_edit imm0_255:$shift)),
4449 (MOVID imm0_255:$shift)>;
4451 def : Pat<(v1i64 immAllZerosV), (MOVID (i32 0))>;
4452 def : Pat<(v2i32 immAllZerosV), (MOVID (i32 0))>;
4453 def : Pat<(v4i16 immAllZerosV), (MOVID (i32 0))>;
4454 def : Pat<(v8i8 immAllZerosV), (MOVID (i32 0))>;
4456 def : Pat<(v1i64 immAllOnesV), (MOVID (i32 255))>;
4457 def : Pat<(v2i32 immAllOnesV), (MOVID (i32 255))>;
4458 def : Pat<(v4i16 immAllOnesV), (MOVID (i32 255))>;
4459 def : Pat<(v8i8 immAllOnesV), (MOVID (i32 255))>;
4461 // EDIT byte mask: 2d
4463 // The movi_edit node has the immediate value already encoded, so we use
4464 // a plain imm0_255 in the pattern
4465 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
4466 def MOVIv2d_ns : SIMDModifiedImmVectorNoShift<1, 1, 0, 0b1110, V128,
4469 [(set (v2i64 V128:$Rd), (AArch64movi_edit imm0_255:$imm8))]>;
4471 def : Pat<(v2i64 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4472 def : Pat<(v4i32 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4473 def : Pat<(v8i16 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4474 def : Pat<(v16i8 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4476 def : Pat<(v2i64 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4477 def : Pat<(v4i32 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4478 def : Pat<(v8i16 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4479 def : Pat<(v16i8 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4481 def : Pat<(v2f64 (AArch64dup (f64 fpimm0))), (MOVIv2d_ns (i32 0))>;
4482 def : Pat<(v4f32 (AArch64dup (f32 fpimm0))), (MOVIv2d_ns (i32 0))>;
4484 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
4485 defm MOVI : SIMDModifiedImmVectorShift<0, 0b10, 0b00, "movi">;
4487 def : InstAlias<"movi $Vd.4h, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4488 def : InstAlias<"movi $Vd.8h, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4489 def : InstAlias<"movi $Vd.2s, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4490 def : InstAlias<"movi $Vd.4s, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4492 def : InstAlias<"movi.4h $Vd, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4493 def : InstAlias<"movi.8h $Vd, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4494 def : InstAlias<"movi.2s $Vd, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4495 def : InstAlias<"movi.4s $Vd, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4497 def : Pat<(v2i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4498 (MOVIv2i32 imm0_255:$imm8, imm:$shift)>;
4499 def : Pat<(v4i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4500 (MOVIv4i32 imm0_255:$imm8, imm:$shift)>;
4501 def : Pat<(v4i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4502 (MOVIv4i16 imm0_255:$imm8, imm:$shift)>;
4503 def : Pat<(v8i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4504 (MOVIv8i16 imm0_255:$imm8, imm:$shift)>;
4506 // EDIT per word: 2s & 4s with MSL shifter
4507 def MOVIv2s_msl : SIMDModifiedImmMoveMSL<0, 0, {1,1,0,?}, V64, "movi", ".2s",
4508 [(set (v2i32 V64:$Rd),
4509 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4510 def MOVIv4s_msl : SIMDModifiedImmMoveMSL<1, 0, {1,1,0,?}, V128, "movi", ".4s",
4511 [(set (v4i32 V128:$Rd),
4512 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4514 // Per byte: 8b & 16b
4515 def MOVIv8b_ns : SIMDModifiedImmVectorNoShift<0, 0, 0, 0b1110, V64, imm0_255,
4517 [(set (v8i8 V64:$Rd), (AArch64movi imm0_255:$imm8))]>;
4518 def MOVIv16b_ns : SIMDModifiedImmVectorNoShift<1, 0, 0, 0b1110, V128, imm0_255,
4520 [(set (v16i8 V128:$Rd), (AArch64movi imm0_255:$imm8))]>;
4524 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
4525 defm MVNI : SIMDModifiedImmVectorShift<1, 0b10, 0b00, "mvni">;
4527 def : InstAlias<"mvni $Vd.4h, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4528 def : InstAlias<"mvni $Vd.8h, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4529 def : InstAlias<"mvni $Vd.2s, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4530 def : InstAlias<"mvni $Vd.4s, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4532 def : InstAlias<"mvni.4h $Vd, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4533 def : InstAlias<"mvni.8h $Vd, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4534 def : InstAlias<"mvni.2s $Vd, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4535 def : InstAlias<"mvni.4s $Vd, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4537 def : Pat<(v2i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4538 (MVNIv2i32 imm0_255:$imm8, imm:$shift)>;
4539 def : Pat<(v4i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4540 (MVNIv4i32 imm0_255:$imm8, imm:$shift)>;
4541 def : Pat<(v4i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4542 (MVNIv4i16 imm0_255:$imm8, imm:$shift)>;
4543 def : Pat<(v8i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4544 (MVNIv8i16 imm0_255:$imm8, imm:$shift)>;
4546 // EDIT per word: 2s & 4s with MSL shifter
4547 def MVNIv2s_msl : SIMDModifiedImmMoveMSL<0, 1, {1,1,0,?}, V64, "mvni", ".2s",
4548 [(set (v2i32 V64:$Rd),
4549 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4550 def MVNIv4s_msl : SIMDModifiedImmMoveMSL<1, 1, {1,1,0,?}, V128, "mvni", ".4s",
4551 [(set (v4i32 V128:$Rd),
4552 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4554 //----------------------------------------------------------------------------
4555 // AdvSIMD indexed element
4556 //----------------------------------------------------------------------------
4558 let hasSideEffects = 0 in {
4559 defm FMLA : SIMDFPIndexedTied<0, 0b0001, "fmla">;
4560 defm FMLS : SIMDFPIndexedTied<0, 0b0101, "fmls">;
4563 // NOTE: Operands are reordered in the FMLA/FMLS PatFrags because the
4564 // instruction expects the addend first, while the intrinsic expects it last.
4566 // On the other hand, there are quite a few valid combinatorial options due to
4567 // the commutativity of multiplication and the fact that (-x) * y = x * (-y).
4568 defm : SIMDFPIndexedTiedPatterns<"FMLA",
4569 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)>>;
4570 defm : SIMDFPIndexedTiedPatterns<"FMLA",
4571 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)>>;
4573 defm : SIMDFPIndexedTiedPatterns<"FMLS",
4574 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
4575 defm : SIMDFPIndexedTiedPatterns<"FMLS",
4576 TriOpFrag<(fma node:$RHS, (fneg node:$MHS), node:$LHS)> >;
4577 defm : SIMDFPIndexedTiedPatterns<"FMLS",
4578 TriOpFrag<(fma (fneg node:$RHS), node:$MHS, node:$LHS)> >;
4579 defm : SIMDFPIndexedTiedPatterns<"FMLS",
4580 TriOpFrag<(fma (fneg node:$MHS), node:$RHS, node:$LHS)> >;
4582 multiclass FMLSIndexedAfterNegPatterns<SDPatternOperator OpNode> {
4583 // 3 variants for the .2s version: DUPLANE from 128-bit, DUPLANE from 64-bit
4585 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4586 (AArch64duplane32 (v4f32 (fneg V128:$Rm)),
4587 VectorIndexS:$idx))),
4588 (FMLSv2i32_indexed V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
4589 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4590 (v2f32 (AArch64duplane32
4591 (v4f32 (insert_subvector undef,
4592 (v2f32 (fneg V64:$Rm)),
4594 VectorIndexS:$idx)))),
4595 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
4596 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
4597 VectorIndexS:$idx)>;
4598 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4599 (AArch64dup (f32 (fneg FPR32Op:$Rm))))),
4600 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
4601 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
4603 // 3 variants for the .4s version: DUPLANE from 128-bit, DUPLANE from 64-bit
4605 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4606 (AArch64duplane32 (v4f32 (fneg V128:$Rm)),
4607 VectorIndexS:$idx))),
4608 (FMLSv4i32_indexed V128:$Rd, V128:$Rn, V128:$Rm,
4609 VectorIndexS:$idx)>;
4610 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4611 (v4f32 (AArch64duplane32
4612 (v4f32 (insert_subvector undef,
4613 (v2f32 (fneg V64:$Rm)),
4615 VectorIndexS:$idx)))),
4616 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
4617 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
4618 VectorIndexS:$idx)>;
4619 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4620 (AArch64dup (f32 (fneg FPR32Op:$Rm))))),
4621 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
4622 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
4624 // 2 variants for the .2d version: DUPLANE from 128-bit, and DUP scalar
4625 // (DUPLANE from 64-bit would be trivial).
4626 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
4627 (AArch64duplane64 (v2f64 (fneg V128:$Rm)),
4628 VectorIndexD:$idx))),
4630 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
4631 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
4632 (AArch64dup (f64 (fneg FPR64Op:$Rm))))),
4633 (FMLSv2i64_indexed V128:$Rd, V128:$Rn,
4634 (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>;
4636 // 2 variants for 32-bit scalar version: extract from .2s or from .4s
4637 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
4638 (vector_extract (v4f32 (fneg V128:$Rm)),
4639 VectorIndexS:$idx))),
4640 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
4641 V128:$Rm, VectorIndexS:$idx)>;
4642 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
4643 (vector_extract (v4f32 (insert_subvector undef,
4644 (v2f32 (fneg V64:$Rm)),
4646 VectorIndexS:$idx))),
4647 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
4648 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>;
4650 // 1 variant for 64-bit scalar version: extract from .1d or from .2d
4651 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
4652 (vector_extract (v2f64 (fneg V128:$Rm)),
4653 VectorIndexS:$idx))),
4654 (FMLSv1i64_indexed FPR64:$Rd, FPR64:$Rn,
4655 V128:$Rm, VectorIndexS:$idx)>;
4658 defm : FMLSIndexedAfterNegPatterns<
4659 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
4660 defm : FMLSIndexedAfterNegPatterns<
4661 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)> >;
4663 defm FMULX : SIMDFPIndexed<1, 0b1001, "fmulx", int_aarch64_neon_fmulx>;
4664 defm FMUL : SIMDFPIndexed<0, 0b1001, "fmul", fmul>;
4666 def : Pat<(v2f32 (fmul V64:$Rn, (AArch64dup (f32 FPR32:$Rm)))),
4667 (FMULv2i32_indexed V64:$Rn,
4668 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
4670 def : Pat<(v4f32 (fmul V128:$Rn, (AArch64dup (f32 FPR32:$Rm)))),
4671 (FMULv4i32_indexed V128:$Rn,
4672 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
4674 def : Pat<(v2f64 (fmul V128:$Rn, (AArch64dup (f64 FPR64:$Rm)))),
4675 (FMULv2i64_indexed V128:$Rn,
4676 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rm, dsub),
4679 defm SQDMULH : SIMDIndexedHS<0, 0b1100, "sqdmulh", int_aarch64_neon_sqdmulh>;
4680 defm SQRDMULH : SIMDIndexedHS<0, 0b1101, "sqrdmulh", int_aarch64_neon_sqrdmulh>;
4681 defm MLA : SIMDVectorIndexedHSTied<1, 0b0000, "mla",
4682 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))>>;
4683 defm MLS : SIMDVectorIndexedHSTied<1, 0b0100, "mls",
4684 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))>>;
4685 defm MUL : SIMDVectorIndexedHS<0, 0b1000, "mul", mul>;
4686 defm SMLAL : SIMDVectorIndexedLongSDTied<0, 0b0010, "smlal",
4687 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
4688 defm SMLSL : SIMDVectorIndexedLongSDTied<0, 0b0110, "smlsl",
4689 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
4690 defm SMULL : SIMDVectorIndexedLongSD<0, 0b1010, "smull",
4691 int_aarch64_neon_smull>;
4692 defm SQDMLAL : SIMDIndexedLongSQDMLXSDTied<0, 0b0011, "sqdmlal",
4693 int_aarch64_neon_sqadd>;
4694 defm SQDMLSL : SIMDIndexedLongSQDMLXSDTied<0, 0b0111, "sqdmlsl",
4695 int_aarch64_neon_sqsub>;
4696 defm SQRDMLAH : SIMDIndexedSQRDMLxHSDTied<1, 0b1101, "sqrdmlah",
4697 int_aarch64_neon_sqadd>;
4698 defm SQRDMLSH : SIMDIndexedSQRDMLxHSDTied<1, 0b1111, "sqrdmlsh",
4699 int_aarch64_neon_sqsub>;
4700 defm SQDMULL : SIMDIndexedLongSD<0, 0b1011, "sqdmull", int_aarch64_neon_sqdmull>;
4701 defm UMLAL : SIMDVectorIndexedLongSDTied<1, 0b0010, "umlal",
4702 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
4703 defm UMLSL : SIMDVectorIndexedLongSDTied<1, 0b0110, "umlsl",
4704 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
4705 defm UMULL : SIMDVectorIndexedLongSD<1, 0b1010, "umull",
4706 int_aarch64_neon_umull>;
4708 // A scalar sqdmull with the second operand being a vector lane can be
4709 // handled directly with the indexed instruction encoding.
4710 def : Pat<(int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
4711 (vector_extract (v4i32 V128:$Vm),
4712 VectorIndexS:$idx)),
4713 (SQDMULLv1i64_indexed FPR32:$Rn, V128:$Vm, VectorIndexS:$idx)>;
4715 //----------------------------------------------------------------------------
4716 // AdvSIMD scalar shift instructions
4717 //----------------------------------------------------------------------------
4718 defm FCVTZS : SIMDFPScalarRShift<0, 0b11111, "fcvtzs">;
4719 defm FCVTZU : SIMDFPScalarRShift<1, 0b11111, "fcvtzu">;
4720 defm SCVTF : SIMDFPScalarRShift<0, 0b11100, "scvtf">;
4721 defm UCVTF : SIMDFPScalarRShift<1, 0b11100, "ucvtf">;
4722 // Codegen patterns for the above. We don't put these directly on the
4723 // instructions because TableGen's type inference can't handle the truth.
4724 // Having the same base pattern for fp <--> int totally freaks it out.
4725 def : Pat<(int_aarch64_neon_vcvtfp2fxs FPR32:$Rn, vecshiftR32:$imm),
4726 (FCVTZSs FPR32:$Rn, vecshiftR32:$imm)>;
4727 def : Pat<(int_aarch64_neon_vcvtfp2fxu FPR32:$Rn, vecshiftR32:$imm),
4728 (FCVTZUs FPR32:$Rn, vecshiftR32:$imm)>;
4729 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxs (f64 FPR64:$Rn), vecshiftR64:$imm)),
4730 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
4731 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxu (f64 FPR64:$Rn), vecshiftR64:$imm)),
4732 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
4733 def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxs (v1f64 FPR64:$Rn),
4735 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
4736 def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxu (v1f64 FPR64:$Rn),
4738 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
4739 def : Pat<(int_aarch64_neon_vcvtfxs2fp FPR32:$Rn, vecshiftR32:$imm),
4740 (SCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
4741 def : Pat<(int_aarch64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR32:$imm),
4742 (UCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
4743 def : Pat<(f64 (int_aarch64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
4744 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4745 def : Pat<(f64 (int_aarch64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
4746 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4747 def : Pat<(v1f64 (int_aarch64_neon_vcvtfxs2fp (v1i64 FPR64:$Rn),
4749 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4750 def : Pat<(v1f64 (int_aarch64_neon_vcvtfxu2fp (v1i64 FPR64:$Rn),
4752 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4754 defm SHL : SIMDScalarLShiftD< 0, 0b01010, "shl", AArch64vshl>;
4755 defm SLI : SIMDScalarLShiftDTied<1, 0b01010, "sli">;
4756 defm SQRSHRN : SIMDScalarRShiftBHS< 0, 0b10011, "sqrshrn",
4757 int_aarch64_neon_sqrshrn>;
4758 defm SQRSHRUN : SIMDScalarRShiftBHS< 1, 0b10001, "sqrshrun",
4759 int_aarch64_neon_sqrshrun>;
4760 defm SQSHLU : SIMDScalarLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>;
4761 defm SQSHL : SIMDScalarLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>;
4762 defm SQSHRN : SIMDScalarRShiftBHS< 0, 0b10010, "sqshrn",
4763 int_aarch64_neon_sqshrn>;
4764 defm SQSHRUN : SIMDScalarRShiftBHS< 1, 0b10000, "sqshrun",
4765 int_aarch64_neon_sqshrun>;
4766 defm SRI : SIMDScalarRShiftDTied< 1, 0b01000, "sri">;
4767 defm SRSHR : SIMDScalarRShiftD< 0, 0b00100, "srshr", AArch64srshri>;
4768 defm SRSRA : SIMDScalarRShiftDTied< 0, 0b00110, "srsra",
4769 TriOpFrag<(add node:$LHS,
4770 (AArch64srshri node:$MHS, node:$RHS))>>;
4771 defm SSHR : SIMDScalarRShiftD< 0, 0b00000, "sshr", AArch64vashr>;
4772 defm SSRA : SIMDScalarRShiftDTied< 0, 0b00010, "ssra",
4773 TriOpFrag<(add node:$LHS,
4774 (AArch64vashr node:$MHS, node:$RHS))>>;
4775 defm UQRSHRN : SIMDScalarRShiftBHS< 1, 0b10011, "uqrshrn",
4776 int_aarch64_neon_uqrshrn>;
4777 defm UQSHL : SIMDScalarLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>;
4778 defm UQSHRN : SIMDScalarRShiftBHS< 1, 0b10010, "uqshrn",
4779 int_aarch64_neon_uqshrn>;
4780 defm URSHR : SIMDScalarRShiftD< 1, 0b00100, "urshr", AArch64urshri>;
4781 defm URSRA : SIMDScalarRShiftDTied< 1, 0b00110, "ursra",
4782 TriOpFrag<(add node:$LHS,
4783 (AArch64urshri node:$MHS, node:$RHS))>>;
4784 defm USHR : SIMDScalarRShiftD< 1, 0b00000, "ushr", AArch64vlshr>;
4785 defm USRA : SIMDScalarRShiftDTied< 1, 0b00010, "usra",
4786 TriOpFrag<(add node:$LHS,
4787 (AArch64vlshr node:$MHS, node:$RHS))>>;
4789 //----------------------------------------------------------------------------
4790 // AdvSIMD vector shift instructions
4791 //----------------------------------------------------------------------------
4792 defm FCVTZS:SIMDVectorRShiftSD<0, 0b11111, "fcvtzs", int_aarch64_neon_vcvtfp2fxs>;
4793 defm FCVTZU:SIMDVectorRShiftSD<1, 0b11111, "fcvtzu", int_aarch64_neon_vcvtfp2fxu>;
4794 defm SCVTF: SIMDVectorRShiftToFP<0, 0b11100, "scvtf",
4795 int_aarch64_neon_vcvtfxs2fp>;
4796 defm RSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10001, "rshrn",
4797 int_aarch64_neon_rshrn>;
4798 defm SHL : SIMDVectorLShiftBHSD<0, 0b01010, "shl", AArch64vshl>;
4799 defm SHRN : SIMDVectorRShiftNarrowBHS<0, 0b10000, "shrn",
4800 BinOpFrag<(trunc (AArch64vashr node:$LHS, node:$RHS))>>;
4801 defm SLI : SIMDVectorLShiftBHSDTied<1, 0b01010, "sli", int_aarch64_neon_vsli>;
4802 def : Pat<(v1i64 (int_aarch64_neon_vsli (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
4803 (i32 vecshiftL64:$imm))),
4804 (SLId FPR64:$Rd, FPR64:$Rn, vecshiftL64:$imm)>;
4805 defm SQRSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10011, "sqrshrn",
4806 int_aarch64_neon_sqrshrn>;
4807 defm SQRSHRUN: SIMDVectorRShiftNarrowBHS<1, 0b10001, "sqrshrun",
4808 int_aarch64_neon_sqrshrun>;
4809 defm SQSHLU : SIMDVectorLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>;
4810 defm SQSHL : SIMDVectorLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>;
4811 defm SQSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10010, "sqshrn",
4812 int_aarch64_neon_sqshrn>;
4813 defm SQSHRUN : SIMDVectorRShiftNarrowBHS<1, 0b10000, "sqshrun",
4814 int_aarch64_neon_sqshrun>;
4815 defm SRI : SIMDVectorRShiftBHSDTied<1, 0b01000, "sri", int_aarch64_neon_vsri>;
4816 def : Pat<(v1i64 (int_aarch64_neon_vsri (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
4817 (i32 vecshiftR64:$imm))),
4818 (SRId FPR64:$Rd, FPR64:$Rn, vecshiftR64:$imm)>;
4819 defm SRSHR : SIMDVectorRShiftBHSD<0, 0b00100, "srshr", AArch64srshri>;
4820 defm SRSRA : SIMDVectorRShiftBHSDTied<0, 0b00110, "srsra",
4821 TriOpFrag<(add node:$LHS,
4822 (AArch64srshri node:$MHS, node:$RHS))> >;
4823 defm SSHLL : SIMDVectorLShiftLongBHSD<0, 0b10100, "sshll",
4824 BinOpFrag<(AArch64vshl (sext node:$LHS), node:$RHS)>>;
4826 defm SSHR : SIMDVectorRShiftBHSD<0, 0b00000, "sshr", AArch64vashr>;
4827 defm SSRA : SIMDVectorRShiftBHSDTied<0, 0b00010, "ssra",
4828 TriOpFrag<(add node:$LHS, (AArch64vashr node:$MHS, node:$RHS))>>;
4829 defm UCVTF : SIMDVectorRShiftToFP<1, 0b11100, "ucvtf",
4830 int_aarch64_neon_vcvtfxu2fp>;
4831 defm UQRSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10011, "uqrshrn",
4832 int_aarch64_neon_uqrshrn>;
4833 defm UQSHL : SIMDVectorLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>;
4834 defm UQSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10010, "uqshrn",
4835 int_aarch64_neon_uqshrn>;
4836 defm URSHR : SIMDVectorRShiftBHSD<1, 0b00100, "urshr", AArch64urshri>;
4837 defm URSRA : SIMDVectorRShiftBHSDTied<1, 0b00110, "ursra",
4838 TriOpFrag<(add node:$LHS,
4839 (AArch64urshri node:$MHS, node:$RHS))> >;
4840 defm USHLL : SIMDVectorLShiftLongBHSD<1, 0b10100, "ushll",
4841 BinOpFrag<(AArch64vshl (zext node:$LHS), node:$RHS)>>;
4842 defm USHR : SIMDVectorRShiftBHSD<1, 0b00000, "ushr", AArch64vlshr>;
4843 defm USRA : SIMDVectorRShiftBHSDTied<1, 0b00010, "usra",
4844 TriOpFrag<(add node:$LHS, (AArch64vlshr node:$MHS, node:$RHS))> >;
4846 // SHRN patterns for when a logical right shift was used instead of arithmetic
4847 // (the immediate guarantees no sign bits actually end up in the result so it
4849 def : Pat<(v8i8 (trunc (AArch64vlshr (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))),
4850 (SHRNv8i8_shift V128:$Rn, vecshiftR16Narrow:$imm)>;
4851 def : Pat<(v4i16 (trunc (AArch64vlshr (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))),
4852 (SHRNv4i16_shift V128:$Rn, vecshiftR32Narrow:$imm)>;
4853 def : Pat<(v2i32 (trunc (AArch64vlshr (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))),
4854 (SHRNv2i32_shift V128:$Rn, vecshiftR64Narrow:$imm)>;
4856 def : Pat<(v16i8 (concat_vectors (v8i8 V64:$Rd),
4857 (trunc (AArch64vlshr (v8i16 V128:$Rn),
4858 vecshiftR16Narrow:$imm)))),
4859 (SHRNv16i8_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4860 V128:$Rn, vecshiftR16Narrow:$imm)>;
4861 def : Pat<(v8i16 (concat_vectors (v4i16 V64:$Rd),
4862 (trunc (AArch64vlshr (v4i32 V128:$Rn),
4863 vecshiftR32Narrow:$imm)))),
4864 (SHRNv8i16_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4865 V128:$Rn, vecshiftR32Narrow:$imm)>;
4866 def : Pat<(v4i32 (concat_vectors (v2i32 V64:$Rd),
4867 (trunc (AArch64vlshr (v2i64 V128:$Rn),
4868 vecshiftR64Narrow:$imm)))),
4869 (SHRNv4i32_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4870 V128:$Rn, vecshiftR32Narrow:$imm)>;
4872 // Vector sign and zero extensions are implemented with SSHLL and USSHLL.
4873 // Anyexts are implemented as zexts.
4874 def : Pat<(v8i16 (sext (v8i8 V64:$Rn))), (SSHLLv8i8_shift V64:$Rn, (i32 0))>;
4875 def : Pat<(v8i16 (zext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
4876 def : Pat<(v8i16 (anyext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
4877 def : Pat<(v4i32 (sext (v4i16 V64:$Rn))), (SSHLLv4i16_shift V64:$Rn, (i32 0))>;
4878 def : Pat<(v4i32 (zext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
4879 def : Pat<(v4i32 (anyext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
4880 def : Pat<(v2i64 (sext (v2i32 V64:$Rn))), (SSHLLv2i32_shift V64:$Rn, (i32 0))>;
4881 def : Pat<(v2i64 (zext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
4882 def : Pat<(v2i64 (anyext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
4883 // Also match an extend from the upper half of a 128 bit source register.
4884 def : Pat<(v8i16 (anyext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4885 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
4886 def : Pat<(v8i16 (zext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4887 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
4888 def : Pat<(v8i16 (sext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4889 (SSHLLv16i8_shift V128:$Rn, (i32 0))>;
4890 def : Pat<(v4i32 (anyext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4891 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
4892 def : Pat<(v4i32 (zext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4893 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
4894 def : Pat<(v4i32 (sext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4895 (SSHLLv8i16_shift V128:$Rn, (i32 0))>;
4896 def : Pat<(v2i64 (anyext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4897 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
4898 def : Pat<(v2i64 (zext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4899 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
4900 def : Pat<(v2i64 (sext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4901 (SSHLLv4i32_shift V128:$Rn, (i32 0))>;
4903 // Vector shift sxtl aliases
4904 def : InstAlias<"sxtl.8h $dst, $src1",
4905 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4906 def : InstAlias<"sxtl $dst.8h, $src1.8b",
4907 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4908 def : InstAlias<"sxtl.4s $dst, $src1",
4909 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4910 def : InstAlias<"sxtl $dst.4s, $src1.4h",
4911 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4912 def : InstAlias<"sxtl.2d $dst, $src1",
4913 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4914 def : InstAlias<"sxtl $dst.2d, $src1.2s",
4915 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4917 // Vector shift sxtl2 aliases
4918 def : InstAlias<"sxtl2.8h $dst, $src1",
4919 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4920 def : InstAlias<"sxtl2 $dst.8h, $src1.16b",
4921 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4922 def : InstAlias<"sxtl2.4s $dst, $src1",
4923 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4924 def : InstAlias<"sxtl2 $dst.4s, $src1.8h",
4925 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4926 def : InstAlias<"sxtl2.2d $dst, $src1",
4927 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4928 def : InstAlias<"sxtl2 $dst.2d, $src1.4s",
4929 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4931 // Vector shift uxtl aliases
4932 def : InstAlias<"uxtl.8h $dst, $src1",
4933 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4934 def : InstAlias<"uxtl $dst.8h, $src1.8b",
4935 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4936 def : InstAlias<"uxtl.4s $dst, $src1",
4937 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4938 def : InstAlias<"uxtl $dst.4s, $src1.4h",
4939 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4940 def : InstAlias<"uxtl.2d $dst, $src1",
4941 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4942 def : InstAlias<"uxtl $dst.2d, $src1.2s",
4943 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4945 // Vector shift uxtl2 aliases
4946 def : InstAlias<"uxtl2.8h $dst, $src1",
4947 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4948 def : InstAlias<"uxtl2 $dst.8h, $src1.16b",
4949 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4950 def : InstAlias<"uxtl2.4s $dst, $src1",
4951 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4952 def : InstAlias<"uxtl2 $dst.4s, $src1.8h",
4953 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4954 def : InstAlias<"uxtl2.2d $dst, $src1",
4955 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4956 def : InstAlias<"uxtl2 $dst.2d, $src1.4s",
4957 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4959 // If an integer is about to be converted to a floating point value,
4960 // just load it on the floating point unit.
4961 // These patterns are more complex because floating point loads do not
4962 // support sign extension.
4963 // The sign extension has to be explicitly added and is only supported for
4964 // one step: byte-to-half, half-to-word, word-to-doubleword.
4965 // SCVTF GPR -> FPR is 9 cycles.
4966 // SCVTF FPR -> FPR is 4 cyclces.
4967 // (sign extension with lengthen) SXTL FPR -> FPR is 2 cycles.
4968 // Therefore, we can do 2 sign extensions and one SCVTF FPR -> FPR
4969 // and still being faster.
4970 // However, this is not good for code size.
4971 // 8-bits -> float. 2 sizes step-up.
4972 class SExtLoadi8CVTf32Pat<dag addrmode, dag INST>
4973 : Pat<(f32 (sint_to_fp (i32 (sextloadi8 addrmode)))),
4974 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4979 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4986 Requires<[NotForCodeSize, UseAlternateSExtLoadCVTF32]>;
4988 def : SExtLoadi8CVTf32Pat<(ro8.Wpat GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext),
4989 (LDRBroW GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext)>;
4990 def : SExtLoadi8CVTf32Pat<(ro8.Xpat GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext),
4991 (LDRBroX GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext)>;
4992 def : SExtLoadi8CVTf32Pat<(am_indexed8 GPR64sp:$Rn, uimm12s1:$offset),
4993 (LDRBui GPR64sp:$Rn, uimm12s1:$offset)>;
4994 def : SExtLoadi8CVTf32Pat<(am_unscaled8 GPR64sp:$Rn, simm9:$offset),
4995 (LDURBi GPR64sp:$Rn, simm9:$offset)>;
4997 // 16-bits -> float. 1 size step-up.
4998 class SExtLoadi16CVTf32Pat<dag addrmode, dag INST>
4999 : Pat<(f32 (sint_to_fp (i32 (sextloadi16 addrmode)))),
5000 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
5002 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
5006 ssub)))>, Requires<[NotForCodeSize]>;
5008 def : SExtLoadi16CVTf32Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
5009 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
5010 def : SExtLoadi16CVTf32Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),
5011 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;
5012 def : SExtLoadi16CVTf32Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),
5013 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;
5014 def : SExtLoadi16CVTf32Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),
5015 (LDURHi GPR64sp:$Rn, simm9:$offset)>;
5017 // 32-bits to 32-bits are handled in target specific dag combine:
5018 // performIntToFpCombine.
5019 // 64-bits integer to 32-bits floating point, not possible with
5020 // SCVTF on floating point registers (both source and destination
5021 // must have the same size).
5023 // Here are the patterns for 8, 16, 32, and 64-bits to double.
5024 // 8-bits -> double. 3 size step-up: give up.
5025 // 16-bits -> double. 2 size step.
5026 class SExtLoadi16CVTf64Pat<dag addrmode, dag INST>
5027 : Pat <(f64 (sint_to_fp (i32 (sextloadi16 addrmode)))),
5028 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
5033 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
5040 Requires<[NotForCodeSize, UseAlternateSExtLoadCVTF32]>;
5042 def : SExtLoadi16CVTf64Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
5043 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
5044 def : SExtLoadi16CVTf64Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),
5045 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;
5046 def : SExtLoadi16CVTf64Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),
5047 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;
5048 def : SExtLoadi16CVTf64Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),
5049 (LDURHi GPR64sp:$Rn, simm9:$offset)>;
5050 // 32-bits -> double. 1 size step-up.
5051 class SExtLoadi32CVTf64Pat<dag addrmode, dag INST>
5052 : Pat <(f64 (sint_to_fp (i32 (load addrmode)))),
5053 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
5055 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
5059 dsub)))>, Requires<[NotForCodeSize]>;
5061 def : SExtLoadi32CVTf64Pat<(ro32.Wpat GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext),
5062 (LDRSroW GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext)>;
5063 def : SExtLoadi32CVTf64Pat<(ro32.Xpat GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext),
5064 (LDRSroX GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext)>;
5065 def : SExtLoadi32CVTf64Pat<(am_indexed32 GPR64sp:$Rn, uimm12s4:$offset),
5066 (LDRSui GPR64sp:$Rn, uimm12s4:$offset)>;
5067 def : SExtLoadi32CVTf64Pat<(am_unscaled32 GPR64sp:$Rn, simm9:$offset),
5068 (LDURSi GPR64sp:$Rn, simm9:$offset)>;
5070 // 64-bits -> double are handled in target specific dag combine:
5071 // performIntToFpCombine.
5074 //----------------------------------------------------------------------------
5075 // AdvSIMD Load-Store Structure
5076 //----------------------------------------------------------------------------
5077 defm LD1 : SIMDLd1Multiple<"ld1">;
5078 defm LD2 : SIMDLd2Multiple<"ld2">;
5079 defm LD3 : SIMDLd3Multiple<"ld3">;
5080 defm LD4 : SIMDLd4Multiple<"ld4">;
5082 defm ST1 : SIMDSt1Multiple<"st1">;
5083 defm ST2 : SIMDSt2Multiple<"st2">;
5084 defm ST3 : SIMDSt3Multiple<"st3">;
5085 defm ST4 : SIMDSt4Multiple<"st4">;
5087 class Ld1Pat<ValueType ty, Instruction INST>
5088 : Pat<(ty (load GPR64sp:$Rn)), (INST GPR64sp:$Rn)>;
5090 def : Ld1Pat<v16i8, LD1Onev16b>;
5091 def : Ld1Pat<v8i16, LD1Onev8h>;
5092 def : Ld1Pat<v4i32, LD1Onev4s>;
5093 def : Ld1Pat<v2i64, LD1Onev2d>;
5094 def : Ld1Pat<v8i8, LD1Onev8b>;
5095 def : Ld1Pat<v4i16, LD1Onev4h>;
5096 def : Ld1Pat<v2i32, LD1Onev2s>;
5097 def : Ld1Pat<v1i64, LD1Onev1d>;
5099 class St1Pat<ValueType ty, Instruction INST>
5100 : Pat<(store ty:$Vt, GPR64sp:$Rn),
5101 (INST ty:$Vt, GPR64sp:$Rn)>;
5103 def : St1Pat<v16i8, ST1Onev16b>;
5104 def : St1Pat<v8i16, ST1Onev8h>;
5105 def : St1Pat<v4i32, ST1Onev4s>;
5106 def : St1Pat<v2i64, ST1Onev2d>;
5107 def : St1Pat<v8i8, ST1Onev8b>;
5108 def : St1Pat<v4i16, ST1Onev4h>;
5109 def : St1Pat<v2i32, ST1Onev2s>;
5110 def : St1Pat<v1i64, ST1Onev1d>;
5116 defm LD1R : SIMDLdR<0, 0b110, 0, "ld1r", "One", 1, 2, 4, 8>;
5117 defm LD2R : SIMDLdR<1, 0b110, 0, "ld2r", "Two", 2, 4, 8, 16>;
5118 defm LD3R : SIMDLdR<0, 0b111, 0, "ld3r", "Three", 3, 6, 12, 24>;
5119 defm LD4R : SIMDLdR<1, 0b111, 0, "ld4r", "Four", 4, 8, 16, 32>;
5120 let mayLoad = 1, hasSideEffects = 0 in {
5121 defm LD1 : SIMDLdSingleBTied<0, 0b000, "ld1", VecListOneb, GPR64pi1>;
5122 defm LD1 : SIMDLdSingleHTied<0, 0b010, 0, "ld1", VecListOneh, GPR64pi2>;
5123 defm LD1 : SIMDLdSingleSTied<0, 0b100, 0b00, "ld1", VecListOnes, GPR64pi4>;
5124 defm LD1 : SIMDLdSingleDTied<0, 0b100, 0b01, "ld1", VecListOned, GPR64pi8>;
5125 defm LD2 : SIMDLdSingleBTied<1, 0b000, "ld2", VecListTwob, GPR64pi2>;
5126 defm LD2 : SIMDLdSingleHTied<1, 0b010, 0, "ld2", VecListTwoh, GPR64pi4>;
5127 defm LD2 : SIMDLdSingleSTied<1, 0b100, 0b00, "ld2", VecListTwos, GPR64pi8>;
5128 defm LD2 : SIMDLdSingleDTied<1, 0b100, 0b01, "ld2", VecListTwod, GPR64pi16>;
5129 defm LD3 : SIMDLdSingleBTied<0, 0b001, "ld3", VecListThreeb, GPR64pi3>;
5130 defm LD3 : SIMDLdSingleHTied<0, 0b011, 0, "ld3", VecListThreeh, GPR64pi6>;
5131 defm LD3 : SIMDLdSingleSTied<0, 0b101, 0b00, "ld3", VecListThrees, GPR64pi12>;
5132 defm LD3 : SIMDLdSingleDTied<0, 0b101, 0b01, "ld3", VecListThreed, GPR64pi24>;
5133 defm LD4 : SIMDLdSingleBTied<1, 0b001, "ld4", VecListFourb, GPR64pi4>;
5134 defm LD4 : SIMDLdSingleHTied<1, 0b011, 0, "ld4", VecListFourh, GPR64pi8>;
5135 defm LD4 : SIMDLdSingleSTied<1, 0b101, 0b00, "ld4", VecListFours, GPR64pi16>;
5136 defm LD4 : SIMDLdSingleDTied<1, 0b101, 0b01, "ld4", VecListFourd, GPR64pi32>;
5139 def : Pat<(v8i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))),
5140 (LD1Rv8b GPR64sp:$Rn)>;
5141 def : Pat<(v16i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))),
5142 (LD1Rv16b GPR64sp:$Rn)>;
5143 def : Pat<(v4i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))),
5144 (LD1Rv4h GPR64sp:$Rn)>;
5145 def : Pat<(v8i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))),
5146 (LD1Rv8h GPR64sp:$Rn)>;
5147 def : Pat<(v2i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
5148 (LD1Rv2s GPR64sp:$Rn)>;
5149 def : Pat<(v4i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
5150 (LD1Rv4s GPR64sp:$Rn)>;
5151 def : Pat<(v2i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
5152 (LD1Rv2d GPR64sp:$Rn)>;
5153 def : Pat<(v1i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
5154 (LD1Rv1d GPR64sp:$Rn)>;
5155 // Grab the floating point version too
5156 def : Pat<(v2f32 (AArch64dup (f32 (load GPR64sp:$Rn)))),
5157 (LD1Rv2s GPR64sp:$Rn)>;
5158 def : Pat<(v4f32 (AArch64dup (f32 (load GPR64sp:$Rn)))),
5159 (LD1Rv4s GPR64sp:$Rn)>;
5160 def : Pat<(v2f64 (AArch64dup (f64 (load GPR64sp:$Rn)))),
5161 (LD1Rv2d GPR64sp:$Rn)>;
5162 def : Pat<(v1f64 (AArch64dup (f64 (load GPR64sp:$Rn)))),
5163 (LD1Rv1d GPR64sp:$Rn)>;
5164 def : Pat<(v4f16 (AArch64dup (f16 (load GPR64sp:$Rn)))),
5165 (LD1Rv4h GPR64sp:$Rn)>;
5166 def : Pat<(v8f16 (AArch64dup (f16 (load GPR64sp:$Rn)))),
5167 (LD1Rv8h GPR64sp:$Rn)>;
5169 class Ld1Lane128Pat<SDPatternOperator scalar_load, Operand VecIndex,
5170 ValueType VTy, ValueType STy, Instruction LD1>
5171 : Pat<(vector_insert (VTy VecListOne128:$Rd),
5172 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
5173 (LD1 VecListOne128:$Rd, VecIndex:$idx, GPR64sp:$Rn)>;
5175 def : Ld1Lane128Pat<extloadi8, VectorIndexB, v16i8, i32, LD1i8>;
5176 def : Ld1Lane128Pat<extloadi16, VectorIndexH, v8i16, i32, LD1i16>;
5177 def : Ld1Lane128Pat<load, VectorIndexS, v4i32, i32, LD1i32>;
5178 def : Ld1Lane128Pat<load, VectorIndexS, v4f32, f32, LD1i32>;
5179 def : Ld1Lane128Pat<load, VectorIndexD, v2i64, i64, LD1i64>;
5180 def : Ld1Lane128Pat<load, VectorIndexD, v2f64, f64, LD1i64>;
5181 def : Ld1Lane128Pat<load, VectorIndexH, v8f16, f16, LD1i16>;
5183 class Ld1Lane64Pat<SDPatternOperator scalar_load, Operand VecIndex,
5184 ValueType VTy, ValueType STy, Instruction LD1>
5185 : Pat<(vector_insert (VTy VecListOne64:$Rd),
5186 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
5188 (LD1 (SUBREG_TO_REG (i32 0), VecListOne64:$Rd, dsub),
5189 VecIndex:$idx, GPR64sp:$Rn),
5192 def : Ld1Lane64Pat<extloadi8, VectorIndexB, v8i8, i32, LD1i8>;
5193 def : Ld1Lane64Pat<extloadi16, VectorIndexH, v4i16, i32, LD1i16>;
5194 def : Ld1Lane64Pat<load, VectorIndexS, v2i32, i32, LD1i32>;
5195 def : Ld1Lane64Pat<load, VectorIndexS, v2f32, f32, LD1i32>;
5196 def : Ld1Lane64Pat<load, VectorIndexH, v4f16, f16, LD1i16>;
5199 defm LD1 : SIMDLdSt1SingleAliases<"ld1">;
5200 defm LD2 : SIMDLdSt2SingleAliases<"ld2">;
5201 defm LD3 : SIMDLdSt3SingleAliases<"ld3">;
5202 defm LD4 : SIMDLdSt4SingleAliases<"ld4">;
5205 defm ST1 : SIMDStSingleB<0, 0b000, "st1", VecListOneb, GPR64pi1>;
5206 defm ST1 : SIMDStSingleH<0, 0b010, 0, "st1", VecListOneh, GPR64pi2>;
5207 defm ST1 : SIMDStSingleS<0, 0b100, 0b00, "st1", VecListOnes, GPR64pi4>;
5208 defm ST1 : SIMDStSingleD<0, 0b100, 0b01, "st1", VecListOned, GPR64pi8>;
5210 let AddedComplexity = 19 in
5211 class St1Lane128Pat<SDPatternOperator scalar_store, Operand VecIndex,
5212 ValueType VTy, ValueType STy, Instruction ST1>
5214 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
5216 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn)>;
5218 def : St1Lane128Pat<truncstorei8, VectorIndexB, v16i8, i32, ST1i8>;
5219 def : St1Lane128Pat<truncstorei16, VectorIndexH, v8i16, i32, ST1i16>;
5220 def : St1Lane128Pat<store, VectorIndexS, v4i32, i32, ST1i32>;
5221 def : St1Lane128Pat<store, VectorIndexS, v4f32, f32, ST1i32>;
5222 def : St1Lane128Pat<store, VectorIndexD, v2i64, i64, ST1i64>;
5223 def : St1Lane128Pat<store, VectorIndexD, v2f64, f64, ST1i64>;
5224 def : St1Lane128Pat<store, VectorIndexH, v8f16, f16, ST1i16>;
5226 let AddedComplexity = 19 in
5227 class St1Lane64Pat<SDPatternOperator scalar_store, Operand VecIndex,
5228 ValueType VTy, ValueType STy, Instruction ST1>
5230 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
5232 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
5233 VecIndex:$idx, GPR64sp:$Rn)>;
5235 def : St1Lane64Pat<truncstorei8, VectorIndexB, v8i8, i32, ST1i8>;
5236 def : St1Lane64Pat<truncstorei16, VectorIndexH, v4i16, i32, ST1i16>;
5237 def : St1Lane64Pat<store, VectorIndexS, v2i32, i32, ST1i32>;
5238 def : St1Lane64Pat<store, VectorIndexS, v2f32, f32, ST1i32>;
5239 def : St1Lane64Pat<store, VectorIndexH, v4f16, f16, ST1i16>;
5241 multiclass St1LanePost64Pat<SDPatternOperator scalar_store, Operand VecIndex,
5242 ValueType VTy, ValueType STy, Instruction ST1,
5244 def : Pat<(scalar_store
5245 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
5246 GPR64sp:$Rn, offset),
5247 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
5248 VecIndex:$idx, GPR64sp:$Rn, XZR)>;
5250 def : Pat<(scalar_store
5251 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
5252 GPR64sp:$Rn, GPR64:$Rm),
5253 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
5254 VecIndex:$idx, GPR64sp:$Rn, $Rm)>;
5257 defm : St1LanePost64Pat<post_truncsti8, VectorIndexB, v8i8, i32, ST1i8_POST, 1>;
5258 defm : St1LanePost64Pat<post_truncsti16, VectorIndexH, v4i16, i32, ST1i16_POST,
5260 defm : St1LanePost64Pat<post_store, VectorIndexS, v2i32, i32, ST1i32_POST, 4>;
5261 defm : St1LanePost64Pat<post_store, VectorIndexS, v2f32, f32, ST1i32_POST, 4>;
5262 defm : St1LanePost64Pat<post_store, VectorIndexD, v1i64, i64, ST1i64_POST, 8>;
5263 defm : St1LanePost64Pat<post_store, VectorIndexD, v1f64, f64, ST1i64_POST, 8>;
5264 defm : St1LanePost64Pat<post_store, VectorIndexH, v4f16, f16, ST1i16_POST, 2>;
5266 multiclass St1LanePost128Pat<SDPatternOperator scalar_store, Operand VecIndex,
5267 ValueType VTy, ValueType STy, Instruction ST1,
5269 def : Pat<(scalar_store
5270 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
5271 GPR64sp:$Rn, offset),
5272 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, XZR)>;
5274 def : Pat<(scalar_store
5275 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
5276 GPR64sp:$Rn, GPR64:$Rm),
5277 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, $Rm)>;
5280 defm : St1LanePost128Pat<post_truncsti8, VectorIndexB, v16i8, i32, ST1i8_POST,
5282 defm : St1LanePost128Pat<post_truncsti16, VectorIndexH, v8i16, i32, ST1i16_POST,
5284 defm : St1LanePost128Pat<post_store, VectorIndexS, v4i32, i32, ST1i32_POST, 4>;
5285 defm : St1LanePost128Pat<post_store, VectorIndexS, v4f32, f32, ST1i32_POST, 4>;
5286 defm : St1LanePost128Pat<post_store, VectorIndexD, v2i64, i64, ST1i64_POST, 8>;
5287 defm : St1LanePost128Pat<post_store, VectorIndexD, v2f64, f64, ST1i64_POST, 8>;
5288 defm : St1LanePost128Pat<post_store, VectorIndexH, v8f16, f16, ST1i16_POST, 2>;
5290 let mayStore = 1, hasSideEffects = 0 in {
5291 defm ST2 : SIMDStSingleB<1, 0b000, "st2", VecListTwob, GPR64pi2>;
5292 defm ST2 : SIMDStSingleH<1, 0b010, 0, "st2", VecListTwoh, GPR64pi4>;
5293 defm ST2 : SIMDStSingleS<1, 0b100, 0b00, "st2", VecListTwos, GPR64pi8>;
5294 defm ST2 : SIMDStSingleD<1, 0b100, 0b01, "st2", VecListTwod, GPR64pi16>;
5295 defm ST3 : SIMDStSingleB<0, 0b001, "st3", VecListThreeb, GPR64pi3>;
5296 defm ST3 : SIMDStSingleH<0, 0b011, 0, "st3", VecListThreeh, GPR64pi6>;
5297 defm ST3 : SIMDStSingleS<0, 0b101, 0b00, "st3", VecListThrees, GPR64pi12>;
5298 defm ST3 : SIMDStSingleD<0, 0b101, 0b01, "st3", VecListThreed, GPR64pi24>;
5299 defm ST4 : SIMDStSingleB<1, 0b001, "st4", VecListFourb, GPR64pi4>;
5300 defm ST4 : SIMDStSingleH<1, 0b011, 0, "st4", VecListFourh, GPR64pi8>;
5301 defm ST4 : SIMDStSingleS<1, 0b101, 0b00, "st4", VecListFours, GPR64pi16>;
5302 defm ST4 : SIMDStSingleD<1, 0b101, 0b01, "st4", VecListFourd, GPR64pi32>;
5305 defm ST1 : SIMDLdSt1SingleAliases<"st1">;
5306 defm ST2 : SIMDLdSt2SingleAliases<"st2">;
5307 defm ST3 : SIMDLdSt3SingleAliases<"st3">;
5308 defm ST4 : SIMDLdSt4SingleAliases<"st4">;
5310 //----------------------------------------------------------------------------
5311 // Crypto extensions
5312 //----------------------------------------------------------------------------
5314 def AESErr : AESTiedInst<0b0100, "aese", int_aarch64_crypto_aese>;
5315 def AESDrr : AESTiedInst<0b0101, "aesd", int_aarch64_crypto_aesd>;
5316 def AESMCrr : AESInst< 0b0110, "aesmc", int_aarch64_crypto_aesmc>;
5317 def AESIMCrr : AESInst< 0b0111, "aesimc", int_aarch64_crypto_aesimc>;
5319 def SHA1Crrr : SHATiedInstQSV<0b000, "sha1c", int_aarch64_crypto_sha1c>;
5320 def SHA1Prrr : SHATiedInstQSV<0b001, "sha1p", int_aarch64_crypto_sha1p>;
5321 def SHA1Mrrr : SHATiedInstQSV<0b010, "sha1m", int_aarch64_crypto_sha1m>;
5322 def SHA1SU0rrr : SHATiedInstVVV<0b011, "sha1su0", int_aarch64_crypto_sha1su0>;
5323 def SHA256Hrrr : SHATiedInstQQV<0b100, "sha256h", int_aarch64_crypto_sha256h>;
5324 def SHA256H2rrr : SHATiedInstQQV<0b101, "sha256h2",int_aarch64_crypto_sha256h2>;
5325 def SHA256SU1rrr :SHATiedInstVVV<0b110, "sha256su1",int_aarch64_crypto_sha256su1>;
5327 def SHA1Hrr : SHAInstSS< 0b0000, "sha1h", int_aarch64_crypto_sha1h>;
5328 def SHA1SU1rr : SHATiedInstVV<0b0001, "sha1su1", int_aarch64_crypto_sha1su1>;
5329 def SHA256SU0rr : SHATiedInstVV<0b0010, "sha256su0",int_aarch64_crypto_sha256su0>;
5331 //----------------------------------------------------------------------------
5333 //----------------------------------------------------------------------------
5334 // FIXME: Like for X86, these should go in their own separate .td file.
5336 def def32 : PatLeaf<(i32 GPR32:$src), [{
5340 // In the case of a 32-bit def that is known to implicitly zero-extend,
5341 // we can use a SUBREG_TO_REG.
5342 def : Pat<(i64 (zext def32:$src)), (SUBREG_TO_REG (i64 0), GPR32:$src, sub_32)>;
5344 // For an anyext, we don't care what the high bits are, so we can perform an
5345 // INSERT_SUBREF into an IMPLICIT_DEF.
5346 def : Pat<(i64 (anyext GPR32:$src)),
5347 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>;
5349 // When we need to explicitly zero-extend, we use a 32-bit MOV instruction and
5350 // then assert the extension has happened.
5351 def : Pat<(i64 (zext GPR32:$src)),
5352 (SUBREG_TO_REG (i32 0), (ORRWrs WZR, GPR32:$src, 0), sub_32)>;
5354 // To sign extend, we use a signed bitfield move instruction (SBFM) on the
5355 // containing super-reg.
5356 def : Pat<(i64 (sext GPR32:$src)),
5357 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
5358 def : Pat<(i64 (sext_inreg GPR64:$src, i32)), (SBFMXri GPR64:$src, 0, 31)>;
5359 def : Pat<(i64 (sext_inreg GPR64:$src, i16)), (SBFMXri GPR64:$src, 0, 15)>;
5360 def : Pat<(i64 (sext_inreg GPR64:$src, i8)), (SBFMXri GPR64:$src, 0, 7)>;
5361 def : Pat<(i64 (sext_inreg GPR64:$src, i1)), (SBFMXri GPR64:$src, 0, 0)>;
5362 def : Pat<(i32 (sext_inreg GPR32:$src, i16)), (SBFMWri GPR32:$src, 0, 15)>;
5363 def : Pat<(i32 (sext_inreg GPR32:$src, i8)), (SBFMWri GPR32:$src, 0, 7)>;
5364 def : Pat<(i32 (sext_inreg GPR32:$src, i1)), (SBFMWri GPR32:$src, 0, 0)>;
5366 def : Pat<(shl (sext_inreg GPR32:$Rn, i8), (i64 imm0_31:$imm)),
5367 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
5368 (i64 (i32shift_sext_i8 imm0_31:$imm)))>;
5369 def : Pat<(shl (sext_inreg GPR64:$Rn, i8), (i64 imm0_63:$imm)),
5370 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
5371 (i64 (i64shift_sext_i8 imm0_63:$imm)))>;
5373 def : Pat<(shl (sext_inreg GPR32:$Rn, i16), (i64 imm0_31:$imm)),
5374 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
5375 (i64 (i32shift_sext_i16 imm0_31:$imm)))>;
5376 def : Pat<(shl (sext_inreg GPR64:$Rn, i16), (i64 imm0_63:$imm)),
5377 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
5378 (i64 (i64shift_sext_i16 imm0_63:$imm)))>;
5380 def : Pat<(shl (i64 (sext GPR32:$Rn)), (i64 imm0_63:$imm)),
5381 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
5382 (i64 (i64shift_a imm0_63:$imm)),
5383 (i64 (i64shift_sext_i32 imm0_63:$imm)))>;
5385 // sra patterns have an AddedComplexity of 10, so make sure we have a higher
5386 // AddedComplexity for the following patterns since we want to match sext + sra
5387 // patterns before we attempt to match a single sra node.
5388 let AddedComplexity = 20 in {
5389 // We support all sext + sra combinations which preserve at least one bit of the
5390 // original value which is to be sign extended. E.g. we support shifts up to
5392 def : Pat<(sra (sext_inreg GPR32:$Rn, i8), (i64 imm0_7:$imm)),
5393 (SBFMWri GPR32:$Rn, (i64 imm0_7:$imm), 7)>;
5394 def : Pat<(sra (sext_inreg GPR64:$Rn, i8), (i64 imm0_7:$imm)),
5395 (SBFMXri GPR64:$Rn, (i64 imm0_7:$imm), 7)>;
5397 def : Pat<(sra (sext_inreg GPR32:$Rn, i16), (i64 imm0_15:$imm)),
5398 (SBFMWri GPR32:$Rn, (i64 imm0_15:$imm), 15)>;
5399 def : Pat<(sra (sext_inreg GPR64:$Rn, i16), (i64 imm0_15:$imm)),
5400 (SBFMXri GPR64:$Rn, (i64 imm0_15:$imm), 15)>;
5402 def : Pat<(sra (i64 (sext GPR32:$Rn)), (i64 imm0_31:$imm)),
5403 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
5404 (i64 imm0_31:$imm), 31)>;
5405 } // AddedComplexity = 20
5407 // To truncate, we can simply extract from a subregister.
5408 def : Pat<(i32 (trunc GPR64sp:$src)),
5409 (i32 (EXTRACT_SUBREG GPR64sp:$src, sub_32))>;
5411 // __builtin_trap() uses the BRK instruction on AArch64.
5412 def : Pat<(trap), (BRK 1)>;
5414 // Conversions within AdvSIMD types in the same register size are free.
5415 // But because we need a consistent lane ordering, in big endian many
5416 // conversions require one or more REV instructions.
5418 // Consider a simple memory load followed by a bitconvert then a store.
5420 // v1 = BITCAST v2i32 v0 to v4i16
5423 // In big endian mode every memory access has an implicit byte swap. LDR and
5424 // STR do a 64-bit byte swap, whereas LD1/ST1 do a byte swap per lane - that
5425 // is, they treat the vector as a sequence of elements to be byte-swapped.
5426 // The two pairs of instructions are fundamentally incompatible. We've decided
5427 // to use LD1/ST1 only to simplify compiler implementation.
5429 // LD1/ST1 perform the equivalent of a sequence of LDR/STR + REV. This makes
5430 // the original code sequence:
5432 // v1 = REV v2i32 (implicit)
5433 // v2 = BITCAST v2i32 v1 to v4i16
5434 // v3 = REV v4i16 v2 (implicit)
5437 // But this is now broken - the value stored is different to the value loaded
5438 // due to lane reordering. To fix this, on every BITCAST we must perform two
5441 // v1 = REV v2i32 (implicit)
5443 // v3 = BITCAST v2i32 v2 to v4i16
5445 // v5 = REV v4i16 v4 (implicit)
5448 // This means an extra two instructions, but actually in most cases the two REV
5449 // instructions can be combined into one. For example:
5450 // (REV64_2s (REV64_4h X)) === (REV32_4h X)
5452 // There is also no 128-bit REV instruction. This must be synthesized with an
5455 // Most bitconverts require some sort of conversion. The only exceptions are:
5456 // a) Identity conversions - vNfX <-> vNiX
5457 // b) Single-lane-to-scalar - v1fX <-> fX or v1iX <-> iX
5460 // Natural vector casts (64 bit)
5461 def : Pat<(v8i8 (AArch64NvCast (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
5462 def : Pat<(v4i16 (AArch64NvCast (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
5463 def : Pat<(v4f16 (AArch64NvCast (v2i32 FPR64:$src))), (v4f16 FPR64:$src)>;
5464 def : Pat<(v2i32 (AArch64NvCast (v2i32 FPR64:$src))), (v2i32 FPR64:$src)>;
5465 def : Pat<(v2f32 (AArch64NvCast (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;
5466 def : Pat<(v1i64 (AArch64NvCast (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
5468 def : Pat<(v8i8 (AArch64NvCast (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
5469 def : Pat<(v4i16 (AArch64NvCast (v4i16 FPR64:$src))), (v4i16 FPR64:$src)>;
5470 def : Pat<(v4f16 (AArch64NvCast (v4i16 FPR64:$src))), (v4f16 FPR64:$src)>;
5471 def : Pat<(v2i32 (AArch64NvCast (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
5472 def : Pat<(v1i64 (AArch64NvCast (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
5474 def : Pat<(v8i8 (AArch64NvCast (v8i8 FPR64:$src))), (v8i8 FPR64:$src)>;
5475 def : Pat<(v4i16 (AArch64NvCast (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
5476 def : Pat<(v4f16 (AArch64NvCast (v8i8 FPR64:$src))), (v4f16 FPR64:$src)>;
5477 def : Pat<(v2i32 (AArch64NvCast (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
5478 def : Pat<(v1i64 (AArch64NvCast (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
5480 def : Pat<(v8i8 (AArch64NvCast (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5481 def : Pat<(v4i16 (AArch64NvCast (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5482 def : Pat<(v4f16 (AArch64NvCast (f64 FPR64:$src))), (v4f16 FPR64:$src)>;
5483 def : Pat<(v2i32 (AArch64NvCast (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5484 def : Pat<(v2f32 (AArch64NvCast (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5485 def : Pat<(v1i64 (AArch64NvCast (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5486 def : Pat<(v1f64 (AArch64NvCast (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
5488 def : Pat<(v8i8 (AArch64NvCast (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
5489 def : Pat<(v4i16 (AArch64NvCast (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
5490 def : Pat<(v2i32 (AArch64NvCast (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
5491 def : Pat<(v2f32 (AArch64NvCast (v2f32 FPR64:$src))), (v2f32 FPR64:$src)>;
5492 def : Pat<(v1i64 (AArch64NvCast (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
5494 // Natural vector casts (128 bit)
5495 def : Pat<(v16i8 (AArch64NvCast (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
5496 def : Pat<(v8i16 (AArch64NvCast (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
5497 def : Pat<(v8f16 (AArch64NvCast (v4i32 FPR128:$src))), (v8f16 FPR128:$src)>;
5498 def : Pat<(v4i32 (AArch64NvCast (v4i32 FPR128:$src))), (v4i32 FPR128:$src)>;
5499 def : Pat<(v4f32 (AArch64NvCast (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
5500 def : Pat<(v2i64 (AArch64NvCast (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
5501 def : Pat<(v2f64 (AArch64NvCast (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>;
5503 def : Pat<(v16i8 (AArch64NvCast (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
5504 def : Pat<(v8i16 (AArch64NvCast (v8i16 FPR128:$src))), (v8i16 FPR128:$src)>;
5505 def : Pat<(v8f16 (AArch64NvCast (v8i16 FPR128:$src))), (v8f16 FPR128:$src)>;
5506 def : Pat<(v4i32 (AArch64NvCast (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
5507 def : Pat<(v2i64 (AArch64NvCast (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;
5508 def : Pat<(v4f32 (AArch64NvCast (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>;
5509 def : Pat<(v2f64 (AArch64NvCast (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>;
5511 def : Pat<(v16i8 (AArch64NvCast (v16i8 FPR128:$src))), (v16i8 FPR128:$src)>;
5512 def : Pat<(v8i16 (AArch64NvCast (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
5513 def : Pat<(v8f16 (AArch64NvCast (v16i8 FPR128:$src))), (v8f16 FPR128:$src)>;
5514 def : Pat<(v4i32 (AArch64NvCast (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
5515 def : Pat<(v2i64 (AArch64NvCast (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;
5516 def : Pat<(v4f32 (AArch64NvCast (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>;
5517 def : Pat<(v2f64 (AArch64NvCast (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>;
5519 def : Pat<(v16i8 (AArch64NvCast (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
5520 def : Pat<(v8i16 (AArch64NvCast (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
5521 def : Pat<(v8f16 (AArch64NvCast (v2i64 FPR128:$src))), (v8f16 FPR128:$src)>;
5522 def : Pat<(v4i32 (AArch64NvCast (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
5523 def : Pat<(v2i64 (AArch64NvCast (v2i64 FPR128:$src))), (v2i64 FPR128:$src)>;
5524 def : Pat<(v4f32 (AArch64NvCast (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;
5525 def : Pat<(v2f64 (AArch64NvCast (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
5527 def : Pat<(v16i8 (AArch64NvCast (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
5528 def : Pat<(v8i16 (AArch64NvCast (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
5529 def : Pat<(v4i32 (AArch64NvCast (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
5530 def : Pat<(v4f32 (AArch64NvCast (v4f32 FPR128:$src))), (v4f32 FPR128:$src)>;
5531 def : Pat<(v2i64 (AArch64NvCast (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
5532 def : Pat<(v8f16 (AArch64NvCast (v4f32 FPR128:$src))), (v8f16 FPR128:$src)>;
5533 def : Pat<(v2f64 (AArch64NvCast (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>;
5535 def : Pat<(v16i8 (AArch64NvCast (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
5536 def : Pat<(v8i16 (AArch64NvCast (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
5537 def : Pat<(v4i32 (AArch64NvCast (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
5538 def : Pat<(v2i64 (AArch64NvCast (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
5539 def : Pat<(v2f64 (AArch64NvCast (v2f64 FPR128:$src))), (v2f64 FPR128:$src)>;
5540 def : Pat<(v8f16 (AArch64NvCast (v2f64 FPR128:$src))), (v8f16 FPR128:$src)>;
5541 def : Pat<(v4f32 (AArch64NvCast (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>;
5543 let Predicates = [IsLE] in {
5544 def : Pat<(v8i8 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5545 def : Pat<(v4i16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5546 def : Pat<(v2i32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5547 def : Pat<(v4f16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5548 def : Pat<(v2f32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5550 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
5551 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5552 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
5553 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5554 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
5555 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5556 def : Pat<(i64 (bitconvert (v4f16 V64:$Vn))),
5557 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5558 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
5559 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5560 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
5561 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5563 let Predicates = [IsBE] in {
5564 def : Pat<(v8i8 (bitconvert GPR64:$Xn)),
5565 (REV64v8i8 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5566 def : Pat<(v4i16 (bitconvert GPR64:$Xn)),
5567 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5568 def : Pat<(v2i32 (bitconvert GPR64:$Xn)),
5569 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5570 def : Pat<(v4f16 (bitconvert GPR64:$Xn)),
5571 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5572 def : Pat<(v2f32 (bitconvert GPR64:$Xn)),
5573 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5575 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
5576 (REV64v8i8 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5577 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
5578 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5579 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
5580 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5581 def : Pat<(i64 (bitconvert (v4f16 V64:$Vn))),
5582 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5583 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
5584 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5586 def : Pat<(v1i64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5587 def : Pat<(v1f64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5588 def : Pat<(i64 (bitconvert (v1i64 V64:$Vn))),
5589 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5590 def : Pat<(v1i64 (scalar_to_vector GPR64:$Xn)),
5591 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5592 def : Pat<(v1f64 (scalar_to_vector GPR64:$Xn)),
5593 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5594 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Xn))), (v1f64 FPR64:$Xn)>;
5596 def : Pat<(f32 (bitconvert (i32 GPR32:$Xn))),
5597 (COPY_TO_REGCLASS GPR32:$Xn, FPR32)>;
5598 def : Pat<(i32 (bitconvert (f32 FPR32:$Xn))),
5599 (COPY_TO_REGCLASS FPR32:$Xn, GPR32)>;
5600 def : Pat<(f64 (bitconvert (i64 GPR64:$Xn))),
5601 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5602 def : Pat<(i64 (bitconvert (f64 FPR64:$Xn))),
5603 (COPY_TO_REGCLASS FPR64:$Xn, GPR64)>;
5604 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
5605 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5607 let Predicates = [IsLE] in {
5608 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
5609 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
5610 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
5611 def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))), (v1i64 FPR64:$src)>;
5612 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
5614 let Predicates = [IsBE] in {
5615 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))),
5616 (v1i64 (REV64v2i32 FPR64:$src))>;
5617 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))),
5618 (v1i64 (REV64v4i16 FPR64:$src))>;
5619 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))),
5620 (v1i64 (REV64v8i8 FPR64:$src))>;
5621 def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))),
5622 (v1i64 (REV64v4i16 FPR64:$src))>;
5623 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))),
5624 (v1i64 (REV64v2i32 FPR64:$src))>;
5626 def : Pat<(v1i64 (bitconvert (v1f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5627 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5629 let Predicates = [IsLE] in {
5630 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))), (v2i32 FPR64:$src)>;
5631 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
5632 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
5633 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5634 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5635 def : Pat<(v2i32 (bitconvert (v4f16 FPR64:$src))), (v2i32 FPR64:$src)>;
5637 let Predicates = [IsBE] in {
5638 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))),
5639 (v2i32 (REV64v2i32 FPR64:$src))>;
5640 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))),
5641 (v2i32 (REV32v4i16 FPR64:$src))>;
5642 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))),
5643 (v2i32 (REV32v8i8 FPR64:$src))>;
5644 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))),
5645 (v2i32 (REV64v2i32 FPR64:$src))>;
5646 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))),
5647 (v2i32 (REV64v2i32 FPR64:$src))>;
5648 def : Pat<(v2i32 (bitconvert (v4f16 FPR64:$src))),
5649 (v2i32 (REV64v4i16 FPR64:$src))>;
5651 def : Pat<(v2i32 (bitconvert (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
5653 let Predicates = [IsLE] in {
5654 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))), (v4i16 FPR64:$src)>;
5655 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
5656 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
5657 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5658 def : Pat<(v4i16 (bitconvert (v4f16 FPR64:$src))), (v4i16 FPR64:$src)>;
5659 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
5660 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5662 let Predicates = [IsBE] in {
5663 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))),
5664 (v4i16 (REV64v4i16 FPR64:$src))>;
5665 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))),
5666 (v4i16 (REV32v4i16 FPR64:$src))>;
5667 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))),
5668 (v4i16 (REV16v8i8 FPR64:$src))>;
5669 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))),
5670 (v4i16 (REV64v4i16 FPR64:$src))>;
5671 def : Pat<(v4i16 (bitconvert (v4f16 FPR64:$src))),
5672 (v4i16 (REV32v4i16 FPR64:$src))>;
5673 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))),
5674 (v4i16 (REV32v4i16 FPR64:$src))>;
5675 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))),
5676 (v4i16 (REV64v4i16 FPR64:$src))>;
5679 let Predicates = [IsLE] in {
5680 def : Pat<(v4f16 (bitconvert (v1i64 FPR64:$src))), (v4f16 FPR64:$src)>;
5681 def : Pat<(v4f16 (bitconvert (v2i32 FPR64:$src))), (v4f16 FPR64:$src)>;
5682 def : Pat<(v4f16 (bitconvert (v4i16 FPR64:$src))), (v4f16 FPR64:$src)>;
5683 def : Pat<(v4f16 (bitconvert (v8i8 FPR64:$src))), (v4f16 FPR64:$src)>;
5684 def : Pat<(v4f16 (bitconvert (f64 FPR64:$src))), (v4f16 FPR64:$src)>;
5685 def : Pat<(v4f16 (bitconvert (v2f32 FPR64:$src))), (v4f16 FPR64:$src)>;
5686 def : Pat<(v4f16 (bitconvert (v1f64 FPR64:$src))), (v4f16 FPR64:$src)>;
5688 let Predicates = [IsBE] in {
5689 def : Pat<(v4f16 (bitconvert (v1i64 FPR64:$src))),
5690 (v4f16 (REV64v4i16 FPR64:$src))>;
5691 def : Pat<(v4f16 (bitconvert (v2i32 FPR64:$src))),
5692 (v4f16 (REV64v4i16 FPR64:$src))>;
5693 def : Pat<(v4f16 (bitconvert (v4i16 FPR64:$src))),
5694 (v4f16 (REV64v4i16 FPR64:$src))>;
5695 def : Pat<(v4f16 (bitconvert (v8i8 FPR64:$src))),
5696 (v4f16 (REV16v8i8 FPR64:$src))>;
5697 def : Pat<(v4f16 (bitconvert (f64 FPR64:$src))),
5698 (v4f16 (REV64v4i16 FPR64:$src))>;
5699 def : Pat<(v4f16 (bitconvert (v2f32 FPR64:$src))),
5700 (v4f16 (REV64v4i16 FPR64:$src))>;
5701 def : Pat<(v4f16 (bitconvert (v1f64 FPR64:$src))),
5702 (v4f16 (REV64v4i16 FPR64:$src))>;
5707 let Predicates = [IsLE] in {
5708 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))), (v8i8 FPR64:$src)>;
5709 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
5710 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
5711 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5712 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
5713 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5714 def : Pat<(v8i8 (bitconvert (v4f16 FPR64:$src))), (v8i8 FPR64:$src)>;
5716 let Predicates = [IsBE] in {
5717 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))),
5718 (v8i8 (REV64v8i8 FPR64:$src))>;
5719 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))),
5720 (v8i8 (REV32v8i8 FPR64:$src))>;
5721 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))),
5722 (v8i8 (REV16v8i8 FPR64:$src))>;
5723 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))),
5724 (v8i8 (REV64v8i8 FPR64:$src))>;
5725 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))),
5726 (v8i8 (REV32v8i8 FPR64:$src))>;
5727 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))),
5728 (v8i8 (REV64v8i8 FPR64:$src))>;
5729 def : Pat<(v8i8 (bitconvert (v4f16 FPR64:$src))),
5730 (v8i8 (REV16v8i8 FPR64:$src))>;
5733 let Predicates = [IsLE] in {
5734 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))), (f64 FPR64:$src)>;
5735 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))), (f64 FPR64:$src)>;
5736 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))), (f64 FPR64:$src)>;
5737 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))), (f64 FPR64:$src)>;
5738 def : Pat<(f64 (bitconvert (v4f16 FPR64:$src))), (f64 FPR64:$src)>;
5740 let Predicates = [IsBE] in {
5741 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))),
5742 (f64 (REV64v2i32 FPR64:$src))>;
5743 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))),
5744 (f64 (REV64v4i16 FPR64:$src))>;
5745 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))),
5746 (f64 (REV64v2i32 FPR64:$src))>;
5747 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))),
5748 (f64 (REV64v8i8 FPR64:$src))>;
5749 def : Pat<(f64 (bitconvert (v4f16 FPR64:$src))),
5750 (f64 (REV64v4i16 FPR64:$src))>;
5752 def : Pat<(f64 (bitconvert (v1i64 FPR64:$src))), (f64 FPR64:$src)>;
5753 def : Pat<(f64 (bitconvert (v1f64 FPR64:$src))), (f64 FPR64:$src)>;
5755 let Predicates = [IsLE] in {
5756 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))), (v1f64 FPR64:$src)>;
5757 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))), (v1f64 FPR64:$src)>;
5758 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))), (v1f64 FPR64:$src)>;
5759 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))), (v1f64 FPR64:$src)>;
5760 def : Pat<(v1f64 (bitconvert (v4f16 FPR64:$src))), (v1f64 FPR64:$src)>;
5762 let Predicates = [IsBE] in {
5763 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))),
5764 (v1f64 (REV64v2i32 FPR64:$src))>;
5765 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))),
5766 (v1f64 (REV64v4i16 FPR64:$src))>;
5767 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))),
5768 (v1f64 (REV64v8i8 FPR64:$src))>;
5769 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))),
5770 (v1f64 (REV64v2i32 FPR64:$src))>;
5771 def : Pat<(v1f64 (bitconvert (v4f16 FPR64:$src))),
5772 (v1f64 (REV64v4i16 FPR64:$src))>;
5774 def : Pat<(v1f64 (bitconvert (v1i64 FPR64:$src))), (v1f64 FPR64:$src)>;
5775 def : Pat<(v1f64 (bitconvert (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
5777 let Predicates = [IsLE] in {
5778 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))), (v2f32 FPR64:$src)>;
5779 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))), (v2f32 FPR64:$src)>;
5780 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))), (v2f32 FPR64:$src)>;
5781 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5782 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5783 def : Pat<(v2f32 (bitconvert (v4f16 FPR64:$src))), (v2f32 FPR64:$src)>;
5785 let Predicates = [IsBE] in {
5786 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))),
5787 (v2f32 (REV64v2i32 FPR64:$src))>;
5788 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))),
5789 (v2f32 (REV32v4i16 FPR64:$src))>;
5790 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))),
5791 (v2f32 (REV32v8i8 FPR64:$src))>;
5792 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))),
5793 (v2f32 (REV64v2i32 FPR64:$src))>;
5794 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))),
5795 (v2f32 (REV64v2i32 FPR64:$src))>;
5796 def : Pat<(v2f32 (bitconvert (v4f16 FPR64:$src))),
5797 (v2f32 (REV64v4i16 FPR64:$src))>;
5799 def : Pat<(v2f32 (bitconvert (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;
5801 let Predicates = [IsLE] in {
5802 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))), (f128 FPR128:$src)>;
5803 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))), (f128 FPR128:$src)>;
5804 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))), (f128 FPR128:$src)>;
5805 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))), (f128 FPR128:$src)>;
5806 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))), (f128 FPR128:$src)>;
5807 def : Pat<(f128 (bitconvert (v8f16 FPR128:$src))), (f128 FPR128:$src)>;
5808 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))), (f128 FPR128:$src)>;
5810 let Predicates = [IsBE] in {
5811 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))),
5812 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
5813 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))),
5814 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
5815 (REV64v4i32 FPR128:$src), (i32 8)))>;
5816 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))),
5817 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src),
5818 (REV64v8i16 FPR128:$src), (i32 8)))>;
5819 def : Pat<(f128 (bitconvert (v8f16 FPR128:$src))),
5820 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src),
5821 (REV64v8i16 FPR128:$src), (i32 8)))>;
5822 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))),
5823 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
5824 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))),
5825 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
5826 (REV64v4i32 FPR128:$src), (i32 8)))>;
5827 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))),
5828 (f128 (EXTv16i8 (REV64v16i8 FPR128:$src),
5829 (REV64v16i8 FPR128:$src), (i32 8)))>;
5832 let Predicates = [IsLE] in {
5833 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), (v2f64 FPR128:$src)>;
5834 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>;
5835 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>;
5836 def : Pat<(v2f64 (bitconvert (v8f16 FPR128:$src))), (v2f64 FPR128:$src)>;
5837 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>;
5838 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>;
5840 let Predicates = [IsBE] in {
5841 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))),
5842 (v2f64 (EXTv16i8 FPR128:$src,
5843 FPR128:$src, (i32 8)))>;
5844 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))),
5845 (v2f64 (REV64v4i32 FPR128:$src))>;
5846 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))),
5847 (v2f64 (REV64v8i16 FPR128:$src))>;
5848 def : Pat<(v2f64 (bitconvert (v8f16 FPR128:$src))),
5849 (v2f64 (REV64v8i16 FPR128:$src))>;
5850 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))),
5851 (v2f64 (REV64v16i8 FPR128:$src))>;
5852 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))),
5853 (v2f64 (REV64v4i32 FPR128:$src))>;
5855 def : Pat<(v2f64 (bitconvert (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
5857 let Predicates = [IsLE] in {
5858 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), (v4f32 FPR128:$src)>;
5859 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>;
5860 def : Pat<(v4f32 (bitconvert (v8f16 FPR128:$src))), (v4f32 FPR128:$src)>;
5861 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>;
5862 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;
5863 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>;
5865 let Predicates = [IsBE] in {
5866 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))),
5867 (v4f32 (EXTv16i8 (REV64v4i32 FPR128:$src),
5868 (REV64v4i32 FPR128:$src), (i32 8)))>;
5869 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))),
5870 (v4f32 (REV32v8i16 FPR128:$src))>;
5871 def : Pat<(v4f32 (bitconvert (v8f16 FPR128:$src))),
5872 (v4f32 (REV32v8i16 FPR128:$src))>;
5873 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))),
5874 (v4f32 (REV32v16i8 FPR128:$src))>;
5875 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))),
5876 (v4f32 (REV64v4i32 FPR128:$src))>;
5877 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))),
5878 (v4f32 (REV64v4i32 FPR128:$src))>;
5880 def : Pat<(v4f32 (bitconvert (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
5882 let Predicates = [IsLE] in {
5883 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), (v2i64 FPR128:$src)>;
5884 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
5885 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;
5886 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;
5887 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
5888 def : Pat<(v2i64 (bitconvert (v8f16 FPR128:$src))), (v2i64 FPR128:$src)>;
5890 let Predicates = [IsBE] in {
5891 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))),
5892 (v2i64 (EXTv16i8 FPR128:$src,
5893 FPR128:$src, (i32 8)))>;
5894 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))),
5895 (v2i64 (REV64v4i32 FPR128:$src))>;
5896 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))),
5897 (v2i64 (REV64v8i16 FPR128:$src))>;
5898 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))),
5899 (v2i64 (REV64v16i8 FPR128:$src))>;
5900 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))),
5901 (v2i64 (REV64v4i32 FPR128:$src))>;
5902 def : Pat<(v2i64 (bitconvert (v8f16 FPR128:$src))),
5903 (v2i64 (REV64v8i16 FPR128:$src))>;
5905 def : Pat<(v2i64 (bitconvert (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
5907 let Predicates = [IsLE] in {
5908 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), (v4i32 FPR128:$src)>;
5909 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
5910 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
5911 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
5912 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
5913 def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))), (v4i32 FPR128:$src)>;
5915 let Predicates = [IsBE] in {
5916 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))),
5917 (v4i32 (EXTv16i8 (REV64v4i32 FPR128:$src),
5918 (REV64v4i32 FPR128:$src),
5920 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))),
5921 (v4i32 (REV64v4i32 FPR128:$src))>;
5922 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))),
5923 (v4i32 (REV32v8i16 FPR128:$src))>;
5924 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))),
5925 (v4i32 (REV32v16i8 FPR128:$src))>;
5926 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))),
5927 (v4i32 (REV64v4i32 FPR128:$src))>;
5928 def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))),
5929 (v4i32 (REV32v8i16 FPR128:$src))>;
5931 def : Pat<(v4i32 (bitconvert (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
5933 let Predicates = [IsLE] in {
5934 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), (v8i16 FPR128:$src)>;
5935 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
5936 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
5937 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
5938 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
5939 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
5940 def : Pat<(v8i16 (bitconvert (v8f16 FPR128:$src))), (v8i16 FPR128:$src)>;
5942 let Predicates = [IsBE] in {
5943 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))),
5944 (v8i16 (EXTv16i8 (REV64v8i16 FPR128:$src),
5945 (REV64v8i16 FPR128:$src),
5947 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))),
5948 (v8i16 (REV64v8i16 FPR128:$src))>;
5949 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))),
5950 (v8i16 (REV32v8i16 FPR128:$src))>;
5951 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))),
5952 (v8i16 (REV16v16i8 FPR128:$src))>;
5953 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))),
5954 (v8i16 (REV64v8i16 FPR128:$src))>;
5955 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))),
5956 (v8i16 (REV32v8i16 FPR128:$src))>;
5957 def : Pat<(v8i16 (bitconvert (v8f16 FPR128:$src))),
5958 (v8i16 (REV32v8i16 FPR128:$src))>;
5961 let Predicates = [IsLE] in {
5962 def : Pat<(v8f16 (bitconvert (f128 FPR128:$src))), (v8f16 FPR128:$src)>;
5963 def : Pat<(v8f16 (bitconvert (v2i64 FPR128:$src))), (v8f16 FPR128:$src)>;
5964 def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))), (v8f16 FPR128:$src)>;
5965 def : Pat<(v8f16 (bitconvert (v8i16 FPR128:$src))), (v8f16 FPR128:$src)>;
5966 def : Pat<(v8f16 (bitconvert (v16i8 FPR128:$src))), (v8f16 FPR128:$src)>;
5967 def : Pat<(v8f16 (bitconvert (v2f64 FPR128:$src))), (v8f16 FPR128:$src)>;
5968 def : Pat<(v8f16 (bitconvert (v4f32 FPR128:$src))), (v8f16 FPR128:$src)>;
5970 let Predicates = [IsBE] in {
5971 def : Pat<(v8f16 (bitconvert (f128 FPR128:$src))),
5972 (v8f16 (EXTv16i8 (REV64v8i16 FPR128:$src),
5973 (REV64v8i16 FPR128:$src),
5975 def : Pat<(v8f16 (bitconvert (v2i64 FPR128:$src))),
5976 (v8f16 (REV64v8i16 FPR128:$src))>;
5977 def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))),
5978 (v8f16 (REV32v8i16 FPR128:$src))>;
5979 def : Pat<(v8f16 (bitconvert (v8i16 FPR128:$src))),
5980 (v8f16 (REV64v8i16 FPR128:$src))>;
5981 def : Pat<(v8f16 (bitconvert (v16i8 FPR128:$src))),
5982 (v8f16 (REV16v16i8 FPR128:$src))>;
5983 def : Pat<(v8f16 (bitconvert (v2f64 FPR128:$src))),
5984 (v8f16 (REV64v8i16 FPR128:$src))>;
5985 def : Pat<(v8f16 (bitconvert (v4f32 FPR128:$src))),
5986 (v8f16 (REV32v8i16 FPR128:$src))>;
5989 let Predicates = [IsLE] in {
5990 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 FPR128:$src)>;
5991 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
5992 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
5993 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
5994 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
5995 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
5996 def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))), (v16i8 FPR128:$src)>;
5998 let Predicates = [IsBE] in {
5999 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))),
6000 (v16i8 (EXTv16i8 (REV64v16i8 FPR128:$src),
6001 (REV64v16i8 FPR128:$src),
6003 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))),
6004 (v16i8 (REV64v16i8 FPR128:$src))>;
6005 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))),
6006 (v16i8 (REV32v16i8 FPR128:$src))>;
6007 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))),
6008 (v16i8 (REV16v16i8 FPR128:$src))>;
6009 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))),
6010 (v16i8 (REV64v16i8 FPR128:$src))>;
6011 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))),
6012 (v16i8 (REV32v16i8 FPR128:$src))>;
6013 def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))),
6014 (v16i8 (REV16v16i8 FPR128:$src))>;
6017 def : Pat<(v4i16 (extract_subvector V128:$Rn, (i64 0))),
6018 (EXTRACT_SUBREG V128:$Rn, dsub)>;
6019 def : Pat<(v8i8 (extract_subvector V128:$Rn, (i64 0))),
6020 (EXTRACT_SUBREG V128:$Rn, dsub)>;
6021 def : Pat<(v2f32 (extract_subvector V128:$Rn, (i64 0))),
6022 (EXTRACT_SUBREG V128:$Rn, dsub)>;
6023 def : Pat<(v4f16 (extract_subvector V128:$Rn, (i64 0))),
6024 (EXTRACT_SUBREG V128:$Rn, dsub)>;
6025 def : Pat<(v2i32 (extract_subvector V128:$Rn, (i64 0))),
6026 (EXTRACT_SUBREG V128:$Rn, dsub)>;
6027 def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 0))),
6028 (EXTRACT_SUBREG V128:$Rn, dsub)>;
6029 def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 0))),
6030 (EXTRACT_SUBREG V128:$Rn, dsub)>;
6032 def : Pat<(v8i8 (extract_subvector (v16i8 FPR128:$Rn), (i64 1))),
6033 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
6034 def : Pat<(v4i16 (extract_subvector (v8i16 FPR128:$Rn), (i64 1))),
6035 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
6036 def : Pat<(v2i32 (extract_subvector (v4i32 FPR128:$Rn), (i64 1))),
6037 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
6038 def : Pat<(v1i64 (extract_subvector (v2i64 FPR128:$Rn), (i64 1))),
6039 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
6041 // A 64-bit subvector insert to the first 128-bit vector position
6042 // is a subregister copy that needs no instruction.
6043 def : Pat<(insert_subvector undef, (v1i64 FPR64:$src), (i32 0)),
6044 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
6045 def : Pat<(insert_subvector undef, (v1f64 FPR64:$src), (i32 0)),
6046 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
6047 def : Pat<(insert_subvector undef, (v2i32 FPR64:$src), (i32 0)),
6048 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
6049 def : Pat<(insert_subvector undef, (v2f32 FPR64:$src), (i32 0)),
6050 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
6051 def : Pat<(insert_subvector undef, (v4i16 FPR64:$src), (i32 0)),
6052 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
6053 def : Pat<(insert_subvector undef, (v4f16 FPR64:$src), (i32 0)),
6054 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
6055 def : Pat<(insert_subvector undef, (v8i8 FPR64:$src), (i32 0)),
6056 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
6058 // Use pair-wise add instructions when summing up the lanes for v2f64, v2i64
6060 def : Pat<(i64 (add (vector_extract (v2i64 FPR128:$Rn), (i64 0)),
6061 (vector_extract (v2i64 FPR128:$Rn), (i64 1)))),
6062 (i64 (ADDPv2i64p (v2i64 FPR128:$Rn)))>;
6063 def : Pat<(f64 (fadd (vector_extract (v2f64 FPR128:$Rn), (i64 0)),
6064 (vector_extract (v2f64 FPR128:$Rn), (i64 1)))),
6065 (f64 (FADDPv2i64p (v2f64 FPR128:$Rn)))>;
6066 // vector_extract on 64-bit vectors gets promoted to a 128 bit vector,
6067 // so we match on v4f32 here, not v2f32. This will also catch adding
6068 // the low two lanes of a true v4f32 vector.
6069 def : Pat<(fadd (vector_extract (v4f32 FPR128:$Rn), (i64 0)),
6070 (vector_extract (v4f32 FPR128:$Rn), (i64 1))),
6071 (f32 (FADDPv2i32p (EXTRACT_SUBREG FPR128:$Rn, dsub)))>;
6073 // Scalar 64-bit shifts in FPR64 registers.
6074 def : Pat<(i64 (int_aarch64_neon_sshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
6075 (SSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
6076 def : Pat<(i64 (int_aarch64_neon_ushl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
6077 (USHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
6078 def : Pat<(i64 (int_aarch64_neon_srshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
6079 (SRSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
6080 def : Pat<(i64 (int_aarch64_neon_urshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
6081 (URSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
6083 // Patterns for nontemporal/no-allocate stores.
6084 // We have to resort to tricks to turn a single-input store into a store pair,
6085 // because there is no single-input nontemporal store, only STNP.
6086 let Predicates = [IsLE] in {
6087 let AddedComplexity = 15 in {
6088 class NTStore128Pat<ValueType VT> :
6089 Pat<(nontemporalstore (VT FPR128:$Rt),
6090 (am_indexed7s64 GPR64sp:$Rn, simm7s8:$offset)),
6091 (STNPDi (EXTRACT_SUBREG FPR128:$Rt, dsub),
6092 (CPYi64 FPR128:$Rt, (i64 1)),
6093 GPR64sp:$Rn, simm7s8:$offset)>;
6095 def : NTStore128Pat<v2i64>;
6096 def : NTStore128Pat<v4i32>;
6097 def : NTStore128Pat<v8i16>;
6098 def : NTStore128Pat<v16i8>;
6100 class NTStore64Pat<ValueType VT> :
6101 Pat<(nontemporalstore (VT FPR64:$Rt),
6102 (am_indexed7s32 GPR64sp:$Rn, simm7s4:$offset)),
6103 (STNPSi (EXTRACT_SUBREG FPR64:$Rt, ssub),
6104 (CPYi32 (SUBREG_TO_REG (i64 0), FPR64:$Rt, dsub), (i64 1)),
6105 GPR64sp:$Rn, simm7s4:$offset)>;
6107 // FIXME: Shouldn't v1f64 loads/stores be promoted to v1i64?
6108 def : NTStore64Pat<v1f64>;
6109 def : NTStore64Pat<v1i64>;
6110 def : NTStore64Pat<v2i32>;
6111 def : NTStore64Pat<v4i16>;
6112 def : NTStore64Pat<v8i8>;
6114 def : Pat<(nontemporalstore GPR64:$Rt,
6115 (am_indexed7s32 GPR64sp:$Rn, simm7s4:$offset)),
6116 (STNPWi (EXTRACT_SUBREG GPR64:$Rt, sub_32),
6117 (EXTRACT_SUBREG (UBFMXri GPR64:$Rt, 32, 63), sub_32),
6118 GPR64sp:$Rn, simm7s4:$offset)>;
6119 } // AddedComplexity=10
6120 } // Predicates = [IsLE]
6122 // Tail call return handling. These are all compiler pseudo-instructions,
6123 // so no encoding information or anything like that.
6124 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
6125 def TCRETURNdi : Pseudo<(outs), (ins i64imm:$dst, i32imm:$FPDiff), []>,
6126 Sched<[WriteBrReg]>;
6127 def TCRETURNri : Pseudo<(outs), (ins tcGPR64:$dst, i32imm:$FPDiff), []>,
6128 Sched<[WriteBrReg]>;
6131 def : Pat<(AArch64tcret tcGPR64:$dst, (i32 timm:$FPDiff)),
6132 (TCRETURNri tcGPR64:$dst, imm:$FPDiff)>;
6133 def : Pat<(AArch64tcret tglobaladdr:$dst, (i32 timm:$FPDiff)),
6134 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
6135 def : Pat<(AArch64tcret texternalsym:$dst, (i32 timm:$FPDiff)),
6136 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
6138 include "AArch64InstrAtomics.td"