1 //=- AArch64InstrInfo.td - Describe the AArch64 Instructions -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // AArch64 Instruction definitions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM Instruction Predicate Definitions.
17 def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">,
18 AssemblerPredicate<"HasV8_1aOps", "armv8.1a">;
19 def HasV8_2a : Predicate<"Subtarget->hasV8_2aOps()">,
20 AssemblerPredicate<"HasV8_2aOps", "armv8.2a">;
21 def HasV8_3a : Predicate<"Subtarget->hasV8_3aOps()">,
22 AssemblerPredicate<"HasV8_3aOps", "armv8.3a">;
23 def HasV8_4a : Predicate<"Subtarget->hasV8_4aOps()">,
24 AssemblerPredicate<"HasV8_4aOps", "armv8.4a">;
25 def HasV8_5a : Predicate<"Subtarget->hasV8_5aOps()">,
26 AssemblerPredicate<"HasV8_5aOps", "armv8.5a">;
27 def HasVH : Predicate<"Subtarget->hasVH()">,
28 AssemblerPredicate<"FeatureVH", "vh">;
30 def HasLOR : Predicate<"Subtarget->hasLOR()">,
31 AssemblerPredicate<"FeatureLOR", "lor">;
33 def HasPA : Predicate<"Subtarget->hasPA()">,
34 AssemblerPredicate<"FeaturePA", "pa">;
36 def HasJS : Predicate<"Subtarget->hasJS()">,
37 AssemblerPredicate<"FeatureJS", "jsconv">;
39 def HasCCIDX : Predicate<"Subtarget->hasCCIDX()">,
40 AssemblerPredicate<"FeatureCCIDX", "ccidx">;
42 def HasComplxNum : Predicate<"Subtarget->hasComplxNum()">,
43 AssemblerPredicate<"FeatureComplxNum", "complxnum">;
45 def HasNV : Predicate<"Subtarget->hasNV()">,
46 AssemblerPredicate<"FeatureNV", "nv">;
48 def HasRASv8_4 : Predicate<"Subtarget->hasRASv8_4()">,
49 AssemblerPredicate<"FeatureRASv8_4", "rasv8_4">;
51 def HasMPAM : Predicate<"Subtarget->hasMPAM()">,
52 AssemblerPredicate<"FeatureMPAM", "mpam">;
54 def HasDIT : Predicate<"Subtarget->hasDIT()">,
55 AssemblerPredicate<"FeatureDIT", "dit">;
57 def HasTRACEV8_4 : Predicate<"Subtarget->hasTRACEV8_4()">,
58 AssemblerPredicate<"FeatureTRACEV8_4", "tracev8.4">;
60 def HasAM : Predicate<"Subtarget->hasAM()">,
61 AssemblerPredicate<"FeatureAM", "am">;
63 def HasSEL2 : Predicate<"Subtarget->hasSEL2()">,
64 AssemblerPredicate<"FeatureSEL2", "sel2">;
66 def HasTLB_RMI : Predicate<"Subtarget->hasTLB_RMI()">,
67 AssemblerPredicate<"FeatureTLB_RMI", "tlb-rmi">;
69 def HasFMI : Predicate<"Subtarget->hasFMI()">,
70 AssemblerPredicate<"FeatureFMI", "fmi">;
72 def HasRCPC_IMMO : Predicate<"Subtarget->hasRCPCImm()">,
73 AssemblerPredicate<"FeatureRCPC_IMMO", "rcpc-immo">;
75 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
76 AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">;
77 def HasNEON : Predicate<"Subtarget->hasNEON()">,
78 AssemblerPredicate<"FeatureNEON", "neon">;
79 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
80 AssemblerPredicate<"FeatureCrypto", "crypto">;
81 def HasSM4 : Predicate<"Subtarget->hasSM4()">,
82 AssemblerPredicate<"FeatureSM4", "sm4">;
83 def HasSHA3 : Predicate<"Subtarget->hasSHA3()">,
84 AssemblerPredicate<"FeatureSHA3", "sha3">;
85 def HasSHA2 : Predicate<"Subtarget->hasSHA2()">,
86 AssemblerPredicate<"FeatureSHA2", "sha2">;
87 def HasAES : Predicate<"Subtarget->hasAES()">,
88 AssemblerPredicate<"FeatureAES", "aes">;
89 def HasDotProd : Predicate<"Subtarget->hasDotProd()">,
90 AssemblerPredicate<"FeatureDotProd", "dotprod">;
91 def HasCRC : Predicate<"Subtarget->hasCRC()">,
92 AssemblerPredicate<"FeatureCRC", "crc">;
93 def HasLSE : Predicate<"Subtarget->hasLSE()">,
94 AssemblerPredicate<"FeatureLSE", "lse">;
95 def HasRAS : Predicate<"Subtarget->hasRAS()">,
96 AssemblerPredicate<"FeatureRAS", "ras">;
97 def HasRDM : Predicate<"Subtarget->hasRDM()">,
98 AssemblerPredicate<"FeatureRDM", "rdm">;
99 def HasPerfMon : Predicate<"Subtarget->hasPerfMon()">;
100 def HasFullFP16 : Predicate<"Subtarget->hasFullFP16()">,
101 AssemblerPredicate<"FeatureFullFP16", "fullfp16">;
102 def HasFP16FML : Predicate<"Subtarget->hasFP16FML()">,
103 AssemblerPredicate<"FeatureFP16FML", "fp16fml">;
104 def HasSPE : Predicate<"Subtarget->hasSPE()">,
105 AssemblerPredicate<"FeatureSPE", "spe">;
106 def HasFuseAES : Predicate<"Subtarget->hasFuseAES()">,
107 AssemblerPredicate<"FeatureFuseAES",
109 def HasSVE : Predicate<"Subtarget->hasSVE()">,
110 AssemblerPredicate<"FeatureSVE", "sve">;
111 def HasRCPC : Predicate<"Subtarget->hasRCPC()">,
112 AssemblerPredicate<"FeatureRCPC", "rcpc">;
113 def HasAltNZCV : Predicate<"Subtarget->hasAlternativeNZCV()">,
114 AssemblerPredicate<"FeatureAltFPCmp", "altnzcv">;
115 def HasFRInt3264 : Predicate<"Subtarget->hasFRInt3264()">,
116 AssemblerPredicate<"FeatureFRInt3264", "frint3264">;
117 def HasSB : Predicate<"Subtarget->hasSB()">,
118 AssemblerPredicate<"FeatureSB", "sb">;
119 def HasPredRes : Predicate<"Subtarget->hasPredRes()">,
120 AssemblerPredicate<"FeaturePredRes", "predres">;
121 def HasCCDP : Predicate<"Subtarget->hasCCDP()">,
122 AssemblerPredicate<"FeatureCacheDeepPersist", "ccdp">;
123 def HasBTI : Predicate<"Subtarget->hasBTI()">,
124 AssemblerPredicate<"FeatureBranchTargetId", "bti">;
125 def HasMTE : Predicate<"Subtarget->hasMTE()">,
126 AssemblerPredicate<"FeatureMTE", "mte">;
127 def IsLE : Predicate<"Subtarget->isLittleEndian()">;
128 def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
129 def UseAlternateSExtLoadCVTF32
130 : Predicate<"Subtarget->useAlternateSExtLoadCVTF32Pattern()">;
132 def UseNegativeImmediates
133 : Predicate<"false">, AssemblerPredicate<"!FeatureNoNegativeImmediates",
134 "NegativeImmediates">;
137 //===----------------------------------------------------------------------===//
138 // AArch64-specific DAG Nodes.
141 // SDTBinaryArithWithFlagsOut - RES1, FLAGS = op LHS, RHS
142 def SDTBinaryArithWithFlagsOut : SDTypeProfile<2, 2,
145 SDTCisInt<0>, SDTCisVT<1, i32>]>;
147 // SDTBinaryArithWithFlagsIn - RES1, FLAGS = op LHS, RHS, FLAGS
148 def SDTBinaryArithWithFlagsIn : SDTypeProfile<1, 3,
154 // SDTBinaryArithWithFlagsInOut - RES1, FLAGS = op LHS, RHS, FLAGS
155 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
162 def SDT_AArch64Brcond : SDTypeProfile<0, 3,
163 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>,
165 def SDT_AArch64cbz : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisVT<1, OtherVT>]>;
166 def SDT_AArch64tbz : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>,
167 SDTCisVT<2, OtherVT>]>;
170 def SDT_AArch64CSel : SDTypeProfile<1, 4,
175 def SDT_AArch64CCMP : SDTypeProfile<1, 5,
182 def SDT_AArch64FCCMP : SDTypeProfile<1, 5,
189 def SDT_AArch64FCmp : SDTypeProfile<0, 2,
191 SDTCisSameAs<0, 1>]>;
192 def SDT_AArch64Dup : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
193 def SDT_AArch64DupLane : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<2>]>;
194 def SDT_AArch64Zip : SDTypeProfile<1, 2, [SDTCisVec<0>,
196 SDTCisSameAs<0, 2>]>;
197 def SDT_AArch64MOVIedit : SDTypeProfile<1, 1, [SDTCisInt<1>]>;
198 def SDT_AArch64MOVIshift : SDTypeProfile<1, 2, [SDTCisInt<1>, SDTCisInt<2>]>;
199 def SDT_AArch64vecimm : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
200 SDTCisInt<2>, SDTCisInt<3>]>;
201 def SDT_AArch64UnaryVec: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
202 def SDT_AArch64ExtVec: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
203 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
204 def SDT_AArch64vshift : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>, SDTCisInt<2>]>;
206 def SDT_AArch64unvec : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
207 def SDT_AArch64fcmpz : SDTypeProfile<1, 1, []>;
208 def SDT_AArch64fcmp : SDTypeProfile<1, 2, [SDTCisSameAs<1,2>]>;
209 def SDT_AArch64binvec : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
211 def SDT_AArch64trivec : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
214 def SDT_AArch64TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>]>;
215 def SDT_AArch64PREFETCH : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<1>]>;
217 def SDT_AArch64ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>;
219 def SDT_AArch64TLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>,
222 // Generates the general dynamic sequences, i.e.
223 // adrp x0, :tlsdesc:var
224 // ldr x1, [x0, #:tlsdesc_lo12:var]
225 // add x0, x0, #:tlsdesc_lo12:var
229 // (the TPIDR_EL0 offset is put directly in X0, hence no "result" here)
230 // number of operands (the variable)
231 def SDT_AArch64TLSDescCallSeq : SDTypeProfile<0,1,
234 def SDT_AArch64WrapperLarge : SDTypeProfile<1, 4,
235 [SDTCisVT<0, i64>, SDTCisVT<1, i32>,
236 SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>,
237 SDTCisSameAs<1, 4>]>;
241 def AArch64adrp : SDNode<"AArch64ISD::ADRP", SDTIntUnaryOp, []>;
242 def AArch64adr : SDNode<"AArch64ISD::ADR", SDTIntUnaryOp, []>;
243 def AArch64addlow : SDNode<"AArch64ISD::ADDlow", SDTIntBinOp, []>;
244 def AArch64LOADgot : SDNode<"AArch64ISD::LOADgot", SDTIntUnaryOp>;
245 def AArch64callseq_start : SDNode<"ISD::CALLSEQ_START",
246 SDCallSeqStart<[ SDTCisVT<0, i32>,
248 [SDNPHasChain, SDNPOutGlue]>;
249 def AArch64callseq_end : SDNode<"ISD::CALLSEQ_END",
250 SDCallSeqEnd<[ SDTCisVT<0, i32>,
252 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
253 def AArch64call : SDNode<"AArch64ISD::CALL",
254 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
255 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
257 def AArch64brcond : SDNode<"AArch64ISD::BRCOND", SDT_AArch64Brcond,
259 def AArch64cbz : SDNode<"AArch64ISD::CBZ", SDT_AArch64cbz,
261 def AArch64cbnz : SDNode<"AArch64ISD::CBNZ", SDT_AArch64cbz,
263 def AArch64tbz : SDNode<"AArch64ISD::TBZ", SDT_AArch64tbz,
265 def AArch64tbnz : SDNode<"AArch64ISD::TBNZ", SDT_AArch64tbz,
269 def AArch64csel : SDNode<"AArch64ISD::CSEL", SDT_AArch64CSel>;
270 def AArch64csinv : SDNode<"AArch64ISD::CSINV", SDT_AArch64CSel>;
271 def AArch64csneg : SDNode<"AArch64ISD::CSNEG", SDT_AArch64CSel>;
272 def AArch64csinc : SDNode<"AArch64ISD::CSINC", SDT_AArch64CSel>;
273 def AArch64retflag : SDNode<"AArch64ISD::RET_FLAG", SDTNone,
274 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
275 def AArch64adc : SDNode<"AArch64ISD::ADC", SDTBinaryArithWithFlagsIn >;
276 def AArch64sbc : SDNode<"AArch64ISD::SBC", SDTBinaryArithWithFlagsIn>;
277 def AArch64add_flag : SDNode<"AArch64ISD::ADDS", SDTBinaryArithWithFlagsOut,
279 def AArch64sub_flag : SDNode<"AArch64ISD::SUBS", SDTBinaryArithWithFlagsOut>;
280 def AArch64and_flag : SDNode<"AArch64ISD::ANDS", SDTBinaryArithWithFlagsOut,
282 def AArch64adc_flag : SDNode<"AArch64ISD::ADCS", SDTBinaryArithWithFlagsInOut>;
283 def AArch64sbc_flag : SDNode<"AArch64ISD::SBCS", SDTBinaryArithWithFlagsInOut>;
285 def AArch64ccmp : SDNode<"AArch64ISD::CCMP", SDT_AArch64CCMP>;
286 def AArch64ccmn : SDNode<"AArch64ISD::CCMN", SDT_AArch64CCMP>;
287 def AArch64fccmp : SDNode<"AArch64ISD::FCCMP", SDT_AArch64FCCMP>;
289 def AArch64threadpointer : SDNode<"AArch64ISD::THREAD_POINTER", SDTPtrLeaf>;
291 def AArch64fcmp : SDNode<"AArch64ISD::FCMP", SDT_AArch64FCmp>;
293 def AArch64dup : SDNode<"AArch64ISD::DUP", SDT_AArch64Dup>;
294 def AArch64duplane8 : SDNode<"AArch64ISD::DUPLANE8", SDT_AArch64DupLane>;
295 def AArch64duplane16 : SDNode<"AArch64ISD::DUPLANE16", SDT_AArch64DupLane>;
296 def AArch64duplane32 : SDNode<"AArch64ISD::DUPLANE32", SDT_AArch64DupLane>;
297 def AArch64duplane64 : SDNode<"AArch64ISD::DUPLANE64", SDT_AArch64DupLane>;
299 def AArch64zip1 : SDNode<"AArch64ISD::ZIP1", SDT_AArch64Zip>;
300 def AArch64zip2 : SDNode<"AArch64ISD::ZIP2", SDT_AArch64Zip>;
301 def AArch64uzp1 : SDNode<"AArch64ISD::UZP1", SDT_AArch64Zip>;
302 def AArch64uzp2 : SDNode<"AArch64ISD::UZP2", SDT_AArch64Zip>;
303 def AArch64trn1 : SDNode<"AArch64ISD::TRN1", SDT_AArch64Zip>;
304 def AArch64trn2 : SDNode<"AArch64ISD::TRN2", SDT_AArch64Zip>;
306 def AArch64movi_edit : SDNode<"AArch64ISD::MOVIedit", SDT_AArch64MOVIedit>;
307 def AArch64movi_shift : SDNode<"AArch64ISD::MOVIshift", SDT_AArch64MOVIshift>;
308 def AArch64movi_msl : SDNode<"AArch64ISD::MOVImsl", SDT_AArch64MOVIshift>;
309 def AArch64mvni_shift : SDNode<"AArch64ISD::MVNIshift", SDT_AArch64MOVIshift>;
310 def AArch64mvni_msl : SDNode<"AArch64ISD::MVNImsl", SDT_AArch64MOVIshift>;
311 def AArch64movi : SDNode<"AArch64ISD::MOVI", SDT_AArch64MOVIedit>;
312 def AArch64fmov : SDNode<"AArch64ISD::FMOV", SDT_AArch64MOVIedit>;
314 def AArch64rev16 : SDNode<"AArch64ISD::REV16", SDT_AArch64UnaryVec>;
315 def AArch64rev32 : SDNode<"AArch64ISD::REV32", SDT_AArch64UnaryVec>;
316 def AArch64rev64 : SDNode<"AArch64ISD::REV64", SDT_AArch64UnaryVec>;
317 def AArch64ext : SDNode<"AArch64ISD::EXT", SDT_AArch64ExtVec>;
319 def AArch64vashr : SDNode<"AArch64ISD::VASHR", SDT_AArch64vshift>;
320 def AArch64vlshr : SDNode<"AArch64ISD::VLSHR", SDT_AArch64vshift>;
321 def AArch64vshl : SDNode<"AArch64ISD::VSHL", SDT_AArch64vshift>;
322 def AArch64sqshli : SDNode<"AArch64ISD::SQSHL_I", SDT_AArch64vshift>;
323 def AArch64uqshli : SDNode<"AArch64ISD::UQSHL_I", SDT_AArch64vshift>;
324 def AArch64sqshlui : SDNode<"AArch64ISD::SQSHLU_I", SDT_AArch64vshift>;
325 def AArch64srshri : SDNode<"AArch64ISD::SRSHR_I", SDT_AArch64vshift>;
326 def AArch64urshri : SDNode<"AArch64ISD::URSHR_I", SDT_AArch64vshift>;
328 def AArch64not: SDNode<"AArch64ISD::NOT", SDT_AArch64unvec>;
329 def AArch64bit: SDNode<"AArch64ISD::BIT", SDT_AArch64trivec>;
330 def AArch64bsl: SDNode<"AArch64ISD::BSL", SDT_AArch64trivec>;
332 def AArch64cmeq: SDNode<"AArch64ISD::CMEQ", SDT_AArch64binvec>;
333 def AArch64cmge: SDNode<"AArch64ISD::CMGE", SDT_AArch64binvec>;
334 def AArch64cmgt: SDNode<"AArch64ISD::CMGT", SDT_AArch64binvec>;
335 def AArch64cmhi: SDNode<"AArch64ISD::CMHI", SDT_AArch64binvec>;
336 def AArch64cmhs: SDNode<"AArch64ISD::CMHS", SDT_AArch64binvec>;
338 def AArch64fcmeq: SDNode<"AArch64ISD::FCMEQ", SDT_AArch64fcmp>;
339 def AArch64fcmge: SDNode<"AArch64ISD::FCMGE", SDT_AArch64fcmp>;
340 def AArch64fcmgt: SDNode<"AArch64ISD::FCMGT", SDT_AArch64fcmp>;
342 def AArch64cmeqz: SDNode<"AArch64ISD::CMEQz", SDT_AArch64unvec>;
343 def AArch64cmgez: SDNode<"AArch64ISD::CMGEz", SDT_AArch64unvec>;
344 def AArch64cmgtz: SDNode<"AArch64ISD::CMGTz", SDT_AArch64unvec>;
345 def AArch64cmlez: SDNode<"AArch64ISD::CMLEz", SDT_AArch64unvec>;
346 def AArch64cmltz: SDNode<"AArch64ISD::CMLTz", SDT_AArch64unvec>;
347 def AArch64cmtst : PatFrag<(ops node:$LHS, node:$RHS),
348 (AArch64not (AArch64cmeqz (and node:$LHS, node:$RHS)))>;
350 def AArch64fcmeqz: SDNode<"AArch64ISD::FCMEQz", SDT_AArch64fcmpz>;
351 def AArch64fcmgez: SDNode<"AArch64ISD::FCMGEz", SDT_AArch64fcmpz>;
352 def AArch64fcmgtz: SDNode<"AArch64ISD::FCMGTz", SDT_AArch64fcmpz>;
353 def AArch64fcmlez: SDNode<"AArch64ISD::FCMLEz", SDT_AArch64fcmpz>;
354 def AArch64fcmltz: SDNode<"AArch64ISD::FCMLTz", SDT_AArch64fcmpz>;
356 def AArch64bici: SDNode<"AArch64ISD::BICi", SDT_AArch64vecimm>;
357 def AArch64orri: SDNode<"AArch64ISD::ORRi", SDT_AArch64vecimm>;
359 def AArch64neg : SDNode<"AArch64ISD::NEG", SDT_AArch64unvec>;
361 def AArch64tcret: SDNode<"AArch64ISD::TC_RETURN", SDT_AArch64TCRET,
362 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
364 def AArch64Prefetch : SDNode<"AArch64ISD::PREFETCH", SDT_AArch64PREFETCH,
365 [SDNPHasChain, SDNPSideEffect]>;
367 def AArch64sitof: SDNode<"AArch64ISD::SITOF", SDT_AArch64ITOF>;
368 def AArch64uitof: SDNode<"AArch64ISD::UITOF", SDT_AArch64ITOF>;
370 def AArch64tlsdesc_callseq : SDNode<"AArch64ISD::TLSDESC_CALLSEQ",
371 SDT_AArch64TLSDescCallSeq,
372 [SDNPInGlue, SDNPOutGlue, SDNPHasChain,
376 def AArch64WrapperLarge : SDNode<"AArch64ISD::WrapperLarge",
377 SDT_AArch64WrapperLarge>;
379 def AArch64NvCast : SDNode<"AArch64ISD::NVCAST", SDTUnaryOp>;
381 def SDT_AArch64mull : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
382 SDTCisSameAs<1, 2>]>;
383 def AArch64smull : SDNode<"AArch64ISD::SMULL", SDT_AArch64mull>;
384 def AArch64umull : SDNode<"AArch64ISD::UMULL", SDT_AArch64mull>;
386 def AArch64frecpe : SDNode<"AArch64ISD::FRECPE", SDTFPUnaryOp>;
387 def AArch64frecps : SDNode<"AArch64ISD::FRECPS", SDTFPBinOp>;
388 def AArch64frsqrte : SDNode<"AArch64ISD::FRSQRTE", SDTFPUnaryOp>;
389 def AArch64frsqrts : SDNode<"AArch64ISD::FRSQRTS", SDTFPBinOp>;
391 def AArch64saddv : SDNode<"AArch64ISD::SADDV", SDT_AArch64UnaryVec>;
392 def AArch64uaddv : SDNode<"AArch64ISD::UADDV", SDT_AArch64UnaryVec>;
393 def AArch64sminv : SDNode<"AArch64ISD::SMINV", SDT_AArch64UnaryVec>;
394 def AArch64uminv : SDNode<"AArch64ISD::UMINV", SDT_AArch64UnaryVec>;
395 def AArch64smaxv : SDNode<"AArch64ISD::SMAXV", SDT_AArch64UnaryVec>;
396 def AArch64umaxv : SDNode<"AArch64ISD::UMAXV", SDT_AArch64UnaryVec>;
398 //===----------------------------------------------------------------------===//
400 //===----------------------------------------------------------------------===//
402 // AArch64 Instruction Predicate Definitions.
403 // We could compute these on a per-module basis but doing so requires accessing
404 // the Function object through the <Target>Subtarget and objections were raised
405 // to that (see post-commit review comments for r301750).
406 let RecomputePerFunction = 1 in {
407 def ForCodeSize : Predicate<"MF->getFunction().optForSize()">;
408 def NotForCodeSize : Predicate<"!MF->getFunction().optForSize()">;
409 // Avoid generating STRQro if it is slow, unless we're optimizing for code size.
410 def UseSTRQro : Predicate<"!Subtarget->isSTRQroSlow() || MF->getFunction().optForSize()">;
412 def UseBTI : Predicate<[{ MF->getFunction().hasFnAttribute("branch-target-enforcement") }]>;
413 def NotUseBTI : Predicate<[{ !MF->getFunction().hasFnAttribute("branch-target-enforcement") }]>;
416 include "AArch64InstrFormats.td"
417 include "SVEInstrFormats.td"
419 //===----------------------------------------------------------------------===//
421 //===----------------------------------------------------------------------===//
422 // Miscellaneous instructions.
423 //===----------------------------------------------------------------------===//
425 let Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1 in {
426 // We set Sched to empty list because we expect these instructions to simply get
427 // removed in most cases.
428 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
429 [(AArch64callseq_start timm:$amt1, timm:$amt2)]>,
431 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
432 [(AArch64callseq_end timm:$amt1, timm:$amt2)]>,
434 } // Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1
436 let isReMaterializable = 1, isCodeGenOnly = 1 in {
437 // FIXME: The following pseudo instructions are only needed because remat
438 // cannot handle multiple instructions. When that changes, they can be
439 // removed, along with the AArch64Wrapper node.
441 let AddedComplexity = 10 in
442 def LOADgot : Pseudo<(outs GPR64:$dst), (ins i64imm:$addr),
443 [(set GPR64:$dst, (AArch64LOADgot tglobaladdr:$addr))]>,
446 // The MOVaddr instruction should match only when the add is not folded
447 // into a load or store address.
449 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
450 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaladdr:$hi),
451 tglobaladdr:$low))]>,
452 Sched<[WriteAdrAdr]>;
454 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
455 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tjumptable:$hi),
457 Sched<[WriteAdrAdr]>;
459 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
460 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tconstpool:$hi),
462 Sched<[WriteAdrAdr]>;
464 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
465 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tblockaddress:$hi),
466 tblockaddress:$low))]>,
467 Sched<[WriteAdrAdr]>;
469 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
470 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaltlsaddr:$hi),
471 tglobaltlsaddr:$low))]>,
472 Sched<[WriteAdrAdr]>;
474 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
475 [(set GPR64:$dst, (AArch64addlow (AArch64adrp texternalsym:$hi),
476 texternalsym:$low))]>,
477 Sched<[WriteAdrAdr]>;
478 // Normally AArch64addlow either gets folded into a following ldr/str,
479 // or together with an adrp into MOVaddr above. For cases with TLS, it
480 // might appear without either of them, so allow lowering it into a plain
483 : Pseudo<(outs GPR64:$dst), (ins GPR64:$src, i64imm:$low),
484 [(set GPR64:$dst, (AArch64addlow GPR64:$src,
485 tglobaltlsaddr:$low))]>,
488 } // isReMaterializable, isCodeGenOnly
490 def : Pat<(AArch64LOADgot tglobaltlsaddr:$addr),
491 (LOADgot tglobaltlsaddr:$addr)>;
493 def : Pat<(AArch64LOADgot texternalsym:$addr),
494 (LOADgot texternalsym:$addr)>;
496 def : Pat<(AArch64LOADgot tconstpool:$addr),
497 (LOADgot tconstpool:$addr)>;
499 // 32-bit jump table destination is actually only 2 instructions since we can
500 // use the table itself as a PC-relative base. But optimization occurs after
501 // branch relaxation so be pessimistic.
502 let Size = 12, Constraints = "@earlyclobber $dst,@earlyclobber $scratch" in {
503 def JumpTableDest32 : Pseudo<(outs GPR64:$dst, GPR64sp:$scratch),
504 (ins GPR64:$table, GPR64:$entry, i32imm:$jti), []>,
506 def JumpTableDest16 : Pseudo<(outs GPR64:$dst, GPR64sp:$scratch),
507 (ins GPR64:$table, GPR64:$entry, i32imm:$jti), []>,
509 def JumpTableDest8 : Pseudo<(outs GPR64:$dst, GPR64sp:$scratch),
510 (ins GPR64:$table, GPR64:$entry, i32imm:$jti), []>,
514 // Space-consuming pseudo to aid testing of placement and reachability
515 // algorithms. Immediate operand is the number of bytes this "instruction"
516 // occupies; register operands can be used to enforce dependency and constrain
518 let hasSideEffects = 1, mayLoad = 1, mayStore = 1 in
519 def SPACE : Pseudo<(outs GPR64:$Rd), (ins i32imm:$size, GPR64:$Rn),
520 [(set GPR64:$Rd, (int_aarch64_space imm:$size, GPR64:$Rn))]>,
523 let hasSideEffects = 1, isCodeGenOnly = 1 in {
524 def SpeculationSafeValueX
525 : Pseudo<(outs GPR64:$dst), (ins GPR64:$src), []>, Sched<[]>;
526 def SpeculationSafeValueW
527 : Pseudo<(outs GPR32:$dst), (ins GPR32:$src), []>, Sched<[]>;
531 //===----------------------------------------------------------------------===//
532 // System instructions.
533 //===----------------------------------------------------------------------===//
535 def HINT : HintI<"hint">;
536 def : InstAlias<"nop", (HINT 0b000)>;
537 def : InstAlias<"yield",(HINT 0b001)>;
538 def : InstAlias<"wfe", (HINT 0b010)>;
539 def : InstAlias<"wfi", (HINT 0b011)>;
540 def : InstAlias<"sev", (HINT 0b100)>;
541 def : InstAlias<"sevl", (HINT 0b101)>;
542 def : InstAlias<"esb", (HINT 0b10000)>, Requires<[HasRAS]>;
543 def : InstAlias<"csdb", (HINT 20)>;
544 def : InstAlias<"bti", (HINT 32)>, Requires<[HasBTI]>;
545 def : InstAlias<"bti $op", (HINT btihint_op:$op)>, Requires<[HasBTI]>;
547 // v8.2a Statistical Profiling extension
548 def : InstAlias<"psb $op", (HINT psbhint_op:$op)>, Requires<[HasSPE]>;
550 // As far as LLVM is concerned this writes to the system's exclusive monitors.
551 let mayLoad = 1, mayStore = 1 in
552 def CLREX : CRmSystemI<imm0_15, 0b010, "clrex">;
554 // NOTE: ideally, this would have mayStore = 0, mayLoad = 0, but we cannot
555 // model patterns with sufficiently fine granularity.
556 let mayLoad = ?, mayStore = ? in {
557 def DMB : CRmSystemI<barrier_op, 0b101, "dmb",
558 [(int_aarch64_dmb (i32 imm32_0_15:$CRm))]>;
560 def DSB : CRmSystemI<barrier_op, 0b100, "dsb",
561 [(int_aarch64_dsb (i32 imm32_0_15:$CRm))]>;
563 def ISB : CRmSystemI<barrier_op, 0b110, "isb",
564 [(int_aarch64_isb (i32 imm32_0_15:$CRm))]>;
566 def TSB : CRmSystemI<barrier_op, 0b010, "tsb", []> {
569 let Predicates = [HasTRACEV8_4];
573 // ARMv8.2-A Dot Product
574 let Predicates = [HasDotProd] in {
575 defm SDOT : SIMDThreeSameVectorDot<0, "sdot", int_aarch64_neon_sdot>;
576 defm UDOT : SIMDThreeSameVectorDot<1, "udot", int_aarch64_neon_udot>;
577 defm SDOTlane : SIMDThreeSameVectorDotIndex<0, "sdot", int_aarch64_neon_sdot>;
578 defm UDOTlane : SIMDThreeSameVectorDotIndex<1, "udot", int_aarch64_neon_udot>;
581 // ARMv8.2-A FP16 Fused Multiply-Add Long
582 let Predicates = [HasNEON, HasFP16FML] in {
583 defm FMLAL : SIMDThreeSameVectorFML<0, 1, 0b001, "fmlal", int_aarch64_neon_fmlal>;
584 defm FMLSL : SIMDThreeSameVectorFML<0, 1, 0b101, "fmlsl", int_aarch64_neon_fmlsl>;
585 defm FMLAL2 : SIMDThreeSameVectorFML<1, 0, 0b001, "fmlal2", int_aarch64_neon_fmlal2>;
586 defm FMLSL2 : SIMDThreeSameVectorFML<1, 0, 0b101, "fmlsl2", int_aarch64_neon_fmlsl2>;
587 defm FMLALlane : SIMDThreeSameVectorFMLIndex<0, 0b0000, "fmlal", int_aarch64_neon_fmlal>;
588 defm FMLSLlane : SIMDThreeSameVectorFMLIndex<0, 0b0100, "fmlsl", int_aarch64_neon_fmlsl>;
589 defm FMLAL2lane : SIMDThreeSameVectorFMLIndex<1, 0b1000, "fmlal2", int_aarch64_neon_fmlal2>;
590 defm FMLSL2lane : SIMDThreeSameVectorFMLIndex<1, 0b1100, "fmlsl2", int_aarch64_neon_fmlsl2>;
593 // Armv8.2-A Crypto extensions
594 let Predicates = [HasSHA3] in {
595 def SHA512H : CryptoRRRTied<0b0, 0b00, "sha512h">;
596 def SHA512H2 : CryptoRRRTied<0b0, 0b01, "sha512h2">;
597 def SHA512SU0 : CryptoRRTied_2D<0b0, 0b00, "sha512su0">;
598 def SHA512SU1 : CryptoRRRTied_2D<0b0, 0b10, "sha512su1">;
599 def RAX1 : CryptoRRR_2D<0b0,0b11, "rax1">;
600 def EOR3 : CryptoRRRR_16B<0b00, "eor3">;
601 def BCAX : CryptoRRRR_16B<0b01, "bcax">;
602 def XAR : CryptoRRRi6<"xar">;
605 let Predicates = [HasSM4] in {
606 def SM3TT1A : CryptoRRRi2Tied<0b0, 0b00, "sm3tt1a">;
607 def SM3TT1B : CryptoRRRi2Tied<0b0, 0b01, "sm3tt1b">;
608 def SM3TT2A : CryptoRRRi2Tied<0b0, 0b10, "sm3tt2a">;
609 def SM3TT2B : CryptoRRRi2Tied<0b0, 0b11, "sm3tt2b">;
610 def SM3SS1 : CryptoRRRR_4S<0b10, "sm3ss1">;
611 def SM3PARTW1 : CryptoRRRTied_4S<0b1, 0b00, "sm3partw1">;
612 def SM3PARTW2 : CryptoRRRTied_4S<0b1, 0b01, "sm3partw2">;
613 def SM4ENCKEY : CryptoRRR_4S<0b1, 0b10, "sm4ekey">;
614 def SM4E : CryptoRRTied_4S<0b0, 0b01, "sm4e">;
617 let Predicates = [HasRCPC] in {
618 // v8.3 Release Consistent Processor Consistent support, optional in v8.2.
619 def LDAPRB : RCPCLoad<0b00, "ldaprb", GPR32>;
620 def LDAPRH : RCPCLoad<0b01, "ldaprh", GPR32>;
621 def LDAPRW : RCPCLoad<0b10, "ldapr", GPR32>;
622 def LDAPRX : RCPCLoad<0b11, "ldapr", GPR64>;
625 // v8.3a complex add and multiply-accumulate. No predicate here, that is done
626 // inside the multiclass as the FP16 versions need different predicates.
627 defm FCMLA : SIMDThreeSameVectorTiedComplexHSD<1, 0b110, complexrotateop,
629 defm FCADD : SIMDThreeSameVectorComplexHSD<1, 0b111, complexrotateopodd,
631 defm FCMLA : SIMDIndexedTiedComplexHSD<1, 0, 1, complexrotateop, "fcmla",
634 // v8.3a Pointer Authentication
635 // These instructions inhabit part of the hint space and so can be used for
637 let Uses = [LR], Defs = [LR] in {
638 def PACIAZ : SystemNoOperands<0b000, "paciaz">;
639 def PACIBZ : SystemNoOperands<0b010, "pacibz">;
640 def AUTIAZ : SystemNoOperands<0b100, "autiaz">;
641 def AUTIBZ : SystemNoOperands<0b110, "autibz">;
643 let Uses = [LR, SP], Defs = [LR] in {
644 def PACIASP : SystemNoOperands<0b001, "paciasp">;
645 def PACIBSP : SystemNoOperands<0b011, "pacibsp">;
646 def AUTIASP : SystemNoOperands<0b101, "autiasp">;
647 def AUTIBSP : SystemNoOperands<0b111, "autibsp">;
649 let Uses = [X16, X17], Defs = [X17], CRm = 0b0001 in {
650 def PACIA1716 : SystemNoOperands<0b000, "pacia1716">;
651 def PACIB1716 : SystemNoOperands<0b010, "pacib1716">;
652 def AUTIA1716 : SystemNoOperands<0b100, "autia1716">;
653 def AUTIB1716 : SystemNoOperands<0b110, "autib1716">;
656 let Uses = [LR], Defs = [LR], CRm = 0b0000 in {
657 def XPACLRI : SystemNoOperands<0b111, "xpaclri">;
660 // These pointer authentication isntructions require armv8.3a
661 let Predicates = [HasPA] in {
662 multiclass SignAuth<bits<3> prefix, bits<3> prefix_z, string asm> {
663 def IA : SignAuthOneData<prefix, 0b00, !strconcat(asm, "ia")>;
664 def IB : SignAuthOneData<prefix, 0b01, !strconcat(asm, "ib")>;
665 def DA : SignAuthOneData<prefix, 0b10, !strconcat(asm, "da")>;
666 def DB : SignAuthOneData<prefix, 0b11, !strconcat(asm, "db")>;
667 def IZA : SignAuthZero<prefix_z, 0b00, !strconcat(asm, "iza")>;
668 def DZA : SignAuthZero<prefix_z, 0b10, !strconcat(asm, "dza")>;
669 def IZB : SignAuthZero<prefix_z, 0b01, !strconcat(asm, "izb")>;
670 def DZB : SignAuthZero<prefix_z, 0b11, !strconcat(asm, "dzb")>;
673 defm PAC : SignAuth<0b000, 0b010, "pac">;
674 defm AUT : SignAuth<0b001, 0b011, "aut">;
676 def XPACI : SignAuthZero<0b100, 0b00, "xpaci">;
677 def XPACD : SignAuthZero<0b100, 0b01, "xpacd">;
678 def PACGA : SignAuthTwoOperand<0b1100, "pacga", null_frag>;
680 // Combined Instructions
681 def BRAA : AuthBranchTwoOperands<0, 0, "braa">;
682 def BRAB : AuthBranchTwoOperands<0, 1, "brab">;
683 def BLRAA : AuthBranchTwoOperands<1, 0, "blraa">;
684 def BLRAB : AuthBranchTwoOperands<1, 1, "blrab">;
686 def BRAAZ : AuthOneOperand<0b000, 0, "braaz">;
687 def BRABZ : AuthOneOperand<0b000, 1, "brabz">;
688 def BLRAAZ : AuthOneOperand<0b001, 0, "blraaz">;
689 def BLRABZ : AuthOneOperand<0b001, 1, "blrabz">;
691 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
692 def RETAA : AuthReturn<0b010, 0, "retaa">;
693 def RETAB : AuthReturn<0b010, 1, "retab">;
694 def ERETAA : AuthReturn<0b100, 0, "eretaa">;
695 def ERETAB : AuthReturn<0b100, 1, "eretab">;
698 defm LDRAA : AuthLoad<0, "ldraa", simm10Scaled>;
699 defm LDRAB : AuthLoad<1, "ldrab", simm10Scaled>;
703 // v8.3a floating point conversion for javascript
704 let Predicates = [HasJS, HasFPARMv8] in
705 def FJCVTZS : BaseFPToIntegerUnscaled<0b01, 0b11, 0b110, FPR64, GPR32,
708 } // HasJS, HasFPARMv8
710 // v8.4 Flag manipulation instructions
711 let Predicates = [HasFMI] in {
712 def CFINV : SimpleSystemI<0, (ins), "cfinv", "">, Sched<[WriteSys]> {
713 let Inst{20-5} = 0b0000001000000000;
715 def SETF8 : BaseFlagManipulation<0, 0, (ins GPR32:$Rn), "setf8", "{\t$Rn}">;
716 def SETF16 : BaseFlagManipulation<0, 1, (ins GPR32:$Rn), "setf16", "{\t$Rn}">;
717 def RMIF : FlagRotate<(ins GPR64:$Rn, uimm6:$imm, imm0_15:$mask), "rmif",
718 "{\t$Rn, $imm, $mask}">;
721 // v8.5 flag manipulation instructions
722 let Predicates = [HasAltNZCV], Uses = [NZCV], Defs = [NZCV] in {
724 def XAFLAG : PstateWriteSimple<(ins), "xaflag", "">, Sched<[WriteSys]> {
725 let Inst{18-16} = 0b000;
726 let Inst{11-8} = 0b0000;
727 let Unpredictable{11-8} = 0b1111;
728 let Inst{7-5} = 0b001;
731 def AXFLAG : PstateWriteSimple<(ins), "axflag", "">, Sched<[WriteSys]> {
732 let Inst{18-16} = 0b000;
733 let Inst{11-8} = 0b0000;
734 let Unpredictable{11-8} = 0b1111;
735 let Inst{7-5} = 0b010;
740 // Armv8.5-A speculation barrier
741 def SB : SimpleSystemI<0, (ins), "sb", "">, Sched<[]> {
742 let Inst{20-5} = 0b0001100110000111;
743 let Unpredictable{11-8} = 0b1111;
744 let Predicates = [HasSB];
745 let hasSideEffects = 1;
748 def : InstAlias<"clrex", (CLREX 0xf)>;
749 def : InstAlias<"isb", (ISB 0xf)>;
750 def : InstAlias<"ssbb", (DSB 0)>;
751 def : InstAlias<"pssbb", (DSB 4)>;
755 def MSRpstateImm1 : MSRpstateImm0_1;
756 def MSRpstateImm4 : MSRpstateImm0_15;
758 // The thread pointer (on Linux, at least, where this has been implemented) is
760 def MOVbaseTLS : Pseudo<(outs GPR64:$dst), (ins),
761 [(set GPR64:$dst, AArch64threadpointer)]>, Sched<[WriteSys]>;
763 // The cycle counter PMC register is PMCCNTR_EL0.
764 let Predicates = [HasPerfMon] in
765 def : Pat<(readcyclecounter), (MRS 0xdce8)>;
768 def : Pat<(i64 (int_aarch64_get_fpcr)), (MRS 0xda20)>;
770 // Generic system instructions
771 def SYSxt : SystemXtI<0, "sys">;
772 def SYSLxt : SystemLXtI<1, "sysl">;
774 def : InstAlias<"sys $op1, $Cn, $Cm, $op2",
775 (SYSxt imm0_7:$op1, sys_cr_op:$Cn,
776 sys_cr_op:$Cm, imm0_7:$op2, XZR)>;
778 //===----------------------------------------------------------------------===//
779 // Move immediate instructions.
780 //===----------------------------------------------------------------------===//
782 defm MOVK : InsertImmediate<0b11, "movk">;
783 defm MOVN : MoveImmediate<0b00, "movn">;
785 let PostEncoderMethod = "fixMOVZ" in
786 defm MOVZ : MoveImmediate<0b10, "movz">;
788 // First group of aliases covers an implicit "lsl #0".
789 def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, imm0_65535:$imm, 0), 0>;
790 def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, imm0_65535:$imm, 0), 0>;
791 def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, imm0_65535:$imm, 0)>;
792 def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, imm0_65535:$imm, 0)>;
793 def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, imm0_65535:$imm, 0)>;
794 def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, imm0_65535:$imm, 0)>;
796 // Next, we have various ELF relocations with the ":XYZ_g0:sym" syntax.
797 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
798 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
799 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
800 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
802 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
803 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
804 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
805 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
807 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g3:$sym, 48), 0>;
808 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g2:$sym, 32), 0>;
809 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g1:$sym, 16), 0>;
810 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g0:$sym, 0), 0>;
812 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
813 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
815 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
816 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
818 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16), 0>;
819 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g0:$sym, 0), 0>;
821 // Final group of aliases covers true "mov $Rd, $imm" cases.
822 multiclass movw_mov_alias<string basename,Instruction INST, RegisterClass GPR,
823 int width, int shift> {
824 def _asmoperand : AsmOperandClass {
825 let Name = basename # width # "_lsl" # shift # "MovAlias";
826 let PredicateMethod = "is" # basename # "MovAlias<" # width # ", "
828 let RenderMethod = "add" # basename # "MovAliasOperands<" # shift # ">";
831 def _movimm : Operand<i32> {
832 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_asmoperand");
835 def : InstAlias<"mov $Rd, $imm",
836 (INST GPR:$Rd, !cast<Operand>(NAME # "_movimm"):$imm, shift)>;
839 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 0>;
840 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 16>;
842 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 0>;
843 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 16>;
844 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 32>;
845 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 48>;
847 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 0>;
848 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 16>;
850 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 0>;
851 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 16>;
852 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 32>;
853 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 48>;
855 let isReMaterializable = 1, isCodeGenOnly = 1, isMoveImm = 1,
856 isAsCheapAsAMove = 1 in {
857 // FIXME: The following pseudo instructions are only needed because remat
858 // cannot handle multiple instructions. When that changes, we can select
859 // directly to the real instructions and get rid of these pseudos.
862 : Pseudo<(outs GPR32:$dst), (ins i32imm:$src),
863 [(set GPR32:$dst, imm:$src)]>,
866 : Pseudo<(outs GPR64:$dst), (ins i64imm:$src),
867 [(set GPR64:$dst, imm:$src)]>,
869 } // isReMaterializable, isCodeGenOnly
871 // If possible, we want to use MOVi32imm even for 64-bit moves. This gives the
872 // eventual expansion code fewer bits to worry about getting right. Marshalling
873 // the types is a little tricky though:
874 def i64imm_32bit : ImmLeaf<i64, [{
875 return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);
878 def s64imm_32bit : ImmLeaf<i64, [{
879 int64_t Imm64 = static_cast<int64_t>(Imm);
880 return Imm64 >= std::numeric_limits<int32_t>::min() &&
881 Imm64 <= std::numeric_limits<int32_t>::max();
884 def trunc_imm : SDNodeXForm<imm, [{
885 return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i32);
888 def gi_trunc_imm : GICustomOperandRenderer<"renderTruncImm">,
889 GISDNodeXFormEquiv<trunc_imm>;
891 def : Pat<(i64 i64imm_32bit:$src),
892 (SUBREG_TO_REG (i64 0), (MOVi32imm (trunc_imm imm:$src)), sub_32)>;
894 // Materialize FP constants via MOVi32imm/MOVi64imm (MachO large code model).
895 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
896 return CurDAG->getTargetConstant(
897 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i32);
900 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
901 return CurDAG->getTargetConstant(
902 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i64);
906 def : Pat<(f32 fpimm:$in),
907 (COPY_TO_REGCLASS (MOVi32imm (bitcast_fpimm_to_i32 f32:$in)), FPR32)>;
908 def : Pat<(f64 fpimm:$in),
909 (COPY_TO_REGCLASS (MOVi64imm (bitcast_fpimm_to_i64 f64:$in)), FPR64)>;
912 // Deal with the various forms of (ELF) large addressing with MOVZ/MOVK
914 def : Pat<(AArch64WrapperLarge tglobaladdr:$g3, tglobaladdr:$g2,
915 tglobaladdr:$g1, tglobaladdr:$g0),
916 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tglobaladdr:$g0, 0),
917 tglobaladdr:$g1, 16),
918 tglobaladdr:$g2, 32),
919 tglobaladdr:$g3, 48)>;
921 def : Pat<(AArch64WrapperLarge tblockaddress:$g3, tblockaddress:$g2,
922 tblockaddress:$g1, tblockaddress:$g0),
923 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tblockaddress:$g0, 0),
924 tblockaddress:$g1, 16),
925 tblockaddress:$g2, 32),
926 tblockaddress:$g3, 48)>;
928 def : Pat<(AArch64WrapperLarge tconstpool:$g3, tconstpool:$g2,
929 tconstpool:$g1, tconstpool:$g0),
930 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tconstpool:$g0, 0),
933 tconstpool:$g3, 48)>;
935 def : Pat<(AArch64WrapperLarge tjumptable:$g3, tjumptable:$g2,
936 tjumptable:$g1, tjumptable:$g0),
937 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tjumptable:$g0, 0),
940 tjumptable:$g3, 48)>;
943 //===----------------------------------------------------------------------===//
944 // Arithmetic instructions.
945 //===----------------------------------------------------------------------===//
947 // Add/subtract with carry.
948 defm ADC : AddSubCarry<0, "adc", "adcs", AArch64adc, AArch64adc_flag>;
949 defm SBC : AddSubCarry<1, "sbc", "sbcs", AArch64sbc, AArch64sbc_flag>;
951 def : InstAlias<"ngc $dst, $src", (SBCWr GPR32:$dst, WZR, GPR32:$src)>;
952 def : InstAlias<"ngc $dst, $src", (SBCXr GPR64:$dst, XZR, GPR64:$src)>;
953 def : InstAlias<"ngcs $dst, $src", (SBCSWr GPR32:$dst, WZR, GPR32:$src)>;
954 def : InstAlias<"ngcs $dst, $src", (SBCSXr GPR64:$dst, XZR, GPR64:$src)>;
957 defm ADD : AddSub<0, "add", "sub", add>;
958 defm SUB : AddSub<1, "sub", "add">;
960 def : InstAlias<"mov $dst, $src",
961 (ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0)>;
962 def : InstAlias<"mov $dst, $src",
963 (ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0)>;
964 def : InstAlias<"mov $dst, $src",
965 (ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0)>;
966 def : InstAlias<"mov $dst, $src",
967 (ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0)>;
969 defm ADDS : AddSubS<0, "adds", AArch64add_flag, "cmn", "subs", "cmp">;
970 defm SUBS : AddSubS<1, "subs", AArch64sub_flag, "cmp", "adds", "cmn">;
972 // Use SUBS instead of SUB to enable CSE between SUBS and SUB.
973 def : Pat<(sub GPR32sp:$Rn, addsub_shifted_imm32:$imm),
974 (SUBSWri GPR32sp:$Rn, addsub_shifted_imm32:$imm)>;
975 def : Pat<(sub GPR64sp:$Rn, addsub_shifted_imm64:$imm),
976 (SUBSXri GPR64sp:$Rn, addsub_shifted_imm64:$imm)>;
977 def : Pat<(sub GPR32:$Rn, GPR32:$Rm),
978 (SUBSWrr GPR32:$Rn, GPR32:$Rm)>;
979 def : Pat<(sub GPR64:$Rn, GPR64:$Rm),
980 (SUBSXrr GPR64:$Rn, GPR64:$Rm)>;
981 def : Pat<(sub GPR32:$Rn, arith_shifted_reg32:$Rm),
982 (SUBSWrs GPR32:$Rn, arith_shifted_reg32:$Rm)>;
983 def : Pat<(sub GPR64:$Rn, arith_shifted_reg64:$Rm),
984 (SUBSXrs GPR64:$Rn, arith_shifted_reg64:$Rm)>;
985 let AddedComplexity = 1 in {
986 def : Pat<(sub GPR32sp:$R2, arith_extended_reg32<i32>:$R3),
987 (SUBSWrx GPR32sp:$R2, arith_extended_reg32<i32>:$R3)>;
988 def : Pat<(sub GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3),
989 (SUBSXrx GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3)>;
992 // Because of the immediate format for add/sub-imm instructions, the
993 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
994 // These patterns capture that transformation.
995 let AddedComplexity = 1 in {
996 def : Pat<(add GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
997 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
998 def : Pat<(add GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
999 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
1000 def : Pat<(sub GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
1001 (ADDWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
1002 def : Pat<(sub GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
1003 (ADDXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
1006 // Because of the immediate format for add/sub-imm instructions, the
1007 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
1008 // These patterns capture that transformation.
1009 let AddedComplexity = 1 in {
1010 def : Pat<(AArch64add_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
1011 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
1012 def : Pat<(AArch64add_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
1013 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
1014 def : Pat<(AArch64sub_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
1015 (ADDSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
1016 def : Pat<(AArch64sub_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
1017 (ADDSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
1020 def : InstAlias<"neg $dst, $src", (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
1021 def : InstAlias<"neg $dst, $src", (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
1022 def : InstAlias<"neg $dst, $src$shift",
1023 (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
1024 def : InstAlias<"neg $dst, $src$shift",
1025 (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
1027 def : InstAlias<"negs $dst, $src", (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
1028 def : InstAlias<"negs $dst, $src", (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
1029 def : InstAlias<"negs $dst, $src$shift",
1030 (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
1031 def : InstAlias<"negs $dst, $src$shift",
1032 (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
1035 // Unsigned/Signed divide
1036 defm UDIV : Div<0, "udiv", udiv>;
1037 defm SDIV : Div<1, "sdiv", sdiv>;
1039 def : Pat<(int_aarch64_udiv GPR32:$Rn, GPR32:$Rm), (UDIVWr GPR32:$Rn, GPR32:$Rm)>;
1040 def : Pat<(int_aarch64_udiv GPR64:$Rn, GPR64:$Rm), (UDIVXr GPR64:$Rn, GPR64:$Rm)>;
1041 def : Pat<(int_aarch64_sdiv GPR32:$Rn, GPR32:$Rm), (SDIVWr GPR32:$Rn, GPR32:$Rm)>;
1042 def : Pat<(int_aarch64_sdiv GPR64:$Rn, GPR64:$Rm), (SDIVXr GPR64:$Rn, GPR64:$Rm)>;
1045 defm ASRV : Shift<0b10, "asr", sra>;
1046 defm LSLV : Shift<0b00, "lsl", shl>;
1047 defm LSRV : Shift<0b01, "lsr", srl>;
1048 defm RORV : Shift<0b11, "ror", rotr>;
1050 def : ShiftAlias<"asrv", ASRVWr, GPR32>;
1051 def : ShiftAlias<"asrv", ASRVXr, GPR64>;
1052 def : ShiftAlias<"lslv", LSLVWr, GPR32>;
1053 def : ShiftAlias<"lslv", LSLVXr, GPR64>;
1054 def : ShiftAlias<"lsrv", LSRVWr, GPR32>;
1055 def : ShiftAlias<"lsrv", LSRVXr, GPR64>;
1056 def : ShiftAlias<"rorv", RORVWr, GPR32>;
1057 def : ShiftAlias<"rorv", RORVXr, GPR64>;
1060 let AddedComplexity = 5 in {
1061 defm MADD : MulAccum<0, "madd", add>;
1062 defm MSUB : MulAccum<1, "msub", sub>;
1064 def : Pat<(i32 (mul GPR32:$Rn, GPR32:$Rm)),
1065 (MADDWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
1066 def : Pat<(i64 (mul GPR64:$Rn, GPR64:$Rm)),
1067 (MADDXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
1069 def : Pat<(i32 (ineg (mul GPR32:$Rn, GPR32:$Rm))),
1070 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
1071 def : Pat<(i64 (ineg (mul GPR64:$Rn, GPR64:$Rm))),
1072 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
1073 def : Pat<(i32 (mul (ineg GPR32:$Rn), GPR32:$Rm)),
1074 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
1075 def : Pat<(i64 (mul (ineg GPR64:$Rn), GPR64:$Rm)),
1076 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
1077 } // AddedComplexity = 5
1079 let AddedComplexity = 5 in {
1080 def SMADDLrrr : WideMulAccum<0, 0b001, "smaddl", add, sext>;
1081 def SMSUBLrrr : WideMulAccum<1, 0b001, "smsubl", sub, sext>;
1082 def UMADDLrrr : WideMulAccum<0, 0b101, "umaddl", add, zext>;
1083 def UMSUBLrrr : WideMulAccum<1, 0b101, "umsubl", sub, zext>;
1085 def : Pat<(i64 (mul (sext GPR32:$Rn), (sext GPR32:$Rm))),
1086 (SMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
1087 def : Pat<(i64 (mul (zext GPR32:$Rn), (zext GPR32:$Rm))),
1088 (UMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
1090 def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (sext GPR32:$Rm)))),
1091 (SMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
1092 def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (zext GPR32:$Rm)))),
1093 (UMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
1095 def : Pat<(i64 (mul (sext GPR32:$Rn), (s64imm_32bit:$C))),
1096 (SMADDLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), XZR)>;
1097 def : Pat<(i64 (mul (zext GPR32:$Rn), (i64imm_32bit:$C))),
1098 (UMADDLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), XZR)>;
1099 def : Pat<(i64 (mul (sext_inreg GPR64:$Rn, i32), (s64imm_32bit:$C))),
1100 (SMADDLrrr (i32 (EXTRACT_SUBREG GPR64:$Rn, sub_32)),
1101 (MOVi32imm (trunc_imm imm:$C)), XZR)>;
1103 def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (s64imm_32bit:$C)))),
1104 (SMSUBLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), XZR)>;
1105 def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (i64imm_32bit:$C)))),
1106 (UMSUBLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), XZR)>;
1107 def : Pat<(i64 (ineg (mul (sext_inreg GPR64:$Rn, i32), (s64imm_32bit:$C)))),
1108 (SMSUBLrrr (i32 (EXTRACT_SUBREG GPR64:$Rn, sub_32)),
1109 (MOVi32imm (trunc_imm imm:$C)), XZR)>;
1111 def : Pat<(i64 (add (mul (sext GPR32:$Rn), (s64imm_32bit:$C)), GPR64:$Ra)),
1112 (SMADDLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>;
1113 def : Pat<(i64 (add (mul (zext GPR32:$Rn), (i64imm_32bit:$C)), GPR64:$Ra)),
1114 (UMADDLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>;
1115 def : Pat<(i64 (add (mul (sext_inreg GPR64:$Rn, i32), (s64imm_32bit:$C)),
1117 (SMADDLrrr (i32 (EXTRACT_SUBREG GPR64:$Rn, sub_32)),
1118 (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>;
1120 def : Pat<(i64 (sub GPR64:$Ra, (mul (sext GPR32:$Rn), (s64imm_32bit:$C)))),
1121 (SMSUBLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>;
1122 def : Pat<(i64 (sub GPR64:$Ra, (mul (zext GPR32:$Rn), (i64imm_32bit:$C)))),
1123 (UMSUBLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>;
1124 def : Pat<(i64 (sub GPR64:$Ra, (mul (sext_inreg GPR64:$Rn, i32),
1125 (s64imm_32bit:$C)))),
1126 (SMSUBLrrr (i32 (EXTRACT_SUBREG GPR64:$Rn, sub_32)),
1127 (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>;
1128 } // AddedComplexity = 5
1130 def : MulAccumWAlias<"mul", MADDWrrr>;
1131 def : MulAccumXAlias<"mul", MADDXrrr>;
1132 def : MulAccumWAlias<"mneg", MSUBWrrr>;
1133 def : MulAccumXAlias<"mneg", MSUBXrrr>;
1134 def : WideMulAccumAlias<"smull", SMADDLrrr>;
1135 def : WideMulAccumAlias<"smnegl", SMSUBLrrr>;
1136 def : WideMulAccumAlias<"umull", UMADDLrrr>;
1137 def : WideMulAccumAlias<"umnegl", UMSUBLrrr>;
1140 def SMULHrr : MulHi<0b010, "smulh", mulhs>;
1141 def UMULHrr : MulHi<0b110, "umulh", mulhu>;
1144 def CRC32Brr : BaseCRC32<0, 0b00, 0, GPR32, int_aarch64_crc32b, "crc32b">;
1145 def CRC32Hrr : BaseCRC32<0, 0b01, 0, GPR32, int_aarch64_crc32h, "crc32h">;
1146 def CRC32Wrr : BaseCRC32<0, 0b10, 0, GPR32, int_aarch64_crc32w, "crc32w">;
1147 def CRC32Xrr : BaseCRC32<1, 0b11, 0, GPR64, int_aarch64_crc32x, "crc32x">;
1149 def CRC32CBrr : BaseCRC32<0, 0b00, 1, GPR32, int_aarch64_crc32cb, "crc32cb">;
1150 def CRC32CHrr : BaseCRC32<0, 0b01, 1, GPR32, int_aarch64_crc32ch, "crc32ch">;
1151 def CRC32CWrr : BaseCRC32<0, 0b10, 1, GPR32, int_aarch64_crc32cw, "crc32cw">;
1152 def CRC32CXrr : BaseCRC32<1, 0b11, 1, GPR64, int_aarch64_crc32cx, "crc32cx">;
1155 defm CAS : CompareAndSwap<0, 0, "">;
1156 defm CASA : CompareAndSwap<1, 0, "a">;
1157 defm CASL : CompareAndSwap<0, 1, "l">;
1158 defm CASAL : CompareAndSwap<1, 1, "al">;
1161 defm CASP : CompareAndSwapPair<0, 0, "">;
1162 defm CASPA : CompareAndSwapPair<1, 0, "a">;
1163 defm CASPL : CompareAndSwapPair<0, 1, "l">;
1164 defm CASPAL : CompareAndSwapPair<1, 1, "al">;
1167 defm SWP : Swap<0, 0, "">;
1168 defm SWPA : Swap<1, 0, "a">;
1169 defm SWPL : Swap<0, 1, "l">;
1170 defm SWPAL : Swap<1, 1, "al">;
1172 // v8.1 atomic LD<OP>(register). Performs load and then ST<OP>(register)
1173 defm LDADD : LDOPregister<0b000, "add", 0, 0, "">;
1174 defm LDADDA : LDOPregister<0b000, "add", 1, 0, "a">;
1175 defm LDADDL : LDOPregister<0b000, "add", 0, 1, "l">;
1176 defm LDADDAL : LDOPregister<0b000, "add", 1, 1, "al">;
1178 defm LDCLR : LDOPregister<0b001, "clr", 0, 0, "">;
1179 defm LDCLRA : LDOPregister<0b001, "clr", 1, 0, "a">;
1180 defm LDCLRL : LDOPregister<0b001, "clr", 0, 1, "l">;
1181 defm LDCLRAL : LDOPregister<0b001, "clr", 1, 1, "al">;
1183 defm LDEOR : LDOPregister<0b010, "eor", 0, 0, "">;
1184 defm LDEORA : LDOPregister<0b010, "eor", 1, 0, "a">;
1185 defm LDEORL : LDOPregister<0b010, "eor", 0, 1, "l">;
1186 defm LDEORAL : LDOPregister<0b010, "eor", 1, 1, "al">;
1188 defm LDSET : LDOPregister<0b011, "set", 0, 0, "">;
1189 defm LDSETA : LDOPregister<0b011, "set", 1, 0, "a">;
1190 defm LDSETL : LDOPregister<0b011, "set", 0, 1, "l">;
1191 defm LDSETAL : LDOPregister<0b011, "set", 1, 1, "al">;
1193 defm LDSMAX : LDOPregister<0b100, "smax", 0, 0, "">;
1194 defm LDSMAXA : LDOPregister<0b100, "smax", 1, 0, "a">;
1195 defm LDSMAXL : LDOPregister<0b100, "smax", 0, 1, "l">;
1196 defm LDSMAXAL : LDOPregister<0b100, "smax", 1, 1, "al">;
1198 defm LDSMIN : LDOPregister<0b101, "smin", 0, 0, "">;
1199 defm LDSMINA : LDOPregister<0b101, "smin", 1, 0, "a">;
1200 defm LDSMINL : LDOPregister<0b101, "smin", 0, 1, "l">;
1201 defm LDSMINAL : LDOPregister<0b101, "smin", 1, 1, "al">;
1203 defm LDUMAX : LDOPregister<0b110, "umax", 0, 0, "">;
1204 defm LDUMAXA : LDOPregister<0b110, "umax", 1, 0, "a">;
1205 defm LDUMAXL : LDOPregister<0b110, "umax", 0, 1, "l">;
1206 defm LDUMAXAL : LDOPregister<0b110, "umax", 1, 1, "al">;
1208 defm LDUMIN : LDOPregister<0b111, "umin", 0, 0, "">;
1209 defm LDUMINA : LDOPregister<0b111, "umin", 1, 0, "a">;
1210 defm LDUMINL : LDOPregister<0b111, "umin", 0, 1, "l">;
1211 defm LDUMINAL : LDOPregister<0b111, "umin", 1, 1, "al">;
1213 // v8.1 atomic ST<OP>(register) as aliases to "LD<OP>(register) when Rt=xZR"
1214 defm : STOPregister<"stadd","LDADD">; // STADDx
1215 defm : STOPregister<"stclr","LDCLR">; // STCLRx
1216 defm : STOPregister<"steor","LDEOR">; // STEORx
1217 defm : STOPregister<"stset","LDSET">; // STSETx
1218 defm : STOPregister<"stsmax","LDSMAX">;// STSMAXx
1219 defm : STOPregister<"stsmin","LDSMIN">;// STSMINx
1220 defm : STOPregister<"stumax","LDUMAX">;// STUMAXx
1221 defm : STOPregister<"stumin","LDUMIN">;// STUMINx
1223 // v8.5 Memory Tagging Extension
1224 let Predicates = [HasMTE] in {
1226 def IRG : BaseTwoOperand<0b0100, GPR64sp, "irg", null_frag, GPR64sp, GPR64>,
1230 def GMI : BaseTwoOperand<0b0101, GPR64, "gmi", null_frag, GPR64sp>, Sched<[]>{
1232 let isNotDuplicable = 1;
1234 def ADDG : AddSubG<0, "addg", null_frag>;
1235 def SUBG : AddSubG<1, "subg", null_frag>;
1237 def : InstAlias<"irg $dst, $src", (IRG GPR64sp:$dst, GPR64sp:$src, XZR), 1>;
1239 def SUBP : SUBP<0, "subp", null_frag>, Sched<[]>;
1240 def SUBPS : SUBP<1, "subps", null_frag>, Sched<[]>{
1244 def : InstAlias<"cmpp $lhs, $rhs", (SUBPS XZR, GPR64sp:$lhs, GPR64sp:$rhs), 0>;
1246 def LDG : MemTagLoad<"ldg", "\t$Rt, [$Rn, $offset]">;
1247 def : InstAlias<"ldg $Rt, [$Rn]", (LDG GPR64:$Rt, GPR64sp:$Rn, 0), 1>;
1249 def LDGV : MemTagVector<1, "ldgv", "\t$Rt, [$Rn]!",
1250 (outs GPR64sp:$wback, GPR64:$Rt), (ins GPR64sp:$Rn)> {
1251 let DecoderMethod = "DecodeLoadAllocTagArrayInstruction";
1253 def STGV : MemTagVector<0, "stgv", "\t$Rt, [$Rn]!",
1254 (outs GPR64sp:$wback), (ins GPR64:$Rt, GPR64sp:$Rn)>;
1256 defm STG : MemTagStore<0b00, "stg">;
1257 defm STZG : MemTagStore<0b01, "stzg">;
1258 defm ST2G : MemTagStore<0b10, "st2g">;
1259 defm STZ2G : MemTagStore<0b11, "stz2g">;
1261 defm STGP : StorePairOffset <0b01, 0, GPR64z, simm7s16, "stgp">;
1262 def STGPpre : StorePairPreIdx <0b01, 0, GPR64z, simm7s16, "stgp">;
1263 def STGPpost : StorePairPostIdx<0b01, 0, GPR64z, simm7s16, "stgp">;
1265 } // Predicates = [HasMTE]
1267 //===----------------------------------------------------------------------===//
1268 // Logical instructions.
1269 //===----------------------------------------------------------------------===//
1272 defm ANDS : LogicalImmS<0b11, "ands", AArch64and_flag, "bics">;
1273 defm AND : LogicalImm<0b00, "and", and, "bic">;
1274 defm EOR : LogicalImm<0b10, "eor", xor, "eon">;
1275 defm ORR : LogicalImm<0b01, "orr", or, "orn">;
1277 // FIXME: these aliases *are* canonical sometimes (when movz can't be
1278 // used). Actually, it seems to be working right now, but putting logical_immXX
1279 // here is a bit dodgy on the AsmParser side too.
1280 def : InstAlias<"mov $dst, $imm", (ORRWri GPR32sp:$dst, WZR,
1281 logical_imm32:$imm), 0>;
1282 def : InstAlias<"mov $dst, $imm", (ORRXri GPR64sp:$dst, XZR,
1283 logical_imm64:$imm), 0>;
1287 defm ANDS : LogicalRegS<0b11, 0, "ands", AArch64and_flag>;
1288 defm BICS : LogicalRegS<0b11, 1, "bics",
1289 BinOpFrag<(AArch64and_flag node:$LHS, (not node:$RHS))>>;
1290 defm AND : LogicalReg<0b00, 0, "and", and>;
1291 defm BIC : LogicalReg<0b00, 1, "bic",
1292 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
1293 defm EON : LogicalReg<0b10, 1, "eon",
1294 BinOpFrag<(not (xor node:$LHS, node:$RHS))>>;
1295 defm EOR : LogicalReg<0b10, 0, "eor", xor>;
1296 defm ORN : LogicalReg<0b01, 1, "orn",
1297 BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
1298 defm ORR : LogicalReg<0b01, 0, "orr", or>;
1300 def : InstAlias<"mov $dst, $src", (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0), 2>;
1301 def : InstAlias<"mov $dst, $src", (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0), 2>;
1303 def : InstAlias<"mvn $Wd, $Wm", (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0), 3>;
1304 def : InstAlias<"mvn $Xd, $Xm", (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0), 3>;
1306 def : InstAlias<"mvn $Wd, $Wm$sh",
1307 (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh), 2>;
1308 def : InstAlias<"mvn $Xd, $Xm$sh",
1309 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh), 2>;
1311 def : InstAlias<"tst $src1, $src2",
1312 (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2), 2>;
1313 def : InstAlias<"tst $src1, $src2",
1314 (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2), 2>;
1316 def : InstAlias<"tst $src1, $src2",
1317 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0), 3>;
1318 def : InstAlias<"tst $src1, $src2",
1319 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0), 3>;
1321 def : InstAlias<"tst $src1, $src2$sh",
1322 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh), 2>;
1323 def : InstAlias<"tst $src1, $src2$sh",
1324 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh), 2>;
1327 def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>;
1328 def : Pat<(not GPR64:$Xm), (ORNXrr XZR, GPR64:$Xm)>;
1331 //===----------------------------------------------------------------------===//
1332 // One operand data processing instructions.
1333 //===----------------------------------------------------------------------===//
1335 defm CLS : OneOperandData<0b101, "cls">;
1336 defm CLZ : OneOperandData<0b100, "clz", ctlz>;
1337 defm RBIT : OneOperandData<0b000, "rbit", bitreverse>;
1339 def REV16Wr : OneWRegData<0b001, "rev16",
1340 UnOpFrag<(rotr (bswap node:$LHS), (i64 16))>>;
1341 def REV16Xr : OneXRegData<0b001, "rev16", null_frag>;
1343 def : Pat<(cttz GPR32:$Rn),
1344 (CLZWr (RBITWr GPR32:$Rn))>;
1345 def : Pat<(cttz GPR64:$Rn),
1346 (CLZXr (RBITXr GPR64:$Rn))>;
1347 def : Pat<(ctlz (or (shl (xor (sra GPR32:$Rn, (i64 31)), GPR32:$Rn), (i64 1)),
1350 def : Pat<(ctlz (or (shl (xor (sra GPR64:$Rn, (i64 63)), GPR64:$Rn), (i64 1)),
1354 // Unlike the other one operand instructions, the instructions with the "rev"
1355 // mnemonic do *not* just different in the size bit, but actually use different
1356 // opcode bits for the different sizes.
1357 def REVWr : OneWRegData<0b010, "rev", bswap>;
1358 def REVXr : OneXRegData<0b011, "rev", bswap>;
1359 def REV32Xr : OneXRegData<0b010, "rev32",
1360 UnOpFrag<(rotr (bswap node:$LHS), (i64 32))>>;
1362 def : InstAlias<"rev64 $Rd, $Rn", (REVXr GPR64:$Rd, GPR64:$Rn), 0>;
1364 // The bswap commutes with the rotr so we want a pattern for both possible
1366 def : Pat<(bswap (rotr GPR32:$Rn, (i64 16))), (REV16Wr GPR32:$Rn)>;
1367 def : Pat<(bswap (rotr GPR64:$Rn, (i64 32))), (REV32Xr GPR64:$Rn)>;
1369 //===----------------------------------------------------------------------===//
1370 // Bitfield immediate extraction instruction.
1371 //===----------------------------------------------------------------------===//
1372 let hasSideEffects = 0 in
1373 defm EXTR : ExtractImm<"extr">;
1374 def : InstAlias<"ror $dst, $src, $shift",
1375 (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift)>;
1376 def : InstAlias<"ror $dst, $src, $shift",
1377 (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift)>;
1379 def : Pat<(rotr GPR32:$Rn, (i64 imm0_31:$imm)),
1380 (EXTRWrri GPR32:$Rn, GPR32:$Rn, imm0_31:$imm)>;
1381 def : Pat<(rotr GPR64:$Rn, (i64 imm0_63:$imm)),
1382 (EXTRXrri GPR64:$Rn, GPR64:$Rn, imm0_63:$imm)>;
1384 //===----------------------------------------------------------------------===//
1385 // Other bitfield immediate instructions.
1386 //===----------------------------------------------------------------------===//
1387 let hasSideEffects = 0 in {
1388 defm BFM : BitfieldImmWith2RegArgs<0b01, "bfm">;
1389 defm SBFM : BitfieldImm<0b00, "sbfm">;
1390 defm UBFM : BitfieldImm<0b10, "ubfm">;
1393 def i32shift_a : Operand<i64>, SDNodeXForm<imm, [{
1394 uint64_t enc = (32 - N->getZExtValue()) & 0x1f;
1395 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
1398 def i32shift_b : Operand<i64>, SDNodeXForm<imm, [{
1399 uint64_t enc = 31 - N->getZExtValue();
1400 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
1403 // min(7, 31 - shift_amt)
1404 def i32shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
1405 uint64_t enc = 31 - N->getZExtValue();
1406 enc = enc > 7 ? 7 : enc;
1407 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
1410 // min(15, 31 - shift_amt)
1411 def i32shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
1412 uint64_t enc = 31 - N->getZExtValue();
1413 enc = enc > 15 ? 15 : enc;
1414 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
1417 def i64shift_a : Operand<i64>, SDNodeXForm<imm, [{
1418 uint64_t enc = (64 - N->getZExtValue()) & 0x3f;
1419 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
1422 def i64shift_b : Operand<i64>, SDNodeXForm<imm, [{
1423 uint64_t enc = 63 - N->getZExtValue();
1424 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
1427 // min(7, 63 - shift_amt)
1428 def i64shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
1429 uint64_t enc = 63 - N->getZExtValue();
1430 enc = enc > 7 ? 7 : enc;
1431 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
1434 // min(15, 63 - shift_amt)
1435 def i64shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
1436 uint64_t enc = 63 - N->getZExtValue();
1437 enc = enc > 15 ? 15 : enc;
1438 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
1441 // min(31, 63 - shift_amt)
1442 def i64shift_sext_i32 : Operand<i64>, SDNodeXForm<imm, [{
1443 uint64_t enc = 63 - N->getZExtValue();
1444 enc = enc > 31 ? 31 : enc;
1445 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
1448 def : Pat<(shl GPR32:$Rn, (i64 imm0_31:$imm)),
1449 (UBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
1450 (i64 (i32shift_b imm0_31:$imm)))>;
1451 def : Pat<(shl GPR64:$Rn, (i64 imm0_63:$imm)),
1452 (UBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
1453 (i64 (i64shift_b imm0_63:$imm)))>;
1455 let AddedComplexity = 10 in {
1456 def : Pat<(sra GPR32:$Rn, (i64 imm0_31:$imm)),
1457 (SBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
1458 def : Pat<(sra GPR64:$Rn, (i64 imm0_63:$imm)),
1459 (SBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
1462 def : InstAlias<"asr $dst, $src, $shift",
1463 (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
1464 def : InstAlias<"asr $dst, $src, $shift",
1465 (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
1466 def : InstAlias<"sxtb $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
1467 def : InstAlias<"sxtb $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
1468 def : InstAlias<"sxth $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
1469 def : InstAlias<"sxth $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
1470 def : InstAlias<"sxtw $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
1472 def : Pat<(srl GPR32:$Rn, (i64 imm0_31:$imm)),
1473 (UBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
1474 def : Pat<(srl GPR64:$Rn, (i64 imm0_63:$imm)),
1475 (UBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
1477 def : InstAlias<"lsr $dst, $src, $shift",
1478 (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
1479 def : InstAlias<"lsr $dst, $src, $shift",
1480 (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
1481 def : InstAlias<"uxtb $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
1482 def : InstAlias<"uxtb $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
1483 def : InstAlias<"uxth $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
1484 def : InstAlias<"uxth $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
1485 def : InstAlias<"uxtw $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
1487 //===----------------------------------------------------------------------===//
1488 // Conditional comparison instructions.
1489 //===----------------------------------------------------------------------===//
1490 defm CCMN : CondComparison<0, "ccmn", AArch64ccmn>;
1491 defm CCMP : CondComparison<1, "ccmp", AArch64ccmp>;
1493 //===----------------------------------------------------------------------===//
1494 // Conditional select instructions.
1495 //===----------------------------------------------------------------------===//
1496 defm CSEL : CondSelect<0, 0b00, "csel">;
1498 def inc : PatFrag<(ops node:$in), (add node:$in, 1)>;
1499 defm CSINC : CondSelectOp<0, 0b01, "csinc", inc>;
1500 defm CSINV : CondSelectOp<1, 0b00, "csinv", not>;
1501 defm CSNEG : CondSelectOp<1, 0b01, "csneg", ineg>;
1503 def : Pat<(AArch64csinv GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
1504 (CSINVWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
1505 def : Pat<(AArch64csinv GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
1506 (CSINVXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
1507 def : Pat<(AArch64csneg GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
1508 (CSNEGWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
1509 def : Pat<(AArch64csneg GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
1510 (CSNEGXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
1511 def : Pat<(AArch64csinc GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
1512 (CSINCWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
1513 def : Pat<(AArch64csinc GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
1514 (CSINCXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
1516 def : Pat<(AArch64csel (i32 0), (i32 1), (i32 imm:$cc), NZCV),
1517 (CSINCWr WZR, WZR, (i32 imm:$cc))>;
1518 def : Pat<(AArch64csel (i64 0), (i64 1), (i32 imm:$cc), NZCV),
1519 (CSINCXr XZR, XZR, (i32 imm:$cc))>;
1520 def : Pat<(AArch64csel GPR32:$tval, (i32 1), (i32 imm:$cc), NZCV),
1521 (CSINCWr GPR32:$tval, WZR, (i32 imm:$cc))>;
1522 def : Pat<(AArch64csel GPR64:$tval, (i64 1), (i32 imm:$cc), NZCV),
1523 (CSINCXr GPR64:$tval, XZR, (i32 imm:$cc))>;
1524 def : Pat<(AArch64csel (i32 1), GPR32:$fval, (i32 imm:$cc), NZCV),
1525 (CSINCWr GPR32:$fval, WZR, (i32 (inv_cond_XFORM imm:$cc)))>;
1526 def : Pat<(AArch64csel (i64 1), GPR64:$fval, (i32 imm:$cc), NZCV),
1527 (CSINCXr GPR64:$fval, XZR, (i32 (inv_cond_XFORM imm:$cc)))>;
1528 def : Pat<(AArch64csel (i32 0), (i32 -1), (i32 imm:$cc), NZCV),
1529 (CSINVWr WZR, WZR, (i32 imm:$cc))>;
1530 def : Pat<(AArch64csel (i64 0), (i64 -1), (i32 imm:$cc), NZCV),
1531 (CSINVXr XZR, XZR, (i32 imm:$cc))>;
1532 def : Pat<(AArch64csel GPR32:$tval, (i32 -1), (i32 imm:$cc), NZCV),
1533 (CSINVWr GPR32:$tval, WZR, (i32 imm:$cc))>;
1534 def : Pat<(AArch64csel GPR64:$tval, (i64 -1), (i32 imm:$cc), NZCV),
1535 (CSINVXr GPR64:$tval, XZR, (i32 imm:$cc))>;
1536 def : Pat<(AArch64csel (i32 -1), GPR32:$fval, (i32 imm:$cc), NZCV),
1537 (CSINVWr GPR32:$fval, WZR, (i32 (inv_cond_XFORM imm:$cc)))>;
1538 def : Pat<(AArch64csel (i64 -1), GPR64:$fval, (i32 imm:$cc), NZCV),
1539 (CSINVXr GPR64:$fval, XZR, (i32 (inv_cond_XFORM imm:$cc)))>;
1541 // The inverse of the condition code from the alias instruction is what is used
1542 // in the aliased instruction. The parser all ready inverts the condition code
1543 // for these aliases.
1544 def : InstAlias<"cset $dst, $cc",
1545 (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
1546 def : InstAlias<"cset $dst, $cc",
1547 (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
1549 def : InstAlias<"csetm $dst, $cc",
1550 (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
1551 def : InstAlias<"csetm $dst, $cc",
1552 (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
1554 def : InstAlias<"cinc $dst, $src, $cc",
1555 (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
1556 def : InstAlias<"cinc $dst, $src, $cc",
1557 (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
1559 def : InstAlias<"cinv $dst, $src, $cc",
1560 (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
1561 def : InstAlias<"cinv $dst, $src, $cc",
1562 (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
1564 def : InstAlias<"cneg $dst, $src, $cc",
1565 (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
1566 def : InstAlias<"cneg $dst, $src, $cc",
1567 (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
1569 //===----------------------------------------------------------------------===//
1570 // PC-relative instructions.
1571 //===----------------------------------------------------------------------===//
1572 let isReMaterializable = 1 in {
1573 let hasSideEffects = 0, mayStore = 0, mayLoad = 0 in {
1574 def ADR : ADRI<0, "adr", adrlabel,
1575 [(set GPR64:$Xd, (AArch64adr tglobaladdr:$label))]>;
1576 } // hasSideEffects = 0
1578 def ADRP : ADRI<1, "adrp", adrplabel,
1579 [(set GPR64:$Xd, (AArch64adrp tglobaladdr:$label))]>;
1580 } // isReMaterializable = 1
1582 // page address of a constant pool entry, block address
1583 def : Pat<(AArch64adr tconstpool:$cp), (ADR tconstpool:$cp)>;
1584 def : Pat<(AArch64adr tblockaddress:$cp), (ADR tblockaddress:$cp)>;
1585 def : Pat<(AArch64adr texternalsym:$sym), (ADR texternalsym:$sym)>;
1586 def : Pat<(AArch64adr tjumptable:$sym), (ADR tjumptable:$sym)>;
1587 def : Pat<(AArch64adrp tconstpool:$cp), (ADRP tconstpool:$cp)>;
1588 def : Pat<(AArch64adrp tblockaddress:$cp), (ADRP tblockaddress:$cp)>;
1589 def : Pat<(AArch64adrp texternalsym:$sym), (ADRP texternalsym:$sym)>;
1591 //===----------------------------------------------------------------------===//
1592 // Unconditional branch (register) instructions.
1593 //===----------------------------------------------------------------------===//
1595 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1596 def RET : BranchReg<0b0010, "ret", []>;
1597 def DRPS : SpecialReturn<0b0101, "drps">;
1598 def ERET : SpecialReturn<0b0100, "eret">;
1599 } // isReturn = 1, isTerminator = 1, isBarrier = 1
1601 // Default to the LR register.
1602 def : InstAlias<"ret", (RET LR)>;
1604 let isCall = 1, Defs = [LR], Uses = [SP] in {
1605 def BLR : BranchReg<0b0001, "blr", [(AArch64call GPR64:$Rn)]>;
1608 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1609 def BR : BranchReg<0b0000, "br", [(brind GPR64:$Rn)]>;
1610 } // isBranch, isTerminator, isBarrier, isIndirectBranch
1612 // Create a separate pseudo-instruction for codegen to use so that we don't
1613 // flag lr as used in every function. It'll be restored before the RET by the
1614 // epilogue if it's legitimately used.
1615 def RET_ReallyLR : Pseudo<(outs), (ins), [(AArch64retflag)]>,
1616 Sched<[WriteBrReg]> {
1617 let isTerminator = 1;
1622 // This is a directive-like pseudo-instruction. The purpose is to insert an
1623 // R_AARCH64_TLSDESC_CALL relocation at the offset of the following instruction
1624 // (which in the usual case is a BLR).
1625 let hasSideEffects = 1 in
1626 def TLSDESCCALL : Pseudo<(outs), (ins i64imm:$sym), []>, Sched<[]> {
1627 let AsmString = ".tlsdesccall $sym";
1630 // Pseudo instruction to tell the streamer to emit a 'B' character into the
1631 // augmentation string.
1632 def EMITBKEY : Pseudo<(outs), (ins), []>, Sched<[]> {}
1634 // FIXME: maybe the scratch register used shouldn't be fixed to X1?
1635 // FIXME: can "hasSideEffects be dropped?
1636 let isCall = 1, Defs = [LR, X0, X1], hasSideEffects = 1,
1637 isCodeGenOnly = 1 in
1639 : Pseudo<(outs), (ins i64imm:$sym),
1640 [(AArch64tlsdesc_callseq tglobaltlsaddr:$sym)]>,
1641 Sched<[WriteI, WriteLD, WriteI, WriteBrReg]>;
1642 def : Pat<(AArch64tlsdesc_callseq texternalsym:$sym),
1643 (TLSDESC_CALLSEQ texternalsym:$sym)>;
1645 //===----------------------------------------------------------------------===//
1646 // Conditional branch (immediate) instruction.
1647 //===----------------------------------------------------------------------===//
1648 def Bcc : BranchCond;
1650 //===----------------------------------------------------------------------===//
1651 // Compare-and-branch instructions.
1652 //===----------------------------------------------------------------------===//
1653 defm CBZ : CmpBranch<0, "cbz", AArch64cbz>;
1654 defm CBNZ : CmpBranch<1, "cbnz", AArch64cbnz>;
1656 //===----------------------------------------------------------------------===//
1657 // Test-bit-and-branch instructions.
1658 //===----------------------------------------------------------------------===//
1659 defm TBZ : TestBranch<0, "tbz", AArch64tbz>;
1660 defm TBNZ : TestBranch<1, "tbnz", AArch64tbnz>;
1662 //===----------------------------------------------------------------------===//
1663 // Unconditional branch (immediate) instructions.
1664 //===----------------------------------------------------------------------===//
1665 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
1666 def B : BranchImm<0, "b", [(br bb:$addr)]>;
1667 } // isBranch, isTerminator, isBarrier
1669 let isCall = 1, Defs = [LR], Uses = [SP] in {
1670 def BL : CallImm<1, "bl", [(AArch64call tglobaladdr:$addr)]>;
1672 def : Pat<(AArch64call texternalsym:$func), (BL texternalsym:$func)>;
1674 //===----------------------------------------------------------------------===//
1675 // Exception generation instructions.
1676 //===----------------------------------------------------------------------===//
1678 def BRK : ExceptionGeneration<0b001, 0b00, "brk">;
1680 def DCPS1 : ExceptionGeneration<0b101, 0b01, "dcps1">;
1681 def DCPS2 : ExceptionGeneration<0b101, 0b10, "dcps2">;
1682 def DCPS3 : ExceptionGeneration<0b101, 0b11, "dcps3">;
1683 def HLT : ExceptionGeneration<0b010, 0b00, "hlt">;
1684 def HVC : ExceptionGeneration<0b000, 0b10, "hvc">;
1685 def SMC : ExceptionGeneration<0b000, 0b11, "smc">;
1686 def SVC : ExceptionGeneration<0b000, 0b01, "svc">;
1688 // DCPSn defaults to an immediate operand of zero if unspecified.
1689 def : InstAlias<"dcps1", (DCPS1 0)>;
1690 def : InstAlias<"dcps2", (DCPS2 0)>;
1691 def : InstAlias<"dcps3", (DCPS3 0)>;
1693 def UDF : UDFType<0, "udf">;
1695 //===----------------------------------------------------------------------===//
1696 // Load instructions.
1697 //===----------------------------------------------------------------------===//
1699 // Pair (indexed, offset)
1700 defm LDPW : LoadPairOffset<0b00, 0, GPR32z, simm7s4, "ldp">;
1701 defm LDPX : LoadPairOffset<0b10, 0, GPR64z, simm7s8, "ldp">;
1702 defm LDPS : LoadPairOffset<0b00, 1, FPR32Op, simm7s4, "ldp">;
1703 defm LDPD : LoadPairOffset<0b01, 1, FPR64Op, simm7s8, "ldp">;
1704 defm LDPQ : LoadPairOffset<0b10, 1, FPR128Op, simm7s16, "ldp">;
1706 defm LDPSW : LoadPairOffset<0b01, 0, GPR64z, simm7s4, "ldpsw">;
1708 // Pair (pre-indexed)
1709 def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32z, simm7s4, "ldp">;
1710 def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64z, simm7s8, "ldp">;
1711 def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32Op, simm7s4, "ldp">;
1712 def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64Op, simm7s8, "ldp">;
1713 def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128Op, simm7s16, "ldp">;
1715 def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64z, simm7s4, "ldpsw">;
1717 // Pair (post-indexed)
1718 def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32z, simm7s4, "ldp">;
1719 def LDPXpost : LoadPairPostIdx<0b10, 0, GPR64z, simm7s8, "ldp">;
1720 def LDPSpost : LoadPairPostIdx<0b00, 1, FPR32Op, simm7s4, "ldp">;
1721 def LDPDpost : LoadPairPostIdx<0b01, 1, FPR64Op, simm7s8, "ldp">;
1722 def LDPQpost : LoadPairPostIdx<0b10, 1, FPR128Op, simm7s16, "ldp">;
1724 def LDPSWpost : LoadPairPostIdx<0b01, 0, GPR64z, simm7s4, "ldpsw">;
1727 // Pair (no allocate)
1728 defm LDNPW : LoadPairNoAlloc<0b00, 0, GPR32z, simm7s4, "ldnp">;
1729 defm LDNPX : LoadPairNoAlloc<0b10, 0, GPR64z, simm7s8, "ldnp">;
1730 defm LDNPS : LoadPairNoAlloc<0b00, 1, FPR32Op, simm7s4, "ldnp">;
1731 defm LDNPD : LoadPairNoAlloc<0b01, 1, FPR64Op, simm7s8, "ldnp">;
1732 defm LDNPQ : LoadPairNoAlloc<0b10, 1, FPR128Op, simm7s16, "ldnp">;
1735 // (register offset)
1739 defm LDRBB : Load8RO<0b00, 0, 0b01, GPR32, "ldrb", i32, zextloadi8>;
1740 defm LDRHH : Load16RO<0b01, 0, 0b01, GPR32, "ldrh", i32, zextloadi16>;
1741 defm LDRW : Load32RO<0b10, 0, 0b01, GPR32, "ldr", i32, load>;
1742 defm LDRX : Load64RO<0b11, 0, 0b01, GPR64, "ldr", i64, load>;
1745 defm LDRB : Load8RO<0b00, 1, 0b01, FPR8Op, "ldr", untyped, load>;
1746 defm LDRH : Load16RO<0b01, 1, 0b01, FPR16Op, "ldr", f16, load>;
1747 defm LDRS : Load32RO<0b10, 1, 0b01, FPR32Op, "ldr", f32, load>;
1748 defm LDRD : Load64RO<0b11, 1, 0b01, FPR64Op, "ldr", f64, load>;
1749 defm LDRQ : Load128RO<0b00, 1, 0b11, FPR128Op, "ldr", f128, load>;
1751 // Load sign-extended half-word
1752 defm LDRSHW : Load16RO<0b01, 0, 0b11, GPR32, "ldrsh", i32, sextloadi16>;
1753 defm LDRSHX : Load16RO<0b01, 0, 0b10, GPR64, "ldrsh", i64, sextloadi16>;
1755 // Load sign-extended byte
1756 defm LDRSBW : Load8RO<0b00, 0, 0b11, GPR32, "ldrsb", i32, sextloadi8>;
1757 defm LDRSBX : Load8RO<0b00, 0, 0b10, GPR64, "ldrsb", i64, sextloadi8>;
1759 // Load sign-extended word
1760 defm LDRSW : Load32RO<0b10, 0, 0b10, GPR64, "ldrsw", i64, sextloadi32>;
1763 defm PRFM : PrefetchRO<0b11, 0, 0b10, "prfm">;
1765 // For regular load, we do not have any alignment requirement.
1766 // Thus, it is safe to directly map the vector loads with interesting
1767 // addressing modes.
1768 // FIXME: We could do the same for bitconvert to floating point vectors.
1769 multiclass ScalToVecROLoadPat<ROAddrMode ro, SDPatternOperator loadop,
1770 ValueType ScalTy, ValueType VecTy,
1771 Instruction LOADW, Instruction LOADX,
1773 def : Pat<(VecTy (scalar_to_vector (ScalTy
1774 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset))))),
1775 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1776 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset),
1779 def : Pat<(VecTy (scalar_to_vector (ScalTy
1780 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset))))),
1781 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1782 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset),
1786 let AddedComplexity = 10 in {
1787 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v8i8, LDRBroW, LDRBroX, bsub>;
1788 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v16i8, LDRBroW, LDRBroX, bsub>;
1790 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v4i16, LDRHroW, LDRHroX, hsub>;
1791 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v8i16, LDRHroW, LDRHroX, hsub>;
1793 defm : ScalToVecROLoadPat<ro16, load, i32, v4f16, LDRHroW, LDRHroX, hsub>;
1794 defm : ScalToVecROLoadPat<ro16, load, i32, v8f16, LDRHroW, LDRHroX, hsub>;
1796 defm : ScalToVecROLoadPat<ro32, load, i32, v2i32, LDRSroW, LDRSroX, ssub>;
1797 defm : ScalToVecROLoadPat<ro32, load, i32, v4i32, LDRSroW, LDRSroX, ssub>;
1799 defm : ScalToVecROLoadPat<ro32, load, f32, v2f32, LDRSroW, LDRSroX, ssub>;
1800 defm : ScalToVecROLoadPat<ro32, load, f32, v4f32, LDRSroW, LDRSroX, ssub>;
1802 defm : ScalToVecROLoadPat<ro64, load, i64, v2i64, LDRDroW, LDRDroX, dsub>;
1804 defm : ScalToVecROLoadPat<ro64, load, f64, v2f64, LDRDroW, LDRDroX, dsub>;
1807 def : Pat <(v1i64 (scalar_to_vector (i64
1808 (load (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
1809 ro_Wextend64:$extend))))),
1810 (LDRDroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend)>;
1812 def : Pat <(v1i64 (scalar_to_vector (i64
1813 (load (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
1814 ro_Xextend64:$extend))))),
1815 (LDRDroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend)>;
1818 // Match all load 64 bits width whose type is compatible with FPR64
1819 multiclass VecROLoadPat<ROAddrMode ro, ValueType VecTy,
1820 Instruction LOADW, Instruction LOADX> {
1822 def : Pat<(VecTy (load (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1823 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1825 def : Pat<(VecTy (load (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1826 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1829 let AddedComplexity = 10 in {
1830 let Predicates = [IsLE] in {
1831 // We must do vector loads with LD1 in big-endian.
1832 defm : VecROLoadPat<ro64, v2i32, LDRDroW, LDRDroX>;
1833 defm : VecROLoadPat<ro64, v2f32, LDRDroW, LDRDroX>;
1834 defm : VecROLoadPat<ro64, v8i8, LDRDroW, LDRDroX>;
1835 defm : VecROLoadPat<ro64, v4i16, LDRDroW, LDRDroX>;
1836 defm : VecROLoadPat<ro64, v4f16, LDRDroW, LDRDroX>;
1839 defm : VecROLoadPat<ro64, v1i64, LDRDroW, LDRDroX>;
1840 defm : VecROLoadPat<ro64, v1f64, LDRDroW, LDRDroX>;
1842 // Match all load 128 bits width whose type is compatible with FPR128
1843 let Predicates = [IsLE] in {
1844 // We must do vector loads with LD1 in big-endian.
1845 defm : VecROLoadPat<ro128, v2i64, LDRQroW, LDRQroX>;
1846 defm : VecROLoadPat<ro128, v2f64, LDRQroW, LDRQroX>;
1847 defm : VecROLoadPat<ro128, v4i32, LDRQroW, LDRQroX>;
1848 defm : VecROLoadPat<ro128, v4f32, LDRQroW, LDRQroX>;
1849 defm : VecROLoadPat<ro128, v8i16, LDRQroW, LDRQroX>;
1850 defm : VecROLoadPat<ro128, v8f16, LDRQroW, LDRQroX>;
1851 defm : VecROLoadPat<ro128, v16i8, LDRQroW, LDRQroX>;
1853 } // AddedComplexity = 10
1856 multiclass ExtLoadTo64ROPat<ROAddrMode ro, SDPatternOperator loadop,
1857 Instruction INSTW, Instruction INSTX> {
1858 def : Pat<(i64 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1859 (SUBREG_TO_REG (i64 0),
1860 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend),
1863 def : Pat<(i64 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1864 (SUBREG_TO_REG (i64 0),
1865 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend),
1869 let AddedComplexity = 10 in {
1870 defm : ExtLoadTo64ROPat<ro8, zextloadi8, LDRBBroW, LDRBBroX>;
1871 defm : ExtLoadTo64ROPat<ro16, zextloadi16, LDRHHroW, LDRHHroX>;
1872 defm : ExtLoadTo64ROPat<ro32, zextloadi32, LDRWroW, LDRWroX>;
1874 // zextloadi1 -> zextloadi8
1875 defm : ExtLoadTo64ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>;
1877 // extload -> zextload
1878 defm : ExtLoadTo64ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>;
1879 defm : ExtLoadTo64ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>;
1880 defm : ExtLoadTo64ROPat<ro32, extloadi32, LDRWroW, LDRWroX>;
1882 // extloadi1 -> zextloadi8
1883 defm : ExtLoadTo64ROPat<ro8, extloadi1, LDRBBroW, LDRBBroX>;
1888 multiclass ExtLoadTo32ROPat<ROAddrMode ro, SDPatternOperator loadop,
1889 Instruction INSTW, Instruction INSTX> {
1890 def : Pat<(i32 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1891 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1893 def : Pat<(i32 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1894 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1898 let AddedComplexity = 10 in {
1899 // extload -> zextload
1900 defm : ExtLoadTo32ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>;
1901 defm : ExtLoadTo32ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>;
1902 defm : ExtLoadTo32ROPat<ro32, extloadi32, LDRWroW, LDRWroX>;
1904 // zextloadi1 -> zextloadi8
1905 defm : ExtLoadTo32ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>;
1909 // (unsigned immediate)
1911 defm LDRX : LoadUI<0b11, 0, 0b01, GPR64z, uimm12s8, "ldr",
1913 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>;
1914 defm LDRW : LoadUI<0b10, 0, 0b01, GPR32z, uimm12s4, "ldr",
1916 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;
1917 defm LDRB : LoadUI<0b00, 1, 0b01, FPR8Op, uimm12s1, "ldr",
1919 (load (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)))]>;
1920 defm LDRH : LoadUI<0b01, 1, 0b01, FPR16Op, uimm12s2, "ldr",
1921 [(set (f16 FPR16Op:$Rt),
1922 (load (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)))]>;
1923 defm LDRS : LoadUI<0b10, 1, 0b01, FPR32Op, uimm12s4, "ldr",
1924 [(set (f32 FPR32Op:$Rt),
1925 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;
1926 defm LDRD : LoadUI<0b11, 1, 0b01, FPR64Op, uimm12s8, "ldr",
1927 [(set (f64 FPR64Op:$Rt),
1928 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>;
1929 defm LDRQ : LoadUI<0b00, 1, 0b11, FPR128Op, uimm12s16, "ldr",
1930 [(set (f128 FPR128Op:$Rt),
1931 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)))]>;
1933 // For regular load, we do not have any alignment requirement.
1934 // Thus, it is safe to directly map the vector loads with interesting
1935 // addressing modes.
1936 // FIXME: We could do the same for bitconvert to floating point vectors.
1937 def : Pat <(v8i8 (scalar_to_vector (i32
1938 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
1939 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
1940 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>;
1941 def : Pat <(v16i8 (scalar_to_vector (i32
1942 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
1943 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1944 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>;
1945 def : Pat <(v4i16 (scalar_to_vector (i32
1946 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
1947 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
1948 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1949 def : Pat <(v8i16 (scalar_to_vector (i32
1950 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
1951 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1952 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1953 def : Pat <(v2i32 (scalar_to_vector (i32
1954 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
1955 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1956 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
1957 def : Pat <(v4i32 (scalar_to_vector (i32
1958 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
1959 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1960 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
1961 def : Pat <(v1i64 (scalar_to_vector (i64
1962 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))),
1963 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1964 def : Pat <(v2i64 (scalar_to_vector (i64
1965 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))),
1966 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
1967 (LDRDui GPR64sp:$Rn, uimm12s8:$offset), dsub)>;
1969 // Match all load 64 bits width whose type is compatible with FPR64
1970 let Predicates = [IsLE] in {
1971 // We must use LD1 to perform vector loads in big-endian.
1972 def : Pat<(v2f32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1973 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1974 def : Pat<(v8i8 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1975 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1976 def : Pat<(v4i16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1977 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1978 def : Pat<(v2i32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1979 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1980 def : Pat<(v4f16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1981 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1983 def : Pat<(v1f64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1984 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1985 def : Pat<(v1i64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1986 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1988 // Match all load 128 bits width whose type is compatible with FPR128
1989 let Predicates = [IsLE] in {
1990 // We must use LD1 to perform vector loads in big-endian.
1991 def : Pat<(v4f32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1992 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1993 def : Pat<(v2f64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1994 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1995 def : Pat<(v16i8 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1996 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1997 def : Pat<(v8i16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1998 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1999 def : Pat<(v4i32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
2000 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
2001 def : Pat<(v2i64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
2002 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
2003 def : Pat<(v8f16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
2004 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
2006 def : Pat<(f128 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
2007 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
2009 defm LDRHH : LoadUI<0b01, 0, 0b01, GPR32, uimm12s2, "ldrh",
2011 (zextloadi16 (am_indexed16 GPR64sp:$Rn,
2012 uimm12s2:$offset)))]>;
2013 defm LDRBB : LoadUI<0b00, 0, 0b01, GPR32, uimm12s1, "ldrb",
2015 (zextloadi8 (am_indexed8 GPR64sp:$Rn,
2016 uimm12s1:$offset)))]>;
2018 def : Pat<(i64 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
2019 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
2020 def : Pat<(i64 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
2021 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
2023 // zextloadi1 -> zextloadi8
2024 def : Pat<(i32 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
2025 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
2026 def : Pat<(i64 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
2027 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
2029 // extload -> zextload
2030 def : Pat<(i32 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
2031 (LDRHHui GPR64sp:$Rn, uimm12s2:$offset)>;
2032 def : Pat<(i32 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
2033 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
2034 def : Pat<(i32 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
2035 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
2036 def : Pat<(i64 (extloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))),
2037 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;
2038 def : Pat<(i64 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
2039 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
2040 def : Pat<(i64 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
2041 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
2042 def : Pat<(i64 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
2043 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
2045 // load sign-extended half-word
2046 defm LDRSHW : LoadUI<0b01, 0, 0b11, GPR32, uimm12s2, "ldrsh",
2048 (sextloadi16 (am_indexed16 GPR64sp:$Rn,
2049 uimm12s2:$offset)))]>;
2050 defm LDRSHX : LoadUI<0b01, 0, 0b10, GPR64, uimm12s2, "ldrsh",
2052 (sextloadi16 (am_indexed16 GPR64sp:$Rn,
2053 uimm12s2:$offset)))]>;
2055 // load sign-extended byte
2056 defm LDRSBW : LoadUI<0b00, 0, 0b11, GPR32, uimm12s1, "ldrsb",
2058 (sextloadi8 (am_indexed8 GPR64sp:$Rn,
2059 uimm12s1:$offset)))]>;
2060 defm LDRSBX : LoadUI<0b00, 0, 0b10, GPR64, uimm12s1, "ldrsb",
2062 (sextloadi8 (am_indexed8 GPR64sp:$Rn,
2063 uimm12s1:$offset)))]>;
2065 // load sign-extended word
2066 defm LDRSW : LoadUI<0b10, 0, 0b10, GPR64, uimm12s4, "ldrsw",
2068 (sextloadi32 (am_indexed32 GPR64sp:$Rn,
2069 uimm12s4:$offset)))]>;
2071 // load zero-extended word
2072 def : Pat<(i64 (zextloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))),
2073 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;
2076 def PRFMui : PrefetchUI<0b11, 0, 0b10, "prfm",
2077 [(AArch64Prefetch imm:$Rt,
2078 (am_indexed64 GPR64sp:$Rn,
2079 uimm12s8:$offset))]>;
2081 def : InstAlias<"prfm $Rt, [$Rn]", (PRFMui prfop:$Rt, GPR64sp:$Rn, 0)>;
2086 def alignedglobal : PatLeaf<(iPTR iPTR:$label), [{
2087 if (auto *G = dyn_cast<GlobalAddressSDNode>(N)) {
2088 const DataLayout &DL = MF->getDataLayout();
2089 unsigned Align = G->getGlobal()->getPointerAlignment(DL);
2090 return Align >= 4 && G->getOffset() % 4 == 0;
2092 if (auto *C = dyn_cast<ConstantPoolSDNode>(N))
2093 return C->getAlignment() >= 4 && C->getOffset() % 4 == 0;
2097 def LDRWl : LoadLiteral<0b00, 0, GPR32z, "ldr",
2098 [(set GPR32z:$Rt, (load (AArch64adr alignedglobal:$label)))]>;
2099 def LDRXl : LoadLiteral<0b01, 0, GPR64z, "ldr",
2100 [(set GPR64z:$Rt, (load (AArch64adr alignedglobal:$label)))]>;
2101 def LDRSl : LoadLiteral<0b00, 1, FPR32Op, "ldr",
2102 [(set (f32 FPR32Op:$Rt), (load (AArch64adr alignedglobal:$label)))]>;
2103 def LDRDl : LoadLiteral<0b01, 1, FPR64Op, "ldr",
2104 [(set (f64 FPR64Op:$Rt), (load (AArch64adr alignedglobal:$label)))]>;
2105 def LDRQl : LoadLiteral<0b10, 1, FPR128Op, "ldr",
2106 [(set (f128 FPR128Op:$Rt), (load (AArch64adr alignedglobal:$label)))]>;
2108 // load sign-extended word
2109 def LDRSWl : LoadLiteral<0b10, 0, GPR64z, "ldrsw",
2110 [(set GPR64z:$Rt, (sextloadi32 (AArch64adr alignedglobal:$label)))]>;
2112 let AddedComplexity = 20 in {
2113 def : Pat<(i64 (zextloadi32 (AArch64adr alignedglobal:$label))),
2114 (SUBREG_TO_REG (i64 0), (LDRWl $label), sub_32)>;
2118 def PRFMl : PrefetchLiteral<0b11, 0, "prfm", []>;
2119 // [(AArch64Prefetch imm:$Rt, tglobaladdr:$label)]>;
2122 // (unscaled immediate)
2123 defm LDURX : LoadUnscaled<0b11, 0, 0b01, GPR64z, "ldur",
2125 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;
2126 defm LDURW : LoadUnscaled<0b10, 0, 0b01, GPR32z, "ldur",
2128 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
2129 defm LDURB : LoadUnscaled<0b00, 1, 0b01, FPR8Op, "ldur",
2131 (load (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
2132 defm LDURH : LoadUnscaled<0b01, 1, 0b01, FPR16Op, "ldur",
2134 (load (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
2135 defm LDURS : LoadUnscaled<0b10, 1, 0b01, FPR32Op, "ldur",
2136 [(set (f32 FPR32Op:$Rt),
2137 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
2138 defm LDURD : LoadUnscaled<0b11, 1, 0b01, FPR64Op, "ldur",
2139 [(set (f64 FPR64Op:$Rt),
2140 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;
2141 defm LDURQ : LoadUnscaled<0b00, 1, 0b11, FPR128Op, "ldur",
2142 [(set (f128 FPR128Op:$Rt),
2143 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset)))]>;
2146 : LoadUnscaled<0b01, 0, 0b01, GPR32, "ldurh",
2148 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
2150 : LoadUnscaled<0b00, 0, 0b01, GPR32, "ldurb",
2152 (zextloadi8 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
2154 // Match all load 64 bits width whose type is compatible with FPR64
2155 let Predicates = [IsLE] in {
2156 def : Pat<(v2f32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
2157 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
2158 def : Pat<(v2i32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
2159 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
2160 def : Pat<(v4i16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
2161 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
2162 def : Pat<(v8i8 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
2163 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
2164 def : Pat<(v4f16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
2165 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
2167 def : Pat<(v1f64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
2168 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
2169 def : Pat<(v1i64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
2170 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
2172 // Match all load 128 bits width whose type is compatible with FPR128
2173 let Predicates = [IsLE] in {
2174 def : Pat<(v2f64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
2175 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
2176 def : Pat<(v2i64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
2177 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
2178 def : Pat<(v4f32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
2179 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
2180 def : Pat<(v4i32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
2181 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
2182 def : Pat<(v8i16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
2183 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
2184 def : Pat<(v16i8 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
2185 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
2186 def : Pat<(v8f16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
2187 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
2191 def : Pat<(i32 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
2192 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
2193 def : Pat<(i32 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
2194 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
2195 def : Pat<(i32 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
2196 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
2197 def : Pat<(i64 (extloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))),
2198 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>;
2199 def : Pat<(i64 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
2200 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
2201 def : Pat<(i64 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
2202 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
2203 def : Pat<(i64 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
2204 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
2206 def : Pat<(i32 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
2207 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
2208 def : Pat<(i32 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
2209 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
2210 def : Pat<(i32 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
2211 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
2212 def : Pat<(i64 (zextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))),
2213 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>;
2214 def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
2215 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
2216 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
2217 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
2218 def : Pat<(i64 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
2219 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
2223 // LDR mnemonics fall back to LDUR for negative or unaligned offsets.
2225 // Define new assembler match classes as we want to only match these when
2226 // the don't otherwise match the scaled addressing mode for LDR/STR. Don't
2227 // associate a DiagnosticType either, as we want the diagnostic for the
2228 // canonical form (the scaled operand) to take precedence.
2229 class SImm9OffsetOperand<int Width> : AsmOperandClass {
2230 let Name = "SImm9OffsetFB" # Width;
2231 let PredicateMethod = "isSImm9OffsetFB<" # Width # ">";
2232 let RenderMethod = "addImmOperands";
2235 def SImm9OffsetFB8Operand : SImm9OffsetOperand<8>;
2236 def SImm9OffsetFB16Operand : SImm9OffsetOperand<16>;
2237 def SImm9OffsetFB32Operand : SImm9OffsetOperand<32>;
2238 def SImm9OffsetFB64Operand : SImm9OffsetOperand<64>;
2239 def SImm9OffsetFB128Operand : SImm9OffsetOperand<128>;
2241 def simm9_offset_fb8 : Operand<i64> {
2242 let ParserMatchClass = SImm9OffsetFB8Operand;
2244 def simm9_offset_fb16 : Operand<i64> {
2245 let ParserMatchClass = SImm9OffsetFB16Operand;
2247 def simm9_offset_fb32 : Operand<i64> {
2248 let ParserMatchClass = SImm9OffsetFB32Operand;
2250 def simm9_offset_fb64 : Operand<i64> {
2251 let ParserMatchClass = SImm9OffsetFB64Operand;
2253 def simm9_offset_fb128 : Operand<i64> {
2254 let ParserMatchClass = SImm9OffsetFB128Operand;
2257 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
2258 (LDURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
2259 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
2260 (LDURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
2261 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
2262 (LDURBi FPR8Op:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2263 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
2264 (LDURHi FPR16Op:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2265 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
2266 (LDURSi FPR32Op:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
2267 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
2268 (LDURDi FPR64Op:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
2269 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
2270 (LDURQi FPR128Op:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;
2273 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
2274 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
2275 def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
2276 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
2278 // load sign-extended half-word
2280 : LoadUnscaled<0b01, 0, 0b11, GPR32, "ldursh",
2282 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
2284 : LoadUnscaled<0b01, 0, 0b10, GPR64, "ldursh",
2286 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
2288 // load sign-extended byte
2290 : LoadUnscaled<0b00, 0, 0b11, GPR32, "ldursb",
2292 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
2294 : LoadUnscaled<0b00, 0, 0b10, GPR64, "ldursb",
2296 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
2298 // load sign-extended word
2300 : LoadUnscaled<0b10, 0, 0b10, GPR64, "ldursw",
2302 (sextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
2304 // zero and sign extending aliases from generic LDR* mnemonics to LDUR*.
2305 def : InstAlias<"ldrb $Rt, [$Rn, $offset]",
2306 (LDURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2307 def : InstAlias<"ldrh $Rt, [$Rn, $offset]",
2308 (LDURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2309 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",
2310 (LDURSBWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2311 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",
2312 (LDURSBXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2313 def : InstAlias<"ldrsh $Rt, [$Rn, $offset]",
2314 (LDURSHWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2315 def : InstAlias<"ldrsh $Rt, [$Rn, $offset]",
2316 (LDURSHXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2317 def : InstAlias<"ldrsw $Rt, [$Rn, $offset]",
2318 (LDURSWi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
2321 defm PRFUM : PrefetchUnscaled<0b11, 0, 0b10, "prfum",
2322 [(AArch64Prefetch imm:$Rt,
2323 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
2326 // (unscaled immediate, unprivileged)
2327 defm LDTRX : LoadUnprivileged<0b11, 0, 0b01, GPR64, "ldtr">;
2328 defm LDTRW : LoadUnprivileged<0b10, 0, 0b01, GPR32, "ldtr">;
2330 defm LDTRH : LoadUnprivileged<0b01, 0, 0b01, GPR32, "ldtrh">;
2331 defm LDTRB : LoadUnprivileged<0b00, 0, 0b01, GPR32, "ldtrb">;
2333 // load sign-extended half-word
2334 defm LDTRSHW : LoadUnprivileged<0b01, 0, 0b11, GPR32, "ldtrsh">;
2335 defm LDTRSHX : LoadUnprivileged<0b01, 0, 0b10, GPR64, "ldtrsh">;
2337 // load sign-extended byte
2338 defm LDTRSBW : LoadUnprivileged<0b00, 0, 0b11, GPR32, "ldtrsb">;
2339 defm LDTRSBX : LoadUnprivileged<0b00, 0, 0b10, GPR64, "ldtrsb">;
2341 // load sign-extended word
2342 defm LDTRSW : LoadUnprivileged<0b10, 0, 0b10, GPR64, "ldtrsw">;
2345 // (immediate pre-indexed)
2346 def LDRWpre : LoadPreIdx<0b10, 0, 0b01, GPR32z, "ldr">;
2347 def LDRXpre : LoadPreIdx<0b11, 0, 0b01, GPR64z, "ldr">;
2348 def LDRBpre : LoadPreIdx<0b00, 1, 0b01, FPR8Op, "ldr">;
2349 def LDRHpre : LoadPreIdx<0b01, 1, 0b01, FPR16Op, "ldr">;
2350 def LDRSpre : LoadPreIdx<0b10, 1, 0b01, FPR32Op, "ldr">;
2351 def LDRDpre : LoadPreIdx<0b11, 1, 0b01, FPR64Op, "ldr">;
2352 def LDRQpre : LoadPreIdx<0b00, 1, 0b11, FPR128Op, "ldr">;
2354 // load sign-extended half-word
2355 def LDRSHWpre : LoadPreIdx<0b01, 0, 0b11, GPR32z, "ldrsh">;
2356 def LDRSHXpre : LoadPreIdx<0b01, 0, 0b10, GPR64z, "ldrsh">;
2358 // load sign-extended byte
2359 def LDRSBWpre : LoadPreIdx<0b00, 0, 0b11, GPR32z, "ldrsb">;
2360 def LDRSBXpre : LoadPreIdx<0b00, 0, 0b10, GPR64z, "ldrsb">;
2362 // load zero-extended byte
2363 def LDRBBpre : LoadPreIdx<0b00, 0, 0b01, GPR32z, "ldrb">;
2364 def LDRHHpre : LoadPreIdx<0b01, 0, 0b01, GPR32z, "ldrh">;
2366 // load sign-extended word
2367 def LDRSWpre : LoadPreIdx<0b10, 0, 0b10, GPR64z, "ldrsw">;
2370 // (immediate post-indexed)
2371 def LDRWpost : LoadPostIdx<0b10, 0, 0b01, GPR32z, "ldr">;
2372 def LDRXpost : LoadPostIdx<0b11, 0, 0b01, GPR64z, "ldr">;
2373 def LDRBpost : LoadPostIdx<0b00, 1, 0b01, FPR8Op, "ldr">;
2374 def LDRHpost : LoadPostIdx<0b01, 1, 0b01, FPR16Op, "ldr">;
2375 def LDRSpost : LoadPostIdx<0b10, 1, 0b01, FPR32Op, "ldr">;
2376 def LDRDpost : LoadPostIdx<0b11, 1, 0b01, FPR64Op, "ldr">;
2377 def LDRQpost : LoadPostIdx<0b00, 1, 0b11, FPR128Op, "ldr">;
2379 // load sign-extended half-word
2380 def LDRSHWpost : LoadPostIdx<0b01, 0, 0b11, GPR32z, "ldrsh">;
2381 def LDRSHXpost : LoadPostIdx<0b01, 0, 0b10, GPR64z, "ldrsh">;
2383 // load sign-extended byte
2384 def LDRSBWpost : LoadPostIdx<0b00, 0, 0b11, GPR32z, "ldrsb">;
2385 def LDRSBXpost : LoadPostIdx<0b00, 0, 0b10, GPR64z, "ldrsb">;
2387 // load zero-extended byte
2388 def LDRBBpost : LoadPostIdx<0b00, 0, 0b01, GPR32z, "ldrb">;
2389 def LDRHHpost : LoadPostIdx<0b01, 0, 0b01, GPR32z, "ldrh">;
2391 // load sign-extended word
2392 def LDRSWpost : LoadPostIdx<0b10, 0, 0b10, GPR64z, "ldrsw">;
2394 //===----------------------------------------------------------------------===//
2395 // Store instructions.
2396 //===----------------------------------------------------------------------===//
2398 // Pair (indexed, offset)
2399 // FIXME: Use dedicated range-checked addressing mode operand here.
2400 defm STPW : StorePairOffset<0b00, 0, GPR32z, simm7s4, "stp">;
2401 defm STPX : StorePairOffset<0b10, 0, GPR64z, simm7s8, "stp">;
2402 defm STPS : StorePairOffset<0b00, 1, FPR32Op, simm7s4, "stp">;
2403 defm STPD : StorePairOffset<0b01, 1, FPR64Op, simm7s8, "stp">;
2404 defm STPQ : StorePairOffset<0b10, 1, FPR128Op, simm7s16, "stp">;
2406 // Pair (pre-indexed)
2407 def STPWpre : StorePairPreIdx<0b00, 0, GPR32z, simm7s4, "stp">;
2408 def STPXpre : StorePairPreIdx<0b10, 0, GPR64z, simm7s8, "stp">;
2409 def STPSpre : StorePairPreIdx<0b00, 1, FPR32Op, simm7s4, "stp">;
2410 def STPDpre : StorePairPreIdx<0b01, 1, FPR64Op, simm7s8, "stp">;
2411 def STPQpre : StorePairPreIdx<0b10, 1, FPR128Op, simm7s16, "stp">;
2413 // Pair (pre-indexed)
2414 def STPWpost : StorePairPostIdx<0b00, 0, GPR32z, simm7s4, "stp">;
2415 def STPXpost : StorePairPostIdx<0b10, 0, GPR64z, simm7s8, "stp">;
2416 def STPSpost : StorePairPostIdx<0b00, 1, FPR32Op, simm7s4, "stp">;
2417 def STPDpost : StorePairPostIdx<0b01, 1, FPR64Op, simm7s8, "stp">;
2418 def STPQpost : StorePairPostIdx<0b10, 1, FPR128Op, simm7s16, "stp">;
2420 // Pair (no allocate)
2421 defm STNPW : StorePairNoAlloc<0b00, 0, GPR32z, simm7s4, "stnp">;
2422 defm STNPX : StorePairNoAlloc<0b10, 0, GPR64z, simm7s8, "stnp">;
2423 defm STNPS : StorePairNoAlloc<0b00, 1, FPR32Op, simm7s4, "stnp">;
2424 defm STNPD : StorePairNoAlloc<0b01, 1, FPR64Op, simm7s8, "stnp">;
2425 defm STNPQ : StorePairNoAlloc<0b10, 1, FPR128Op, simm7s16, "stnp">;
2428 // (Register offset)
2431 defm STRBB : Store8RO< 0b00, 0, 0b00, GPR32, "strb", i32, truncstorei8>;
2432 defm STRHH : Store16RO<0b01, 0, 0b00, GPR32, "strh", i32, truncstorei16>;
2433 defm STRW : Store32RO<0b10, 0, 0b00, GPR32, "str", i32, store>;
2434 defm STRX : Store64RO<0b11, 0, 0b00, GPR64, "str", i64, store>;
2438 defm STRB : Store8RO< 0b00, 1, 0b00, FPR8Op, "str", untyped, store>;
2439 defm STRH : Store16RO<0b01, 1, 0b00, FPR16Op, "str", f16, store>;
2440 defm STRS : Store32RO<0b10, 1, 0b00, FPR32Op, "str", f32, store>;
2441 defm STRD : Store64RO<0b11, 1, 0b00, FPR64Op, "str", f64, store>;
2442 defm STRQ : Store128RO<0b00, 1, 0b10, FPR128Op, "str", f128, store>;
2444 let Predicates = [UseSTRQro], AddedComplexity = 10 in {
2445 def : Pat<(store (f128 FPR128:$Rt),
2446 (ro_Windexed128 GPR64sp:$Rn, GPR32:$Rm,
2447 ro_Wextend128:$extend)),
2448 (STRQroW FPR128:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend128:$extend)>;
2449 def : Pat<(store (f128 FPR128:$Rt),
2450 (ro_Xindexed128 GPR64sp:$Rn, GPR64:$Rm,
2451 ro_Xextend128:$extend)),
2452 (STRQroX FPR128:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Wextend128:$extend)>;
2455 multiclass TruncStoreFrom64ROPat<ROAddrMode ro, SDPatternOperator storeop,
2456 Instruction STRW, Instruction STRX> {
2458 def : Pat<(storeop GPR64:$Rt,
2459 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
2460 (STRW (EXTRACT_SUBREG GPR64:$Rt, sub_32),
2461 GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
2463 def : Pat<(storeop GPR64:$Rt,
2464 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
2465 (STRX (EXTRACT_SUBREG GPR64:$Rt, sub_32),
2466 GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
2469 let AddedComplexity = 10 in {
2471 defm : TruncStoreFrom64ROPat<ro8, truncstorei8, STRBBroW, STRBBroX>;
2472 defm : TruncStoreFrom64ROPat<ro16, truncstorei16, STRHHroW, STRHHroX>;
2473 defm : TruncStoreFrom64ROPat<ro32, truncstorei32, STRWroW, STRWroX>;
2476 multiclass VecROStorePat<ROAddrMode ro, ValueType VecTy, RegisterClass FPR,
2477 Instruction STRW, Instruction STRX> {
2478 def : Pat<(store (VecTy FPR:$Rt),
2479 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
2480 (STRW FPR:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
2482 def : Pat<(store (VecTy FPR:$Rt),
2483 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
2484 (STRX FPR:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
2487 let AddedComplexity = 10 in {
2488 // Match all store 64 bits width whose type is compatible with FPR64
2489 let Predicates = [IsLE] in {
2490 // We must use ST1 to store vectors in big-endian.
2491 defm : VecROStorePat<ro64, v2i32, FPR64, STRDroW, STRDroX>;
2492 defm : VecROStorePat<ro64, v2f32, FPR64, STRDroW, STRDroX>;
2493 defm : VecROStorePat<ro64, v4i16, FPR64, STRDroW, STRDroX>;
2494 defm : VecROStorePat<ro64, v8i8, FPR64, STRDroW, STRDroX>;
2495 defm : VecROStorePat<ro64, v4f16, FPR64, STRDroW, STRDroX>;
2498 defm : VecROStorePat<ro64, v1i64, FPR64, STRDroW, STRDroX>;
2499 defm : VecROStorePat<ro64, v1f64, FPR64, STRDroW, STRDroX>;
2501 // Match all store 128 bits width whose type is compatible with FPR128
2502 let Predicates = [IsLE, UseSTRQro] in {
2503 // We must use ST1 to store vectors in big-endian.
2504 defm : VecROStorePat<ro128, v2i64, FPR128, STRQroW, STRQroX>;
2505 defm : VecROStorePat<ro128, v2f64, FPR128, STRQroW, STRQroX>;
2506 defm : VecROStorePat<ro128, v4i32, FPR128, STRQroW, STRQroX>;
2507 defm : VecROStorePat<ro128, v4f32, FPR128, STRQroW, STRQroX>;
2508 defm : VecROStorePat<ro128, v8i16, FPR128, STRQroW, STRQroX>;
2509 defm : VecROStorePat<ro128, v16i8, FPR128, STRQroW, STRQroX>;
2510 defm : VecROStorePat<ro128, v8f16, FPR128, STRQroW, STRQroX>;
2512 } // AddedComplexity = 10
2514 // Match stores from lane 0 to the appropriate subreg's store.
2515 multiclass VecROStoreLane0Pat<ROAddrMode ro, SDPatternOperator storeop,
2516 ValueType VecTy, ValueType STy,
2517 SubRegIndex SubRegIdx,
2518 Instruction STRW, Instruction STRX> {
2520 def : Pat<(storeop (STy (vector_extract (VecTy VecListOne128:$Vt), 0)),
2521 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
2522 (STRW (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx),
2523 GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
2525 def : Pat<(storeop (STy (vector_extract (VecTy VecListOne128:$Vt), 0)),
2526 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
2527 (STRX (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx),
2528 GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
2531 let AddedComplexity = 19 in {
2532 defm : VecROStoreLane0Pat<ro16, truncstorei16, v8i16, i32, hsub, STRHroW, STRHroX>;
2533 defm : VecROStoreLane0Pat<ro16, store, v8f16, f16, hsub, STRHroW, STRHroX>;
2534 defm : VecROStoreLane0Pat<ro32, store, v4i32, i32, ssub, STRSroW, STRSroX>;
2535 defm : VecROStoreLane0Pat<ro32, store, v4f32, f32, ssub, STRSroW, STRSroX>;
2536 defm : VecROStoreLane0Pat<ro64, store, v2i64, i64, dsub, STRDroW, STRDroX>;
2537 defm : VecROStoreLane0Pat<ro64, store, v2f64, f64, dsub, STRDroW, STRDroX>;
2541 // (unsigned immediate)
2542 defm STRX : StoreUIz<0b11, 0, 0b00, GPR64z, uimm12s8, "str",
2544 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>;
2545 defm STRW : StoreUIz<0b10, 0, 0b00, GPR32z, uimm12s4, "str",
2547 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>;
2548 defm STRB : StoreUI<0b00, 1, 0b00, FPR8Op, uimm12s1, "str",
2550 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))]>;
2551 defm STRH : StoreUI<0b01, 1, 0b00, FPR16Op, uimm12s2, "str",
2552 [(store (f16 FPR16Op:$Rt),
2553 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))]>;
2554 defm STRS : StoreUI<0b10, 1, 0b00, FPR32Op, uimm12s4, "str",
2555 [(store (f32 FPR32Op:$Rt),
2556 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>;
2557 defm STRD : StoreUI<0b11, 1, 0b00, FPR64Op, uimm12s8, "str",
2558 [(store (f64 FPR64Op:$Rt),
2559 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>;
2560 defm STRQ : StoreUI<0b00, 1, 0b10, FPR128Op, uimm12s16, "str", []>;
2562 defm STRHH : StoreUIz<0b01, 0, 0b00, GPR32z, uimm12s2, "strh",
2563 [(truncstorei16 GPR32z:$Rt,
2564 (am_indexed16 GPR64sp:$Rn,
2565 uimm12s2:$offset))]>;
2566 defm STRBB : StoreUIz<0b00, 0, 0b00, GPR32z, uimm12s1, "strb",
2567 [(truncstorei8 GPR32z:$Rt,
2568 (am_indexed8 GPR64sp:$Rn,
2569 uimm12s1:$offset))]>;
2571 let AddedComplexity = 10 in {
2573 // Match all store 64 bits width whose type is compatible with FPR64
2574 def : Pat<(store (v1i64 FPR64:$Rt),
2575 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2576 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2577 def : Pat<(store (v1f64 FPR64:$Rt),
2578 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2579 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2581 let Predicates = [IsLE] in {
2582 // We must use ST1 to store vectors in big-endian.
2583 def : Pat<(store (v2f32 FPR64:$Rt),
2584 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2585 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2586 def : Pat<(store (v8i8 FPR64:$Rt),
2587 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2588 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2589 def : Pat<(store (v4i16 FPR64:$Rt),
2590 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2591 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2592 def : Pat<(store (v2i32 FPR64:$Rt),
2593 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2594 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2595 def : Pat<(store (v4f16 FPR64:$Rt),
2596 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2597 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2600 // Match all store 128 bits width whose type is compatible with FPR128
2601 def : Pat<(store (f128 FPR128:$Rt),
2602 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2603 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2605 let Predicates = [IsLE] in {
2606 // We must use ST1 to store vectors in big-endian.
2607 def : Pat<(store (v4f32 FPR128:$Rt),
2608 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2609 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2610 def : Pat<(store (v2f64 FPR128:$Rt),
2611 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2612 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2613 def : Pat<(store (v16i8 FPR128:$Rt),
2614 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2615 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2616 def : Pat<(store (v8i16 FPR128:$Rt),
2617 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2618 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2619 def : Pat<(store (v4i32 FPR128:$Rt),
2620 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2621 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2622 def : Pat<(store (v2i64 FPR128:$Rt),
2623 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2624 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2625 def : Pat<(store (v8f16 FPR128:$Rt),
2626 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2627 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2631 def : Pat<(truncstorei32 GPR64:$Rt,
2632 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)),
2633 (STRWui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s4:$offset)>;
2634 def : Pat<(truncstorei16 GPR64:$Rt,
2635 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)),
2636 (STRHHui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s2:$offset)>;
2637 def : Pat<(truncstorei8 GPR64:$Rt, (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)),
2638 (STRBBui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s1:$offset)>;
2640 } // AddedComplexity = 10
2642 // Match stores from lane 0 to the appropriate subreg's store.
2643 multiclass VecStoreLane0Pat<Operand UIAddrMode, SDPatternOperator storeop,
2644 ValueType VTy, ValueType STy,
2645 SubRegIndex SubRegIdx, Operand IndexType,
2647 def : Pat<(storeop (STy (vector_extract (VTy VecListOne128:$Vt), 0)),
2648 (UIAddrMode GPR64sp:$Rn, IndexType:$offset)),
2649 (STR (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx),
2650 GPR64sp:$Rn, IndexType:$offset)>;
2653 let AddedComplexity = 19 in {
2654 defm : VecStoreLane0Pat<am_indexed16, truncstorei16, v8i16, i32, hsub, uimm12s2, STRHui>;
2655 defm : VecStoreLane0Pat<am_indexed16, store, v8f16, f16, hsub, uimm12s2, STRHui>;
2656 defm : VecStoreLane0Pat<am_indexed32, store, v4i32, i32, ssub, uimm12s4, STRSui>;
2657 defm : VecStoreLane0Pat<am_indexed32, store, v4f32, f32, ssub, uimm12s4, STRSui>;
2658 defm : VecStoreLane0Pat<am_indexed64, store, v2i64, i64, dsub, uimm12s8, STRDui>;
2659 defm : VecStoreLane0Pat<am_indexed64, store, v2f64, f64, dsub, uimm12s8, STRDui>;
2663 // (unscaled immediate)
2664 defm STURX : StoreUnscaled<0b11, 0, 0b00, GPR64z, "stur",
2666 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
2667 defm STURW : StoreUnscaled<0b10, 0, 0b00, GPR32z, "stur",
2669 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>;
2670 defm STURB : StoreUnscaled<0b00, 1, 0b00, FPR8Op, "stur",
2672 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
2673 defm STURH : StoreUnscaled<0b01, 1, 0b00, FPR16Op, "stur",
2674 [(store (f16 FPR16Op:$Rt),
2675 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>;
2676 defm STURS : StoreUnscaled<0b10, 1, 0b00, FPR32Op, "stur",
2677 [(store (f32 FPR32Op:$Rt),
2678 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>;
2679 defm STURD : StoreUnscaled<0b11, 1, 0b00, FPR64Op, "stur",
2680 [(store (f64 FPR64Op:$Rt),
2681 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
2682 defm STURQ : StoreUnscaled<0b00, 1, 0b10, FPR128Op, "stur",
2683 [(store (f128 FPR128Op:$Rt),
2684 (am_unscaled128 GPR64sp:$Rn, simm9:$offset))]>;
2685 defm STURHH : StoreUnscaled<0b01, 0, 0b00, GPR32z, "sturh",
2686 [(truncstorei16 GPR32z:$Rt,
2687 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>;
2688 defm STURBB : StoreUnscaled<0b00, 0, 0b00, GPR32z, "sturb",
2689 [(truncstorei8 GPR32z:$Rt,
2690 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
2692 // Armv8.4 Weaker Release Consistency enhancements
2693 // LDAPR & STLR with Immediate Offset instructions
2694 let Predicates = [HasRCPC_IMMO] in {
2695 defm STLURB : BaseStoreUnscaleV84<"stlurb", 0b00, 0b00, GPR32>;
2696 defm STLURH : BaseStoreUnscaleV84<"stlurh", 0b01, 0b00, GPR32>;
2697 defm STLURW : BaseStoreUnscaleV84<"stlur", 0b10, 0b00, GPR32>;
2698 defm STLURX : BaseStoreUnscaleV84<"stlur", 0b11, 0b00, GPR64>;
2699 defm LDAPURB : BaseLoadUnscaleV84<"ldapurb", 0b00, 0b01, GPR32>;
2700 defm LDAPURSBW : BaseLoadUnscaleV84<"ldapursb", 0b00, 0b11, GPR32>;
2701 defm LDAPURSBX : BaseLoadUnscaleV84<"ldapursb", 0b00, 0b10, GPR64>;
2702 defm LDAPURH : BaseLoadUnscaleV84<"ldapurh", 0b01, 0b01, GPR32>;
2703 defm LDAPURSHW : BaseLoadUnscaleV84<"ldapursh", 0b01, 0b11, GPR32>;
2704 defm LDAPURSHX : BaseLoadUnscaleV84<"ldapursh", 0b01, 0b10, GPR64>;
2705 defm LDAPUR : BaseLoadUnscaleV84<"ldapur", 0b10, 0b01, GPR32>;
2706 defm LDAPURSW : BaseLoadUnscaleV84<"ldapursw", 0b10, 0b10, GPR64>;
2707 defm LDAPURX : BaseLoadUnscaleV84<"ldapur", 0b11, 0b01, GPR64>;
2710 // Match all store 64 bits width whose type is compatible with FPR64
2711 def : Pat<(store (v1f64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2712 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2713 def : Pat<(store (v1i64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2714 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2716 let AddedComplexity = 10 in {
2718 let Predicates = [IsLE] in {
2719 // We must use ST1 to store vectors in big-endian.
2720 def : Pat<(store (v2f32 FPR64:$Rt),
2721 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2722 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2723 def : Pat<(store (v8i8 FPR64:$Rt),
2724 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2725 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2726 def : Pat<(store (v4i16 FPR64:$Rt),
2727 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2728 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2729 def : Pat<(store (v2i32 FPR64:$Rt),
2730 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2731 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2732 def : Pat<(store (v4f16 FPR64:$Rt),
2733 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2734 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2737 // Match all store 128 bits width whose type is compatible with FPR128
2738 def : Pat<(store (f128 FPR128:$Rt), (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2739 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2741 let Predicates = [IsLE] in {
2742 // We must use ST1 to store vectors in big-endian.
2743 def : Pat<(store (v4f32 FPR128:$Rt),
2744 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2745 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2746 def : Pat<(store (v2f64 FPR128:$Rt),
2747 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2748 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2749 def : Pat<(store (v16i8 FPR128:$Rt),
2750 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2751 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2752 def : Pat<(store (v8i16 FPR128:$Rt),
2753 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2754 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2755 def : Pat<(store (v4i32 FPR128:$Rt),
2756 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2757 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2758 def : Pat<(store (v2i64 FPR128:$Rt),
2759 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2760 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2761 def : Pat<(store (v2f64 FPR128:$Rt),
2762 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2763 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2764 def : Pat<(store (v8f16 FPR128:$Rt),
2765 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2766 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2769 } // AddedComplexity = 10
2771 // unscaled i64 truncating stores
2772 def : Pat<(truncstorei32 GPR64:$Rt, (am_unscaled32 GPR64sp:$Rn, simm9:$offset)),
2773 (STURWi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2774 def : Pat<(truncstorei16 GPR64:$Rt, (am_unscaled16 GPR64sp:$Rn, simm9:$offset)),
2775 (STURHHi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2776 def : Pat<(truncstorei8 GPR64:$Rt, (am_unscaled8 GPR64sp:$Rn, simm9:$offset)),
2777 (STURBBi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2779 // Match stores from lane 0 to the appropriate subreg's store.
2780 multiclass VecStoreULane0Pat<SDPatternOperator StoreOp,
2781 ValueType VTy, ValueType STy,
2782 SubRegIndex SubRegIdx, Instruction STR> {
2783 defm : VecStoreLane0Pat<am_unscaled128, StoreOp, VTy, STy, SubRegIdx, simm9, STR>;
2786 let AddedComplexity = 19 in {
2787 defm : VecStoreULane0Pat<truncstorei16, v8i16, i32, hsub, STURHi>;
2788 defm : VecStoreULane0Pat<store, v8f16, f16, hsub, STURHi>;
2789 defm : VecStoreULane0Pat<store, v4i32, i32, ssub, STURSi>;
2790 defm : VecStoreULane0Pat<store, v4f32, f32, ssub, STURSi>;
2791 defm : VecStoreULane0Pat<store, v2i64, i64, dsub, STURDi>;
2792 defm : VecStoreULane0Pat<store, v2f64, f64, dsub, STURDi>;
2796 // STR mnemonics fall back to STUR for negative or unaligned offsets.
2797 def : InstAlias<"str $Rt, [$Rn, $offset]",
2798 (STURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
2799 def : InstAlias<"str $Rt, [$Rn, $offset]",
2800 (STURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
2801 def : InstAlias<"str $Rt, [$Rn, $offset]",
2802 (STURBi FPR8Op:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2803 def : InstAlias<"str $Rt, [$Rn, $offset]",
2804 (STURHi FPR16Op:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2805 def : InstAlias<"str $Rt, [$Rn, $offset]",
2806 (STURSi FPR32Op:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
2807 def : InstAlias<"str $Rt, [$Rn, $offset]",
2808 (STURDi FPR64Op:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
2809 def : InstAlias<"str $Rt, [$Rn, $offset]",
2810 (STURQi FPR128Op:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;
2812 def : InstAlias<"strb $Rt, [$Rn, $offset]",
2813 (STURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2814 def : InstAlias<"strh $Rt, [$Rn, $offset]",
2815 (STURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2818 // (unscaled immediate, unprivileged)
2819 defm STTRW : StoreUnprivileged<0b10, 0, 0b00, GPR32, "sttr">;
2820 defm STTRX : StoreUnprivileged<0b11, 0, 0b00, GPR64, "sttr">;
2822 defm STTRH : StoreUnprivileged<0b01, 0, 0b00, GPR32, "sttrh">;
2823 defm STTRB : StoreUnprivileged<0b00, 0, 0b00, GPR32, "sttrb">;
2826 // (immediate pre-indexed)
2827 def STRWpre : StorePreIdx<0b10, 0, 0b00, GPR32z, "str", pre_store, i32>;
2828 def STRXpre : StorePreIdx<0b11, 0, 0b00, GPR64z, "str", pre_store, i64>;
2829 def STRBpre : StorePreIdx<0b00, 1, 0b00, FPR8Op, "str", pre_store, untyped>;
2830 def STRHpre : StorePreIdx<0b01, 1, 0b00, FPR16Op, "str", pre_store, f16>;
2831 def STRSpre : StorePreIdx<0b10, 1, 0b00, FPR32Op, "str", pre_store, f32>;
2832 def STRDpre : StorePreIdx<0b11, 1, 0b00, FPR64Op, "str", pre_store, f64>;
2833 def STRQpre : StorePreIdx<0b00, 1, 0b10, FPR128Op, "str", pre_store, f128>;
2835 def STRBBpre : StorePreIdx<0b00, 0, 0b00, GPR32z, "strb", pre_truncsti8, i32>;
2836 def STRHHpre : StorePreIdx<0b01, 0, 0b00, GPR32z, "strh", pre_truncsti16, i32>;
2839 def : Pat<(pre_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2840 (STRWpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2842 def : Pat<(pre_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2843 (STRHHpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2845 def : Pat<(pre_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2846 (STRBBpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2849 def : Pat<(pre_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2850 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2851 def : Pat<(pre_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2852 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2853 def : Pat<(pre_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2854 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2855 def : Pat<(pre_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2856 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2857 def : Pat<(pre_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2858 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2859 def : Pat<(pre_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2860 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2861 def : Pat<(pre_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2862 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2864 def : Pat<(pre_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2865 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2866 def : Pat<(pre_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2867 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2868 def : Pat<(pre_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2869 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2870 def : Pat<(pre_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2871 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2872 def : Pat<(pre_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2873 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2874 def : Pat<(pre_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2875 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2876 def : Pat<(pre_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2877 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2880 // (immediate post-indexed)
2881 def STRWpost : StorePostIdx<0b10, 0, 0b00, GPR32z, "str", post_store, i32>;
2882 def STRXpost : StorePostIdx<0b11, 0, 0b00, GPR64z, "str", post_store, i64>;
2883 def STRBpost : StorePostIdx<0b00, 1, 0b00, FPR8Op, "str", post_store, untyped>;
2884 def STRHpost : StorePostIdx<0b01, 1, 0b00, FPR16Op, "str", post_store, f16>;
2885 def STRSpost : StorePostIdx<0b10, 1, 0b00, FPR32Op, "str", post_store, f32>;
2886 def STRDpost : StorePostIdx<0b11, 1, 0b00, FPR64Op, "str", post_store, f64>;
2887 def STRQpost : StorePostIdx<0b00, 1, 0b10, FPR128Op, "str", post_store, f128>;
2889 def STRBBpost : StorePostIdx<0b00, 0, 0b00, GPR32z, "strb", post_truncsti8, i32>;
2890 def STRHHpost : StorePostIdx<0b01, 0, 0b00, GPR32z, "strh", post_truncsti16, i32>;
2893 def : Pat<(post_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2894 (STRWpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2896 def : Pat<(post_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2897 (STRHHpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2899 def : Pat<(post_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2900 (STRBBpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2903 def : Pat<(post_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2904 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2905 def : Pat<(post_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2906 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2907 def : Pat<(post_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2908 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2909 def : Pat<(post_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2910 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2911 def : Pat<(post_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2912 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2913 def : Pat<(post_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2914 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2915 def : Pat<(post_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2916 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2918 def : Pat<(post_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2919 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2920 def : Pat<(post_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2921 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2922 def : Pat<(post_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2923 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2924 def : Pat<(post_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2925 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2926 def : Pat<(post_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2927 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2928 def : Pat<(post_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2929 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2930 def : Pat<(post_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2931 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2933 //===----------------------------------------------------------------------===//
2934 // Load/store exclusive instructions.
2935 //===----------------------------------------------------------------------===//
2937 def LDARW : LoadAcquire <0b10, 1, 1, 0, 1, GPR32, "ldar">;
2938 def LDARX : LoadAcquire <0b11, 1, 1, 0, 1, GPR64, "ldar">;
2939 def LDARB : LoadAcquire <0b00, 1, 1, 0, 1, GPR32, "ldarb">;
2940 def LDARH : LoadAcquire <0b01, 1, 1, 0, 1, GPR32, "ldarh">;
2942 def LDAXRW : LoadExclusive <0b10, 0, 1, 0, 1, GPR32, "ldaxr">;
2943 def LDAXRX : LoadExclusive <0b11, 0, 1, 0, 1, GPR64, "ldaxr">;
2944 def LDAXRB : LoadExclusive <0b00, 0, 1, 0, 1, GPR32, "ldaxrb">;
2945 def LDAXRH : LoadExclusive <0b01, 0, 1, 0, 1, GPR32, "ldaxrh">;
2947 def LDXRW : LoadExclusive <0b10, 0, 1, 0, 0, GPR32, "ldxr">;
2948 def LDXRX : LoadExclusive <0b11, 0, 1, 0, 0, GPR64, "ldxr">;
2949 def LDXRB : LoadExclusive <0b00, 0, 1, 0, 0, GPR32, "ldxrb">;
2950 def LDXRH : LoadExclusive <0b01, 0, 1, 0, 0, GPR32, "ldxrh">;
2952 def STLRW : StoreRelease <0b10, 1, 0, 0, 1, GPR32, "stlr">;
2953 def STLRX : StoreRelease <0b11, 1, 0, 0, 1, GPR64, "stlr">;
2954 def STLRB : StoreRelease <0b00, 1, 0, 0, 1, GPR32, "stlrb">;
2955 def STLRH : StoreRelease <0b01, 1, 0, 0, 1, GPR32, "stlrh">;
2957 def STLXRW : StoreExclusive<0b10, 0, 0, 0, 1, GPR32, "stlxr">;
2958 def STLXRX : StoreExclusive<0b11, 0, 0, 0, 1, GPR64, "stlxr">;
2959 def STLXRB : StoreExclusive<0b00, 0, 0, 0, 1, GPR32, "stlxrb">;
2960 def STLXRH : StoreExclusive<0b01, 0, 0, 0, 1, GPR32, "stlxrh">;
2962 def STXRW : StoreExclusive<0b10, 0, 0, 0, 0, GPR32, "stxr">;
2963 def STXRX : StoreExclusive<0b11, 0, 0, 0, 0, GPR64, "stxr">;
2964 def STXRB : StoreExclusive<0b00, 0, 0, 0, 0, GPR32, "stxrb">;
2965 def STXRH : StoreExclusive<0b01, 0, 0, 0, 0, GPR32, "stxrh">;
2967 def LDAXPW : LoadExclusivePair<0b10, 0, 1, 1, 1, GPR32, "ldaxp">;
2968 def LDAXPX : LoadExclusivePair<0b11, 0, 1, 1, 1, GPR64, "ldaxp">;
2970 def LDXPW : LoadExclusivePair<0b10, 0, 1, 1, 0, GPR32, "ldxp">;
2971 def LDXPX : LoadExclusivePair<0b11, 0, 1, 1, 0, GPR64, "ldxp">;
2973 def STLXPW : StoreExclusivePair<0b10, 0, 0, 1, 1, GPR32, "stlxp">;
2974 def STLXPX : StoreExclusivePair<0b11, 0, 0, 1, 1, GPR64, "stlxp">;
2976 def STXPW : StoreExclusivePair<0b10, 0, 0, 1, 0, GPR32, "stxp">;
2977 def STXPX : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">;
2979 let Predicates = [HasLOR] in {
2980 // v8.1a "Limited Order Region" extension load-acquire instructions
2981 def LDLARW : LoadAcquire <0b10, 1, 1, 0, 0, GPR32, "ldlar">;
2982 def LDLARX : LoadAcquire <0b11, 1, 1, 0, 0, GPR64, "ldlar">;
2983 def LDLARB : LoadAcquire <0b00, 1, 1, 0, 0, GPR32, "ldlarb">;
2984 def LDLARH : LoadAcquire <0b01, 1, 1, 0, 0, GPR32, "ldlarh">;
2986 // v8.1a "Limited Order Region" extension store-release instructions
2987 def STLLRW : StoreRelease <0b10, 1, 0, 0, 0, GPR32, "stllr">;
2988 def STLLRX : StoreRelease <0b11, 1, 0, 0, 0, GPR64, "stllr">;
2989 def STLLRB : StoreRelease <0b00, 1, 0, 0, 0, GPR32, "stllrb">;
2990 def STLLRH : StoreRelease <0b01, 1, 0, 0, 0, GPR32, "stllrh">;
2993 //===----------------------------------------------------------------------===//
2994 // Scaled floating point to integer conversion instructions.
2995 //===----------------------------------------------------------------------===//
2997 defm FCVTAS : FPToIntegerUnscaled<0b00, 0b100, "fcvtas", int_aarch64_neon_fcvtas>;
2998 defm FCVTAU : FPToIntegerUnscaled<0b00, 0b101, "fcvtau", int_aarch64_neon_fcvtau>;
2999 defm FCVTMS : FPToIntegerUnscaled<0b10, 0b000, "fcvtms", int_aarch64_neon_fcvtms>;
3000 defm FCVTMU : FPToIntegerUnscaled<0b10, 0b001, "fcvtmu", int_aarch64_neon_fcvtmu>;
3001 defm FCVTNS : FPToIntegerUnscaled<0b00, 0b000, "fcvtns", int_aarch64_neon_fcvtns>;
3002 defm FCVTNU : FPToIntegerUnscaled<0b00, 0b001, "fcvtnu", int_aarch64_neon_fcvtnu>;
3003 defm FCVTPS : FPToIntegerUnscaled<0b01, 0b000, "fcvtps", int_aarch64_neon_fcvtps>;
3004 defm FCVTPU : FPToIntegerUnscaled<0b01, 0b001, "fcvtpu", int_aarch64_neon_fcvtpu>;
3005 defm FCVTZS : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
3006 defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
3007 defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
3008 defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
3010 multiclass FPToIntegerIntPats<Intrinsic round, string INST> {
3011 def : Pat<(i32 (round f16:$Rn)), (!cast<Instruction>(INST # UWHr) $Rn)>;
3012 def : Pat<(i64 (round f16:$Rn)), (!cast<Instruction>(INST # UXHr) $Rn)>;
3013 def : Pat<(i32 (round f32:$Rn)), (!cast<Instruction>(INST # UWSr) $Rn)>;
3014 def : Pat<(i64 (round f32:$Rn)), (!cast<Instruction>(INST # UXSr) $Rn)>;
3015 def : Pat<(i32 (round f64:$Rn)), (!cast<Instruction>(INST # UWDr) $Rn)>;
3016 def : Pat<(i64 (round f64:$Rn)), (!cast<Instruction>(INST # UXDr) $Rn)>;
3018 def : Pat<(i32 (round (fmul f16:$Rn, fixedpoint_f16_i32:$scale))),
3019 (!cast<Instruction>(INST # SWHri) $Rn, $scale)>;
3020 def : Pat<(i64 (round (fmul f16:$Rn, fixedpoint_f16_i64:$scale))),
3021 (!cast<Instruction>(INST # SXHri) $Rn, $scale)>;
3022 def : Pat<(i32 (round (fmul f32:$Rn, fixedpoint_f32_i32:$scale))),
3023 (!cast<Instruction>(INST # SWSri) $Rn, $scale)>;
3024 def : Pat<(i64 (round (fmul f32:$Rn, fixedpoint_f32_i64:$scale))),
3025 (!cast<Instruction>(INST # SXSri) $Rn, $scale)>;
3026 def : Pat<(i32 (round (fmul f64:$Rn, fixedpoint_f64_i32:$scale))),
3027 (!cast<Instruction>(INST # SWDri) $Rn, $scale)>;
3028 def : Pat<(i64 (round (fmul f64:$Rn, fixedpoint_f64_i64:$scale))),
3029 (!cast<Instruction>(INST # SXDri) $Rn, $scale)>;
3032 defm : FPToIntegerIntPats<int_aarch64_neon_fcvtzs, "FCVTZS">;
3033 defm : FPToIntegerIntPats<int_aarch64_neon_fcvtzu, "FCVTZU">;
3035 multiclass FPToIntegerPats<SDNode to_int, SDNode round, string INST> {
3036 def : Pat<(i32 (to_int (round f32:$Rn))),
3037 (!cast<Instruction>(INST # UWSr) f32:$Rn)>;
3038 def : Pat<(i64 (to_int (round f32:$Rn))),
3039 (!cast<Instruction>(INST # UXSr) f32:$Rn)>;
3040 def : Pat<(i32 (to_int (round f64:$Rn))),
3041 (!cast<Instruction>(INST # UWDr) f64:$Rn)>;
3042 def : Pat<(i64 (to_int (round f64:$Rn))),
3043 (!cast<Instruction>(INST # UXDr) f64:$Rn)>;
3046 defm : FPToIntegerPats<fp_to_sint, fceil, "FCVTPS">;
3047 defm : FPToIntegerPats<fp_to_uint, fceil, "FCVTPU">;
3048 defm : FPToIntegerPats<fp_to_sint, ffloor, "FCVTMS">;
3049 defm : FPToIntegerPats<fp_to_uint, ffloor, "FCVTMU">;
3050 defm : FPToIntegerPats<fp_to_sint, ftrunc, "FCVTZS">;
3051 defm : FPToIntegerPats<fp_to_uint, ftrunc, "FCVTZU">;
3052 defm : FPToIntegerPats<fp_to_sint, fround, "FCVTAS">;
3053 defm : FPToIntegerPats<fp_to_uint, fround, "FCVTAU">;
3055 //===----------------------------------------------------------------------===//
3056 // Scaled integer to floating point conversion instructions.
3057 //===----------------------------------------------------------------------===//
3059 defm SCVTF : IntegerToFP<0, "scvtf", sint_to_fp>;
3060 defm UCVTF : IntegerToFP<1, "ucvtf", uint_to_fp>;
3062 //===----------------------------------------------------------------------===//
3063 // Unscaled integer to floating point conversion instruction.
3064 //===----------------------------------------------------------------------===//
3066 defm FMOV : UnscaledConversion<"fmov">;
3068 // Add pseudo ops for FMOV 0 so we can mark them as isReMaterializable
3069 let isReMaterializable = 1, isCodeGenOnly = 1, isAsCheapAsAMove = 1 in {
3070 def FMOVH0 : Pseudo<(outs FPR16:$Rd), (ins), [(set f16:$Rd, (fpimm0))]>,
3071 Sched<[WriteF]>, Requires<[HasFullFP16]>;
3072 def FMOVS0 : Pseudo<(outs FPR32:$Rd), (ins), [(set f32:$Rd, (fpimm0))]>,
3074 def FMOVD0 : Pseudo<(outs FPR64:$Rd), (ins), [(set f64:$Rd, (fpimm0))]>,
3077 // Similarly add aliases
3078 def : InstAlias<"fmov $Rd, #0.0", (FMOVWHr FPR16:$Rd, WZR), 0>,
3079 Requires<[HasFullFP16]>;
3080 def : InstAlias<"fmov $Rd, #0.0", (FMOVWSr FPR32:$Rd, WZR), 0>;
3081 def : InstAlias<"fmov $Rd, #0.0", (FMOVXDr FPR64:$Rd, XZR), 0>;
3083 //===----------------------------------------------------------------------===//
3084 // Floating point conversion instruction.
3085 //===----------------------------------------------------------------------===//
3087 defm FCVT : FPConversion<"fcvt">;
3089 //===----------------------------------------------------------------------===//
3090 // Floating point single operand instructions.
3091 //===----------------------------------------------------------------------===//
3093 defm FABS : SingleOperandFPData<0b0001, "fabs", fabs>;
3094 defm FMOV : SingleOperandFPData<0b0000, "fmov">;
3095 defm FNEG : SingleOperandFPData<0b0010, "fneg", fneg>;
3096 defm FRINTA : SingleOperandFPData<0b1100, "frinta", fround>;
3097 defm FRINTI : SingleOperandFPData<0b1111, "frinti", fnearbyint>;
3098 defm FRINTM : SingleOperandFPData<0b1010, "frintm", ffloor>;
3099 defm FRINTN : SingleOperandFPData<0b1000, "frintn", int_aarch64_neon_frintn>;
3100 defm FRINTP : SingleOperandFPData<0b1001, "frintp", fceil>;
3102 def : Pat<(v1f64 (int_aarch64_neon_frintn (v1f64 FPR64:$Rn))),
3103 (FRINTNDr FPR64:$Rn)>;
3105 defm FRINTX : SingleOperandFPData<0b1110, "frintx", frint>;
3106 defm FRINTZ : SingleOperandFPData<0b1011, "frintz", ftrunc>;
3108 let SchedRW = [WriteFDiv] in {
3109 defm FSQRT : SingleOperandFPData<0b0011, "fsqrt", fsqrt>;
3112 let Predicates = [HasFRInt3264] in {
3113 defm FRINT32Z : FRIntNNT<0b00, "frint32z">;
3114 defm FRINT64Z : FRIntNNT<0b10, "frint64z">;
3115 defm FRINT32X : FRIntNNT<0b01, "frint32x">;
3116 defm FRINT64X : FRIntNNT<0b11, "frint64x">;
3119 //===----------------------------------------------------------------------===//
3120 // Floating point two operand instructions.
3121 //===----------------------------------------------------------------------===//
3123 defm FADD : TwoOperandFPData<0b0010, "fadd", fadd>;
3124 let SchedRW = [WriteFDiv] in {
3125 defm FDIV : TwoOperandFPData<0b0001, "fdiv", fdiv>;
3127 defm FMAXNM : TwoOperandFPData<0b0110, "fmaxnm", fmaxnum>;
3128 defm FMAX : TwoOperandFPData<0b0100, "fmax", fmaximum>;
3129 defm FMINNM : TwoOperandFPData<0b0111, "fminnm", fminnum>;
3130 defm FMIN : TwoOperandFPData<0b0101, "fmin", fminimum>;
3131 let SchedRW = [WriteFMul] in {
3132 defm FMUL : TwoOperandFPData<0b0000, "fmul", fmul>;
3133 defm FNMUL : TwoOperandFPDataNeg<0b1000, "fnmul", fmul>;
3135 defm FSUB : TwoOperandFPData<0b0011, "fsub", fsub>;
3137 def : Pat<(v1f64 (fmaximum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
3138 (FMAXDrr FPR64:$Rn, FPR64:$Rm)>;
3139 def : Pat<(v1f64 (fminimum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
3140 (FMINDrr FPR64:$Rn, FPR64:$Rm)>;
3141 def : Pat<(v1f64 (fmaxnum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
3142 (FMAXNMDrr FPR64:$Rn, FPR64:$Rm)>;
3143 def : Pat<(v1f64 (fminnum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
3144 (FMINNMDrr FPR64:$Rn, FPR64:$Rm)>;
3146 //===----------------------------------------------------------------------===//
3147 // Floating point three operand instructions.
3148 //===----------------------------------------------------------------------===//
3150 defm FMADD : ThreeOperandFPData<0, 0, "fmadd", fma>;
3151 defm FMSUB : ThreeOperandFPData<0, 1, "fmsub",
3152 TriOpFrag<(fma node:$LHS, (fneg node:$MHS), node:$RHS)> >;
3153 defm FNMADD : ThreeOperandFPData<1, 0, "fnmadd",
3154 TriOpFrag<(fneg (fma node:$LHS, node:$MHS, node:$RHS))> >;
3155 defm FNMSUB : ThreeOperandFPData<1, 1, "fnmsub",
3156 TriOpFrag<(fma node:$LHS, node:$MHS, (fneg node:$RHS))> >;
3158 // The following def pats catch the case where the LHS of an FMA is negated.
3159 // The TriOpFrag above catches the case where the middle operand is negated.
3161 // N.b. FMSUB etc have the accumulator at the *end* of (outs), unlike
3162 // the NEON variant.
3163 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, FPR32:$Ra)),
3164 (FMSUBSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
3166 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, FPR64:$Ra)),
3167 (FMSUBDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
3169 // We handled -(a + b*c) for FNMADD above, now it's time for "(-a) + (-b)*c" and
3171 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, (fneg FPR32:$Ra))),
3172 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
3174 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, (fneg FPR64:$Ra))),
3175 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
3177 def : Pat<(f32 (fma FPR32:$Rn, (fneg FPR32:$Rm), (fneg FPR32:$Ra))),
3178 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
3180 def : Pat<(f64 (fma FPR64:$Rn, (fneg FPR64:$Rm), (fneg FPR64:$Ra))),
3181 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
3183 //===----------------------------------------------------------------------===//
3184 // Floating point comparison instructions.
3185 //===----------------------------------------------------------------------===//
3187 defm FCMPE : FPComparison<1, "fcmpe">;
3188 defm FCMP : FPComparison<0, "fcmp", AArch64fcmp>;
3190 //===----------------------------------------------------------------------===//
3191 // Floating point conditional comparison instructions.
3192 //===----------------------------------------------------------------------===//
3194 defm FCCMPE : FPCondComparison<1, "fccmpe">;
3195 defm FCCMP : FPCondComparison<0, "fccmp", AArch64fccmp>;
3197 //===----------------------------------------------------------------------===//
3198 // Floating point conditional select instruction.
3199 //===----------------------------------------------------------------------===//
3201 defm FCSEL : FPCondSelect<"fcsel">;
3203 // CSEL instructions providing f128 types need to be handled by a
3204 // pseudo-instruction since the eventual code will need to introduce basic
3205 // blocks and control flow.
3206 def F128CSEL : Pseudo<(outs FPR128:$Rd),
3207 (ins FPR128:$Rn, FPR128:$Rm, ccode:$cond),
3208 [(set (f128 FPR128:$Rd),
3209 (AArch64csel FPR128:$Rn, FPR128:$Rm,
3210 (i32 imm:$cond), NZCV))]> {
3212 let usesCustomInserter = 1;
3213 let hasNoSchedulingInfo = 1;
3216 //===----------------------------------------------------------------------===//
3217 // Instructions used for emitting unwind opcodes on ARM64 Windows.
3218 //===----------------------------------------------------------------------===//
3219 let isPseudo = 1 in {
3220 def SEH_StackAlloc : Pseudo<(outs), (ins i32imm:$size), []>, Sched<[]>;
3221 def SEH_SaveFPLR : Pseudo<(outs), (ins i32imm:$offs), []>, Sched<[]>;
3222 def SEH_SaveFPLR_X : Pseudo<(outs), (ins i32imm:$offs), []>, Sched<[]>;
3223 def SEH_SaveReg : Pseudo<(outs), (ins i32imm:$reg, i32imm:$offs), []>, Sched<[]>;
3224 def SEH_SaveReg_X : Pseudo<(outs), (ins i32imm:$reg, i32imm:$offs), []>, Sched<[]>;
3225 def SEH_SaveRegP : Pseudo<(outs), (ins i32imm:$reg0, i32imm:$reg1, i32imm:$offs), []>, Sched<[]>;
3226 def SEH_SaveRegP_X : Pseudo<(outs), (ins i32imm:$reg0, i32imm:$reg1, i32imm:$offs), []>, Sched<[]>;
3227 def SEH_SaveFReg : Pseudo<(outs), (ins i32imm:$reg, i32imm:$offs), []>, Sched<[]>;
3228 def SEH_SaveFReg_X : Pseudo<(outs), (ins i32imm:$reg, i32imm:$offs), []>, Sched<[]>;
3229 def SEH_SaveFRegP : Pseudo<(outs), (ins i32imm:$reg0, i32imm:$reg1, i32imm:$offs), []>, Sched<[]>;
3230 def SEH_SaveFRegP_X : Pseudo<(outs), (ins i32imm:$reg0, i32imm:$reg1, i32imm:$offs), []>, Sched<[]>;
3231 def SEH_SetFP : Pseudo<(outs), (ins), []>, Sched<[]>;
3232 def SEH_AddFP : Pseudo<(outs), (ins i32imm:$offs), []>, Sched<[]>;
3233 def SEH_Nop : Pseudo<(outs), (ins), []>, Sched<[]>;
3234 def SEH_PrologEnd : Pseudo<(outs), (ins), []>, Sched<[]>;
3235 def SEH_EpilogStart : Pseudo<(outs), (ins), []>, Sched<[]>;
3236 def SEH_EpilogEnd : Pseudo<(outs), (ins), []>, Sched<[]>;
3239 // Pseudo instructions for Windows EH
3240 //===----------------------------------------------------------------------===//
3241 let isTerminator = 1, hasSideEffects = 1, isBarrier = 1, hasCtrlDep = 1,
3242 isCodeGenOnly = 1, isReturn = 1, isEHScopeReturn = 1, isPseudo = 1 in {
3243 def CLEANUPRET : Pseudo<(outs), (ins), [(cleanupret)]>, Sched<[]>;
3244 let usesCustomInserter = 1 in
3245 def CATCHRET : Pseudo<(outs), (ins am_brcond:$dst, am_brcond:$src), [(catchret bb:$dst, bb:$src)]>,
3249 let hasSideEffects = 1, hasCtrlDep = 1, isCodeGenOnly = 1,
3250 usesCustomInserter = 1 in
3251 def CATCHPAD : Pseudo<(outs), (ins), [(catchpad)]>, Sched<[]>;
3253 //===----------------------------------------------------------------------===//
3254 // Floating point immediate move.
3255 //===----------------------------------------------------------------------===//
3257 let isReMaterializable = 1 in {
3258 defm FMOV : FPMoveImmediate<"fmov">;
3261 //===----------------------------------------------------------------------===//
3262 // Advanced SIMD two vector instructions.
3263 //===----------------------------------------------------------------------===//
3265 defm UABDL : SIMDLongThreeVectorBHSabdl<1, 0b0111, "uabdl",
3266 int_aarch64_neon_uabd>;
3267 // Match UABDL in log2-shuffle patterns.
3268 def : Pat<(abs (v8i16 (sub (zext (v8i8 V64:$opA)),
3269 (zext (v8i8 V64:$opB))))),
3270 (UABDLv8i8_v8i16 V64:$opA, V64:$opB)>;
3271 def : Pat<(xor (v8i16 (AArch64vashr v8i16:$src, (i32 15))),
3272 (v8i16 (add (sub (zext (v8i8 V64:$opA)),
3273 (zext (v8i8 V64:$opB))),
3274 (AArch64vashr v8i16:$src, (i32 15))))),
3275 (UABDLv8i8_v8i16 V64:$opA, V64:$opB)>;
3276 def : Pat<(abs (v8i16 (sub (zext (extract_high_v16i8 V128:$opA)),
3277 (zext (extract_high_v16i8 V128:$opB))))),
3278 (UABDLv16i8_v8i16 V128:$opA, V128:$opB)>;
3279 def : Pat<(xor (v8i16 (AArch64vashr v8i16:$src, (i32 15))),
3280 (v8i16 (add (sub (zext (extract_high_v16i8 V128:$opA)),
3281 (zext (extract_high_v16i8 V128:$opB))),
3282 (AArch64vashr v8i16:$src, (i32 15))))),
3283 (UABDLv16i8_v8i16 V128:$opA, V128:$opB)>;
3284 def : Pat<(abs (v4i32 (sub (zext (v4i16 V64:$opA)),
3285 (zext (v4i16 V64:$opB))))),
3286 (UABDLv4i16_v4i32 V64:$opA, V64:$opB)>;
3287 def : Pat<(abs (v4i32 (sub (zext (extract_high_v8i16 V128:$opA)),
3288 (zext (extract_high_v8i16 V128:$opB))))),
3289 (UABDLv8i16_v4i32 V128:$opA, V128:$opB)>;
3290 def : Pat<(abs (v2i64 (sub (zext (v2i32 V64:$opA)),
3291 (zext (v2i32 V64:$opB))))),
3292 (UABDLv2i32_v2i64 V64:$opA, V64:$opB)>;
3293 def : Pat<(abs (v2i64 (sub (zext (extract_high_v4i32 V128:$opA)),
3294 (zext (extract_high_v4i32 V128:$opB))))),
3295 (UABDLv4i32_v2i64 V128:$opA, V128:$opB)>;
3297 defm ABS : SIMDTwoVectorBHSD<0, 0b01011, "abs", abs>;
3298 defm CLS : SIMDTwoVectorBHS<0, 0b00100, "cls", int_aarch64_neon_cls>;
3299 defm CLZ : SIMDTwoVectorBHS<1, 0b00100, "clz", ctlz>;
3300 defm CMEQ : SIMDCmpTwoVector<0, 0b01001, "cmeq", AArch64cmeqz>;
3301 defm CMGE : SIMDCmpTwoVector<1, 0b01000, "cmge", AArch64cmgez>;
3302 defm CMGT : SIMDCmpTwoVector<0, 0b01000, "cmgt", AArch64cmgtz>;
3303 defm CMLE : SIMDCmpTwoVector<1, 0b01001, "cmle", AArch64cmlez>;
3304 defm CMLT : SIMDCmpTwoVector<0, 0b01010, "cmlt", AArch64cmltz>;
3305 defm CNT : SIMDTwoVectorB<0, 0b00, 0b00101, "cnt", ctpop>;
3306 defm FABS : SIMDTwoVectorFP<0, 1, 0b01111, "fabs", fabs>;
3308 defm FCMEQ : SIMDFPCmpTwoVector<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>;
3309 defm FCMGE : SIMDFPCmpTwoVector<1, 1, 0b01100, "fcmge", AArch64fcmgez>;
3310 defm FCMGT : SIMDFPCmpTwoVector<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>;
3311 defm FCMLE : SIMDFPCmpTwoVector<1, 1, 0b01101, "fcmle", AArch64fcmlez>;
3312 defm FCMLT : SIMDFPCmpTwoVector<0, 1, 0b01110, "fcmlt", AArch64fcmltz>;
3313 defm FCVTAS : SIMDTwoVectorFPToInt<0,0,0b11100, "fcvtas",int_aarch64_neon_fcvtas>;
3314 defm FCVTAU : SIMDTwoVectorFPToInt<1,0,0b11100, "fcvtau",int_aarch64_neon_fcvtau>;
3315 defm FCVTL : SIMDFPWidenTwoVector<0, 0, 0b10111, "fcvtl">;
3316 def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (v4i16 V64:$Rn))),
3317 (FCVTLv4i16 V64:$Rn)>;
3318 def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (extract_subvector (v8i16 V128:$Rn),
3320 (FCVTLv8i16 V128:$Rn)>;
3321 def : Pat<(v2f64 (fpextend (v2f32 V64:$Rn))), (FCVTLv2i32 V64:$Rn)>;
3322 def : Pat<(v2f64 (fpextend (v2f32 (extract_subvector (v4f32 V128:$Rn),
3324 (FCVTLv4i32 V128:$Rn)>;
3326 def : Pat<(v4f32 (fpextend (v4f16 V64:$Rn))), (FCVTLv4i16 V64:$Rn)>;
3327 def : Pat<(v4f32 (fpextend (v4f16 (extract_subvector (v8f16 V128:$Rn),
3329 (FCVTLv8i16 V128:$Rn)>;
3331 defm FCVTMS : SIMDTwoVectorFPToInt<0,0,0b11011, "fcvtms",int_aarch64_neon_fcvtms>;
3332 defm FCVTMU : SIMDTwoVectorFPToInt<1,0,0b11011, "fcvtmu",int_aarch64_neon_fcvtmu>;
3333 defm FCVTNS : SIMDTwoVectorFPToInt<0,0,0b11010, "fcvtns",int_aarch64_neon_fcvtns>;
3334 defm FCVTNU : SIMDTwoVectorFPToInt<1,0,0b11010, "fcvtnu",int_aarch64_neon_fcvtnu>;
3335 defm FCVTN : SIMDFPNarrowTwoVector<0, 0, 0b10110, "fcvtn">;
3336 def : Pat<(v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn))),
3337 (FCVTNv4i16 V128:$Rn)>;
3338 def : Pat<(concat_vectors V64:$Rd,
3339 (v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn)))),
3340 (FCVTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
3341 def : Pat<(v2f32 (fpround (v2f64 V128:$Rn))), (FCVTNv2i32 V128:$Rn)>;
3342 def : Pat<(v4f16 (fpround (v4f32 V128:$Rn))), (FCVTNv4i16 V128:$Rn)>;
3343 def : Pat<(concat_vectors V64:$Rd, (v2f32 (fpround (v2f64 V128:$Rn)))),
3344 (FCVTNv4i32 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
3345 defm FCVTPS : SIMDTwoVectorFPToInt<0,1,0b11010, "fcvtps",int_aarch64_neon_fcvtps>;
3346 defm FCVTPU : SIMDTwoVectorFPToInt<1,1,0b11010, "fcvtpu",int_aarch64_neon_fcvtpu>;
3347 defm FCVTXN : SIMDFPInexactCvtTwoVector<1, 0, 0b10110, "fcvtxn",
3348 int_aarch64_neon_fcvtxn>;
3349 defm FCVTZS : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs", fp_to_sint>;
3350 defm FCVTZU : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu", fp_to_uint>;
3352 def : Pat<(v4i16 (int_aarch64_neon_fcvtzs v4f16:$Rn)), (FCVTZSv4f16 $Rn)>;
3353 def : Pat<(v8i16 (int_aarch64_neon_fcvtzs v8f16:$Rn)), (FCVTZSv8f16 $Rn)>;
3354 def : Pat<(v2i32 (int_aarch64_neon_fcvtzs v2f32:$Rn)), (FCVTZSv2f32 $Rn)>;
3355 def : Pat<(v4i32 (int_aarch64_neon_fcvtzs v4f32:$Rn)), (FCVTZSv4f32 $Rn)>;
3356 def : Pat<(v2i64 (int_aarch64_neon_fcvtzs v2f64:$Rn)), (FCVTZSv2f64 $Rn)>;
3358 def : Pat<(v4i16 (int_aarch64_neon_fcvtzu v4f16:$Rn)), (FCVTZUv4f16 $Rn)>;
3359 def : Pat<(v8i16 (int_aarch64_neon_fcvtzu v8f16:$Rn)), (FCVTZUv8f16 $Rn)>;
3360 def : Pat<(v2i32 (int_aarch64_neon_fcvtzu v2f32:$Rn)), (FCVTZUv2f32 $Rn)>;
3361 def : Pat<(v4i32 (int_aarch64_neon_fcvtzu v4f32:$Rn)), (FCVTZUv4f32 $Rn)>;
3362 def : Pat<(v2i64 (int_aarch64_neon_fcvtzu v2f64:$Rn)), (FCVTZUv2f64 $Rn)>;
3364 defm FNEG : SIMDTwoVectorFP<1, 1, 0b01111, "fneg", fneg>;
3365 defm FRECPE : SIMDTwoVectorFP<0, 1, 0b11101, "frecpe", int_aarch64_neon_frecpe>;
3366 defm FRINTA : SIMDTwoVectorFP<1, 0, 0b11000, "frinta", fround>;
3367 defm FRINTI : SIMDTwoVectorFP<1, 1, 0b11001, "frinti", fnearbyint>;
3368 defm FRINTM : SIMDTwoVectorFP<0, 0, 0b11001, "frintm", ffloor>;
3369 defm FRINTN : SIMDTwoVectorFP<0, 0, 0b11000, "frintn", int_aarch64_neon_frintn>;
3370 defm FRINTP : SIMDTwoVectorFP<0, 1, 0b11000, "frintp", fceil>;
3371 defm FRINTX : SIMDTwoVectorFP<1, 0, 0b11001, "frintx", frint>;
3372 defm FRINTZ : SIMDTwoVectorFP<0, 1, 0b11001, "frintz", ftrunc>;
3374 let Predicates = [HasFRInt3264] in {
3375 defm FRINT32Z : FRIntNNTVector<0, 0, "frint32z">;
3376 defm FRINT64Z : FRIntNNTVector<0, 1, "frint64z">;
3377 defm FRINT32X : FRIntNNTVector<1, 0, "frint32x">;
3378 defm FRINT64X : FRIntNNTVector<1, 1, "frint64x">;
3381 defm FRSQRTE: SIMDTwoVectorFP<1, 1, 0b11101, "frsqrte", int_aarch64_neon_frsqrte>;
3382 defm FSQRT : SIMDTwoVectorFP<1, 1, 0b11111, "fsqrt", fsqrt>;
3383 defm NEG : SIMDTwoVectorBHSD<1, 0b01011, "neg",
3384 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
3385 defm NOT : SIMDTwoVectorB<1, 0b00, 0b00101, "not", vnot>;
3386 // Aliases for MVN -> NOT.
3387 def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}",
3388 (NOTv8i8 V64:$Vd, V64:$Vn)>;
3389 def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}",
3390 (NOTv16i8 V128:$Vd, V128:$Vn)>;
3392 def : Pat<(AArch64neg (v8i8 V64:$Rn)), (NEGv8i8 V64:$Rn)>;
3393 def : Pat<(AArch64neg (v16i8 V128:$Rn)), (NEGv16i8 V128:$Rn)>;
3394 def : Pat<(AArch64neg (v4i16 V64:$Rn)), (NEGv4i16 V64:$Rn)>;
3395 def : Pat<(AArch64neg (v8i16 V128:$Rn)), (NEGv8i16 V128:$Rn)>;
3396 def : Pat<(AArch64neg (v2i32 V64:$Rn)), (NEGv2i32 V64:$Rn)>;
3397 def : Pat<(AArch64neg (v4i32 V128:$Rn)), (NEGv4i32 V128:$Rn)>;
3398 def : Pat<(AArch64neg (v2i64 V128:$Rn)), (NEGv2i64 V128:$Rn)>;
3400 def : Pat<(AArch64not (v8i8 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
3401 def : Pat<(AArch64not (v16i8 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
3402 def : Pat<(AArch64not (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
3403 def : Pat<(AArch64not (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
3404 def : Pat<(AArch64not (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
3405 def : Pat<(AArch64not (v1i64 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
3406 def : Pat<(AArch64not (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
3407 def : Pat<(AArch64not (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
3409 def : Pat<(vnot (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
3410 def : Pat<(vnot (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
3411 def : Pat<(vnot (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
3412 def : Pat<(vnot (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
3413 def : Pat<(vnot (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
3415 defm RBIT : SIMDTwoVectorB<1, 0b01, 0b00101, "rbit", int_aarch64_neon_rbit>;
3416 defm REV16 : SIMDTwoVectorB<0, 0b00, 0b00001, "rev16", AArch64rev16>;
3417 defm REV32 : SIMDTwoVectorBH<1, 0b00000, "rev32", AArch64rev32>;
3418 defm REV64 : SIMDTwoVectorBHS<0, 0b00000, "rev64", AArch64rev64>;
3419 defm SADALP : SIMDLongTwoVectorTied<0, 0b00110, "sadalp",
3420 BinOpFrag<(add node:$LHS, (int_aarch64_neon_saddlp node:$RHS))> >;
3421 defm SADDLP : SIMDLongTwoVector<0, 0b00010, "saddlp", int_aarch64_neon_saddlp>;
3422 defm SCVTF : SIMDTwoVectorIntToFP<0, 0, 0b11101, "scvtf", sint_to_fp>;
3423 defm SHLL : SIMDVectorLShiftLongBySizeBHS;
3424 defm SQABS : SIMDTwoVectorBHSD<0, 0b00111, "sqabs", int_aarch64_neon_sqabs>;
3425 defm SQNEG : SIMDTwoVectorBHSD<1, 0b00111, "sqneg", int_aarch64_neon_sqneg>;
3426 defm SQXTN : SIMDMixedTwoVector<0, 0b10100, "sqxtn", int_aarch64_neon_sqxtn>;
3427 defm SQXTUN : SIMDMixedTwoVector<1, 0b10010, "sqxtun", int_aarch64_neon_sqxtun>;
3428 defm SUQADD : SIMDTwoVectorBHSDTied<0, 0b00011, "suqadd",int_aarch64_neon_suqadd>;
3429 defm UADALP : SIMDLongTwoVectorTied<1, 0b00110, "uadalp",
3430 BinOpFrag<(add node:$LHS, (int_aarch64_neon_uaddlp node:$RHS))> >;
3431 defm UADDLP : SIMDLongTwoVector<1, 0b00010, "uaddlp",
3432 int_aarch64_neon_uaddlp>;
3433 defm UCVTF : SIMDTwoVectorIntToFP<1, 0, 0b11101, "ucvtf", uint_to_fp>;
3434 defm UQXTN : SIMDMixedTwoVector<1, 0b10100, "uqxtn", int_aarch64_neon_uqxtn>;
3435 defm URECPE : SIMDTwoVectorS<0, 1, 0b11100, "urecpe", int_aarch64_neon_urecpe>;
3436 defm URSQRTE: SIMDTwoVectorS<1, 1, 0b11100, "ursqrte", int_aarch64_neon_ursqrte>;
3437 defm USQADD : SIMDTwoVectorBHSDTied<1, 0b00011, "usqadd",int_aarch64_neon_usqadd>;
3438 defm XTN : SIMDMixedTwoVector<0, 0b10010, "xtn", trunc>;
3440 def : Pat<(v4f16 (AArch64rev32 V64:$Rn)), (REV32v4i16 V64:$Rn)>;
3441 def : Pat<(v4f16 (AArch64rev64 V64:$Rn)), (REV64v4i16 V64:$Rn)>;
3442 def : Pat<(v8f16 (AArch64rev32 V128:$Rn)), (REV32v8i16 V128:$Rn)>;
3443 def : Pat<(v8f16 (AArch64rev64 V128:$Rn)), (REV64v8i16 V128:$Rn)>;
3444 def : Pat<(v2f32 (AArch64rev64 V64:$Rn)), (REV64v2i32 V64:$Rn)>;
3445 def : Pat<(v4f32 (AArch64rev64 V128:$Rn)), (REV64v4i32 V128:$Rn)>;
3447 // Patterns for vector long shift (by element width). These need to match all
3448 // three of zext, sext and anyext so it's easier to pull the patterns out of the
3450 multiclass SIMDVectorLShiftLongBySizeBHSPats<SDPatternOperator ext> {
3451 def : Pat<(AArch64vshl (v8i16 (ext (v8i8 V64:$Rn))), (i32 8)),
3452 (SHLLv8i8 V64:$Rn)>;
3453 def : Pat<(AArch64vshl (v8i16 (ext (extract_high_v16i8 V128:$Rn))), (i32 8)),
3454 (SHLLv16i8 V128:$Rn)>;
3455 def : Pat<(AArch64vshl (v4i32 (ext (v4i16 V64:$Rn))), (i32 16)),
3456 (SHLLv4i16 V64:$Rn)>;
3457 def : Pat<(AArch64vshl (v4i32 (ext (extract_high_v8i16 V128:$Rn))), (i32 16)),
3458 (SHLLv8i16 V128:$Rn)>;
3459 def : Pat<(AArch64vshl (v2i64 (ext (v2i32 V64:$Rn))), (i32 32)),
3460 (SHLLv2i32 V64:$Rn)>;
3461 def : Pat<(AArch64vshl (v2i64 (ext (extract_high_v4i32 V128:$Rn))), (i32 32)),
3462 (SHLLv4i32 V128:$Rn)>;
3465 defm : SIMDVectorLShiftLongBySizeBHSPats<anyext>;
3466 defm : SIMDVectorLShiftLongBySizeBHSPats<zext>;
3467 defm : SIMDVectorLShiftLongBySizeBHSPats<sext>;
3469 //===----------------------------------------------------------------------===//
3470 // Advanced SIMD three vector instructions.
3471 //===----------------------------------------------------------------------===//
3473 defm ADD : SIMDThreeSameVector<0, 0b10000, "add", add>;
3474 defm ADDP : SIMDThreeSameVector<0, 0b10111, "addp", int_aarch64_neon_addp>;
3475 defm CMEQ : SIMDThreeSameVector<1, 0b10001, "cmeq", AArch64cmeq>;
3476 defm CMGE : SIMDThreeSameVector<0, 0b00111, "cmge", AArch64cmge>;
3477 defm CMGT : SIMDThreeSameVector<0, 0b00110, "cmgt", AArch64cmgt>;
3478 defm CMHI : SIMDThreeSameVector<1, 0b00110, "cmhi", AArch64cmhi>;
3479 defm CMHS : SIMDThreeSameVector<1, 0b00111, "cmhs", AArch64cmhs>;
3480 defm CMTST : SIMDThreeSameVector<0, 0b10001, "cmtst", AArch64cmtst>;
3481 defm FABD : SIMDThreeSameVectorFP<1,1,0b010,"fabd", int_aarch64_neon_fabd>;
3482 let Predicates = [HasNEON] in {
3483 foreach VT = [ v2f32, v4f32, v2f64 ] in
3484 def : Pat<(fabs (fsub VT:$Rn, VT:$Rm)), (!cast<Instruction>("FABD"#VT) VT:$Rn, VT:$Rm)>;
3486 let Predicates = [HasNEON, HasFullFP16] in {
3487 foreach VT = [ v4f16, v8f16 ] in
3488 def : Pat<(fabs (fsub VT:$Rn, VT:$Rm)), (!cast<Instruction>("FABD"#VT) VT:$Rn, VT:$Rm)>;
3490 defm FACGE : SIMDThreeSameVectorFPCmp<1,0,0b101,"facge",int_aarch64_neon_facge>;
3491 defm FACGT : SIMDThreeSameVectorFPCmp<1,1,0b101,"facgt",int_aarch64_neon_facgt>;
3492 defm FADDP : SIMDThreeSameVectorFP<1,0,0b010,"faddp",int_aarch64_neon_addp>;
3493 defm FADD : SIMDThreeSameVectorFP<0,0,0b010,"fadd", fadd>;
3494 defm FCMEQ : SIMDThreeSameVectorFPCmp<0, 0, 0b100, "fcmeq", AArch64fcmeq>;
3495 defm FCMGE : SIMDThreeSameVectorFPCmp<1, 0, 0b100, "fcmge", AArch64fcmge>;
3496 defm FCMGT : SIMDThreeSameVectorFPCmp<1, 1, 0b100, "fcmgt", AArch64fcmgt>;
3497 defm FDIV : SIMDThreeSameVectorFP<1,0,0b111,"fdiv", fdiv>;
3498 defm FMAXNMP : SIMDThreeSameVectorFP<1,0,0b000,"fmaxnmp", int_aarch64_neon_fmaxnmp>;
3499 defm FMAXNM : SIMDThreeSameVectorFP<0,0,0b000,"fmaxnm", fmaxnum>;
3500 defm FMAXP : SIMDThreeSameVectorFP<1,0,0b110,"fmaxp", int_aarch64_neon_fmaxp>;
3501 defm FMAX : SIMDThreeSameVectorFP<0,0,0b110,"fmax", fmaximum>;
3502 defm FMINNMP : SIMDThreeSameVectorFP<1,1,0b000,"fminnmp", int_aarch64_neon_fminnmp>;
3503 defm FMINNM : SIMDThreeSameVectorFP<0,1,0b000,"fminnm", fminnum>;
3504 defm FMINP : SIMDThreeSameVectorFP<1,1,0b110,"fminp", int_aarch64_neon_fminp>;
3505 defm FMIN : SIMDThreeSameVectorFP<0,1,0b110,"fmin", fminimum>;
3507 // NOTE: The operands of the PatFrag are reordered on FMLA/FMLS because the
3508 // instruction expects the addend first, while the fma intrinsic puts it last.
3509 defm FMLA : SIMDThreeSameVectorFPTied<0, 0, 0b001, "fmla",
3510 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
3511 defm FMLS : SIMDThreeSameVectorFPTied<0, 1, 0b001, "fmls",
3512 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
3514 // The following def pats catch the case where the LHS of an FMA is negated.
3515 // The TriOpFrag above catches the case where the middle operand is negated.
3516 def : Pat<(v2f32 (fma (fneg V64:$Rn), V64:$Rm, V64:$Rd)),
3517 (FMLSv2f32 V64:$Rd, V64:$Rn, V64:$Rm)>;
3519 def : Pat<(v4f32 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
3520 (FMLSv4f32 V128:$Rd, V128:$Rn, V128:$Rm)>;
3522 def : Pat<(v2f64 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
3523 (FMLSv2f64 V128:$Rd, V128:$Rn, V128:$Rm)>;
3525 defm FMULX : SIMDThreeSameVectorFP<0,0,0b011,"fmulx", int_aarch64_neon_fmulx>;
3526 defm FMUL : SIMDThreeSameVectorFP<1,0,0b011,"fmul", fmul>;
3527 defm FRECPS : SIMDThreeSameVectorFP<0,0,0b111,"frecps", int_aarch64_neon_frecps>;
3528 defm FRSQRTS : SIMDThreeSameVectorFP<0,1,0b111,"frsqrts", int_aarch64_neon_frsqrts>;
3529 defm FSUB : SIMDThreeSameVectorFP<0,1,0b010,"fsub", fsub>;
3530 defm MLA : SIMDThreeSameVectorBHSTied<0, 0b10010, "mla",
3531 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))> >;
3532 defm MLS : SIMDThreeSameVectorBHSTied<1, 0b10010, "mls",
3533 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))> >;
3534 defm MUL : SIMDThreeSameVectorBHS<0, 0b10011, "mul", mul>;
3535 defm PMUL : SIMDThreeSameVectorB<1, 0b10011, "pmul", int_aarch64_neon_pmul>;
3536 defm SABA : SIMDThreeSameVectorBHSTied<0, 0b01111, "saba",
3537 TriOpFrag<(add node:$LHS, (int_aarch64_neon_sabd node:$MHS, node:$RHS))> >;
3538 defm SABD : SIMDThreeSameVectorBHS<0,0b01110,"sabd", int_aarch64_neon_sabd>;
3539 defm SHADD : SIMDThreeSameVectorBHS<0,0b00000,"shadd", int_aarch64_neon_shadd>;
3540 defm SHSUB : SIMDThreeSameVectorBHS<0,0b00100,"shsub", int_aarch64_neon_shsub>;
3541 defm SMAXP : SIMDThreeSameVectorBHS<0,0b10100,"smaxp", int_aarch64_neon_smaxp>;
3542 defm SMAX : SIMDThreeSameVectorBHS<0,0b01100,"smax", smax>;
3543 defm SMINP : SIMDThreeSameVectorBHS<0,0b10101,"sminp", int_aarch64_neon_sminp>;
3544 defm SMIN : SIMDThreeSameVectorBHS<0,0b01101,"smin", smin>;
3545 defm SQADD : SIMDThreeSameVector<0,0b00001,"sqadd", int_aarch64_neon_sqadd>;
3546 defm SQDMULH : SIMDThreeSameVectorHS<0,0b10110,"sqdmulh",int_aarch64_neon_sqdmulh>;
3547 defm SQRDMULH : SIMDThreeSameVectorHS<1,0b10110,"sqrdmulh",int_aarch64_neon_sqrdmulh>;
3548 defm SQRSHL : SIMDThreeSameVector<0,0b01011,"sqrshl", int_aarch64_neon_sqrshl>;
3549 defm SQSHL : SIMDThreeSameVector<0,0b01001,"sqshl", int_aarch64_neon_sqshl>;
3550 defm SQSUB : SIMDThreeSameVector<0,0b00101,"sqsub", int_aarch64_neon_sqsub>;
3551 defm SRHADD : SIMDThreeSameVectorBHS<0,0b00010,"srhadd",int_aarch64_neon_srhadd>;
3552 defm SRSHL : SIMDThreeSameVector<0,0b01010,"srshl", int_aarch64_neon_srshl>;
3553 defm SSHL : SIMDThreeSameVector<0,0b01000,"sshl", int_aarch64_neon_sshl>;
3554 defm SUB : SIMDThreeSameVector<1,0b10000,"sub", sub>;
3555 defm UABA : SIMDThreeSameVectorBHSTied<1, 0b01111, "uaba",
3556 TriOpFrag<(add node:$LHS, (int_aarch64_neon_uabd node:$MHS, node:$RHS))> >;
3557 defm UABD : SIMDThreeSameVectorBHS<1,0b01110,"uabd", int_aarch64_neon_uabd>;
3558 defm UHADD : SIMDThreeSameVectorBHS<1,0b00000,"uhadd", int_aarch64_neon_uhadd>;
3559 defm UHSUB : SIMDThreeSameVectorBHS<1,0b00100,"uhsub", int_aarch64_neon_uhsub>;
3560 defm UMAXP : SIMDThreeSameVectorBHS<1,0b10100,"umaxp", int_aarch64_neon_umaxp>;
3561 defm UMAX : SIMDThreeSameVectorBHS<1,0b01100,"umax", umax>;
3562 defm UMINP : SIMDThreeSameVectorBHS<1,0b10101,"uminp", int_aarch64_neon_uminp>;
3563 defm UMIN : SIMDThreeSameVectorBHS<1,0b01101,"umin", umin>;
3564 defm UQADD : SIMDThreeSameVector<1,0b00001,"uqadd", int_aarch64_neon_uqadd>;
3565 defm UQRSHL : SIMDThreeSameVector<1,0b01011,"uqrshl", int_aarch64_neon_uqrshl>;
3566 defm UQSHL : SIMDThreeSameVector<1,0b01001,"uqshl", int_aarch64_neon_uqshl>;
3567 defm UQSUB : SIMDThreeSameVector<1,0b00101,"uqsub", int_aarch64_neon_uqsub>;
3568 defm URHADD : SIMDThreeSameVectorBHS<1,0b00010,"urhadd", int_aarch64_neon_urhadd>;
3569 defm URSHL : SIMDThreeSameVector<1,0b01010,"urshl", int_aarch64_neon_urshl>;
3570 defm USHL : SIMDThreeSameVector<1,0b01000,"ushl", int_aarch64_neon_ushl>;
3571 defm SQRDMLAH : SIMDThreeSameVectorSQRDMLxHTiedHS<1,0b10000,"sqrdmlah",
3572 int_aarch64_neon_sqadd>;
3573 defm SQRDMLSH : SIMDThreeSameVectorSQRDMLxHTiedHS<1,0b10001,"sqrdmlsh",
3574 int_aarch64_neon_sqsub>;
3576 defm AND : SIMDLogicalThreeVector<0, 0b00, "and", and>;
3577 defm BIC : SIMDLogicalThreeVector<0, 0b01, "bic",
3578 BinOpFrag<(and node:$LHS, (vnot node:$RHS))> >;
3579 defm BIF : SIMDLogicalThreeVector<1, 0b11, "bif">;
3580 defm BIT : SIMDLogicalThreeVectorTied<1, 0b10, "bit", AArch64bit>;
3581 defm BSL : SIMDLogicalThreeVectorTied<1, 0b01, "bsl",
3582 TriOpFrag<(or (and node:$LHS, node:$MHS), (and (vnot node:$LHS), node:$RHS))>>;
3583 defm EOR : SIMDLogicalThreeVector<1, 0b00, "eor", xor>;
3584 defm ORN : SIMDLogicalThreeVector<0, 0b11, "orn",
3585 BinOpFrag<(or node:$LHS, (vnot node:$RHS))> >;
3586 defm ORR : SIMDLogicalThreeVector<0, 0b10, "orr", or>;
3589 def : Pat<(AArch64bsl (v8i8 V64:$Rd), V64:$Rn, V64:$Rm),
3590 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
3591 def : Pat<(AArch64bsl (v4i16 V64:$Rd), V64:$Rn, V64:$Rm),
3592 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
3593 def : Pat<(AArch64bsl (v2i32 V64:$Rd), V64:$Rn, V64:$Rm),
3594 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
3595 def : Pat<(AArch64bsl (v1i64 V64:$Rd), V64:$Rn, V64:$Rm),
3596 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
3598 def : Pat<(AArch64bsl (v16i8 V128:$Rd), V128:$Rn, V128:$Rm),
3599 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
3600 def : Pat<(AArch64bsl (v8i16 V128:$Rd), V128:$Rn, V128:$Rm),
3601 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
3602 def : Pat<(AArch64bsl (v4i32 V128:$Rd), V128:$Rn, V128:$Rm),
3603 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
3604 def : Pat<(AArch64bsl (v2i64 V128:$Rd), V128:$Rn, V128:$Rm),
3605 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
3607 def : InstAlias<"mov{\t$dst.16b, $src.16b|.16b\t$dst, $src}",
3608 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 1>;
3609 def : InstAlias<"mov{\t$dst.8h, $src.8h|.8h\t$dst, $src}",
3610 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
3611 def : InstAlias<"mov{\t$dst.4s, $src.4s|.4s\t$dst, $src}",
3612 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
3613 def : InstAlias<"mov{\t$dst.2d, $src.2d|.2d\t$dst, $src}",
3614 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
3616 def : InstAlias<"mov{\t$dst.8b, $src.8b|.8b\t$dst, $src}",
3617 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 1>;
3618 def : InstAlias<"mov{\t$dst.4h, $src.4h|.4h\t$dst, $src}",
3619 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
3620 def : InstAlias<"mov{\t$dst.2s, $src.2s|.2s\t$dst, $src}",
3621 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
3622 def : InstAlias<"mov{\t$dst.1d, $src.1d|.1d\t$dst, $src}",
3623 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
3625 def : InstAlias<"{cmls\t$dst.8b, $src1.8b, $src2.8b" #
3626 "|cmls.8b\t$dst, $src1, $src2}",
3627 (CMHSv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
3628 def : InstAlias<"{cmls\t$dst.16b, $src1.16b, $src2.16b" #
3629 "|cmls.16b\t$dst, $src1, $src2}",
3630 (CMHSv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
3631 def : InstAlias<"{cmls\t$dst.4h, $src1.4h, $src2.4h" #
3632 "|cmls.4h\t$dst, $src1, $src2}",
3633 (CMHSv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
3634 def : InstAlias<"{cmls\t$dst.8h, $src1.8h, $src2.8h" #
3635 "|cmls.8h\t$dst, $src1, $src2}",
3636 (CMHSv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
3637 def : InstAlias<"{cmls\t$dst.2s, $src1.2s, $src2.2s" #
3638 "|cmls.2s\t$dst, $src1, $src2}",
3639 (CMHSv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
3640 def : InstAlias<"{cmls\t$dst.4s, $src1.4s, $src2.4s" #
3641 "|cmls.4s\t$dst, $src1, $src2}",
3642 (CMHSv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
3643 def : InstAlias<"{cmls\t$dst.2d, $src1.2d, $src2.2d" #
3644 "|cmls.2d\t$dst, $src1, $src2}",
3645 (CMHSv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
3647 def : InstAlias<"{cmlo\t$dst.8b, $src1.8b, $src2.8b" #
3648 "|cmlo.8b\t$dst, $src1, $src2}",
3649 (CMHIv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
3650 def : InstAlias<"{cmlo\t$dst.16b, $src1.16b, $src2.16b" #
3651 "|cmlo.16b\t$dst, $src1, $src2}",
3652 (CMHIv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
3653 def : InstAlias<"{cmlo\t$dst.4h, $src1.4h, $src2.4h" #
3654 "|cmlo.4h\t$dst, $src1, $src2}",
3655 (CMHIv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
3656 def : InstAlias<"{cmlo\t$dst.8h, $src1.8h, $src2.8h" #
3657 "|cmlo.8h\t$dst, $src1, $src2}",
3658 (CMHIv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
3659 def : InstAlias<"{cmlo\t$dst.2s, $src1.2s, $src2.2s" #
3660 "|cmlo.2s\t$dst, $src1, $src2}",
3661 (CMHIv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
3662 def : InstAlias<"{cmlo\t$dst.4s, $src1.4s, $src2.4s" #
3663 "|cmlo.4s\t$dst, $src1, $src2}",
3664 (CMHIv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
3665 def : InstAlias<"{cmlo\t$dst.2d, $src1.2d, $src2.2d" #
3666 "|cmlo.2d\t$dst, $src1, $src2}",
3667 (CMHIv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
3669 def : InstAlias<"{cmle\t$dst.8b, $src1.8b, $src2.8b" #
3670 "|cmle.8b\t$dst, $src1, $src2}",
3671 (CMGEv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
3672 def : InstAlias<"{cmle\t$dst.16b, $src1.16b, $src2.16b" #
3673 "|cmle.16b\t$dst, $src1, $src2}",
3674 (CMGEv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
3675 def : InstAlias<"{cmle\t$dst.4h, $src1.4h, $src2.4h" #
3676 "|cmle.4h\t$dst, $src1, $src2}",
3677 (CMGEv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
3678 def : InstAlias<"{cmle\t$dst.8h, $src1.8h, $src2.8h" #
3679 "|cmle.8h\t$dst, $src1, $src2}",
3680 (CMGEv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
3681 def : InstAlias<"{cmle\t$dst.2s, $src1.2s, $src2.2s" #
3682 "|cmle.2s\t$dst, $src1, $src2}",
3683 (CMGEv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
3684 def : InstAlias<"{cmle\t$dst.4s, $src1.4s, $src2.4s" #
3685 "|cmle.4s\t$dst, $src1, $src2}",
3686 (CMGEv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
3687 def : InstAlias<"{cmle\t$dst.2d, $src1.2d, $src2.2d" #
3688 "|cmle.2d\t$dst, $src1, $src2}",
3689 (CMGEv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
3691 def : InstAlias<"{cmlt\t$dst.8b, $src1.8b, $src2.8b" #
3692 "|cmlt.8b\t$dst, $src1, $src2}",
3693 (CMGTv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
3694 def : InstAlias<"{cmlt\t$dst.16b, $src1.16b, $src2.16b" #
3695 "|cmlt.16b\t$dst, $src1, $src2}",
3696 (CMGTv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
3697 def : InstAlias<"{cmlt\t$dst.4h, $src1.4h, $src2.4h" #
3698 "|cmlt.4h\t$dst, $src1, $src2}",
3699 (CMGTv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
3700 def : InstAlias<"{cmlt\t$dst.8h, $src1.8h, $src2.8h" #
3701 "|cmlt.8h\t$dst, $src1, $src2}",
3702 (CMGTv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
3703 def : InstAlias<"{cmlt\t$dst.2s, $src1.2s, $src2.2s" #
3704 "|cmlt.2s\t$dst, $src1, $src2}",
3705 (CMGTv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
3706 def : InstAlias<"{cmlt\t$dst.4s, $src1.4s, $src2.4s" #
3707 "|cmlt.4s\t$dst, $src1, $src2}",
3708 (CMGTv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
3709 def : InstAlias<"{cmlt\t$dst.2d, $src1.2d, $src2.2d" #
3710 "|cmlt.2d\t$dst, $src1, $src2}",
3711 (CMGTv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
3713 let Predicates = [HasNEON, HasFullFP16] in {
3714 def : InstAlias<"{fcmle\t$dst.4h, $src1.4h, $src2.4h" #
3715 "|fcmle.4h\t$dst, $src1, $src2}",
3716 (FCMGEv4f16 V64:$dst, V64:$src2, V64:$src1), 0>;
3717 def : InstAlias<"{fcmle\t$dst.8h, $src1.8h, $src2.8h" #
3718 "|fcmle.8h\t$dst, $src1, $src2}",
3719 (FCMGEv8f16 V128:$dst, V128:$src2, V128:$src1), 0>;
3721 def : InstAlias<"{fcmle\t$dst.2s, $src1.2s, $src2.2s" #
3722 "|fcmle.2s\t$dst, $src1, $src2}",
3723 (FCMGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
3724 def : InstAlias<"{fcmle\t$dst.4s, $src1.4s, $src2.4s" #
3725 "|fcmle.4s\t$dst, $src1, $src2}",
3726 (FCMGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
3727 def : InstAlias<"{fcmle\t$dst.2d, $src1.2d, $src2.2d" #
3728 "|fcmle.2d\t$dst, $src1, $src2}",
3729 (FCMGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
3731 let Predicates = [HasNEON, HasFullFP16] in {
3732 def : InstAlias<"{fcmlt\t$dst.4h, $src1.4h, $src2.4h" #
3733 "|fcmlt.4h\t$dst, $src1, $src2}",
3734 (FCMGTv4f16 V64:$dst, V64:$src2, V64:$src1), 0>;
3735 def : InstAlias<"{fcmlt\t$dst.8h, $src1.8h, $src2.8h" #
3736 "|fcmlt.8h\t$dst, $src1, $src2}",
3737 (FCMGTv8f16 V128:$dst, V128:$src2, V128:$src1), 0>;
3739 def : InstAlias<"{fcmlt\t$dst.2s, $src1.2s, $src2.2s" #
3740 "|fcmlt.2s\t$dst, $src1, $src2}",
3741 (FCMGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
3742 def : InstAlias<"{fcmlt\t$dst.4s, $src1.4s, $src2.4s" #
3743 "|fcmlt.4s\t$dst, $src1, $src2}",
3744 (FCMGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
3745 def : InstAlias<"{fcmlt\t$dst.2d, $src1.2d, $src2.2d" #
3746 "|fcmlt.2d\t$dst, $src1, $src2}",
3747 (FCMGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
3749 let Predicates = [HasNEON, HasFullFP16] in {
3750 def : InstAlias<"{facle\t$dst.4h, $src1.4h, $src2.4h" #
3751 "|facle.4h\t$dst, $src1, $src2}",
3752 (FACGEv4f16 V64:$dst, V64:$src2, V64:$src1), 0>;
3753 def : InstAlias<"{facle\t$dst.8h, $src1.8h, $src2.8h" #
3754 "|facle.8h\t$dst, $src1, $src2}",
3755 (FACGEv8f16 V128:$dst, V128:$src2, V128:$src1), 0>;
3757 def : InstAlias<"{facle\t$dst.2s, $src1.2s, $src2.2s" #
3758 "|facle.2s\t$dst, $src1, $src2}",
3759 (FACGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
3760 def : InstAlias<"{facle\t$dst.4s, $src1.4s, $src2.4s" #
3761 "|facle.4s\t$dst, $src1, $src2}",
3762 (FACGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
3763 def : InstAlias<"{facle\t$dst.2d, $src1.2d, $src2.2d" #
3764 "|facle.2d\t$dst, $src1, $src2}",
3765 (FACGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
3767 let Predicates = [HasNEON, HasFullFP16] in {
3768 def : InstAlias<"{faclt\t$dst.4h, $src1.4h, $src2.4h" #
3769 "|faclt.4h\t$dst, $src1, $src2}",
3770 (FACGTv4f16 V64:$dst, V64:$src2, V64:$src1), 0>;
3771 def : InstAlias<"{faclt\t$dst.8h, $src1.8h, $src2.8h" #
3772 "|faclt.8h\t$dst, $src1, $src2}",
3773 (FACGTv8f16 V128:$dst, V128:$src2, V128:$src1), 0>;
3775 def : InstAlias<"{faclt\t$dst.2s, $src1.2s, $src2.2s" #
3776 "|faclt.2s\t$dst, $src1, $src2}",
3777 (FACGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
3778 def : InstAlias<"{faclt\t$dst.4s, $src1.4s, $src2.4s" #
3779 "|faclt.4s\t$dst, $src1, $src2}",
3780 (FACGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
3781 def : InstAlias<"{faclt\t$dst.2d, $src1.2d, $src2.2d" #
3782 "|faclt.2d\t$dst, $src1, $src2}",
3783 (FACGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
3785 //===----------------------------------------------------------------------===//
3786 // Advanced SIMD three scalar instructions.
3787 //===----------------------------------------------------------------------===//
3789 defm ADD : SIMDThreeScalarD<0, 0b10000, "add", add>;
3790 defm CMEQ : SIMDThreeScalarD<1, 0b10001, "cmeq", AArch64cmeq>;
3791 defm CMGE : SIMDThreeScalarD<0, 0b00111, "cmge", AArch64cmge>;
3792 defm CMGT : SIMDThreeScalarD<0, 0b00110, "cmgt", AArch64cmgt>;
3793 defm CMHI : SIMDThreeScalarD<1, 0b00110, "cmhi", AArch64cmhi>;
3794 defm CMHS : SIMDThreeScalarD<1, 0b00111, "cmhs", AArch64cmhs>;
3795 defm CMTST : SIMDThreeScalarD<0, 0b10001, "cmtst", AArch64cmtst>;
3796 defm FABD : SIMDFPThreeScalar<1, 1, 0b010, "fabd", int_aarch64_sisd_fabd>;
3797 def : Pat<(v1f64 (int_aarch64_neon_fabd (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
3798 (FABD64 FPR64:$Rn, FPR64:$Rm)>;
3799 let Predicates = [HasFullFP16] in {
3800 def : Pat<(fabs (fsub f16:$Rn, f16:$Rm)), (FABD16 f16:$Rn, f16:$Rm)>;
3802 def : Pat<(fabs (fsub f32:$Rn, f32:$Rm)), (FABD32 f32:$Rn, f32:$Rm)>;
3803 def : Pat<(fabs (fsub f64:$Rn, f64:$Rm)), (FABD64 f64:$Rn, f64:$Rm)>;
3804 defm FACGE : SIMDThreeScalarFPCmp<1, 0, 0b101, "facge",
3805 int_aarch64_neon_facge>;
3806 defm FACGT : SIMDThreeScalarFPCmp<1, 1, 0b101, "facgt",
3807 int_aarch64_neon_facgt>;
3808 defm FCMEQ : SIMDThreeScalarFPCmp<0, 0, 0b100, "fcmeq", AArch64fcmeq>;
3809 defm FCMGE : SIMDThreeScalarFPCmp<1, 0, 0b100, "fcmge", AArch64fcmge>;
3810 defm FCMGT : SIMDThreeScalarFPCmp<1, 1, 0b100, "fcmgt", AArch64fcmgt>;
3811 defm FMULX : SIMDFPThreeScalar<0, 0, 0b011, "fmulx", int_aarch64_neon_fmulx>;
3812 defm FRECPS : SIMDFPThreeScalar<0, 0, 0b111, "frecps", int_aarch64_neon_frecps>;
3813 defm FRSQRTS : SIMDFPThreeScalar<0, 1, 0b111, "frsqrts", int_aarch64_neon_frsqrts>;
3814 defm SQADD : SIMDThreeScalarBHSD<0, 0b00001, "sqadd", int_aarch64_neon_sqadd>;
3815 defm SQDMULH : SIMDThreeScalarHS< 0, 0b10110, "sqdmulh", int_aarch64_neon_sqdmulh>;
3816 defm SQRDMULH : SIMDThreeScalarHS< 1, 0b10110, "sqrdmulh", int_aarch64_neon_sqrdmulh>;
3817 defm SQRSHL : SIMDThreeScalarBHSD<0, 0b01011, "sqrshl",int_aarch64_neon_sqrshl>;
3818 defm SQSHL : SIMDThreeScalarBHSD<0, 0b01001, "sqshl", int_aarch64_neon_sqshl>;
3819 defm SQSUB : SIMDThreeScalarBHSD<0, 0b00101, "sqsub", int_aarch64_neon_sqsub>;
3820 defm SRSHL : SIMDThreeScalarD< 0, 0b01010, "srshl", int_aarch64_neon_srshl>;
3821 defm SSHL : SIMDThreeScalarD< 0, 0b01000, "sshl", int_aarch64_neon_sshl>;
3822 defm SUB : SIMDThreeScalarD< 1, 0b10000, "sub", sub>;
3823 defm UQADD : SIMDThreeScalarBHSD<1, 0b00001, "uqadd", int_aarch64_neon_uqadd>;
3824 defm UQRSHL : SIMDThreeScalarBHSD<1, 0b01011, "uqrshl",int_aarch64_neon_uqrshl>;
3825 defm UQSHL : SIMDThreeScalarBHSD<1, 0b01001, "uqshl", int_aarch64_neon_uqshl>;
3826 defm UQSUB : SIMDThreeScalarBHSD<1, 0b00101, "uqsub", int_aarch64_neon_uqsub>;
3827 defm URSHL : SIMDThreeScalarD< 1, 0b01010, "urshl", int_aarch64_neon_urshl>;
3828 defm USHL : SIMDThreeScalarD< 1, 0b01000, "ushl", int_aarch64_neon_ushl>;
3829 let Predicates = [HasRDM] in {
3830 defm SQRDMLAH : SIMDThreeScalarHSTied<1, 0, 0b10000, "sqrdmlah">;
3831 defm SQRDMLSH : SIMDThreeScalarHSTied<1, 0, 0b10001, "sqrdmlsh">;
3832 def : Pat<(i32 (int_aarch64_neon_sqadd
3834 (i32 (int_aarch64_neon_sqrdmulh (i32 FPR32:$Rn),
3835 (i32 FPR32:$Rm))))),
3836 (SQRDMLAHv1i32 FPR32:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3837 def : Pat<(i32 (int_aarch64_neon_sqsub
3839 (i32 (int_aarch64_neon_sqrdmulh (i32 FPR32:$Rn),
3840 (i32 FPR32:$Rm))))),
3841 (SQRDMLSHv1i32 FPR32:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3844 def : InstAlias<"cmls $dst, $src1, $src2",
3845 (CMHSv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3846 def : InstAlias<"cmle $dst, $src1, $src2",
3847 (CMGEv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3848 def : InstAlias<"cmlo $dst, $src1, $src2",
3849 (CMHIv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3850 def : InstAlias<"cmlt $dst, $src1, $src2",
3851 (CMGTv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3852 def : InstAlias<"fcmle $dst, $src1, $src2",
3853 (FCMGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3854 def : InstAlias<"fcmle $dst, $src1, $src2",
3855 (FCMGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3856 def : InstAlias<"fcmlt $dst, $src1, $src2",
3857 (FCMGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3858 def : InstAlias<"fcmlt $dst, $src1, $src2",
3859 (FCMGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3860 def : InstAlias<"facle $dst, $src1, $src2",
3861 (FACGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3862 def : InstAlias<"facle $dst, $src1, $src2",
3863 (FACGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3864 def : InstAlias<"faclt $dst, $src1, $src2",
3865 (FACGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3866 def : InstAlias<"faclt $dst, $src1, $src2",
3867 (FACGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3869 //===----------------------------------------------------------------------===//
3870 // Advanced SIMD three scalar instructions (mixed operands).
3871 //===----------------------------------------------------------------------===//
3872 defm SQDMULL : SIMDThreeScalarMixedHS<0, 0b11010, "sqdmull",
3873 int_aarch64_neon_sqdmulls_scalar>;
3874 defm SQDMLAL : SIMDThreeScalarMixedTiedHS<0, 0b10010, "sqdmlal">;
3875 defm SQDMLSL : SIMDThreeScalarMixedTiedHS<0, 0b10110, "sqdmlsl">;
3877 def : Pat<(i64 (int_aarch64_neon_sqadd (i64 FPR64:$Rd),
3878 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
3879 (i32 FPR32:$Rm))))),
3880 (SQDMLALi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3881 def : Pat<(i64 (int_aarch64_neon_sqsub (i64 FPR64:$Rd),
3882 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
3883 (i32 FPR32:$Rm))))),
3884 (SQDMLSLi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3886 //===----------------------------------------------------------------------===//
3887 // Advanced SIMD two scalar instructions.
3888 //===----------------------------------------------------------------------===//
3890 defm ABS : SIMDTwoScalarD< 0, 0b01011, "abs", abs>;
3891 defm CMEQ : SIMDCmpTwoScalarD< 0, 0b01001, "cmeq", AArch64cmeqz>;
3892 defm CMGE : SIMDCmpTwoScalarD< 1, 0b01000, "cmge", AArch64cmgez>;
3893 defm CMGT : SIMDCmpTwoScalarD< 0, 0b01000, "cmgt", AArch64cmgtz>;
3894 defm CMLE : SIMDCmpTwoScalarD< 1, 0b01001, "cmle", AArch64cmlez>;
3895 defm CMLT : SIMDCmpTwoScalarD< 0, 0b01010, "cmlt", AArch64cmltz>;
3896 defm FCMEQ : SIMDFPCmpTwoScalar<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>;
3897 defm FCMGE : SIMDFPCmpTwoScalar<1, 1, 0b01100, "fcmge", AArch64fcmgez>;
3898 defm FCMGT : SIMDFPCmpTwoScalar<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>;
3899 defm FCMLE : SIMDFPCmpTwoScalar<1, 1, 0b01101, "fcmle", AArch64fcmlez>;
3900 defm FCMLT : SIMDFPCmpTwoScalar<0, 1, 0b01110, "fcmlt", AArch64fcmltz>;
3901 defm FCVTAS : SIMDFPTwoScalar< 0, 0, 0b11100, "fcvtas">;
3902 defm FCVTAU : SIMDFPTwoScalar< 1, 0, 0b11100, "fcvtau">;
3903 defm FCVTMS : SIMDFPTwoScalar< 0, 0, 0b11011, "fcvtms">;
3904 defm FCVTMU : SIMDFPTwoScalar< 1, 0, 0b11011, "fcvtmu">;
3905 defm FCVTNS : SIMDFPTwoScalar< 0, 0, 0b11010, "fcvtns">;
3906 defm FCVTNU : SIMDFPTwoScalar< 1, 0, 0b11010, "fcvtnu">;
3907 defm FCVTPS : SIMDFPTwoScalar< 0, 1, 0b11010, "fcvtps">;
3908 defm FCVTPU : SIMDFPTwoScalar< 1, 1, 0b11010, "fcvtpu">;
3909 def FCVTXNv1i64 : SIMDInexactCvtTwoScalar<0b10110, "fcvtxn">;
3910 defm FCVTZS : SIMDFPTwoScalar< 0, 1, 0b11011, "fcvtzs">;
3911 defm FCVTZU : SIMDFPTwoScalar< 1, 1, 0b11011, "fcvtzu">;
3912 defm FRECPE : SIMDFPTwoScalar< 0, 1, 0b11101, "frecpe">;
3913 defm FRECPX : SIMDFPTwoScalar< 0, 1, 0b11111, "frecpx">;
3914 defm FRSQRTE : SIMDFPTwoScalar< 1, 1, 0b11101, "frsqrte">;
3915 defm NEG : SIMDTwoScalarD< 1, 0b01011, "neg",
3916 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
3917 defm SCVTF : SIMDFPTwoScalarCVT< 0, 0, 0b11101, "scvtf", AArch64sitof>;
3918 defm SQABS : SIMDTwoScalarBHSD< 0, 0b00111, "sqabs", int_aarch64_neon_sqabs>;
3919 defm SQNEG : SIMDTwoScalarBHSD< 1, 0b00111, "sqneg", int_aarch64_neon_sqneg>;
3920 defm SQXTN : SIMDTwoScalarMixedBHS< 0, 0b10100, "sqxtn", int_aarch64_neon_scalar_sqxtn>;
3921 defm SQXTUN : SIMDTwoScalarMixedBHS< 1, 0b10010, "sqxtun", int_aarch64_neon_scalar_sqxtun>;
3922 defm SUQADD : SIMDTwoScalarBHSDTied< 0, 0b00011, "suqadd",
3923 int_aarch64_neon_suqadd>;
3924 defm UCVTF : SIMDFPTwoScalarCVT< 1, 0, 0b11101, "ucvtf", AArch64uitof>;
3925 defm UQXTN : SIMDTwoScalarMixedBHS<1, 0b10100, "uqxtn", int_aarch64_neon_scalar_uqxtn>;
3926 defm USQADD : SIMDTwoScalarBHSDTied< 1, 0b00011, "usqadd",
3927 int_aarch64_neon_usqadd>;
3929 def : Pat<(AArch64neg (v1i64 V64:$Rn)), (NEGv1i64 V64:$Rn)>;
3931 def : Pat<(v1i64 (int_aarch64_neon_fcvtas (v1f64 FPR64:$Rn))),
3932 (FCVTASv1i64 FPR64:$Rn)>;
3933 def : Pat<(v1i64 (int_aarch64_neon_fcvtau (v1f64 FPR64:$Rn))),
3934 (FCVTAUv1i64 FPR64:$Rn)>;
3935 def : Pat<(v1i64 (int_aarch64_neon_fcvtms (v1f64 FPR64:$Rn))),
3936 (FCVTMSv1i64 FPR64:$Rn)>;
3937 def : Pat<(v1i64 (int_aarch64_neon_fcvtmu (v1f64 FPR64:$Rn))),
3938 (FCVTMUv1i64 FPR64:$Rn)>;
3939 def : Pat<(v1i64 (int_aarch64_neon_fcvtns (v1f64 FPR64:$Rn))),
3940 (FCVTNSv1i64 FPR64:$Rn)>;
3941 def : Pat<(v1i64 (int_aarch64_neon_fcvtnu (v1f64 FPR64:$Rn))),
3942 (FCVTNUv1i64 FPR64:$Rn)>;
3943 def : Pat<(v1i64 (int_aarch64_neon_fcvtps (v1f64 FPR64:$Rn))),
3944 (FCVTPSv1i64 FPR64:$Rn)>;
3945 def : Pat<(v1i64 (int_aarch64_neon_fcvtpu (v1f64 FPR64:$Rn))),
3946 (FCVTPUv1i64 FPR64:$Rn)>;
3948 def : Pat<(f16 (int_aarch64_neon_frecpe (f16 FPR16:$Rn))),
3949 (FRECPEv1f16 FPR16:$Rn)>;
3950 def : Pat<(f32 (int_aarch64_neon_frecpe (f32 FPR32:$Rn))),
3951 (FRECPEv1i32 FPR32:$Rn)>;
3952 def : Pat<(f64 (int_aarch64_neon_frecpe (f64 FPR64:$Rn))),
3953 (FRECPEv1i64 FPR64:$Rn)>;
3954 def : Pat<(v1f64 (int_aarch64_neon_frecpe (v1f64 FPR64:$Rn))),
3955 (FRECPEv1i64 FPR64:$Rn)>;
3957 def : Pat<(f32 (AArch64frecpe (f32 FPR32:$Rn))),
3958 (FRECPEv1i32 FPR32:$Rn)>;
3959 def : Pat<(v2f32 (AArch64frecpe (v2f32 V64:$Rn))),
3960 (FRECPEv2f32 V64:$Rn)>;
3961 def : Pat<(v4f32 (AArch64frecpe (v4f32 FPR128:$Rn))),
3962 (FRECPEv4f32 FPR128:$Rn)>;
3963 def : Pat<(f64 (AArch64frecpe (f64 FPR64:$Rn))),
3964 (FRECPEv1i64 FPR64:$Rn)>;
3965 def : Pat<(v1f64 (AArch64frecpe (v1f64 FPR64:$Rn))),
3966 (FRECPEv1i64 FPR64:$Rn)>;
3967 def : Pat<(v2f64 (AArch64frecpe (v2f64 FPR128:$Rn))),
3968 (FRECPEv2f64 FPR128:$Rn)>;
3970 def : Pat<(f32 (AArch64frecps (f32 FPR32:$Rn), (f32 FPR32:$Rm))),
3971 (FRECPS32 FPR32:$Rn, FPR32:$Rm)>;
3972 def : Pat<(v2f32 (AArch64frecps (v2f32 V64:$Rn), (v2f32 V64:$Rm))),
3973 (FRECPSv2f32 V64:$Rn, V64:$Rm)>;
3974 def : Pat<(v4f32 (AArch64frecps (v4f32 FPR128:$Rn), (v4f32 FPR128:$Rm))),
3975 (FRECPSv4f32 FPR128:$Rn, FPR128:$Rm)>;
3976 def : Pat<(f64 (AArch64frecps (f64 FPR64:$Rn), (f64 FPR64:$Rm))),
3977 (FRECPS64 FPR64:$Rn, FPR64:$Rm)>;
3978 def : Pat<(v2f64 (AArch64frecps (v2f64 FPR128:$Rn), (v2f64 FPR128:$Rm))),
3979 (FRECPSv2f64 FPR128:$Rn, FPR128:$Rm)>;
3981 def : Pat<(f16 (int_aarch64_neon_frecpx (f16 FPR16:$Rn))),
3982 (FRECPXv1f16 FPR16:$Rn)>;
3983 def : Pat<(f32 (int_aarch64_neon_frecpx (f32 FPR32:$Rn))),
3984 (FRECPXv1i32 FPR32:$Rn)>;
3985 def : Pat<(f64 (int_aarch64_neon_frecpx (f64 FPR64:$Rn))),
3986 (FRECPXv1i64 FPR64:$Rn)>;
3988 def : Pat<(f16 (int_aarch64_neon_frsqrte (f16 FPR16:$Rn))),
3989 (FRSQRTEv1f16 FPR16:$Rn)>;
3990 def : Pat<(f32 (int_aarch64_neon_frsqrte (f32 FPR32:$Rn))),
3991 (FRSQRTEv1i32 FPR32:$Rn)>;
3992 def : Pat<(f64 (int_aarch64_neon_frsqrte (f64 FPR64:$Rn))),
3993 (FRSQRTEv1i64 FPR64:$Rn)>;
3994 def : Pat<(v1f64 (int_aarch64_neon_frsqrte (v1f64 FPR64:$Rn))),
3995 (FRSQRTEv1i64 FPR64:$Rn)>;
3997 def : Pat<(f32 (AArch64frsqrte (f32 FPR32:$Rn))),
3998 (FRSQRTEv1i32 FPR32:$Rn)>;
3999 def : Pat<(v2f32 (AArch64frsqrte (v2f32 V64:$Rn))),
4000 (FRSQRTEv2f32 V64:$Rn)>;
4001 def : Pat<(v4f32 (AArch64frsqrte (v4f32 FPR128:$Rn))),
4002 (FRSQRTEv4f32 FPR128:$Rn)>;
4003 def : Pat<(f64 (AArch64frsqrte (f64 FPR64:$Rn))),
4004 (FRSQRTEv1i64 FPR64:$Rn)>;
4005 def : Pat<(v1f64 (AArch64frsqrte (v1f64 FPR64:$Rn))),
4006 (FRSQRTEv1i64 FPR64:$Rn)>;
4007 def : Pat<(v2f64 (AArch64frsqrte (v2f64 FPR128:$Rn))),
4008 (FRSQRTEv2f64 FPR128:$Rn)>;
4010 def : Pat<(f32 (AArch64frsqrts (f32 FPR32:$Rn), (f32 FPR32:$Rm))),
4011 (FRSQRTS32 FPR32:$Rn, FPR32:$Rm)>;
4012 def : Pat<(v2f32 (AArch64frsqrts (v2f32 V64:$Rn), (v2f32 V64:$Rm))),
4013 (FRSQRTSv2f32 V64:$Rn, V64:$Rm)>;
4014 def : Pat<(v4f32 (AArch64frsqrts (v4f32 FPR128:$Rn), (v4f32 FPR128:$Rm))),
4015 (FRSQRTSv4f32 FPR128:$Rn, FPR128:$Rm)>;
4016 def : Pat<(f64 (AArch64frsqrts (f64 FPR64:$Rn), (f64 FPR64:$Rm))),
4017 (FRSQRTS64 FPR64:$Rn, FPR64:$Rm)>;
4018 def : Pat<(v2f64 (AArch64frsqrts (v2f64 FPR128:$Rn), (v2f64 FPR128:$Rm))),
4019 (FRSQRTSv2f64 FPR128:$Rn, FPR128:$Rm)>;
4021 // If an integer is about to be converted to a floating point value,
4022 // just load it on the floating point unit.
4023 // Here are the patterns for 8 and 16-bits to float.
4025 multiclass UIntToFPROLoadPat<ValueType DstTy, ValueType SrcTy,
4026 SDPatternOperator loadop, Instruction UCVTF,
4027 ROAddrMode ro, Instruction LDRW, Instruction LDRX,
4029 def : Pat<(DstTy (uint_to_fp (SrcTy
4030 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm,
4031 ro.Wext:$extend))))),
4032 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
4033 (LDRW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend),
4036 def : Pat<(DstTy (uint_to_fp (SrcTy
4037 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm,
4038 ro.Wext:$extend))))),
4039 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
4040 (LDRX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend),
4044 defm : UIntToFPROLoadPat<f32, i32, zextloadi8,
4045 UCVTFv1i32, ro8, LDRBroW, LDRBroX, bsub>;
4046 def : Pat <(f32 (uint_to_fp (i32
4047 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
4048 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
4049 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>;
4050 def : Pat <(f32 (uint_to_fp (i32
4051 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),
4052 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
4053 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>;
4054 // 16-bits -> float.
4055 defm : UIntToFPROLoadPat<f32, i32, zextloadi16,
4056 UCVTFv1i32, ro16, LDRHroW, LDRHroX, hsub>;
4057 def : Pat <(f32 (uint_to_fp (i32
4058 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
4059 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
4060 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
4061 def : Pat <(f32 (uint_to_fp (i32
4062 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),
4063 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
4064 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;
4065 // 32-bits are handled in target specific dag combine:
4066 // performIntToFpCombine.
4067 // 64-bits integer to 32-bits floating point, not possible with
4068 // UCVTF on floating point registers (both source and destination
4069 // must have the same size).
4071 // Here are the patterns for 8, 16, 32, and 64-bits to double.
4072 // 8-bits -> double.
4073 defm : UIntToFPROLoadPat<f64, i32, zextloadi8,
4074 UCVTFv1i64, ro8, LDRBroW, LDRBroX, bsub>;
4075 def : Pat <(f64 (uint_to_fp (i32
4076 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
4077 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4078 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>;
4079 def : Pat <(f64 (uint_to_fp (i32
4080 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),
4081 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4082 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>;
4083 // 16-bits -> double.
4084 defm : UIntToFPROLoadPat<f64, i32, zextloadi16,
4085 UCVTFv1i64, ro16, LDRHroW, LDRHroX, hsub>;
4086 def : Pat <(f64 (uint_to_fp (i32
4087 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
4088 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4089 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
4090 def : Pat <(f64 (uint_to_fp (i32
4091 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),
4092 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4093 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;
4094 // 32-bits -> double.
4095 defm : UIntToFPROLoadPat<f64, i32, load,
4096 UCVTFv1i64, ro32, LDRSroW, LDRSroX, ssub>;
4097 def : Pat <(f64 (uint_to_fp (i32
4098 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
4099 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4100 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub))>;
4101 def : Pat <(f64 (uint_to_fp (i32
4102 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset))))),
4103 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4104 (LDURSi GPR64sp:$Rn, simm9:$offset), ssub))>;
4105 // 64-bits -> double are handled in target specific dag combine:
4106 // performIntToFpCombine.
4108 //===----------------------------------------------------------------------===//
4109 // Advanced SIMD three different-sized vector instructions.
4110 //===----------------------------------------------------------------------===//
4112 defm ADDHN : SIMDNarrowThreeVectorBHS<0,0b0100,"addhn", int_aarch64_neon_addhn>;
4113 defm SUBHN : SIMDNarrowThreeVectorBHS<0,0b0110,"subhn", int_aarch64_neon_subhn>;
4114 defm RADDHN : SIMDNarrowThreeVectorBHS<1,0b0100,"raddhn",int_aarch64_neon_raddhn>;
4115 defm RSUBHN : SIMDNarrowThreeVectorBHS<1,0b0110,"rsubhn",int_aarch64_neon_rsubhn>;
4116 defm PMULL : SIMDDifferentThreeVectorBD<0,0b1110,"pmull",int_aarch64_neon_pmull>;
4117 defm SABAL : SIMDLongThreeVectorTiedBHSabal<0,0b0101,"sabal",
4118 int_aarch64_neon_sabd>;
4119 defm SABDL : SIMDLongThreeVectorBHSabdl<0, 0b0111, "sabdl",
4120 int_aarch64_neon_sabd>;
4121 defm SADDL : SIMDLongThreeVectorBHS< 0, 0b0000, "saddl",
4122 BinOpFrag<(add (sext node:$LHS), (sext node:$RHS))>>;
4123 defm SADDW : SIMDWideThreeVectorBHS< 0, 0b0001, "saddw",
4124 BinOpFrag<(add node:$LHS, (sext node:$RHS))>>;
4125 defm SMLAL : SIMDLongThreeVectorTiedBHS<0, 0b1000, "smlal",
4126 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
4127 defm SMLSL : SIMDLongThreeVectorTiedBHS<0, 0b1010, "smlsl",
4128 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
4129 defm SMULL : SIMDLongThreeVectorBHS<0, 0b1100, "smull", int_aarch64_neon_smull>;
4130 defm SQDMLAL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1001, "sqdmlal",
4131 int_aarch64_neon_sqadd>;
4132 defm SQDMLSL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1011, "sqdmlsl",
4133 int_aarch64_neon_sqsub>;
4134 defm SQDMULL : SIMDLongThreeVectorHS<0, 0b1101, "sqdmull",
4135 int_aarch64_neon_sqdmull>;
4136 defm SSUBL : SIMDLongThreeVectorBHS<0, 0b0010, "ssubl",
4137 BinOpFrag<(sub (sext node:$LHS), (sext node:$RHS))>>;
4138 defm SSUBW : SIMDWideThreeVectorBHS<0, 0b0011, "ssubw",
4139 BinOpFrag<(sub node:$LHS, (sext node:$RHS))>>;
4140 defm UABAL : SIMDLongThreeVectorTiedBHSabal<1, 0b0101, "uabal",
4141 int_aarch64_neon_uabd>;
4142 defm UADDL : SIMDLongThreeVectorBHS<1, 0b0000, "uaddl",
4143 BinOpFrag<(add (zext node:$LHS), (zext node:$RHS))>>;
4144 defm UADDW : SIMDWideThreeVectorBHS<1, 0b0001, "uaddw",
4145 BinOpFrag<(add node:$LHS, (zext node:$RHS))>>;
4146 defm UMLAL : SIMDLongThreeVectorTiedBHS<1, 0b1000, "umlal",
4147 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
4148 defm UMLSL : SIMDLongThreeVectorTiedBHS<1, 0b1010, "umlsl",
4149 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
4150 defm UMULL : SIMDLongThreeVectorBHS<1, 0b1100, "umull", int_aarch64_neon_umull>;
4151 defm USUBL : SIMDLongThreeVectorBHS<1, 0b0010, "usubl",
4152 BinOpFrag<(sub (zext node:$LHS), (zext node:$RHS))>>;
4153 defm USUBW : SIMDWideThreeVectorBHS< 1, 0b0011, "usubw",
4154 BinOpFrag<(sub node:$LHS, (zext node:$RHS))>>;
4156 // Additional patterns for SMULL and UMULL
4157 multiclass Neon_mul_widen_patterns<SDPatternOperator opnode,
4158 Instruction INST8B, Instruction INST4H, Instruction INST2S> {
4159 def : Pat<(v8i16 (opnode (v8i8 V64:$Rn), (v8i8 V64:$Rm))),
4160 (INST8B V64:$Rn, V64:$Rm)>;
4161 def : Pat<(v4i32 (opnode (v4i16 V64:$Rn), (v4i16 V64:$Rm))),
4162 (INST4H V64:$Rn, V64:$Rm)>;
4163 def : Pat<(v2i64 (opnode (v2i32 V64:$Rn), (v2i32 V64:$Rm))),
4164 (INST2S V64:$Rn, V64:$Rm)>;
4167 defm : Neon_mul_widen_patterns<AArch64smull, SMULLv8i8_v8i16,
4168 SMULLv4i16_v4i32, SMULLv2i32_v2i64>;
4169 defm : Neon_mul_widen_patterns<AArch64umull, UMULLv8i8_v8i16,
4170 UMULLv4i16_v4i32, UMULLv2i32_v2i64>;
4172 // Additional patterns for SMLAL/SMLSL and UMLAL/UMLSL
4173 multiclass Neon_mulacc_widen_patterns<SDPatternOperator opnode,
4174 Instruction INST8B, Instruction INST4H, Instruction INST2S> {
4175 def : Pat<(v8i16 (opnode (v8i16 V128:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm))),
4176 (INST8B V128:$Rd, V64:$Rn, V64:$Rm)>;
4177 def : Pat<(v4i32 (opnode (v4i32 V128:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm))),
4178 (INST4H V128:$Rd, V64:$Rn, V64:$Rm)>;
4179 def : Pat<(v2i64 (opnode (v2i64 V128:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm))),
4180 (INST2S V128:$Rd, V64:$Rn, V64:$Rm)>;
4183 defm : Neon_mulacc_widen_patterns<
4184 TriOpFrag<(add node:$LHS, (AArch64smull node:$MHS, node:$RHS))>,
4185 SMLALv8i8_v8i16, SMLALv4i16_v4i32, SMLALv2i32_v2i64>;
4186 defm : Neon_mulacc_widen_patterns<
4187 TriOpFrag<(add node:$LHS, (AArch64umull node:$MHS, node:$RHS))>,
4188 UMLALv8i8_v8i16, UMLALv4i16_v4i32, UMLALv2i32_v2i64>;
4189 defm : Neon_mulacc_widen_patterns<
4190 TriOpFrag<(sub node:$LHS, (AArch64smull node:$MHS, node:$RHS))>,
4191 SMLSLv8i8_v8i16, SMLSLv4i16_v4i32, SMLSLv2i32_v2i64>;
4192 defm : Neon_mulacc_widen_patterns<
4193 TriOpFrag<(sub node:$LHS, (AArch64umull node:$MHS, node:$RHS))>,
4194 UMLSLv8i8_v8i16, UMLSLv4i16_v4i32, UMLSLv2i32_v2i64>;
4196 // Patterns for 64-bit pmull
4197 def : Pat<(int_aarch64_neon_pmull64 V64:$Rn, V64:$Rm),
4198 (PMULLv1i64 V64:$Rn, V64:$Rm)>;
4199 def : Pat<(int_aarch64_neon_pmull64 (extractelt (v2i64 V128:$Rn), (i64 1)),
4200 (extractelt (v2i64 V128:$Rm), (i64 1))),
4201 (PMULLv2i64 V128:$Rn, V128:$Rm)>;
4203 // CodeGen patterns for addhn and subhn instructions, which can actually be
4204 // written in LLVM IR without too much difficulty.
4207 def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm), (i32 8))))),
4208 (ADDHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
4209 def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm),
4211 (ADDHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
4212 def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm),
4214 (ADDHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
4215 def : Pat<(concat_vectors (v8i8 V64:$Rd),
4216 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm),
4218 (ADDHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
4219 V128:$Rn, V128:$Rm)>;
4220 def : Pat<(concat_vectors (v4i16 V64:$Rd),
4221 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm),
4223 (ADDHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
4224 V128:$Rn, V128:$Rm)>;
4225 def : Pat<(concat_vectors (v2i32 V64:$Rd),
4226 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm),
4228 (ADDHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
4229 V128:$Rn, V128:$Rm)>;
4232 def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm), (i32 8))))),
4233 (SUBHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
4234 def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
4236 (SUBHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
4237 def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
4239 (SUBHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
4240 def : Pat<(concat_vectors (v8i8 V64:$Rd),
4241 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
4243 (SUBHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
4244 V128:$Rn, V128:$Rm)>;
4245 def : Pat<(concat_vectors (v4i16 V64:$Rd),
4246 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
4248 (SUBHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
4249 V128:$Rn, V128:$Rm)>;
4250 def : Pat<(concat_vectors (v2i32 V64:$Rd),
4251 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
4253 (SUBHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
4254 V128:$Rn, V128:$Rm)>;
4256 //----------------------------------------------------------------------------
4257 // AdvSIMD bitwise extract from vector instruction.
4258 //----------------------------------------------------------------------------
4260 defm EXT : SIMDBitwiseExtract<"ext">;
4262 def AdjustExtImm : SDNodeXForm<imm, [{
4263 return CurDAG->getTargetConstant(8 + N->getZExtValue(), SDLoc(N), MVT::i32);
4265 multiclass ExtPat<ValueType VT64, ValueType VT128, int N> {
4266 def : Pat<(VT64 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
4267 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
4268 def : Pat<(VT128 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
4269 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
4270 // We use EXT to handle extract_subvector to copy the upper 64-bits of a
4272 def : Pat<(VT64 (extract_subvector V128:$Rn, (i64 N))),
4273 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
4274 // A 64-bit EXT of two halves of the same 128-bit register can be done as a
4275 // single 128-bit EXT.
4276 def : Pat<(VT64 (AArch64ext (extract_subvector V128:$Rn, (i64 0)),
4277 (extract_subvector V128:$Rn, (i64 N)),
4279 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, imm:$imm), dsub)>;
4280 // A 64-bit EXT of the high half of a 128-bit register can be done using a
4281 // 128-bit EXT of the whole register with an adjustment to the immediate. The
4282 // top half of the other operand will be unset, but that doesn't matter as it
4283 // will not be used.
4284 def : Pat<(VT64 (AArch64ext (extract_subvector V128:$Rn, (i64 N)),
4287 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn,
4288 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
4289 (AdjustExtImm imm:$imm)), dsub)>;
4292 defm : ExtPat<v8i8, v16i8, 8>;
4293 defm : ExtPat<v4i16, v8i16, 4>;
4294 defm : ExtPat<v4f16, v8f16, 4>;
4295 defm : ExtPat<v2i32, v4i32, 2>;
4296 defm : ExtPat<v2f32, v4f32, 2>;
4297 defm : ExtPat<v1i64, v2i64, 1>;
4298 defm : ExtPat<v1f64, v2f64, 1>;
4300 //----------------------------------------------------------------------------
4301 // AdvSIMD zip vector
4302 //----------------------------------------------------------------------------
4304 defm TRN1 : SIMDZipVector<0b010, "trn1", AArch64trn1>;
4305 defm TRN2 : SIMDZipVector<0b110, "trn2", AArch64trn2>;
4306 defm UZP1 : SIMDZipVector<0b001, "uzp1", AArch64uzp1>;
4307 defm UZP2 : SIMDZipVector<0b101, "uzp2", AArch64uzp2>;
4308 defm ZIP1 : SIMDZipVector<0b011, "zip1", AArch64zip1>;
4309 defm ZIP2 : SIMDZipVector<0b111, "zip2", AArch64zip2>;
4311 //----------------------------------------------------------------------------
4312 // AdvSIMD TBL/TBX instructions
4313 //----------------------------------------------------------------------------
4315 defm TBL : SIMDTableLookup< 0, "tbl">;
4316 defm TBX : SIMDTableLookupTied<1, "tbx">;
4318 def : Pat<(v8i8 (int_aarch64_neon_tbl1 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
4319 (TBLv8i8One VecListOne128:$Rn, V64:$Ri)>;
4320 def : Pat<(v16i8 (int_aarch64_neon_tbl1 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
4321 (TBLv16i8One V128:$Ri, V128:$Rn)>;
4323 def : Pat<(v8i8 (int_aarch64_neon_tbx1 (v8i8 V64:$Rd),
4324 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
4325 (TBXv8i8One V64:$Rd, VecListOne128:$Rn, V64:$Ri)>;
4326 def : Pat<(v16i8 (int_aarch64_neon_tbx1 (v16i8 V128:$Rd),
4327 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
4328 (TBXv16i8One V128:$Rd, V128:$Ri, V128:$Rn)>;
4331 //----------------------------------------------------------------------------
4332 // AdvSIMD scalar CPY instruction
4333 //----------------------------------------------------------------------------
4335 defm CPY : SIMDScalarCPY<"cpy">;
4337 //----------------------------------------------------------------------------
4338 // AdvSIMD scalar pairwise instructions
4339 //----------------------------------------------------------------------------
4341 defm ADDP : SIMDPairwiseScalarD<0, 0b11011, "addp">;
4342 defm FADDP : SIMDFPPairwiseScalar<0, 0b01101, "faddp">;
4343 defm FMAXNMP : SIMDFPPairwiseScalar<0, 0b01100, "fmaxnmp">;
4344 defm FMAXP : SIMDFPPairwiseScalar<0, 0b01111, "fmaxp">;
4345 defm FMINNMP : SIMDFPPairwiseScalar<1, 0b01100, "fminnmp">;
4346 defm FMINP : SIMDFPPairwiseScalar<1, 0b01111, "fminp">;
4347 def : Pat<(v2i64 (AArch64saddv V128:$Rn)),
4348 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), (ADDPv2i64p V128:$Rn), dsub)>;
4349 def : Pat<(v2i64 (AArch64uaddv V128:$Rn)),
4350 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), (ADDPv2i64p V128:$Rn), dsub)>;
4351 def : Pat<(f32 (int_aarch64_neon_faddv (v2f32 V64:$Rn))),
4352 (FADDPv2i32p V64:$Rn)>;
4353 def : Pat<(f32 (int_aarch64_neon_faddv (v4f32 V128:$Rn))),
4354 (FADDPv2i32p (EXTRACT_SUBREG (FADDPv4f32 V128:$Rn, V128:$Rn), dsub))>;
4355 def : Pat<(f64 (int_aarch64_neon_faddv (v2f64 V128:$Rn))),
4356 (FADDPv2i64p V128:$Rn)>;
4357 def : Pat<(f32 (int_aarch64_neon_fmaxnmv (v2f32 V64:$Rn))),
4358 (FMAXNMPv2i32p V64:$Rn)>;
4359 def : Pat<(f64 (int_aarch64_neon_fmaxnmv (v2f64 V128:$Rn))),
4360 (FMAXNMPv2i64p V128:$Rn)>;
4361 def : Pat<(f32 (int_aarch64_neon_fmaxv (v2f32 V64:$Rn))),
4362 (FMAXPv2i32p V64:$Rn)>;
4363 def : Pat<(f64 (int_aarch64_neon_fmaxv (v2f64 V128:$Rn))),
4364 (FMAXPv2i64p V128:$Rn)>;
4365 def : Pat<(f32 (int_aarch64_neon_fminnmv (v2f32 V64:$Rn))),
4366 (FMINNMPv2i32p V64:$Rn)>;
4367 def : Pat<(f64 (int_aarch64_neon_fminnmv (v2f64 V128:$Rn))),
4368 (FMINNMPv2i64p V128:$Rn)>;
4369 def : Pat<(f32 (int_aarch64_neon_fminv (v2f32 V64:$Rn))),
4370 (FMINPv2i32p V64:$Rn)>;
4371 def : Pat<(f64 (int_aarch64_neon_fminv (v2f64 V128:$Rn))),
4372 (FMINPv2i64p V128:$Rn)>;
4374 //----------------------------------------------------------------------------
4375 // AdvSIMD INS/DUP instructions
4376 //----------------------------------------------------------------------------
4378 def DUPv8i8gpr : SIMDDupFromMain<0, {?,?,?,?,1}, ".8b", v8i8, V64, GPR32>;
4379 def DUPv16i8gpr : SIMDDupFromMain<1, {?,?,?,?,1}, ".16b", v16i8, V128, GPR32>;
4380 def DUPv4i16gpr : SIMDDupFromMain<0, {?,?,?,1,0}, ".4h", v4i16, V64, GPR32>;
4381 def DUPv8i16gpr : SIMDDupFromMain<1, {?,?,?,1,0}, ".8h", v8i16, V128, GPR32>;
4382 def DUPv2i32gpr : SIMDDupFromMain<0, {?,?,1,0,0}, ".2s", v2i32, V64, GPR32>;
4383 def DUPv4i32gpr : SIMDDupFromMain<1, {?,?,1,0,0}, ".4s", v4i32, V128, GPR32>;
4384 def DUPv2i64gpr : SIMDDupFromMain<1, {?,1,0,0,0}, ".2d", v2i64, V128, GPR64>;
4386 def DUPv2i64lane : SIMDDup64FromElement;
4387 def DUPv2i32lane : SIMDDup32FromElement<0, ".2s", v2i32, V64>;
4388 def DUPv4i32lane : SIMDDup32FromElement<1, ".4s", v4i32, V128>;
4389 def DUPv4i16lane : SIMDDup16FromElement<0, ".4h", v4i16, V64>;
4390 def DUPv8i16lane : SIMDDup16FromElement<1, ".8h", v8i16, V128>;
4391 def DUPv8i8lane : SIMDDup8FromElement <0, ".8b", v8i8, V64>;
4392 def DUPv16i8lane : SIMDDup8FromElement <1, ".16b", v16i8, V128>;
4394 // DUP from a 64-bit register to a 64-bit register is just a copy
4395 def : Pat<(v1i64 (AArch64dup (i64 GPR64:$Rn))),
4396 (COPY_TO_REGCLASS GPR64:$Rn, FPR64)>;
4397 def : Pat<(v1f64 (AArch64dup (f64 FPR64:$Rn))),
4398 (COPY_TO_REGCLASS FPR64:$Rn, FPR64)>;
4400 def : Pat<(v2f32 (AArch64dup (f32 FPR32:$Rn))),
4401 (v2f32 (DUPv2i32lane
4402 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
4404 def : Pat<(v4f32 (AArch64dup (f32 FPR32:$Rn))),
4405 (v4f32 (DUPv4i32lane
4406 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
4408 def : Pat<(v2f64 (AArch64dup (f64 FPR64:$Rn))),
4409 (v2f64 (DUPv2i64lane
4410 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rn, dsub),
4412 def : Pat<(v4f16 (AArch64dup (f16 FPR16:$Rn))),
4413 (v4f16 (DUPv4i16lane
4414 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub),
4416 def : Pat<(v8f16 (AArch64dup (f16 FPR16:$Rn))),
4417 (v8f16 (DUPv8i16lane
4418 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub),
4421 def : Pat<(v4f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)),
4422 (DUPv4i16lane V128:$Rn, VectorIndexH:$imm)>;
4423 def : Pat<(v8f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)),
4424 (DUPv8i16lane V128:$Rn, VectorIndexH:$imm)>;
4426 def : Pat<(v2f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
4427 (DUPv2i32lane V128:$Rn, VectorIndexS:$imm)>;
4428 def : Pat<(v4f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
4429 (DUPv4i32lane V128:$Rn, VectorIndexS:$imm)>;
4430 def : Pat<(v2f64 (AArch64duplane64 (v2f64 V128:$Rn), VectorIndexD:$imm)),
4431 (DUPv2i64lane V128:$Rn, VectorIndexD:$imm)>;
4433 // If there's an (AArch64dup (vector_extract ...) ...), we can use a duplane
4434 // instruction even if the types don't match: we just have to remap the lane
4435 // carefully. N.b. this trick only applies to truncations.
4436 def VecIndex_x2 : SDNodeXForm<imm, [{
4437 return CurDAG->getTargetConstant(2 * N->getZExtValue(), SDLoc(N), MVT::i64);
4439 def VecIndex_x4 : SDNodeXForm<imm, [{
4440 return CurDAG->getTargetConstant(4 * N->getZExtValue(), SDLoc(N), MVT::i64);
4442 def VecIndex_x8 : SDNodeXForm<imm, [{
4443 return CurDAG->getTargetConstant(8 * N->getZExtValue(), SDLoc(N), MVT::i64);
4446 multiclass DUPWithTruncPats<ValueType ResVT, ValueType Src64VT,
4447 ValueType Src128VT, ValueType ScalVT,
4448 Instruction DUP, SDNodeXForm IdxXFORM> {
4449 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src128VT V128:$Rn),
4451 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
4453 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src64VT V64:$Rn),
4455 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
4458 defm : DUPWithTruncPats<v8i8, v4i16, v8i16, i32, DUPv8i8lane, VecIndex_x2>;
4459 defm : DUPWithTruncPats<v8i8, v2i32, v4i32, i32, DUPv8i8lane, VecIndex_x4>;
4460 defm : DUPWithTruncPats<v4i16, v2i32, v4i32, i32, DUPv4i16lane, VecIndex_x2>;
4462 defm : DUPWithTruncPats<v16i8, v4i16, v8i16, i32, DUPv16i8lane, VecIndex_x2>;
4463 defm : DUPWithTruncPats<v16i8, v2i32, v4i32, i32, DUPv16i8lane, VecIndex_x4>;
4464 defm : DUPWithTruncPats<v8i16, v2i32, v4i32, i32, DUPv8i16lane, VecIndex_x2>;
4466 multiclass DUPWithTrunci64Pats<ValueType ResVT, Instruction DUP,
4467 SDNodeXForm IdxXFORM> {
4468 def : Pat<(ResVT (AArch64dup (i32 (trunc (extractelt (v2i64 V128:$Rn),
4470 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
4472 def : Pat<(ResVT (AArch64dup (i32 (trunc (extractelt (v1i64 V64:$Rn),
4474 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
4477 defm : DUPWithTrunci64Pats<v8i8, DUPv8i8lane, VecIndex_x8>;
4478 defm : DUPWithTrunci64Pats<v4i16, DUPv4i16lane, VecIndex_x4>;
4479 defm : DUPWithTrunci64Pats<v2i32, DUPv2i32lane, VecIndex_x2>;
4481 defm : DUPWithTrunci64Pats<v16i8, DUPv16i8lane, VecIndex_x8>;
4482 defm : DUPWithTrunci64Pats<v8i16, DUPv8i16lane, VecIndex_x4>;
4483 defm : DUPWithTrunci64Pats<v4i32, DUPv4i32lane, VecIndex_x2>;
4485 // SMOV and UMOV definitions, with some extra patterns for convenience
4489 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
4490 (i32 (SMOVvi8to32 V128:$Rn, VectorIndexB:$idx))>;
4491 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
4492 (i64 (SMOVvi8to64 V128:$Rn, VectorIndexB:$idx))>;
4493 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
4494 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
4495 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
4496 (i64 (SMOVvi16to64 V128:$Rn, VectorIndexH:$idx))>;
4497 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
4498 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
4499 def : Pat<(sext (i32 (vector_extract (v4i32 V128:$Rn), VectorIndexS:$idx))),
4500 (i64 (SMOVvi32to64 V128:$Rn, VectorIndexS:$idx))>;
4502 def : Pat<(sext_inreg (i64 (anyext (i32 (vector_extract (v16i8 V128:$Rn),
4503 VectorIndexB:$idx)))), i8),
4504 (i64 (SMOVvi8to64 V128:$Rn, VectorIndexB:$idx))>;
4505 def : Pat<(sext_inreg (i64 (anyext (i32 (vector_extract (v8i16 V128:$Rn),
4506 VectorIndexH:$idx)))), i16),
4507 (i64 (SMOVvi16to64 V128:$Rn, VectorIndexH:$idx))>;
4509 // Extracting i8 or i16 elements will have the zero-extend transformed to
4510 // an 'and' mask by type legalization since neither i8 nor i16 are legal types
4511 // for AArch64. Match these patterns here since UMOV already zeroes out the high
4512 // bits of the destination register.
4513 def : Pat<(and (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx),
4515 (i32 (UMOVvi8 V128:$Rn, VectorIndexB:$idx))>;
4516 def : Pat<(and (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),
4518 (i32 (UMOVvi16 V128:$Rn, VectorIndexH:$idx))>;
4522 def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)),
4523 (SUBREG_TO_REG (i32 0),
4524 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
4525 def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)),
4526 (SUBREG_TO_REG (i32 0),
4527 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
4529 def : Pat<(v8i16 (scalar_to_vector GPR32:$Rn)),
4530 (SUBREG_TO_REG (i32 0),
4531 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
4532 def : Pat<(v4i16 (scalar_to_vector GPR32:$Rn)),
4533 (SUBREG_TO_REG (i32 0),
4534 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
4536 def : Pat<(v4f16 (scalar_to_vector (f16 FPR16:$Rn))),
4537 (INSERT_SUBREG (v4f16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>;
4538 def : Pat<(v8f16 (scalar_to_vector (f16 FPR16:$Rn))),
4539 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>;
4541 def : Pat<(v2i32 (scalar_to_vector (i32 FPR32:$Rn))),
4542 (v2i32 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
4543 (i32 FPR32:$Rn), ssub))>;
4544 def : Pat<(v4i32 (scalar_to_vector (i32 FPR32:$Rn))),
4545 (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
4546 (i32 FPR32:$Rn), ssub))>;
4548 def : Pat<(v2i64 (scalar_to_vector (i64 FPR64:$Rn))),
4549 (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
4550 (i64 FPR64:$Rn), dsub))>;
4552 def : Pat<(v4f16 (scalar_to_vector (f16 FPR16:$Rn))),
4553 (INSERT_SUBREG (v4f16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>;
4554 def : Pat<(v8f16 (scalar_to_vector (f16 FPR16:$Rn))),
4555 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>;
4557 def : Pat<(v4f32 (scalar_to_vector (f32 FPR32:$Rn))),
4558 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
4559 def : Pat<(v2f32 (scalar_to_vector (f32 FPR32:$Rn))),
4560 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
4562 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$Rn))),
4563 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rn, dsub)>;
4565 def : Pat<(v4f16 (vector_insert (v4f16 V64:$Rn),
4566 (f16 FPR16:$Rm), (i64 VectorIndexS:$imm))),
4569 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), V64:$Rn, dsub)),
4571 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)),
4575 def : Pat<(v8f16 (vector_insert (v8f16 V128:$Rn),
4576 (f16 FPR16:$Rm), (i64 VectorIndexH:$imm))),
4578 V128:$Rn, VectorIndexH:$imm,
4579 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)),
4582 def : Pat<(v2f32 (vector_insert (v2f32 V64:$Rn),
4583 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
4586 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), V64:$Rn, dsub)),
4588 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
4591 def : Pat<(v4f32 (vector_insert (v4f32 V128:$Rn),
4592 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
4594 V128:$Rn, VectorIndexS:$imm,
4595 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
4597 def : Pat<(v2f64 (vector_insert (v2f64 V128:$Rn),
4598 (f64 FPR64:$Rm), (i64 VectorIndexD:$imm))),
4600 V128:$Rn, VectorIndexD:$imm,
4601 (v2f64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rm, dsub)),
4604 // Copy an element at a constant index in one vector into a constant indexed
4605 // element of another.
4606 // FIXME refactor to a shared class/dev parameterized on vector type, vector
4607 // index type and INS extension
4608 def : Pat<(v16i8 (int_aarch64_neon_vcopy_lane
4609 (v16i8 V128:$Vd), VectorIndexB:$idx, (v16i8 V128:$Vs),
4610 VectorIndexB:$idx2)),
4612 V128:$Vd, VectorIndexB:$idx, V128:$Vs, VectorIndexB:$idx2)
4614 def : Pat<(v8i16 (int_aarch64_neon_vcopy_lane
4615 (v8i16 V128:$Vd), VectorIndexH:$idx, (v8i16 V128:$Vs),
4616 VectorIndexH:$idx2)),
4618 V128:$Vd, VectorIndexH:$idx, V128:$Vs, VectorIndexH:$idx2)
4620 def : Pat<(v4i32 (int_aarch64_neon_vcopy_lane
4621 (v4i32 V128:$Vd), VectorIndexS:$idx, (v4i32 V128:$Vs),
4622 VectorIndexS:$idx2)),
4624 V128:$Vd, VectorIndexS:$idx, V128:$Vs, VectorIndexS:$idx2)
4626 def : Pat<(v2i64 (int_aarch64_neon_vcopy_lane
4627 (v2i64 V128:$Vd), VectorIndexD:$idx, (v2i64 V128:$Vs),
4628 VectorIndexD:$idx2)),
4630 V128:$Vd, VectorIndexD:$idx, V128:$Vs, VectorIndexD:$idx2)
4633 multiclass Neon_INS_elt_pattern<ValueType VT128, ValueType VT64,
4634 ValueType VTScal, Instruction INS> {
4635 def : Pat<(VT128 (vector_insert V128:$src,
4636 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
4638 (INS V128:$src, imm:$Immd, V128:$Rn, imm:$Immn)>;
4640 def : Pat<(VT128 (vector_insert V128:$src,
4641 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
4643 (INS V128:$src, imm:$Immd,
4644 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn)>;
4646 def : Pat<(VT64 (vector_insert V64:$src,
4647 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
4649 (EXTRACT_SUBREG (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub),
4650 imm:$Immd, V128:$Rn, imm:$Immn),
4653 def : Pat<(VT64 (vector_insert V64:$src,
4654 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
4657 (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), imm:$Immd,
4658 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn),
4662 defm : Neon_INS_elt_pattern<v8f16, v4f16, f16, INSvi16lane>;
4663 defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, INSvi32lane>;
4664 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, INSvi64lane>;
4667 // Floating point vector extractions are codegen'd as either a sequence of
4668 // subregister extractions, or a MOV (aka CPY here, alias for DUP) if
4669 // the lane number is anything other than zero.
4670 def : Pat<(vector_extract (v2f64 V128:$Rn), 0),
4671 (f64 (EXTRACT_SUBREG V128:$Rn, dsub))>;
4672 def : Pat<(vector_extract (v4f32 V128:$Rn), 0),
4673 (f32 (EXTRACT_SUBREG V128:$Rn, ssub))>;
4674 def : Pat<(vector_extract (v8f16 V128:$Rn), 0),
4675 (f16 (EXTRACT_SUBREG V128:$Rn, hsub))>;
4677 def : Pat<(vector_extract (v2f64 V128:$Rn), VectorIndexD:$idx),
4678 (f64 (CPYi64 V128:$Rn, VectorIndexD:$idx))>;
4679 def : Pat<(vector_extract (v4f32 V128:$Rn), VectorIndexS:$idx),
4680 (f32 (CPYi32 V128:$Rn, VectorIndexS:$idx))>;
4681 def : Pat<(vector_extract (v8f16 V128:$Rn), VectorIndexH:$idx),
4682 (f16 (CPYi16 V128:$Rn, VectorIndexH:$idx))>;
4684 // All concat_vectors operations are canonicalised to act on i64 vectors for
4685 // AArch64. In the general case we need an instruction, which had just as well be
4687 class ConcatPat<ValueType DstTy, ValueType SrcTy>
4688 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rd), V64:$Rn)),
4689 (INSvi64lane (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 1,
4690 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub), 0)>;
4692 def : ConcatPat<v2i64, v1i64>;
4693 def : ConcatPat<v2f64, v1f64>;
4694 def : ConcatPat<v4i32, v2i32>;
4695 def : ConcatPat<v4f32, v2f32>;
4696 def : ConcatPat<v8i16, v4i16>;
4697 def : ConcatPat<v8f16, v4f16>;
4698 def : ConcatPat<v16i8, v8i8>;
4700 // If the high lanes are undef, though, we can just ignore them:
4701 class ConcatUndefPat<ValueType DstTy, ValueType SrcTy>
4702 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rn), undef)),
4703 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub)>;
4705 def : ConcatUndefPat<v2i64, v1i64>;
4706 def : ConcatUndefPat<v2f64, v1f64>;
4707 def : ConcatUndefPat<v4i32, v2i32>;
4708 def : ConcatUndefPat<v4f32, v2f32>;
4709 def : ConcatUndefPat<v8i16, v4i16>;
4710 def : ConcatUndefPat<v16i8, v8i8>;
4712 //----------------------------------------------------------------------------
4713 // AdvSIMD across lanes instructions
4714 //----------------------------------------------------------------------------
4716 defm ADDV : SIMDAcrossLanesBHS<0, 0b11011, "addv">;
4717 defm SMAXV : SIMDAcrossLanesBHS<0, 0b01010, "smaxv">;
4718 defm SMINV : SIMDAcrossLanesBHS<0, 0b11010, "sminv">;
4719 defm UMAXV : SIMDAcrossLanesBHS<1, 0b01010, "umaxv">;
4720 defm UMINV : SIMDAcrossLanesBHS<1, 0b11010, "uminv">;
4721 defm SADDLV : SIMDAcrossLanesHSD<0, 0b00011, "saddlv">;
4722 defm UADDLV : SIMDAcrossLanesHSD<1, 0b00011, "uaddlv">;
4723 defm FMAXNMV : SIMDFPAcrossLanes<0b01100, 0, "fmaxnmv", int_aarch64_neon_fmaxnmv>;
4724 defm FMAXV : SIMDFPAcrossLanes<0b01111, 0, "fmaxv", int_aarch64_neon_fmaxv>;
4725 defm FMINNMV : SIMDFPAcrossLanes<0b01100, 1, "fminnmv", int_aarch64_neon_fminnmv>;
4726 defm FMINV : SIMDFPAcrossLanes<0b01111, 1, "fminv", int_aarch64_neon_fminv>;
4728 // Patterns for across-vector intrinsics, that have a node equivalent, that
4729 // returns a vector (with only the low lane defined) instead of a scalar.
4730 // In effect, opNode is the same as (scalar_to_vector (IntNode)).
4731 multiclass SIMDAcrossLanesIntrinsic<string baseOpc,
4732 SDPatternOperator opNode> {
4733 // If a lane instruction caught the vector_extract around opNode, we can
4734 // directly match the latter to the instruction.
4735 def : Pat<(v8i8 (opNode V64:$Rn)),
4736 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
4737 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub)>;
4738 def : Pat<(v16i8 (opNode V128:$Rn)),
4739 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4740 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub)>;
4741 def : Pat<(v4i16 (opNode V64:$Rn)),
4742 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
4743 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub)>;
4744 def : Pat<(v8i16 (opNode V128:$Rn)),
4745 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
4746 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub)>;
4747 def : Pat<(v4i32 (opNode V128:$Rn)),
4748 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
4749 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub)>;
4752 // If none did, fallback to the explicit patterns, consuming the vector_extract.
4753 def : Pat<(i32 (vector_extract (insert_subvector undef, (v8i8 (opNode V64:$Rn)),
4754 (i32 0)), (i64 0))),
4755 (EXTRACT_SUBREG (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
4756 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn),
4758 def : Pat<(i32 (vector_extract (v16i8 (opNode V128:$Rn)), (i64 0))),
4759 (EXTRACT_SUBREG (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4760 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn),
4762 def : Pat<(i32 (vector_extract (insert_subvector undef,
4763 (v4i16 (opNode V64:$Rn)), (i32 0)), (i64 0))),
4764 (EXTRACT_SUBREG (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
4765 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn),
4767 def : Pat<(i32 (vector_extract (v8i16 (opNode V128:$Rn)), (i64 0))),
4768 (EXTRACT_SUBREG (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
4769 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn),
4771 def : Pat<(i32 (vector_extract (v4i32 (opNode V128:$Rn)), (i64 0))),
4772 (EXTRACT_SUBREG (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
4773 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn),
4778 multiclass SIMDAcrossLanesSignedIntrinsic<string baseOpc,
4779 SDPatternOperator opNode>
4780 : SIMDAcrossLanesIntrinsic<baseOpc, opNode> {
4781 // If there is a sign extension after this intrinsic, consume it as smov already
4783 def : Pat<(i32 (sext_inreg (i32 (vector_extract (insert_subvector undef,
4784 (opNode (v8i8 V64:$Rn)), (i32 0)), (i64 0))), i8)),
4786 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4787 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
4789 def : Pat<(i32 (sext_inreg (i32 (vector_extract
4790 (opNode (v16i8 V128:$Rn)), (i64 0))), i8)),
4792 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4793 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
4795 def : Pat<(i32 (sext_inreg (i32 (vector_extract (insert_subvector undef,
4796 (opNode (v4i16 V64:$Rn)), (i32 0)), (i64 0))), i16)),
4798 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4799 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
4801 def : Pat<(i32 (sext_inreg (i32 (vector_extract
4802 (opNode (v8i16 V128:$Rn)), (i64 0))), i16)),
4804 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4805 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
4809 multiclass SIMDAcrossLanesUnsignedIntrinsic<string baseOpc,
4810 SDPatternOperator opNode>
4811 : SIMDAcrossLanesIntrinsic<baseOpc, opNode> {
4812 // If there is a masking operation keeping only what has been actually
4813 // generated, consume it.
4814 def : Pat<(i32 (and (i32 (vector_extract (insert_subvector undef,
4815 (opNode (v8i8 V64:$Rn)), (i32 0)), (i64 0))), maski8_or_more)),
4816 (i32 (EXTRACT_SUBREG
4817 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4818 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
4820 def : Pat<(i32 (and (i32 (vector_extract (opNode (v16i8 V128:$Rn)), (i64 0))),
4822 (i32 (EXTRACT_SUBREG
4823 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4824 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
4826 def : Pat<(i32 (and (i32 (vector_extract (insert_subvector undef,
4827 (opNode (v4i16 V64:$Rn)), (i32 0)), (i64 0))), maski16_or_more)),
4828 (i32 (EXTRACT_SUBREG
4829 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4830 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
4832 def : Pat<(i32 (and (i32 (vector_extract (opNode (v8i16 V128:$Rn)), (i64 0))),
4834 (i32 (EXTRACT_SUBREG
4835 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4836 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
4840 defm : SIMDAcrossLanesSignedIntrinsic<"ADDV", AArch64saddv>;
4841 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
4842 def : Pat<(v2i32 (AArch64saddv (v2i32 V64:$Rn))),
4843 (ADDPv2i32 V64:$Rn, V64:$Rn)>;
4845 defm : SIMDAcrossLanesUnsignedIntrinsic<"ADDV", AArch64uaddv>;
4846 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
4847 def : Pat<(v2i32 (AArch64uaddv (v2i32 V64:$Rn))),
4848 (ADDPv2i32 V64:$Rn, V64:$Rn)>;
4850 defm : SIMDAcrossLanesSignedIntrinsic<"SMAXV", AArch64smaxv>;
4851 def : Pat<(v2i32 (AArch64smaxv (v2i32 V64:$Rn))),
4852 (SMAXPv2i32 V64:$Rn, V64:$Rn)>;
4854 defm : SIMDAcrossLanesSignedIntrinsic<"SMINV", AArch64sminv>;
4855 def : Pat<(v2i32 (AArch64sminv (v2i32 V64:$Rn))),
4856 (SMINPv2i32 V64:$Rn, V64:$Rn)>;
4858 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMAXV", AArch64umaxv>;
4859 def : Pat<(v2i32 (AArch64umaxv (v2i32 V64:$Rn))),
4860 (UMAXPv2i32 V64:$Rn, V64:$Rn)>;
4862 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMINV", AArch64uminv>;
4863 def : Pat<(v2i32 (AArch64uminv (v2i32 V64:$Rn))),
4864 (UMINPv2i32 V64:$Rn, V64:$Rn)>;
4866 multiclass SIMDAcrossLanesSignedLongIntrinsic<string baseOpc, Intrinsic intOp> {
4867 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
4869 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4870 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
4872 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
4874 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4875 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
4878 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
4879 (i32 (EXTRACT_SUBREG
4880 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4881 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
4883 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
4884 (i32 (EXTRACT_SUBREG
4885 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4886 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
4889 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
4890 (i64 (EXTRACT_SUBREG
4891 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4892 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
4896 multiclass SIMDAcrossLanesUnsignedLongIntrinsic<string baseOpc,
4898 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
4899 (i32 (EXTRACT_SUBREG
4900 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4901 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
4903 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
4904 (i32 (EXTRACT_SUBREG
4905 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4906 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
4909 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
4910 (i32 (EXTRACT_SUBREG
4911 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4912 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
4914 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
4915 (i32 (EXTRACT_SUBREG
4916 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4917 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
4920 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
4921 (i64 (EXTRACT_SUBREG
4922 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4923 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
4927 defm : SIMDAcrossLanesSignedLongIntrinsic<"SADDLV", int_aarch64_neon_saddlv>;
4928 defm : SIMDAcrossLanesUnsignedLongIntrinsic<"UADDLV", int_aarch64_neon_uaddlv>;
4930 // The vaddlv_s32 intrinsic gets mapped to SADDLP.
4931 def : Pat<(i64 (int_aarch64_neon_saddlv (v2i32 V64:$Rn))),
4932 (i64 (EXTRACT_SUBREG
4933 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4934 (SADDLPv2i32_v1i64 V64:$Rn), dsub),
4936 // The vaddlv_u32 intrinsic gets mapped to UADDLP.
4937 def : Pat<(i64 (int_aarch64_neon_uaddlv (v2i32 V64:$Rn))),
4938 (i64 (EXTRACT_SUBREG
4939 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4940 (UADDLPv2i32_v1i64 V64:$Rn), dsub),
4943 //------------------------------------------------------------------------------
4944 // AdvSIMD modified immediate instructions
4945 //------------------------------------------------------------------------------
4948 defm BIC : SIMDModifiedImmVectorShiftTied<1, 0b11, 0b01, "bic", AArch64bici>;
4950 defm ORR : SIMDModifiedImmVectorShiftTied<0, 0b11, 0b01, "orr", AArch64orri>;
4952 def : InstAlias<"bic $Vd.4h, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0)>;
4953 def : InstAlias<"bic $Vd.8h, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>;
4954 def : InstAlias<"bic $Vd.2s, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0)>;
4955 def : InstAlias<"bic $Vd.4s, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0)>;
4957 def : InstAlias<"bic.4h $Vd, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0)>;
4958 def : InstAlias<"bic.8h $Vd, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>;
4959 def : InstAlias<"bic.2s $Vd, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0)>;
4960 def : InstAlias<"bic.4s $Vd, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0)>;
4962 def : InstAlias<"orr $Vd.4h, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0)>;
4963 def : InstAlias<"orr $Vd.8h, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0)>;
4964 def : InstAlias<"orr $Vd.2s, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0)>;
4965 def : InstAlias<"orr $Vd.4s, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>;
4967 def : InstAlias<"orr.4h $Vd, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0)>;
4968 def : InstAlias<"orr.8h $Vd, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0)>;
4969 def : InstAlias<"orr.2s $Vd, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0)>;
4970 def : InstAlias<"orr.4s $Vd, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>;
4973 def FMOVv2f64_ns : SIMDModifiedImmVectorNoShift<1, 1, 0, 0b1111, V128, fpimm8,
4975 [(set (v2f64 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4976 def FMOVv2f32_ns : SIMDModifiedImmVectorNoShift<0, 0, 0, 0b1111, V64, fpimm8,
4978 [(set (v2f32 V64:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4979 def FMOVv4f32_ns : SIMDModifiedImmVectorNoShift<1, 0, 0, 0b1111, V128, fpimm8,
4981 [(set (v4f32 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4982 let Predicates = [HasNEON, HasFullFP16] in {
4983 def FMOVv4f16_ns : SIMDModifiedImmVectorNoShift<0, 0, 1, 0b1111, V64, fpimm8,
4985 [(set (v4f16 V64:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4986 def FMOVv8f16_ns : SIMDModifiedImmVectorNoShift<1, 0, 1, 0b1111, V128, fpimm8,
4988 [(set (v8f16 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4989 } // Predicates = [HasNEON, HasFullFP16]
4993 // EDIT byte mask: scalar
4994 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
4995 def MOVID : SIMDModifiedImmScalarNoShift<0, 1, 0b1110, "movi",
4996 [(set FPR64:$Rd, simdimmtype10:$imm8)]>;
4997 // The movi_edit node has the immediate value already encoded, so we use
4998 // a plain imm0_255 here.
4999 def : Pat<(f64 (AArch64movi_edit imm0_255:$shift)),
5000 (MOVID imm0_255:$shift)>;
5002 // EDIT byte mask: 2d
5004 // The movi_edit node has the immediate value already encoded, so we use
5005 // a plain imm0_255 in the pattern
5006 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
5007 def MOVIv2d_ns : SIMDModifiedImmVectorNoShift<1, 1, 0, 0b1110, V128,
5010 [(set (v2i64 V128:$Rd), (AArch64movi_edit imm0_255:$imm8))]>;
5012 def : Pat<(v2i64 immAllZerosV), (MOVIv2d_ns (i32 0))>;
5013 def : Pat<(v4i32 immAllZerosV), (MOVIv2d_ns (i32 0))>;
5014 def : Pat<(v8i16 immAllZerosV), (MOVIv2d_ns (i32 0))>;
5015 def : Pat<(v16i8 immAllZerosV), (MOVIv2d_ns (i32 0))>;
5017 def : Pat<(v2i64 immAllOnesV), (MOVIv2d_ns (i32 255))>;
5018 def : Pat<(v4i32 immAllOnesV), (MOVIv2d_ns (i32 255))>;
5019 def : Pat<(v8i16 immAllOnesV), (MOVIv2d_ns (i32 255))>;
5020 def : Pat<(v16i8 immAllOnesV), (MOVIv2d_ns (i32 255))>;
5022 // Set 64-bit vectors to all 0/1 by extracting from a 128-bit register as the
5023 // extract is free and this gives better MachineCSE results.
5024 def : Pat<(v1i64 immAllZerosV), (EXTRACT_SUBREG (MOVIv2d_ns (i32 0)), dsub)>;
5025 def : Pat<(v2i32 immAllZerosV), (EXTRACT_SUBREG (MOVIv2d_ns (i32 0)), dsub)>;
5026 def : Pat<(v4i16 immAllZerosV), (EXTRACT_SUBREG (MOVIv2d_ns (i32 0)), dsub)>;
5027 def : Pat<(v8i8 immAllZerosV), (EXTRACT_SUBREG (MOVIv2d_ns (i32 0)), dsub)>;
5029 def : Pat<(v1i64 immAllOnesV), (EXTRACT_SUBREG (MOVIv2d_ns (i32 255)), dsub)>;
5030 def : Pat<(v2i32 immAllOnesV), (EXTRACT_SUBREG (MOVIv2d_ns (i32 255)), dsub)>;
5031 def : Pat<(v4i16 immAllOnesV), (EXTRACT_SUBREG (MOVIv2d_ns (i32 255)), dsub)>;
5032 def : Pat<(v8i8 immAllOnesV), (EXTRACT_SUBREG (MOVIv2d_ns (i32 255)), dsub)>;
5034 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
5035 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
5036 defm MOVI : SIMDModifiedImmVectorShift<0, 0b10, 0b00, "movi">;
5038 def : InstAlias<"movi $Vd.4h, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
5039 def : InstAlias<"movi $Vd.8h, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
5040 def : InstAlias<"movi $Vd.2s, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
5041 def : InstAlias<"movi $Vd.4s, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
5043 def : InstAlias<"movi.4h $Vd, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
5044 def : InstAlias<"movi.8h $Vd, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
5045 def : InstAlias<"movi.2s $Vd, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
5046 def : InstAlias<"movi.4s $Vd, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
5048 def : Pat<(v2i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
5049 (MOVIv2i32 imm0_255:$imm8, imm:$shift)>;
5050 def : Pat<(v4i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
5051 (MOVIv4i32 imm0_255:$imm8, imm:$shift)>;
5052 def : Pat<(v4i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
5053 (MOVIv4i16 imm0_255:$imm8, imm:$shift)>;
5054 def : Pat<(v8i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
5055 (MOVIv8i16 imm0_255:$imm8, imm:$shift)>;
5057 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
5058 // EDIT per word: 2s & 4s with MSL shifter
5059 def MOVIv2s_msl : SIMDModifiedImmMoveMSL<0, 0, {1,1,0,?}, V64, "movi", ".2s",
5060 [(set (v2i32 V64:$Rd),
5061 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
5062 def MOVIv4s_msl : SIMDModifiedImmMoveMSL<1, 0, {1,1,0,?}, V128, "movi", ".4s",
5063 [(set (v4i32 V128:$Rd),
5064 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
5066 // Per byte: 8b & 16b
5067 def MOVIv8b_ns : SIMDModifiedImmVectorNoShift<0, 0, 0, 0b1110, V64, imm0_255,
5069 [(set (v8i8 V64:$Rd), (AArch64movi imm0_255:$imm8))]>;
5071 def MOVIv16b_ns : SIMDModifiedImmVectorNoShift<1, 0, 0, 0b1110, V128, imm0_255,
5073 [(set (v16i8 V128:$Rd), (AArch64movi imm0_255:$imm8))]>;
5078 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
5079 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
5080 defm MVNI : SIMDModifiedImmVectorShift<1, 0b10, 0b00, "mvni">;
5082 def : InstAlias<"mvni $Vd.4h, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
5083 def : InstAlias<"mvni $Vd.8h, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
5084 def : InstAlias<"mvni $Vd.2s, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
5085 def : InstAlias<"mvni $Vd.4s, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
5087 def : InstAlias<"mvni.4h $Vd, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
5088 def : InstAlias<"mvni.8h $Vd, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
5089 def : InstAlias<"mvni.2s $Vd, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
5090 def : InstAlias<"mvni.4s $Vd, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
5092 def : Pat<(v2i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
5093 (MVNIv2i32 imm0_255:$imm8, imm:$shift)>;
5094 def : Pat<(v4i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
5095 (MVNIv4i32 imm0_255:$imm8, imm:$shift)>;
5096 def : Pat<(v4i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
5097 (MVNIv4i16 imm0_255:$imm8, imm:$shift)>;
5098 def : Pat<(v8i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
5099 (MVNIv8i16 imm0_255:$imm8, imm:$shift)>;
5101 // EDIT per word: 2s & 4s with MSL shifter
5102 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
5103 def MVNIv2s_msl : SIMDModifiedImmMoveMSL<0, 1, {1,1,0,?}, V64, "mvni", ".2s",
5104 [(set (v2i32 V64:$Rd),
5105 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
5106 def MVNIv4s_msl : SIMDModifiedImmMoveMSL<1, 1, {1,1,0,?}, V128, "mvni", ".4s",
5107 [(set (v4i32 V128:$Rd),
5108 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
5111 //----------------------------------------------------------------------------
5112 // AdvSIMD indexed element
5113 //----------------------------------------------------------------------------
5115 let hasSideEffects = 0 in {
5116 defm FMLA : SIMDFPIndexedTied<0, 0b0001, "fmla">;
5117 defm FMLS : SIMDFPIndexedTied<0, 0b0101, "fmls">;
5120 // NOTE: Operands are reordered in the FMLA/FMLS PatFrags because the
5121 // instruction expects the addend first, while the intrinsic expects it last.
5123 // On the other hand, there are quite a few valid combinatorial options due to
5124 // the commutativity of multiplication and the fact that (-x) * y = x * (-y).
5125 defm : SIMDFPIndexedTiedPatterns<"FMLA",
5126 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)>>;
5127 defm : SIMDFPIndexedTiedPatterns<"FMLA",
5128 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)>>;
5130 defm : SIMDFPIndexedTiedPatterns<"FMLS",
5131 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
5132 defm : SIMDFPIndexedTiedPatterns<"FMLS",
5133 TriOpFrag<(fma node:$RHS, (fneg node:$MHS), node:$LHS)> >;
5134 defm : SIMDFPIndexedTiedPatterns<"FMLS",
5135 TriOpFrag<(fma (fneg node:$RHS), node:$MHS, node:$LHS)> >;
5136 defm : SIMDFPIndexedTiedPatterns<"FMLS",
5137 TriOpFrag<(fma (fneg node:$MHS), node:$RHS, node:$LHS)> >;
5139 multiclass FMLSIndexedAfterNegPatterns<SDPatternOperator OpNode> {
5140 // 3 variants for the .2s version: DUPLANE from 128-bit, DUPLANE from 64-bit
5142 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
5143 (AArch64duplane32 (v4f32 (fneg V128:$Rm)),
5144 VectorIndexS:$idx))),
5145 (FMLSv2i32_indexed V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
5146 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
5147 (v2f32 (AArch64duplane32
5148 (v4f32 (insert_subvector undef,
5149 (v2f32 (fneg V64:$Rm)),
5151 VectorIndexS:$idx)))),
5152 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
5153 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
5154 VectorIndexS:$idx)>;
5155 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
5156 (AArch64dup (f32 (fneg FPR32Op:$Rm))))),
5157 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
5158 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
5160 // 3 variants for the .4s version: DUPLANE from 128-bit, DUPLANE from 64-bit
5162 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
5163 (AArch64duplane32 (v4f32 (fneg V128:$Rm)),
5164 VectorIndexS:$idx))),
5165 (FMLSv4i32_indexed V128:$Rd, V128:$Rn, V128:$Rm,
5166 VectorIndexS:$idx)>;
5167 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
5168 (v4f32 (AArch64duplane32
5169 (v4f32 (insert_subvector undef,
5170 (v2f32 (fneg V64:$Rm)),
5172 VectorIndexS:$idx)))),
5173 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
5174 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
5175 VectorIndexS:$idx)>;
5176 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
5177 (AArch64dup (f32 (fneg FPR32Op:$Rm))))),
5178 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
5179 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
5181 // 2 variants for the .2d version: DUPLANE from 128-bit, and DUP scalar
5182 // (DUPLANE from 64-bit would be trivial).
5183 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
5184 (AArch64duplane64 (v2f64 (fneg V128:$Rm)),
5185 VectorIndexD:$idx))),
5187 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
5188 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
5189 (AArch64dup (f64 (fneg FPR64Op:$Rm))))),
5190 (FMLSv2i64_indexed V128:$Rd, V128:$Rn,
5191 (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>;
5193 // 2 variants for 32-bit scalar version: extract from .2s or from .4s
5194 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
5195 (vector_extract (v4f32 (fneg V128:$Rm)),
5196 VectorIndexS:$idx))),
5197 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
5198 V128:$Rm, VectorIndexS:$idx)>;
5199 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
5200 (vector_extract (v4f32 (insert_subvector undef,
5201 (v2f32 (fneg V64:$Rm)),
5203 VectorIndexS:$idx))),
5204 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
5205 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>;
5207 // 1 variant for 64-bit scalar version: extract from .1d or from .2d
5208 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
5209 (vector_extract (v2f64 (fneg V128:$Rm)),
5210 VectorIndexS:$idx))),
5211 (FMLSv1i64_indexed FPR64:$Rd, FPR64:$Rn,
5212 V128:$Rm, VectorIndexS:$idx)>;
5215 defm : FMLSIndexedAfterNegPatterns<
5216 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
5217 defm : FMLSIndexedAfterNegPatterns<
5218 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)> >;
5220 defm FMULX : SIMDFPIndexed<1, 0b1001, "fmulx", int_aarch64_neon_fmulx>;
5221 defm FMUL : SIMDFPIndexed<0, 0b1001, "fmul", fmul>;
5223 def : Pat<(v2f32 (fmul V64:$Rn, (AArch64dup (f32 FPR32:$Rm)))),
5224 (FMULv2i32_indexed V64:$Rn,
5225 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
5227 def : Pat<(v4f32 (fmul V128:$Rn, (AArch64dup (f32 FPR32:$Rm)))),
5228 (FMULv4i32_indexed V128:$Rn,
5229 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
5231 def : Pat<(v2f64 (fmul V128:$Rn, (AArch64dup (f64 FPR64:$Rm)))),
5232 (FMULv2i64_indexed V128:$Rn,
5233 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rm, dsub),
5236 defm SQDMULH : SIMDIndexedHS<0, 0b1100, "sqdmulh", int_aarch64_neon_sqdmulh>;
5237 defm SQRDMULH : SIMDIndexedHS<0, 0b1101, "sqrdmulh", int_aarch64_neon_sqrdmulh>;
5238 defm MLA : SIMDVectorIndexedHSTied<1, 0b0000, "mla",
5239 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))>>;
5240 defm MLS : SIMDVectorIndexedHSTied<1, 0b0100, "mls",
5241 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))>>;
5242 defm MUL : SIMDVectorIndexedHS<0, 0b1000, "mul", mul>;
5243 defm SMLAL : SIMDVectorIndexedLongSDTied<0, 0b0010, "smlal",
5244 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
5245 defm SMLSL : SIMDVectorIndexedLongSDTied<0, 0b0110, "smlsl",
5246 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
5247 defm SMULL : SIMDVectorIndexedLongSD<0, 0b1010, "smull",
5248 int_aarch64_neon_smull>;
5249 defm SQDMLAL : SIMDIndexedLongSQDMLXSDTied<0, 0b0011, "sqdmlal",
5250 int_aarch64_neon_sqadd>;
5251 defm SQDMLSL : SIMDIndexedLongSQDMLXSDTied<0, 0b0111, "sqdmlsl",
5252 int_aarch64_neon_sqsub>;
5253 defm SQRDMLAH : SIMDIndexedSQRDMLxHSDTied<1, 0b1101, "sqrdmlah",
5254 int_aarch64_neon_sqadd>;
5255 defm SQRDMLSH : SIMDIndexedSQRDMLxHSDTied<1, 0b1111, "sqrdmlsh",
5256 int_aarch64_neon_sqsub>;
5257 defm SQDMULL : SIMDIndexedLongSD<0, 0b1011, "sqdmull", int_aarch64_neon_sqdmull>;
5258 defm UMLAL : SIMDVectorIndexedLongSDTied<1, 0b0010, "umlal",
5259 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
5260 defm UMLSL : SIMDVectorIndexedLongSDTied<1, 0b0110, "umlsl",
5261 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
5262 defm UMULL : SIMDVectorIndexedLongSD<1, 0b1010, "umull",
5263 int_aarch64_neon_umull>;
5265 // A scalar sqdmull with the second operand being a vector lane can be
5266 // handled directly with the indexed instruction encoding.
5267 def : Pat<(int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
5268 (vector_extract (v4i32 V128:$Vm),
5269 VectorIndexS:$idx)),
5270 (SQDMULLv1i64_indexed FPR32:$Rn, V128:$Vm, VectorIndexS:$idx)>;
5272 //----------------------------------------------------------------------------
5273 // AdvSIMD scalar shift instructions
5274 //----------------------------------------------------------------------------
5275 defm FCVTZS : SIMDFPScalarRShift<0, 0b11111, "fcvtzs">;
5276 defm FCVTZU : SIMDFPScalarRShift<1, 0b11111, "fcvtzu">;
5277 defm SCVTF : SIMDFPScalarRShift<0, 0b11100, "scvtf">;
5278 defm UCVTF : SIMDFPScalarRShift<1, 0b11100, "ucvtf">;
5279 // Codegen patterns for the above. We don't put these directly on the
5280 // instructions because TableGen's type inference can't handle the truth.
5281 // Having the same base pattern for fp <--> int totally freaks it out.
5282 def : Pat<(int_aarch64_neon_vcvtfp2fxs FPR32:$Rn, vecshiftR32:$imm),
5283 (FCVTZSs FPR32:$Rn, vecshiftR32:$imm)>;
5284 def : Pat<(int_aarch64_neon_vcvtfp2fxu FPR32:$Rn, vecshiftR32:$imm),
5285 (FCVTZUs FPR32:$Rn, vecshiftR32:$imm)>;
5286 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxs (f64 FPR64:$Rn), vecshiftR64:$imm)),
5287 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
5288 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxu (f64 FPR64:$Rn), vecshiftR64:$imm)),
5289 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
5290 def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxs (v1f64 FPR64:$Rn),
5292 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
5293 def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxu (v1f64 FPR64:$Rn),
5295 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
5296 def : Pat<(int_aarch64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR32:$imm),
5297 (UCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
5298 def : Pat<(f64 (int_aarch64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
5299 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
5300 def : Pat<(v1f64 (int_aarch64_neon_vcvtfxs2fp (v1i64 FPR64:$Rn),
5302 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
5303 def : Pat<(f64 (int_aarch64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
5304 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
5305 def : Pat<(v1f64 (int_aarch64_neon_vcvtfxu2fp (v1i64 FPR64:$Rn),
5307 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
5308 def : Pat<(int_aarch64_neon_vcvtfxs2fp FPR32:$Rn, vecshiftR32:$imm),
5309 (SCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
5311 // Patterns for FP16 Instrinsics - requires reg copy to/from as i16s not supported.
5313 def : Pat<(f16 (int_aarch64_neon_vcvtfxs2fp (i32 (sext_inreg FPR32:$Rn, i16)), vecshiftR16:$imm)),
5314 (SCVTFh (EXTRACT_SUBREG FPR32:$Rn, hsub), vecshiftR16:$imm)>;
5315 def : Pat<(f16 (int_aarch64_neon_vcvtfxs2fp (i32 FPR32:$Rn), vecshiftR16:$imm)),
5316 (SCVTFh (EXTRACT_SUBREG FPR32:$Rn, hsub), vecshiftR16:$imm)>;
5317 def : Pat<(f16 (int_aarch64_neon_vcvtfxu2fp
5318 (and FPR32:$Rn, (i32 65535)),
5320 (UCVTFh (EXTRACT_SUBREG FPR32:$Rn, hsub), vecshiftR16:$imm)>;
5321 def : Pat<(f16 (int_aarch64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR16:$imm)),
5322 (UCVTFh (EXTRACT_SUBREG FPR32:$Rn, hsub), vecshiftR16:$imm)>;
5323 def : Pat<(f16 (int_aarch64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR16:$imm)),
5324 (UCVTFh (EXTRACT_SUBREG FPR64:$Rn, hsub), vecshiftR16:$imm)>;
5325 def : Pat<(i32 (int_aarch64_neon_vcvtfp2fxs (f16 FPR16:$Rn), vecshiftR32:$imm)),
5327 (i32 (IMPLICIT_DEF)),
5328 (FCVTZSh FPR16:$Rn, vecshiftR32:$imm),
5330 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxs (f16 FPR16:$Rn), vecshiftR64:$imm)),
5332 (i64 (IMPLICIT_DEF)),
5333 (FCVTZSh FPR16:$Rn, vecshiftR64:$imm),
5335 def : Pat<(i32 (int_aarch64_neon_vcvtfp2fxu (f16 FPR16:$Rn), vecshiftR32:$imm)),
5337 (i32 (IMPLICIT_DEF)),
5338 (FCVTZUh FPR16:$Rn, vecshiftR32:$imm),
5340 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxu (f16 FPR16:$Rn), vecshiftR64:$imm)),
5342 (i64 (IMPLICIT_DEF)),
5343 (FCVTZUh FPR16:$Rn, vecshiftR64:$imm),
5346 defm SHL : SIMDScalarLShiftD< 0, 0b01010, "shl", AArch64vshl>;
5347 defm SLI : SIMDScalarLShiftDTied<1, 0b01010, "sli">;
5348 defm SQRSHRN : SIMDScalarRShiftBHS< 0, 0b10011, "sqrshrn",
5349 int_aarch64_neon_sqrshrn>;
5350 defm SQRSHRUN : SIMDScalarRShiftBHS< 1, 0b10001, "sqrshrun",
5351 int_aarch64_neon_sqrshrun>;
5352 defm SQSHLU : SIMDScalarLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>;
5353 defm SQSHL : SIMDScalarLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>;
5354 defm SQSHRN : SIMDScalarRShiftBHS< 0, 0b10010, "sqshrn",
5355 int_aarch64_neon_sqshrn>;
5356 defm SQSHRUN : SIMDScalarRShiftBHS< 1, 0b10000, "sqshrun",
5357 int_aarch64_neon_sqshrun>;
5358 defm SRI : SIMDScalarRShiftDTied< 1, 0b01000, "sri">;
5359 defm SRSHR : SIMDScalarRShiftD< 0, 0b00100, "srshr", AArch64srshri>;
5360 defm SRSRA : SIMDScalarRShiftDTied< 0, 0b00110, "srsra",
5361 TriOpFrag<(add node:$LHS,
5362 (AArch64srshri node:$MHS, node:$RHS))>>;
5363 defm SSHR : SIMDScalarRShiftD< 0, 0b00000, "sshr", AArch64vashr>;
5364 defm SSRA : SIMDScalarRShiftDTied< 0, 0b00010, "ssra",
5365 TriOpFrag<(add node:$LHS,
5366 (AArch64vashr node:$MHS, node:$RHS))>>;
5367 defm UQRSHRN : SIMDScalarRShiftBHS< 1, 0b10011, "uqrshrn",
5368 int_aarch64_neon_uqrshrn>;
5369 defm UQSHL : SIMDScalarLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>;
5370 defm UQSHRN : SIMDScalarRShiftBHS< 1, 0b10010, "uqshrn",
5371 int_aarch64_neon_uqshrn>;
5372 defm URSHR : SIMDScalarRShiftD< 1, 0b00100, "urshr", AArch64urshri>;
5373 defm URSRA : SIMDScalarRShiftDTied< 1, 0b00110, "ursra",
5374 TriOpFrag<(add node:$LHS,
5375 (AArch64urshri node:$MHS, node:$RHS))>>;
5376 defm USHR : SIMDScalarRShiftD< 1, 0b00000, "ushr", AArch64vlshr>;
5377 defm USRA : SIMDScalarRShiftDTied< 1, 0b00010, "usra",
5378 TriOpFrag<(add node:$LHS,
5379 (AArch64vlshr node:$MHS, node:$RHS))>>;
5381 //----------------------------------------------------------------------------
5382 // AdvSIMD vector shift instructions
5383 //----------------------------------------------------------------------------
5384 defm FCVTZS:SIMDVectorRShiftSD<0, 0b11111, "fcvtzs", int_aarch64_neon_vcvtfp2fxs>;
5385 defm FCVTZU:SIMDVectorRShiftSD<1, 0b11111, "fcvtzu", int_aarch64_neon_vcvtfp2fxu>;
5386 defm SCVTF: SIMDVectorRShiftToFP<0, 0b11100, "scvtf",
5387 int_aarch64_neon_vcvtfxs2fp>;
5388 defm RSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10001, "rshrn",
5389 int_aarch64_neon_rshrn>;
5390 defm SHL : SIMDVectorLShiftBHSD<0, 0b01010, "shl", AArch64vshl>;
5391 defm SHRN : SIMDVectorRShiftNarrowBHS<0, 0b10000, "shrn",
5392 BinOpFrag<(trunc (AArch64vashr node:$LHS, node:$RHS))>>;
5393 defm SLI : SIMDVectorLShiftBHSDTied<1, 0b01010, "sli", int_aarch64_neon_vsli>;
5394 def : Pat<(v1i64 (int_aarch64_neon_vsli (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
5395 (i32 vecshiftL64:$imm))),
5396 (SLId FPR64:$Rd, FPR64:$Rn, vecshiftL64:$imm)>;
5397 defm SQRSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10011, "sqrshrn",
5398 int_aarch64_neon_sqrshrn>;
5399 defm SQRSHRUN: SIMDVectorRShiftNarrowBHS<1, 0b10001, "sqrshrun",
5400 int_aarch64_neon_sqrshrun>;
5401 defm SQSHLU : SIMDVectorLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>;
5402 defm SQSHL : SIMDVectorLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>;
5403 defm SQSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10010, "sqshrn",
5404 int_aarch64_neon_sqshrn>;
5405 defm SQSHRUN : SIMDVectorRShiftNarrowBHS<1, 0b10000, "sqshrun",
5406 int_aarch64_neon_sqshrun>;
5407 defm SRI : SIMDVectorRShiftBHSDTied<1, 0b01000, "sri", int_aarch64_neon_vsri>;
5408 def : Pat<(v1i64 (int_aarch64_neon_vsri (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
5409 (i32 vecshiftR64:$imm))),
5410 (SRId FPR64:$Rd, FPR64:$Rn, vecshiftR64:$imm)>;
5411 defm SRSHR : SIMDVectorRShiftBHSD<0, 0b00100, "srshr", AArch64srshri>;
5412 defm SRSRA : SIMDVectorRShiftBHSDTied<0, 0b00110, "srsra",
5413 TriOpFrag<(add node:$LHS,
5414 (AArch64srshri node:$MHS, node:$RHS))> >;
5415 defm SSHLL : SIMDVectorLShiftLongBHSD<0, 0b10100, "sshll",
5416 BinOpFrag<(AArch64vshl (sext node:$LHS), node:$RHS)>>;
5418 defm SSHR : SIMDVectorRShiftBHSD<0, 0b00000, "sshr", AArch64vashr>;
5419 defm SSRA : SIMDVectorRShiftBHSDTied<0, 0b00010, "ssra",
5420 TriOpFrag<(add node:$LHS, (AArch64vashr node:$MHS, node:$RHS))>>;
5421 defm UCVTF : SIMDVectorRShiftToFP<1, 0b11100, "ucvtf",
5422 int_aarch64_neon_vcvtfxu2fp>;
5423 defm UQRSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10011, "uqrshrn",
5424 int_aarch64_neon_uqrshrn>;
5425 defm UQSHL : SIMDVectorLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>;
5426 defm UQSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10010, "uqshrn",
5427 int_aarch64_neon_uqshrn>;
5428 defm URSHR : SIMDVectorRShiftBHSD<1, 0b00100, "urshr", AArch64urshri>;
5429 defm URSRA : SIMDVectorRShiftBHSDTied<1, 0b00110, "ursra",
5430 TriOpFrag<(add node:$LHS,
5431 (AArch64urshri node:$MHS, node:$RHS))> >;
5432 defm USHLL : SIMDVectorLShiftLongBHSD<1, 0b10100, "ushll",
5433 BinOpFrag<(AArch64vshl (zext node:$LHS), node:$RHS)>>;
5434 defm USHR : SIMDVectorRShiftBHSD<1, 0b00000, "ushr", AArch64vlshr>;
5435 defm USRA : SIMDVectorRShiftBHSDTied<1, 0b00010, "usra",
5436 TriOpFrag<(add node:$LHS, (AArch64vlshr node:$MHS, node:$RHS))> >;
5438 // SHRN patterns for when a logical right shift was used instead of arithmetic
5439 // (the immediate guarantees no sign bits actually end up in the result so it
5441 def : Pat<(v8i8 (trunc (AArch64vlshr (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))),
5442 (SHRNv8i8_shift V128:$Rn, vecshiftR16Narrow:$imm)>;
5443 def : Pat<(v4i16 (trunc (AArch64vlshr (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))),
5444 (SHRNv4i16_shift V128:$Rn, vecshiftR32Narrow:$imm)>;
5445 def : Pat<(v2i32 (trunc (AArch64vlshr (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))),
5446 (SHRNv2i32_shift V128:$Rn, vecshiftR64Narrow:$imm)>;
5448 def : Pat<(v16i8 (concat_vectors (v8i8 V64:$Rd),
5449 (trunc (AArch64vlshr (v8i16 V128:$Rn),
5450 vecshiftR16Narrow:$imm)))),
5451 (SHRNv16i8_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
5452 V128:$Rn, vecshiftR16Narrow:$imm)>;
5453 def : Pat<(v8i16 (concat_vectors (v4i16 V64:$Rd),
5454 (trunc (AArch64vlshr (v4i32 V128:$Rn),
5455 vecshiftR32Narrow:$imm)))),
5456 (SHRNv8i16_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
5457 V128:$Rn, vecshiftR32Narrow:$imm)>;
5458 def : Pat<(v4i32 (concat_vectors (v2i32 V64:$Rd),
5459 (trunc (AArch64vlshr (v2i64 V128:$Rn),
5460 vecshiftR64Narrow:$imm)))),
5461 (SHRNv4i32_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
5462 V128:$Rn, vecshiftR32Narrow:$imm)>;
5464 // Vector sign and zero extensions are implemented with SSHLL and USSHLL.
5465 // Anyexts are implemented as zexts.
5466 def : Pat<(v8i16 (sext (v8i8 V64:$Rn))), (SSHLLv8i8_shift V64:$Rn, (i32 0))>;
5467 def : Pat<(v8i16 (zext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
5468 def : Pat<(v8i16 (anyext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
5469 def : Pat<(v4i32 (sext (v4i16 V64:$Rn))), (SSHLLv4i16_shift V64:$Rn, (i32 0))>;
5470 def : Pat<(v4i32 (zext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
5471 def : Pat<(v4i32 (anyext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
5472 def : Pat<(v2i64 (sext (v2i32 V64:$Rn))), (SSHLLv2i32_shift V64:$Rn, (i32 0))>;
5473 def : Pat<(v2i64 (zext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
5474 def : Pat<(v2i64 (anyext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
5475 // Also match an extend from the upper half of a 128 bit source register.
5476 def : Pat<(v8i16 (anyext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
5477 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
5478 def : Pat<(v8i16 (zext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
5479 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
5480 def : Pat<(v8i16 (sext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
5481 (SSHLLv16i8_shift V128:$Rn, (i32 0))>;
5482 def : Pat<(v4i32 (anyext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
5483 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
5484 def : Pat<(v4i32 (zext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
5485 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
5486 def : Pat<(v4i32 (sext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
5487 (SSHLLv8i16_shift V128:$Rn, (i32 0))>;
5488 def : Pat<(v2i64 (anyext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
5489 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
5490 def : Pat<(v2i64 (zext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
5491 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
5492 def : Pat<(v2i64 (sext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
5493 (SSHLLv4i32_shift V128:$Rn, (i32 0))>;
5495 // Vector shift sxtl aliases
5496 def : InstAlias<"sxtl.8h $dst, $src1",
5497 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
5498 def : InstAlias<"sxtl $dst.8h, $src1.8b",
5499 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
5500 def : InstAlias<"sxtl.4s $dst, $src1",
5501 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
5502 def : InstAlias<"sxtl $dst.4s, $src1.4h",
5503 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
5504 def : InstAlias<"sxtl.2d $dst, $src1",
5505 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
5506 def : InstAlias<"sxtl $dst.2d, $src1.2s",
5507 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
5509 // Vector shift sxtl2 aliases
5510 def : InstAlias<"sxtl2.8h $dst, $src1",
5511 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
5512 def : InstAlias<"sxtl2 $dst.8h, $src1.16b",
5513 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
5514 def : InstAlias<"sxtl2.4s $dst, $src1",
5515 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
5516 def : InstAlias<"sxtl2 $dst.4s, $src1.8h",
5517 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
5518 def : InstAlias<"sxtl2.2d $dst, $src1",
5519 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
5520 def : InstAlias<"sxtl2 $dst.2d, $src1.4s",
5521 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
5523 // Vector shift uxtl aliases
5524 def : InstAlias<"uxtl.8h $dst, $src1",
5525 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
5526 def : InstAlias<"uxtl $dst.8h, $src1.8b",
5527 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
5528 def : InstAlias<"uxtl.4s $dst, $src1",
5529 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
5530 def : InstAlias<"uxtl $dst.4s, $src1.4h",
5531 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
5532 def : InstAlias<"uxtl.2d $dst, $src1",
5533 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
5534 def : InstAlias<"uxtl $dst.2d, $src1.2s",
5535 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
5537 // Vector shift uxtl2 aliases
5538 def : InstAlias<"uxtl2.8h $dst, $src1",
5539 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
5540 def : InstAlias<"uxtl2 $dst.8h, $src1.16b",
5541 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
5542 def : InstAlias<"uxtl2.4s $dst, $src1",
5543 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
5544 def : InstAlias<"uxtl2 $dst.4s, $src1.8h",
5545 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
5546 def : InstAlias<"uxtl2.2d $dst, $src1",
5547 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
5548 def : InstAlias<"uxtl2 $dst.2d, $src1.4s",
5549 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
5551 // If an integer is about to be converted to a floating point value,
5552 // just load it on the floating point unit.
5553 // These patterns are more complex because floating point loads do not
5554 // support sign extension.
5555 // The sign extension has to be explicitly added and is only supported for
5556 // one step: byte-to-half, half-to-word, word-to-doubleword.
5557 // SCVTF GPR -> FPR is 9 cycles.
5558 // SCVTF FPR -> FPR is 4 cyclces.
5559 // (sign extension with lengthen) SXTL FPR -> FPR is 2 cycles.
5560 // Therefore, we can do 2 sign extensions and one SCVTF FPR -> FPR
5561 // and still being faster.
5562 // However, this is not good for code size.
5563 // 8-bits -> float. 2 sizes step-up.
5564 class SExtLoadi8CVTf32Pat<dag addrmode, dag INST>
5565 : Pat<(f32 (sint_to_fp (i32 (sextloadi8 addrmode)))),
5566 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
5571 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
5578 Requires<[NotForCodeSize, UseAlternateSExtLoadCVTF32]>;
5580 def : SExtLoadi8CVTf32Pat<(ro8.Wpat GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext),
5581 (LDRBroW GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext)>;
5582 def : SExtLoadi8CVTf32Pat<(ro8.Xpat GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext),
5583 (LDRBroX GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext)>;
5584 def : SExtLoadi8CVTf32Pat<(am_indexed8 GPR64sp:$Rn, uimm12s1:$offset),
5585 (LDRBui GPR64sp:$Rn, uimm12s1:$offset)>;
5586 def : SExtLoadi8CVTf32Pat<(am_unscaled8 GPR64sp:$Rn, simm9:$offset),
5587 (LDURBi GPR64sp:$Rn, simm9:$offset)>;
5589 // 16-bits -> float. 1 size step-up.
5590 class SExtLoadi16CVTf32Pat<dag addrmode, dag INST>
5591 : Pat<(f32 (sint_to_fp (i32 (sextloadi16 addrmode)))),
5592 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
5594 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
5598 ssub)))>, Requires<[NotForCodeSize]>;
5600 def : SExtLoadi16CVTf32Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
5601 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
5602 def : SExtLoadi16CVTf32Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),
5603 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;
5604 def : SExtLoadi16CVTf32Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),
5605 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;
5606 def : SExtLoadi16CVTf32Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),
5607 (LDURHi GPR64sp:$Rn, simm9:$offset)>;
5609 // 32-bits to 32-bits are handled in target specific dag combine:
5610 // performIntToFpCombine.
5611 // 64-bits integer to 32-bits floating point, not possible with
5612 // SCVTF on floating point registers (both source and destination
5613 // must have the same size).
5615 // Here are the patterns for 8, 16, 32, and 64-bits to double.
5616 // 8-bits -> double. 3 size step-up: give up.
5617 // 16-bits -> double. 2 size step.
5618 class SExtLoadi16CVTf64Pat<dag addrmode, dag INST>
5619 : Pat <(f64 (sint_to_fp (i32 (sextloadi16 addrmode)))),
5620 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
5625 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
5632 Requires<[NotForCodeSize, UseAlternateSExtLoadCVTF32]>;
5634 def : SExtLoadi16CVTf64Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
5635 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
5636 def : SExtLoadi16CVTf64Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),
5637 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;
5638 def : SExtLoadi16CVTf64Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),
5639 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;
5640 def : SExtLoadi16CVTf64Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),
5641 (LDURHi GPR64sp:$Rn, simm9:$offset)>;
5642 // 32-bits -> double. 1 size step-up.
5643 class SExtLoadi32CVTf64Pat<dag addrmode, dag INST>
5644 : Pat <(f64 (sint_to_fp (i32 (load addrmode)))),
5645 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
5647 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
5651 dsub)))>, Requires<[NotForCodeSize]>;
5653 def : SExtLoadi32CVTf64Pat<(ro32.Wpat GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext),
5654 (LDRSroW GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext)>;
5655 def : SExtLoadi32CVTf64Pat<(ro32.Xpat GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext),
5656 (LDRSroX GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext)>;
5657 def : SExtLoadi32CVTf64Pat<(am_indexed32 GPR64sp:$Rn, uimm12s4:$offset),
5658 (LDRSui GPR64sp:$Rn, uimm12s4:$offset)>;
5659 def : SExtLoadi32CVTf64Pat<(am_unscaled32 GPR64sp:$Rn, simm9:$offset),
5660 (LDURSi GPR64sp:$Rn, simm9:$offset)>;
5662 // 64-bits -> double are handled in target specific dag combine:
5663 // performIntToFpCombine.
5666 //----------------------------------------------------------------------------
5667 // AdvSIMD Load-Store Structure
5668 //----------------------------------------------------------------------------
5669 defm LD1 : SIMDLd1Multiple<"ld1">;
5670 defm LD2 : SIMDLd2Multiple<"ld2">;
5671 defm LD3 : SIMDLd3Multiple<"ld3">;
5672 defm LD4 : SIMDLd4Multiple<"ld4">;
5674 defm ST1 : SIMDSt1Multiple<"st1">;
5675 defm ST2 : SIMDSt2Multiple<"st2">;
5676 defm ST3 : SIMDSt3Multiple<"st3">;
5677 defm ST4 : SIMDSt4Multiple<"st4">;
5679 class Ld1Pat<ValueType ty, Instruction INST>
5680 : Pat<(ty (load GPR64sp:$Rn)), (INST GPR64sp:$Rn)>;
5682 def : Ld1Pat<v16i8, LD1Onev16b>;
5683 def : Ld1Pat<v8i16, LD1Onev8h>;
5684 def : Ld1Pat<v4i32, LD1Onev4s>;
5685 def : Ld1Pat<v2i64, LD1Onev2d>;
5686 def : Ld1Pat<v8i8, LD1Onev8b>;
5687 def : Ld1Pat<v4i16, LD1Onev4h>;
5688 def : Ld1Pat<v2i32, LD1Onev2s>;
5689 def : Ld1Pat<v1i64, LD1Onev1d>;
5691 class St1Pat<ValueType ty, Instruction INST>
5692 : Pat<(store ty:$Vt, GPR64sp:$Rn),
5693 (INST ty:$Vt, GPR64sp:$Rn)>;
5695 def : St1Pat<v16i8, ST1Onev16b>;
5696 def : St1Pat<v8i16, ST1Onev8h>;
5697 def : St1Pat<v4i32, ST1Onev4s>;
5698 def : St1Pat<v2i64, ST1Onev2d>;
5699 def : St1Pat<v8i8, ST1Onev8b>;
5700 def : St1Pat<v4i16, ST1Onev4h>;
5701 def : St1Pat<v2i32, ST1Onev2s>;
5702 def : St1Pat<v1i64, ST1Onev1d>;
5708 defm LD1R : SIMDLdR<0, 0b110, 0, "ld1r", "One", 1, 2, 4, 8>;
5709 defm LD2R : SIMDLdR<1, 0b110, 0, "ld2r", "Two", 2, 4, 8, 16>;
5710 defm LD3R : SIMDLdR<0, 0b111, 0, "ld3r", "Three", 3, 6, 12, 24>;
5711 defm LD4R : SIMDLdR<1, 0b111, 0, "ld4r", "Four", 4, 8, 16, 32>;
5712 let mayLoad = 1, hasSideEffects = 0 in {
5713 defm LD1 : SIMDLdSingleBTied<0, 0b000, "ld1", VecListOneb, GPR64pi1>;
5714 defm LD1 : SIMDLdSingleHTied<0, 0b010, 0, "ld1", VecListOneh, GPR64pi2>;
5715 defm LD1 : SIMDLdSingleSTied<0, 0b100, 0b00, "ld1", VecListOnes, GPR64pi4>;
5716 defm LD1 : SIMDLdSingleDTied<0, 0b100, 0b01, "ld1", VecListOned, GPR64pi8>;
5717 defm LD2 : SIMDLdSingleBTied<1, 0b000, "ld2", VecListTwob, GPR64pi2>;
5718 defm LD2 : SIMDLdSingleHTied<1, 0b010, 0, "ld2", VecListTwoh, GPR64pi4>;
5719 defm LD2 : SIMDLdSingleSTied<1, 0b100, 0b00, "ld2", VecListTwos, GPR64pi8>;
5720 defm LD2 : SIMDLdSingleDTied<1, 0b100, 0b01, "ld2", VecListTwod, GPR64pi16>;
5721 defm LD3 : SIMDLdSingleBTied<0, 0b001, "ld3", VecListThreeb, GPR64pi3>;
5722 defm LD3 : SIMDLdSingleHTied<0, 0b011, 0, "ld3", VecListThreeh, GPR64pi6>;
5723 defm LD3 : SIMDLdSingleSTied<0, 0b101, 0b00, "ld3", VecListThrees, GPR64pi12>;
5724 defm LD3 : SIMDLdSingleDTied<0, 0b101, 0b01, "ld3", VecListThreed, GPR64pi24>;
5725 defm LD4 : SIMDLdSingleBTied<1, 0b001, "ld4", VecListFourb, GPR64pi4>;
5726 defm LD4 : SIMDLdSingleHTied<1, 0b011, 0, "ld4", VecListFourh, GPR64pi8>;
5727 defm LD4 : SIMDLdSingleSTied<1, 0b101, 0b00, "ld4", VecListFours, GPR64pi16>;
5728 defm LD4 : SIMDLdSingleDTied<1, 0b101, 0b01, "ld4", VecListFourd, GPR64pi32>;
5731 def : Pat<(v8i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))),
5732 (LD1Rv8b GPR64sp:$Rn)>;
5733 def : Pat<(v16i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))),
5734 (LD1Rv16b GPR64sp:$Rn)>;
5735 def : Pat<(v4i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))),
5736 (LD1Rv4h GPR64sp:$Rn)>;
5737 def : Pat<(v8i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))),
5738 (LD1Rv8h GPR64sp:$Rn)>;
5739 def : Pat<(v2i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
5740 (LD1Rv2s GPR64sp:$Rn)>;
5741 def : Pat<(v4i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
5742 (LD1Rv4s GPR64sp:$Rn)>;
5743 def : Pat<(v2i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
5744 (LD1Rv2d GPR64sp:$Rn)>;
5745 def : Pat<(v1i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
5746 (LD1Rv1d GPR64sp:$Rn)>;
5747 // Grab the floating point version too
5748 def : Pat<(v2f32 (AArch64dup (f32 (load GPR64sp:$Rn)))),
5749 (LD1Rv2s GPR64sp:$Rn)>;
5750 def : Pat<(v4f32 (AArch64dup (f32 (load GPR64sp:$Rn)))),
5751 (LD1Rv4s GPR64sp:$Rn)>;
5752 def : Pat<(v2f64 (AArch64dup (f64 (load GPR64sp:$Rn)))),
5753 (LD1Rv2d GPR64sp:$Rn)>;
5754 def : Pat<(v1f64 (AArch64dup (f64 (load GPR64sp:$Rn)))),
5755 (LD1Rv1d GPR64sp:$Rn)>;
5756 def : Pat<(v4f16 (AArch64dup (f16 (load GPR64sp:$Rn)))),
5757 (LD1Rv4h GPR64sp:$Rn)>;
5758 def : Pat<(v8f16 (AArch64dup (f16 (load GPR64sp:$Rn)))),
5759 (LD1Rv8h GPR64sp:$Rn)>;
5761 class Ld1Lane128Pat<SDPatternOperator scalar_load, Operand VecIndex,
5762 ValueType VTy, ValueType STy, Instruction LD1>
5763 : Pat<(vector_insert (VTy VecListOne128:$Rd),
5764 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
5765 (LD1 VecListOne128:$Rd, VecIndex:$idx, GPR64sp:$Rn)>;
5767 def : Ld1Lane128Pat<extloadi8, VectorIndexB, v16i8, i32, LD1i8>;
5768 def : Ld1Lane128Pat<extloadi16, VectorIndexH, v8i16, i32, LD1i16>;
5769 def : Ld1Lane128Pat<load, VectorIndexS, v4i32, i32, LD1i32>;
5770 def : Ld1Lane128Pat<load, VectorIndexS, v4f32, f32, LD1i32>;
5771 def : Ld1Lane128Pat<load, VectorIndexD, v2i64, i64, LD1i64>;
5772 def : Ld1Lane128Pat<load, VectorIndexD, v2f64, f64, LD1i64>;
5773 def : Ld1Lane128Pat<load, VectorIndexH, v8f16, f16, LD1i16>;
5775 class Ld1Lane64Pat<SDPatternOperator scalar_load, Operand VecIndex,
5776 ValueType VTy, ValueType STy, Instruction LD1>
5777 : Pat<(vector_insert (VTy VecListOne64:$Rd),
5778 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
5780 (LD1 (SUBREG_TO_REG (i32 0), VecListOne64:$Rd, dsub),
5781 VecIndex:$idx, GPR64sp:$Rn),
5784 def : Ld1Lane64Pat<extloadi8, VectorIndexB, v8i8, i32, LD1i8>;
5785 def : Ld1Lane64Pat<extloadi16, VectorIndexH, v4i16, i32, LD1i16>;
5786 def : Ld1Lane64Pat<load, VectorIndexS, v2i32, i32, LD1i32>;
5787 def : Ld1Lane64Pat<load, VectorIndexS, v2f32, f32, LD1i32>;
5788 def : Ld1Lane64Pat<load, VectorIndexH, v4f16, f16, LD1i16>;
5791 defm LD1 : SIMDLdSt1SingleAliases<"ld1">;
5792 defm LD2 : SIMDLdSt2SingleAliases<"ld2">;
5793 defm LD3 : SIMDLdSt3SingleAliases<"ld3">;
5794 defm LD4 : SIMDLdSt4SingleAliases<"ld4">;
5797 defm ST1 : SIMDStSingleB<0, 0b000, "st1", VecListOneb, GPR64pi1>;
5798 defm ST1 : SIMDStSingleH<0, 0b010, 0, "st1", VecListOneh, GPR64pi2>;
5799 defm ST1 : SIMDStSingleS<0, 0b100, 0b00, "st1", VecListOnes, GPR64pi4>;
5800 defm ST1 : SIMDStSingleD<0, 0b100, 0b01, "st1", VecListOned, GPR64pi8>;
5802 let AddedComplexity = 19 in
5803 class St1Lane128Pat<SDPatternOperator scalar_store, Operand VecIndex,
5804 ValueType VTy, ValueType STy, Instruction ST1>
5806 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
5808 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn)>;
5810 def : St1Lane128Pat<truncstorei8, VectorIndexB, v16i8, i32, ST1i8>;
5811 def : St1Lane128Pat<truncstorei16, VectorIndexH, v8i16, i32, ST1i16>;
5812 def : St1Lane128Pat<store, VectorIndexS, v4i32, i32, ST1i32>;
5813 def : St1Lane128Pat<store, VectorIndexS, v4f32, f32, ST1i32>;
5814 def : St1Lane128Pat<store, VectorIndexD, v2i64, i64, ST1i64>;
5815 def : St1Lane128Pat<store, VectorIndexD, v2f64, f64, ST1i64>;
5816 def : St1Lane128Pat<store, VectorIndexH, v8f16, f16, ST1i16>;
5818 let AddedComplexity = 19 in
5819 class St1Lane64Pat<SDPatternOperator scalar_store, Operand VecIndex,
5820 ValueType VTy, ValueType STy, Instruction ST1>
5822 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
5824 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
5825 VecIndex:$idx, GPR64sp:$Rn)>;
5827 def : St1Lane64Pat<truncstorei8, VectorIndexB, v8i8, i32, ST1i8>;
5828 def : St1Lane64Pat<truncstorei16, VectorIndexH, v4i16, i32, ST1i16>;
5829 def : St1Lane64Pat<store, VectorIndexS, v2i32, i32, ST1i32>;
5830 def : St1Lane64Pat<store, VectorIndexS, v2f32, f32, ST1i32>;
5831 def : St1Lane64Pat<store, VectorIndexH, v4f16, f16, ST1i16>;
5833 multiclass St1LanePost64Pat<SDPatternOperator scalar_store, Operand VecIndex,
5834 ValueType VTy, ValueType STy, Instruction ST1,
5836 def : Pat<(scalar_store
5837 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
5838 GPR64sp:$Rn, offset),
5839 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
5840 VecIndex:$idx, GPR64sp:$Rn, XZR)>;
5842 def : Pat<(scalar_store
5843 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
5844 GPR64sp:$Rn, GPR64:$Rm),
5845 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
5846 VecIndex:$idx, GPR64sp:$Rn, $Rm)>;
5849 defm : St1LanePost64Pat<post_truncsti8, VectorIndexB, v8i8, i32, ST1i8_POST, 1>;
5850 defm : St1LanePost64Pat<post_truncsti16, VectorIndexH, v4i16, i32, ST1i16_POST,
5852 defm : St1LanePost64Pat<post_store, VectorIndexS, v2i32, i32, ST1i32_POST, 4>;
5853 defm : St1LanePost64Pat<post_store, VectorIndexS, v2f32, f32, ST1i32_POST, 4>;
5854 defm : St1LanePost64Pat<post_store, VectorIndexD, v1i64, i64, ST1i64_POST, 8>;
5855 defm : St1LanePost64Pat<post_store, VectorIndexD, v1f64, f64, ST1i64_POST, 8>;
5856 defm : St1LanePost64Pat<post_store, VectorIndexH, v4f16, f16, ST1i16_POST, 2>;
5858 multiclass St1LanePost128Pat<SDPatternOperator scalar_store, Operand VecIndex,
5859 ValueType VTy, ValueType STy, Instruction ST1,
5861 def : Pat<(scalar_store
5862 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
5863 GPR64sp:$Rn, offset),
5864 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, XZR)>;
5866 def : Pat<(scalar_store
5867 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
5868 GPR64sp:$Rn, GPR64:$Rm),
5869 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, $Rm)>;
5872 defm : St1LanePost128Pat<post_truncsti8, VectorIndexB, v16i8, i32, ST1i8_POST,
5874 defm : St1LanePost128Pat<post_truncsti16, VectorIndexH, v8i16, i32, ST1i16_POST,
5876 defm : St1LanePost128Pat<post_store, VectorIndexS, v4i32, i32, ST1i32_POST, 4>;
5877 defm : St1LanePost128Pat<post_store, VectorIndexS, v4f32, f32, ST1i32_POST, 4>;
5878 defm : St1LanePost128Pat<post_store, VectorIndexD, v2i64, i64, ST1i64_POST, 8>;
5879 defm : St1LanePost128Pat<post_store, VectorIndexD, v2f64, f64, ST1i64_POST, 8>;
5880 defm : St1LanePost128Pat<post_store, VectorIndexH, v8f16, f16, ST1i16_POST, 2>;
5882 let mayStore = 1, hasSideEffects = 0 in {
5883 defm ST2 : SIMDStSingleB<1, 0b000, "st2", VecListTwob, GPR64pi2>;
5884 defm ST2 : SIMDStSingleH<1, 0b010, 0, "st2", VecListTwoh, GPR64pi4>;
5885 defm ST2 : SIMDStSingleS<1, 0b100, 0b00, "st2", VecListTwos, GPR64pi8>;
5886 defm ST2 : SIMDStSingleD<1, 0b100, 0b01, "st2", VecListTwod, GPR64pi16>;
5887 defm ST3 : SIMDStSingleB<0, 0b001, "st3", VecListThreeb, GPR64pi3>;
5888 defm ST3 : SIMDStSingleH<0, 0b011, 0, "st3", VecListThreeh, GPR64pi6>;
5889 defm ST3 : SIMDStSingleS<0, 0b101, 0b00, "st3", VecListThrees, GPR64pi12>;
5890 defm ST3 : SIMDStSingleD<0, 0b101, 0b01, "st3", VecListThreed, GPR64pi24>;
5891 defm ST4 : SIMDStSingleB<1, 0b001, "st4", VecListFourb, GPR64pi4>;
5892 defm ST4 : SIMDStSingleH<1, 0b011, 0, "st4", VecListFourh, GPR64pi8>;
5893 defm ST4 : SIMDStSingleS<1, 0b101, 0b00, "st4", VecListFours, GPR64pi16>;
5894 defm ST4 : SIMDStSingleD<1, 0b101, 0b01, "st4", VecListFourd, GPR64pi32>;
5897 defm ST1 : SIMDLdSt1SingleAliases<"st1">;
5898 defm ST2 : SIMDLdSt2SingleAliases<"st2">;
5899 defm ST3 : SIMDLdSt3SingleAliases<"st3">;
5900 defm ST4 : SIMDLdSt4SingleAliases<"st4">;
5902 //----------------------------------------------------------------------------
5903 // Crypto extensions
5904 //----------------------------------------------------------------------------
5906 let Predicates = [HasAES] in {
5907 def AESErr : AESTiedInst<0b0100, "aese", int_aarch64_crypto_aese>;
5908 def AESDrr : AESTiedInst<0b0101, "aesd", int_aarch64_crypto_aesd>;
5909 def AESMCrr : AESInst< 0b0110, "aesmc", int_aarch64_crypto_aesmc>;
5910 def AESIMCrr : AESInst< 0b0111, "aesimc", int_aarch64_crypto_aesimc>;
5913 // Pseudo instructions for AESMCrr/AESIMCrr with a register constraint required
5914 // for AES fusion on some CPUs.
5915 let hasSideEffects = 0, mayStore = 0, mayLoad = 0 in {
5916 def AESMCrrTied: Pseudo<(outs V128:$Rd), (ins V128:$Rn), [], "$Rn = $Rd">,
5918 def AESIMCrrTied: Pseudo<(outs V128:$Rd), (ins V128:$Rn), [], "$Rn = $Rd">,
5922 // Only use constrained versions of AES(I)MC instructions if they are paired with
5924 def : Pat<(v16i8 (int_aarch64_crypto_aesmc
5925 (v16i8 (int_aarch64_crypto_aese (v16i8 V128:$src1),
5926 (v16i8 V128:$src2))))),
5927 (v16i8 (AESMCrrTied (v16i8 (AESErr (v16i8 V128:$src1),
5928 (v16i8 V128:$src2)))))>,
5929 Requires<[HasFuseAES]>;
5931 def : Pat<(v16i8 (int_aarch64_crypto_aesimc
5932 (v16i8 (int_aarch64_crypto_aesd (v16i8 V128:$src1),
5933 (v16i8 V128:$src2))))),
5934 (v16i8 (AESIMCrrTied (v16i8 (AESDrr (v16i8 V128:$src1),
5935 (v16i8 V128:$src2)))))>,
5936 Requires<[HasFuseAES]>;
5938 let Predicates = [HasSHA2] in {
5939 def SHA1Crrr : SHATiedInstQSV<0b000, "sha1c", int_aarch64_crypto_sha1c>;
5940 def SHA1Prrr : SHATiedInstQSV<0b001, "sha1p", int_aarch64_crypto_sha1p>;
5941 def SHA1Mrrr : SHATiedInstQSV<0b010, "sha1m", int_aarch64_crypto_sha1m>;
5942 def SHA1SU0rrr : SHATiedInstVVV<0b011, "sha1su0", int_aarch64_crypto_sha1su0>;
5943 def SHA256Hrrr : SHATiedInstQQV<0b100, "sha256h", int_aarch64_crypto_sha256h>;
5944 def SHA256H2rrr : SHATiedInstQQV<0b101, "sha256h2",int_aarch64_crypto_sha256h2>;
5945 def SHA256SU1rrr :SHATiedInstVVV<0b110, "sha256su1",int_aarch64_crypto_sha256su1>;
5947 def SHA1Hrr : SHAInstSS< 0b0000, "sha1h", int_aarch64_crypto_sha1h>;
5948 def SHA1SU1rr : SHATiedInstVV<0b0001, "sha1su1", int_aarch64_crypto_sha1su1>;
5949 def SHA256SU0rr : SHATiedInstVV<0b0010, "sha256su0",int_aarch64_crypto_sha256su0>;
5952 //----------------------------------------------------------------------------
5954 //----------------------------------------------------------------------------
5955 // FIXME: Like for X86, these should go in their own separate .td file.
5957 def def32 : PatLeaf<(i32 GPR32:$src), [{
5961 // In the case of a 32-bit def that is known to implicitly zero-extend,
5962 // we can use a SUBREG_TO_REG.
5963 def : Pat<(i64 (zext def32:$src)), (SUBREG_TO_REG (i64 0), GPR32:$src, sub_32)>;
5965 // For an anyext, we don't care what the high bits are, so we can perform an
5966 // INSERT_SUBREF into an IMPLICIT_DEF.
5967 def : Pat<(i64 (anyext GPR32:$src)),
5968 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>;
5970 // When we need to explicitly zero-extend, we use a 32-bit MOV instruction and
5971 // then assert the extension has happened.
5972 def : Pat<(i64 (zext GPR32:$src)),
5973 (SUBREG_TO_REG (i32 0), (ORRWrs WZR, GPR32:$src, 0), sub_32)>;
5975 // To sign extend, we use a signed bitfield move instruction (SBFM) on the
5976 // containing super-reg.
5977 def : Pat<(i64 (sext GPR32:$src)),
5978 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
5979 def : Pat<(i64 (sext_inreg GPR64:$src, i32)), (SBFMXri GPR64:$src, 0, 31)>;
5980 def : Pat<(i64 (sext_inreg GPR64:$src, i16)), (SBFMXri GPR64:$src, 0, 15)>;
5981 def : Pat<(i64 (sext_inreg GPR64:$src, i8)), (SBFMXri GPR64:$src, 0, 7)>;
5982 def : Pat<(i64 (sext_inreg GPR64:$src, i1)), (SBFMXri GPR64:$src, 0, 0)>;
5983 def : Pat<(i32 (sext_inreg GPR32:$src, i16)), (SBFMWri GPR32:$src, 0, 15)>;
5984 def : Pat<(i32 (sext_inreg GPR32:$src, i8)), (SBFMWri GPR32:$src, 0, 7)>;
5985 def : Pat<(i32 (sext_inreg GPR32:$src, i1)), (SBFMWri GPR32:$src, 0, 0)>;
5987 def : Pat<(shl (sext_inreg GPR32:$Rn, i8), (i64 imm0_31:$imm)),
5988 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
5989 (i64 (i32shift_sext_i8 imm0_31:$imm)))>;
5990 def : Pat<(shl (sext_inreg GPR64:$Rn, i8), (i64 imm0_63:$imm)),
5991 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
5992 (i64 (i64shift_sext_i8 imm0_63:$imm)))>;
5994 def : Pat<(shl (sext_inreg GPR32:$Rn, i16), (i64 imm0_31:$imm)),
5995 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
5996 (i64 (i32shift_sext_i16 imm0_31:$imm)))>;
5997 def : Pat<(shl (sext_inreg GPR64:$Rn, i16), (i64 imm0_63:$imm)),
5998 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
5999 (i64 (i64shift_sext_i16 imm0_63:$imm)))>;
6001 def : Pat<(shl (i64 (sext GPR32:$Rn)), (i64 imm0_63:$imm)),
6002 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
6003 (i64 (i64shift_a imm0_63:$imm)),
6004 (i64 (i64shift_sext_i32 imm0_63:$imm)))>;
6006 // sra patterns have an AddedComplexity of 10, so make sure we have a higher
6007 // AddedComplexity for the following patterns since we want to match sext + sra
6008 // patterns before we attempt to match a single sra node.
6009 let AddedComplexity = 20 in {
6010 // We support all sext + sra combinations which preserve at least one bit of the
6011 // original value which is to be sign extended. E.g. we support shifts up to
6013 def : Pat<(sra (sext_inreg GPR32:$Rn, i8), (i64 imm0_7:$imm)),
6014 (SBFMWri GPR32:$Rn, (i64 imm0_7:$imm), 7)>;
6015 def : Pat<(sra (sext_inreg GPR64:$Rn, i8), (i64 imm0_7:$imm)),
6016 (SBFMXri GPR64:$Rn, (i64 imm0_7:$imm), 7)>;
6018 def : Pat<(sra (sext_inreg GPR32:$Rn, i16), (i64 imm0_15:$imm)),
6019 (SBFMWri GPR32:$Rn, (i64 imm0_15:$imm), 15)>;
6020 def : Pat<(sra (sext_inreg GPR64:$Rn, i16), (i64 imm0_15:$imm)),
6021 (SBFMXri GPR64:$Rn, (i64 imm0_15:$imm), 15)>;
6023 def : Pat<(sra (i64 (sext GPR32:$Rn)), (i64 imm0_31:$imm)),
6024 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
6025 (i64 imm0_31:$imm), 31)>;
6026 } // AddedComplexity = 20
6028 // To truncate, we can simply extract from a subregister.
6029 def : Pat<(i32 (trunc GPR64sp:$src)),
6030 (i32 (EXTRACT_SUBREG GPR64sp:$src, sub_32))>;
6032 // __builtin_trap() uses the BRK instruction on AArch64.
6033 def : Pat<(trap), (BRK 1)>;
6035 // Multiply high patterns which multiply the lower subvector using smull/umull
6036 // and the upper subvector with smull2/umull2. Then shuffle the high the high
6037 // part of both results together.
6038 def : Pat<(v16i8 (mulhs V128:$Rn, V128:$Rm)),
6040 (SMULLv8i8_v8i16 (EXTRACT_SUBREG V128:$Rn, dsub),
6041 (EXTRACT_SUBREG V128:$Rm, dsub)),
6042 (SMULLv16i8_v8i16 V128:$Rn, V128:$Rm))>;
6043 def : Pat<(v8i16 (mulhs V128:$Rn, V128:$Rm)),
6045 (SMULLv4i16_v4i32 (EXTRACT_SUBREG V128:$Rn, dsub),
6046 (EXTRACT_SUBREG V128:$Rm, dsub)),
6047 (SMULLv8i16_v4i32 V128:$Rn, V128:$Rm))>;
6048 def : Pat<(v4i32 (mulhs V128:$Rn, V128:$Rm)),
6050 (SMULLv2i32_v2i64 (EXTRACT_SUBREG V128:$Rn, dsub),
6051 (EXTRACT_SUBREG V128:$Rm, dsub)),
6052 (SMULLv4i32_v2i64 V128:$Rn, V128:$Rm))>;
6054 def : Pat<(v16i8 (mulhu V128:$Rn, V128:$Rm)),
6056 (UMULLv8i8_v8i16 (EXTRACT_SUBREG V128:$Rn, dsub),
6057 (EXTRACT_SUBREG V128:$Rm, dsub)),
6058 (UMULLv16i8_v8i16 V128:$Rn, V128:$Rm))>;
6059 def : Pat<(v8i16 (mulhu V128:$Rn, V128:$Rm)),
6061 (UMULLv4i16_v4i32 (EXTRACT_SUBREG V128:$Rn, dsub),
6062 (EXTRACT_SUBREG V128:$Rm, dsub)),
6063 (UMULLv8i16_v4i32 V128:$Rn, V128:$Rm))>;
6064 def : Pat<(v4i32 (mulhu V128:$Rn, V128:$Rm)),
6066 (UMULLv2i32_v2i64 (EXTRACT_SUBREG V128:$Rn, dsub),
6067 (EXTRACT_SUBREG V128:$Rm, dsub)),
6068 (UMULLv4i32_v2i64 V128:$Rn, V128:$Rm))>;
6070 // Conversions within AdvSIMD types in the same register size are free.
6071 // But because we need a consistent lane ordering, in big endian many
6072 // conversions require one or more REV instructions.
6074 // Consider a simple memory load followed by a bitconvert then a store.
6076 // v1 = BITCAST v2i32 v0 to v4i16
6079 // In big endian mode every memory access has an implicit byte swap. LDR and
6080 // STR do a 64-bit byte swap, whereas LD1/ST1 do a byte swap per lane - that
6081 // is, they treat the vector as a sequence of elements to be byte-swapped.
6082 // The two pairs of instructions are fundamentally incompatible. We've decided
6083 // to use LD1/ST1 only to simplify compiler implementation.
6085 // LD1/ST1 perform the equivalent of a sequence of LDR/STR + REV. This makes
6086 // the original code sequence:
6088 // v1 = REV v2i32 (implicit)
6089 // v2 = BITCAST v2i32 v1 to v4i16
6090 // v3 = REV v4i16 v2 (implicit)
6093 // But this is now broken - the value stored is different to the value loaded
6094 // due to lane reordering. To fix this, on every BITCAST we must perform two
6097 // v1 = REV v2i32 (implicit)
6099 // v3 = BITCAST v2i32 v2 to v4i16
6101 // v5 = REV v4i16 v4 (implicit)
6104 // This means an extra two instructions, but actually in most cases the two REV
6105 // instructions can be combined into one. For example:
6106 // (REV64_2s (REV64_4h X)) === (REV32_4h X)
6108 // There is also no 128-bit REV instruction. This must be synthesized with an
6111 // Most bitconverts require some sort of conversion. The only exceptions are:
6112 // a) Identity conversions - vNfX <-> vNiX
6113 // b) Single-lane-to-scalar - v1fX <-> fX or v1iX <-> iX
6116 // Natural vector casts (64 bit)
6117 def : Pat<(v8i8 (AArch64NvCast (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
6118 def : Pat<(v4i16 (AArch64NvCast (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
6119 def : Pat<(v4f16 (AArch64NvCast (v2i32 FPR64:$src))), (v4f16 FPR64:$src)>;
6120 def : Pat<(v2i32 (AArch64NvCast (v2i32 FPR64:$src))), (v2i32 FPR64:$src)>;
6121 def : Pat<(v2f32 (AArch64NvCast (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;
6122 def : Pat<(v1i64 (AArch64NvCast (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
6124 def : Pat<(v8i8 (AArch64NvCast (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
6125 def : Pat<(v4i16 (AArch64NvCast (v4i16 FPR64:$src))), (v4i16 FPR64:$src)>;
6126 def : Pat<(v4f16 (AArch64NvCast (v4i16 FPR64:$src))), (v4f16 FPR64:$src)>;
6127 def : Pat<(v2i32 (AArch64NvCast (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
6128 def : Pat<(v1i64 (AArch64NvCast (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
6130 def : Pat<(v8i8 (AArch64NvCast (v8i8 FPR64:$src))), (v8i8 FPR64:$src)>;
6131 def : Pat<(v4i16 (AArch64NvCast (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
6132 def : Pat<(v4f16 (AArch64NvCast (v8i8 FPR64:$src))), (v4f16 FPR64:$src)>;
6133 def : Pat<(v2i32 (AArch64NvCast (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
6134 def : Pat<(v2f32 (AArch64NvCast (v8i8 FPR64:$src))), (v2f32 FPR64:$src)>;
6135 def : Pat<(v1i64 (AArch64NvCast (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
6137 def : Pat<(v8i8 (AArch64NvCast (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
6138 def : Pat<(v4i16 (AArch64NvCast (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
6139 def : Pat<(v4f16 (AArch64NvCast (f64 FPR64:$src))), (v4f16 FPR64:$src)>;
6140 def : Pat<(v2i32 (AArch64NvCast (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
6141 def : Pat<(v2f32 (AArch64NvCast (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
6142 def : Pat<(v1i64 (AArch64NvCast (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
6143 def : Pat<(v1f64 (AArch64NvCast (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
6145 def : Pat<(v8i8 (AArch64NvCast (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
6146 def : Pat<(v4i16 (AArch64NvCast (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
6147 def : Pat<(v2i32 (AArch64NvCast (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
6148 def : Pat<(v2f32 (AArch64NvCast (v2f32 FPR64:$src))), (v2f32 FPR64:$src)>;
6149 def : Pat<(v1i64 (AArch64NvCast (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
6151 // Natural vector casts (128 bit)
6152 def : Pat<(v16i8 (AArch64NvCast (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
6153 def : Pat<(v8i16 (AArch64NvCast (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
6154 def : Pat<(v8f16 (AArch64NvCast (v4i32 FPR128:$src))), (v8f16 FPR128:$src)>;
6155 def : Pat<(v4i32 (AArch64NvCast (v4i32 FPR128:$src))), (v4i32 FPR128:$src)>;
6156 def : Pat<(v4f32 (AArch64NvCast (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
6157 def : Pat<(v2i64 (AArch64NvCast (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
6158 def : Pat<(v2f64 (AArch64NvCast (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>;
6160 def : Pat<(v16i8 (AArch64NvCast (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
6161 def : Pat<(v8i16 (AArch64NvCast (v8i16 FPR128:$src))), (v8i16 FPR128:$src)>;
6162 def : Pat<(v8f16 (AArch64NvCast (v8i16 FPR128:$src))), (v8f16 FPR128:$src)>;
6163 def : Pat<(v4i32 (AArch64NvCast (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
6164 def : Pat<(v2i64 (AArch64NvCast (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;
6165 def : Pat<(v4f32 (AArch64NvCast (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>;
6166 def : Pat<(v2f64 (AArch64NvCast (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>;
6168 def : Pat<(v16i8 (AArch64NvCast (v16i8 FPR128:$src))), (v16i8 FPR128:$src)>;
6169 def : Pat<(v8i16 (AArch64NvCast (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
6170 def : Pat<(v8f16 (AArch64NvCast (v16i8 FPR128:$src))), (v8f16 FPR128:$src)>;
6171 def : Pat<(v4i32 (AArch64NvCast (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
6172 def : Pat<(v2i64 (AArch64NvCast (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;
6173 def : Pat<(v4f32 (AArch64NvCast (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>;
6174 def : Pat<(v2f64 (AArch64NvCast (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>;
6176 def : Pat<(v16i8 (AArch64NvCast (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
6177 def : Pat<(v8i16 (AArch64NvCast (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
6178 def : Pat<(v8f16 (AArch64NvCast (v2i64 FPR128:$src))), (v8f16 FPR128:$src)>;
6179 def : Pat<(v4i32 (AArch64NvCast (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
6180 def : Pat<(v2i64 (AArch64NvCast (v2i64 FPR128:$src))), (v2i64 FPR128:$src)>;
6181 def : Pat<(v4f32 (AArch64NvCast (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;
6182 def : Pat<(v2f64 (AArch64NvCast (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
6184 def : Pat<(v16i8 (AArch64NvCast (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
6185 def : Pat<(v8i16 (AArch64NvCast (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
6186 def : Pat<(v4i32 (AArch64NvCast (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
6187 def : Pat<(v4f32 (AArch64NvCast (v4f32 FPR128:$src))), (v4f32 FPR128:$src)>;
6188 def : Pat<(v2i64 (AArch64NvCast (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
6189 def : Pat<(v8f16 (AArch64NvCast (v4f32 FPR128:$src))), (v8f16 FPR128:$src)>;
6190 def : Pat<(v2f64 (AArch64NvCast (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>;
6192 def : Pat<(v16i8 (AArch64NvCast (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
6193 def : Pat<(v8i16 (AArch64NvCast (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
6194 def : Pat<(v4i32 (AArch64NvCast (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
6195 def : Pat<(v2i64 (AArch64NvCast (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
6196 def : Pat<(v2f64 (AArch64NvCast (v2f64 FPR128:$src))), (v2f64 FPR128:$src)>;
6197 def : Pat<(v8f16 (AArch64NvCast (v2f64 FPR128:$src))), (v8f16 FPR128:$src)>;
6198 def : Pat<(v4f32 (AArch64NvCast (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>;
6200 let Predicates = [IsLE] in {
6201 def : Pat<(v8i8 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
6202 def : Pat<(v4i16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
6203 def : Pat<(v2i32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
6204 def : Pat<(v4f16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
6205 def : Pat<(v2f32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
6207 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
6208 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
6209 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
6210 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
6211 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
6212 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
6213 def : Pat<(i64 (bitconvert (v4f16 V64:$Vn))),
6214 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
6215 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
6216 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
6217 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
6218 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
6220 let Predicates = [IsBE] in {
6221 def : Pat<(v8i8 (bitconvert GPR64:$Xn)),
6222 (REV64v8i8 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
6223 def : Pat<(v4i16 (bitconvert GPR64:$Xn)),
6224 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
6225 def : Pat<(v2i32 (bitconvert GPR64:$Xn)),
6226 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
6227 def : Pat<(v4f16 (bitconvert GPR64:$Xn)),
6228 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
6229 def : Pat<(v2f32 (bitconvert GPR64:$Xn)),
6230 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
6232 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
6233 (REV64v8i8 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
6234 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
6235 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
6236 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
6237 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
6238 def : Pat<(i64 (bitconvert (v4f16 V64:$Vn))),
6239 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
6240 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
6241 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
6243 def : Pat<(v1i64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
6244 def : Pat<(v1f64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
6245 def : Pat<(i64 (bitconvert (v1i64 V64:$Vn))),
6246 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
6247 def : Pat<(v1i64 (scalar_to_vector GPR64:$Xn)),
6248 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
6249 def : Pat<(v1f64 (scalar_to_vector GPR64:$Xn)),
6250 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
6251 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Xn))), (v1f64 FPR64:$Xn)>;
6253 def : Pat<(f32 (bitconvert (i32 GPR32:$Xn))),
6254 (COPY_TO_REGCLASS GPR32:$Xn, FPR32)>;
6255 def : Pat<(i32 (bitconvert (f32 FPR32:$Xn))),
6256 (COPY_TO_REGCLASS FPR32:$Xn, GPR32)>;
6257 def : Pat<(f64 (bitconvert (i64 GPR64:$Xn))),
6258 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
6259 def : Pat<(i64 (bitconvert (f64 FPR64:$Xn))),
6260 (COPY_TO_REGCLASS FPR64:$Xn, GPR64)>;
6261 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
6262 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
6264 let Predicates = [IsLE] in {
6265 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
6266 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
6267 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
6268 def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))), (v1i64 FPR64:$src)>;
6269 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
6271 let Predicates = [IsBE] in {
6272 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))),
6273 (v1i64 (REV64v2i32 FPR64:$src))>;
6274 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))),
6275 (v1i64 (REV64v4i16 FPR64:$src))>;
6276 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))),
6277 (v1i64 (REV64v8i8 FPR64:$src))>;
6278 def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))),
6279 (v1i64 (REV64v4i16 FPR64:$src))>;
6280 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))),
6281 (v1i64 (REV64v2i32 FPR64:$src))>;
6283 def : Pat<(v1i64 (bitconvert (v1f64 FPR64:$src))), (v1i64 FPR64:$src)>;
6284 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
6286 let Predicates = [IsLE] in {
6287 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))), (v2i32 FPR64:$src)>;
6288 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
6289 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
6290 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
6291 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))), (v2i32 FPR64:$src)>;
6292 def : Pat<(v2i32 (bitconvert (v4f16 FPR64:$src))), (v2i32 FPR64:$src)>;
6294 let Predicates = [IsBE] in {
6295 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))),
6296 (v2i32 (REV64v2i32 FPR64:$src))>;
6297 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))),
6298 (v2i32 (REV32v4i16 FPR64:$src))>;
6299 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))),
6300 (v2i32 (REV32v8i8 FPR64:$src))>;
6301 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))),
6302 (v2i32 (REV64v2i32 FPR64:$src))>;
6303 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))),
6304 (v2i32 (REV64v2i32 FPR64:$src))>;
6305 def : Pat<(v2i32 (bitconvert (v4f16 FPR64:$src))),
6306 (v2i32 (REV32v4i16 FPR64:$src))>;
6308 def : Pat<(v2i32 (bitconvert (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
6310 let Predicates = [IsLE] in {
6311 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))), (v4i16 FPR64:$src)>;
6312 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
6313 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
6314 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
6315 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
6316 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))), (v4i16 FPR64:$src)>;
6318 let Predicates = [IsBE] in {
6319 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))),
6320 (v4i16 (REV64v4i16 FPR64:$src))>;
6321 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))),
6322 (v4i16 (REV32v4i16 FPR64:$src))>;
6323 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))),
6324 (v4i16 (REV16v8i8 FPR64:$src))>;
6325 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))),
6326 (v4i16 (REV64v4i16 FPR64:$src))>;
6327 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))),
6328 (v4i16 (REV32v4i16 FPR64:$src))>;
6329 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))),
6330 (v4i16 (REV64v4i16 FPR64:$src))>;
6332 def : Pat<(v4i16 (bitconvert (v4f16 FPR64:$src))), (v4i16 FPR64:$src)>;
6334 let Predicates = [IsLE] in {
6335 def : Pat<(v4f16 (bitconvert (v1i64 FPR64:$src))), (v4f16 FPR64:$src)>;
6336 def : Pat<(v4f16 (bitconvert (v2i32 FPR64:$src))), (v4f16 FPR64:$src)>;
6337 def : Pat<(v4f16 (bitconvert (v8i8 FPR64:$src))), (v4f16 FPR64:$src)>;
6338 def : Pat<(v4f16 (bitconvert (f64 FPR64:$src))), (v4f16 FPR64:$src)>;
6339 def : Pat<(v4f16 (bitconvert (v2f32 FPR64:$src))), (v4f16 FPR64:$src)>;
6340 def : Pat<(v4f16 (bitconvert (v1f64 FPR64:$src))), (v4f16 FPR64:$src)>;
6342 let Predicates = [IsBE] in {
6343 def : Pat<(v4f16 (bitconvert (v1i64 FPR64:$src))),
6344 (v4f16 (REV64v4i16 FPR64:$src))>;
6345 def : Pat<(v4f16 (bitconvert (v2i32 FPR64:$src))),
6346 (v4f16 (REV32v4i16 FPR64:$src))>;
6347 def : Pat<(v4f16 (bitconvert (v8i8 FPR64:$src))),
6348 (v4f16 (REV16v8i8 FPR64:$src))>;
6349 def : Pat<(v4f16 (bitconvert (f64 FPR64:$src))),
6350 (v4f16 (REV64v4i16 FPR64:$src))>;
6351 def : Pat<(v4f16 (bitconvert (v2f32 FPR64:$src))),
6352 (v4f16 (REV32v4i16 FPR64:$src))>;
6353 def : Pat<(v4f16 (bitconvert (v1f64 FPR64:$src))),
6354 (v4f16 (REV64v4i16 FPR64:$src))>;
6356 def : Pat<(v4f16 (bitconvert (v4i16 FPR64:$src))), (v4f16 FPR64:$src)>;
6358 let Predicates = [IsLE] in {
6359 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))), (v8i8 FPR64:$src)>;
6360 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
6361 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
6362 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
6363 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
6364 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))), (v8i8 FPR64:$src)>;
6365 def : Pat<(v8i8 (bitconvert (v4f16 FPR64:$src))), (v8i8 FPR64:$src)>;
6367 let Predicates = [IsBE] in {
6368 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))),
6369 (v8i8 (REV64v8i8 FPR64:$src))>;
6370 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))),
6371 (v8i8 (REV32v8i8 FPR64:$src))>;
6372 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))),
6373 (v8i8 (REV16v8i8 FPR64:$src))>;
6374 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))),
6375 (v8i8 (REV64v8i8 FPR64:$src))>;
6376 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))),
6377 (v8i8 (REV32v8i8 FPR64:$src))>;
6378 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))),
6379 (v8i8 (REV64v8i8 FPR64:$src))>;
6380 def : Pat<(v8i8 (bitconvert (v4f16 FPR64:$src))),
6381 (v8i8 (REV16v8i8 FPR64:$src))>;
6384 let Predicates = [IsLE] in {
6385 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))), (f64 FPR64:$src)>;
6386 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))), (f64 FPR64:$src)>;
6387 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))), (f64 FPR64:$src)>;
6388 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))), (f64 FPR64:$src)>;
6389 def : Pat<(f64 (bitconvert (v4f16 FPR64:$src))), (f64 FPR64:$src)>;
6391 let Predicates = [IsBE] in {
6392 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))),
6393 (f64 (REV64v2i32 FPR64:$src))>;
6394 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))),
6395 (f64 (REV64v4i16 FPR64:$src))>;
6396 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))),
6397 (f64 (REV64v2i32 FPR64:$src))>;
6398 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))),
6399 (f64 (REV64v8i8 FPR64:$src))>;
6400 def : Pat<(f64 (bitconvert (v4f16 FPR64:$src))),
6401 (f64 (REV64v4i16 FPR64:$src))>;
6403 def : Pat<(f64 (bitconvert (v1i64 FPR64:$src))), (f64 FPR64:$src)>;
6404 def : Pat<(f64 (bitconvert (v1f64 FPR64:$src))), (f64 FPR64:$src)>;
6406 let Predicates = [IsLE] in {
6407 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))), (v1f64 FPR64:$src)>;
6408 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))), (v1f64 FPR64:$src)>;
6409 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))), (v1f64 FPR64:$src)>;
6410 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))), (v1f64 FPR64:$src)>;
6411 def : Pat<(v1f64 (bitconvert (v4f16 FPR64:$src))), (v1f64 FPR64:$src)>;
6413 let Predicates = [IsBE] in {
6414 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))),
6415 (v1f64 (REV64v2i32 FPR64:$src))>;
6416 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))),
6417 (v1f64 (REV64v4i16 FPR64:$src))>;
6418 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))),
6419 (v1f64 (REV64v8i8 FPR64:$src))>;
6420 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))),
6421 (v1f64 (REV64v2i32 FPR64:$src))>;
6422 def : Pat<(v1f64 (bitconvert (v4f16 FPR64:$src))),
6423 (v1f64 (REV64v4i16 FPR64:$src))>;
6425 def : Pat<(v1f64 (bitconvert (v1i64 FPR64:$src))), (v1f64 FPR64:$src)>;
6426 def : Pat<(v1f64 (bitconvert (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
6428 let Predicates = [IsLE] in {
6429 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))), (v2f32 FPR64:$src)>;
6430 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))), (v2f32 FPR64:$src)>;
6431 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))), (v2f32 FPR64:$src)>;
6432 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))), (v2f32 FPR64:$src)>;
6433 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
6434 def : Pat<(v2f32 (bitconvert (v4f16 FPR64:$src))), (v2f32 FPR64:$src)>;
6436 let Predicates = [IsBE] in {
6437 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))),
6438 (v2f32 (REV64v2i32 FPR64:$src))>;
6439 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))),
6440 (v2f32 (REV32v4i16 FPR64:$src))>;
6441 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))),
6442 (v2f32 (REV32v8i8 FPR64:$src))>;
6443 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))),
6444 (v2f32 (REV64v2i32 FPR64:$src))>;
6445 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))),
6446 (v2f32 (REV64v2i32 FPR64:$src))>;
6447 def : Pat<(v2f32 (bitconvert (v4f16 FPR64:$src))),
6448 (v2f32 (REV32v4i16 FPR64:$src))>;
6450 def : Pat<(v2f32 (bitconvert (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;
6452 let Predicates = [IsLE] in {
6453 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))), (f128 FPR128:$src)>;
6454 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))), (f128 FPR128:$src)>;
6455 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))), (f128 FPR128:$src)>;
6456 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))), (f128 FPR128:$src)>;
6457 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))), (f128 FPR128:$src)>;
6458 def : Pat<(f128 (bitconvert (v8f16 FPR128:$src))), (f128 FPR128:$src)>;
6459 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))), (f128 FPR128:$src)>;
6461 let Predicates = [IsBE] in {
6462 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))),
6463 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
6464 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))),
6465 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
6466 (REV64v4i32 FPR128:$src), (i32 8)))>;
6467 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))),
6468 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src),
6469 (REV64v8i16 FPR128:$src), (i32 8)))>;
6470 def : Pat<(f128 (bitconvert (v8f16 FPR128:$src))),
6471 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src),
6472 (REV64v8i16 FPR128:$src), (i32 8)))>;
6473 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))),
6474 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
6475 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))),
6476 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
6477 (REV64v4i32 FPR128:$src), (i32 8)))>;
6478 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))),
6479 (f128 (EXTv16i8 (REV64v16i8 FPR128:$src),
6480 (REV64v16i8 FPR128:$src), (i32 8)))>;
6483 let Predicates = [IsLE] in {
6484 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), (v2f64 FPR128:$src)>;
6485 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>;
6486 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>;
6487 def : Pat<(v2f64 (bitconvert (v8f16 FPR128:$src))), (v2f64 FPR128:$src)>;
6488 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>;
6489 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>;
6491 let Predicates = [IsBE] in {
6492 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))),
6493 (v2f64 (EXTv16i8 FPR128:$src,
6494 FPR128:$src, (i32 8)))>;
6495 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))),
6496 (v2f64 (REV64v4i32 FPR128:$src))>;
6497 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))),
6498 (v2f64 (REV64v8i16 FPR128:$src))>;
6499 def : Pat<(v2f64 (bitconvert (v8f16 FPR128:$src))),
6500 (v2f64 (REV64v8i16 FPR128:$src))>;
6501 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))),
6502 (v2f64 (REV64v16i8 FPR128:$src))>;
6503 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))),
6504 (v2f64 (REV64v4i32 FPR128:$src))>;
6506 def : Pat<(v2f64 (bitconvert (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
6508 let Predicates = [IsLE] in {
6509 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), (v4f32 FPR128:$src)>;
6510 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>;
6511 def : Pat<(v4f32 (bitconvert (v8f16 FPR128:$src))), (v4f32 FPR128:$src)>;
6512 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>;
6513 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;
6514 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>;
6516 let Predicates = [IsBE] in {
6517 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))),
6518 (v4f32 (EXTv16i8 (REV64v4i32 FPR128:$src),
6519 (REV64v4i32 FPR128:$src), (i32 8)))>;
6520 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))),
6521 (v4f32 (REV32v8i16 FPR128:$src))>;
6522 def : Pat<(v4f32 (bitconvert (v8f16 FPR128:$src))),
6523 (v4f32 (REV32v8i16 FPR128:$src))>;
6524 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))),
6525 (v4f32 (REV32v16i8 FPR128:$src))>;
6526 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))),
6527 (v4f32 (REV64v4i32 FPR128:$src))>;
6528 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))),
6529 (v4f32 (REV64v4i32 FPR128:$src))>;
6531 def : Pat<(v4f32 (bitconvert (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
6533 let Predicates = [IsLE] in {
6534 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), (v2i64 FPR128:$src)>;
6535 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
6536 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;
6537 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;
6538 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
6539 def : Pat<(v2i64 (bitconvert (v8f16 FPR128:$src))), (v2i64 FPR128:$src)>;
6541 let Predicates = [IsBE] in {
6542 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))),
6543 (v2i64 (EXTv16i8 FPR128:$src,
6544 FPR128:$src, (i32 8)))>;
6545 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))),
6546 (v2i64 (REV64v4i32 FPR128:$src))>;
6547 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))),
6548 (v2i64 (REV64v8i16 FPR128:$src))>;
6549 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))),
6550 (v2i64 (REV64v16i8 FPR128:$src))>;
6551 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))),
6552 (v2i64 (REV64v4i32 FPR128:$src))>;
6553 def : Pat<(v2i64 (bitconvert (v8f16 FPR128:$src))),
6554 (v2i64 (REV64v8i16 FPR128:$src))>;
6556 def : Pat<(v2i64 (bitconvert (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
6558 let Predicates = [IsLE] in {
6559 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), (v4i32 FPR128:$src)>;
6560 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
6561 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
6562 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
6563 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
6564 def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))), (v4i32 FPR128:$src)>;
6566 let Predicates = [IsBE] in {
6567 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))),
6568 (v4i32 (EXTv16i8 (REV64v4i32 FPR128:$src),
6569 (REV64v4i32 FPR128:$src),
6571 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))),
6572 (v4i32 (REV64v4i32 FPR128:$src))>;
6573 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))),
6574 (v4i32 (REV32v8i16 FPR128:$src))>;
6575 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))),
6576 (v4i32 (REV32v16i8 FPR128:$src))>;
6577 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))),
6578 (v4i32 (REV64v4i32 FPR128:$src))>;
6579 def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))),
6580 (v4i32 (REV32v8i16 FPR128:$src))>;
6582 def : Pat<(v4i32 (bitconvert (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
6584 let Predicates = [IsLE] in {
6585 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), (v8i16 FPR128:$src)>;
6586 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
6587 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
6588 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
6589 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
6590 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
6592 let Predicates = [IsBE] in {
6593 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))),
6594 (v8i16 (EXTv16i8 (REV64v8i16 FPR128:$src),
6595 (REV64v8i16 FPR128:$src),
6597 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))),
6598 (v8i16 (REV64v8i16 FPR128:$src))>;
6599 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))),
6600 (v8i16 (REV32v8i16 FPR128:$src))>;
6601 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))),
6602 (v8i16 (REV16v16i8 FPR128:$src))>;
6603 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))),
6604 (v8i16 (REV64v8i16 FPR128:$src))>;
6605 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))),
6606 (v8i16 (REV32v8i16 FPR128:$src))>;
6608 def : Pat<(v8i16 (bitconvert (v8f16 FPR128:$src))), (v8i16 FPR128:$src)>;
6610 let Predicates = [IsLE] in {
6611 def : Pat<(v8f16 (bitconvert (f128 FPR128:$src))), (v8f16 FPR128:$src)>;
6612 def : Pat<(v8f16 (bitconvert (v2i64 FPR128:$src))), (v8f16 FPR128:$src)>;
6613 def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))), (v8f16 FPR128:$src)>;
6614 def : Pat<(v8f16 (bitconvert (v16i8 FPR128:$src))), (v8f16 FPR128:$src)>;
6615 def : Pat<(v8f16 (bitconvert (v2f64 FPR128:$src))), (v8f16 FPR128:$src)>;
6616 def : Pat<(v8f16 (bitconvert (v4f32 FPR128:$src))), (v8f16 FPR128:$src)>;
6618 let Predicates = [IsBE] in {
6619 def : Pat<(v8f16 (bitconvert (f128 FPR128:$src))),
6620 (v8f16 (EXTv16i8 (REV64v8i16 FPR128:$src),
6621 (REV64v8i16 FPR128:$src),
6623 def : Pat<(v8f16 (bitconvert (v2i64 FPR128:$src))),
6624 (v8f16 (REV64v8i16 FPR128:$src))>;
6625 def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))),
6626 (v8f16 (REV32v8i16 FPR128:$src))>;
6627 def : Pat<(v8f16 (bitconvert (v16i8 FPR128:$src))),
6628 (v8f16 (REV16v16i8 FPR128:$src))>;
6629 def : Pat<(v8f16 (bitconvert (v2f64 FPR128:$src))),
6630 (v8f16 (REV64v8i16 FPR128:$src))>;
6631 def : Pat<(v8f16 (bitconvert (v4f32 FPR128:$src))),
6632 (v8f16 (REV32v8i16 FPR128:$src))>;
6634 def : Pat<(v8f16 (bitconvert (v8i16 FPR128:$src))), (v8f16 FPR128:$src)>;
6636 let Predicates = [IsLE] in {
6637 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 FPR128:$src)>;
6638 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
6639 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
6640 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
6641 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
6642 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
6643 def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))), (v16i8 FPR128:$src)>;
6645 let Predicates = [IsBE] in {
6646 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))),
6647 (v16i8 (EXTv16i8 (REV64v16i8 FPR128:$src),
6648 (REV64v16i8 FPR128:$src),
6650 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))),
6651 (v16i8 (REV64v16i8 FPR128:$src))>;
6652 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))),
6653 (v16i8 (REV32v16i8 FPR128:$src))>;
6654 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))),
6655 (v16i8 (REV16v16i8 FPR128:$src))>;
6656 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))),
6657 (v16i8 (REV64v16i8 FPR128:$src))>;
6658 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))),
6659 (v16i8 (REV32v16i8 FPR128:$src))>;
6660 def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))),
6661 (v16i8 (REV16v16i8 FPR128:$src))>;
6664 def : Pat<(v4i16 (extract_subvector V128:$Rn, (i64 0))),
6665 (EXTRACT_SUBREG V128:$Rn, dsub)>;
6666 def : Pat<(v8i8 (extract_subvector V128:$Rn, (i64 0))),
6667 (EXTRACT_SUBREG V128:$Rn, dsub)>;
6668 def : Pat<(v2f32 (extract_subvector V128:$Rn, (i64 0))),
6669 (EXTRACT_SUBREG V128:$Rn, dsub)>;
6670 def : Pat<(v4f16 (extract_subvector V128:$Rn, (i64 0))),
6671 (EXTRACT_SUBREG V128:$Rn, dsub)>;
6672 def : Pat<(v2i32 (extract_subvector V128:$Rn, (i64 0))),
6673 (EXTRACT_SUBREG V128:$Rn, dsub)>;
6674 def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 0))),
6675 (EXTRACT_SUBREG V128:$Rn, dsub)>;
6676 def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 0))),
6677 (EXTRACT_SUBREG V128:$Rn, dsub)>;
6679 def : Pat<(v8i8 (extract_subvector (v16i8 FPR128:$Rn), (i64 1))),
6680 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
6681 def : Pat<(v4i16 (extract_subvector (v8i16 FPR128:$Rn), (i64 1))),
6682 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
6683 def : Pat<(v2i32 (extract_subvector (v4i32 FPR128:$Rn), (i64 1))),
6684 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
6685 def : Pat<(v1i64 (extract_subvector (v2i64 FPR128:$Rn), (i64 1))),
6686 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
6688 // A 64-bit subvector insert to the first 128-bit vector position
6689 // is a subregister copy that needs no instruction.
6690 multiclass InsertSubvectorUndef<ValueType Ty> {
6691 def : Pat<(insert_subvector undef, (v1i64 FPR64:$src), (Ty 0)),
6692 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
6693 def : Pat<(insert_subvector undef, (v1f64 FPR64:$src), (Ty 0)),
6694 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
6695 def : Pat<(insert_subvector undef, (v2i32 FPR64:$src), (Ty 0)),
6696 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
6697 def : Pat<(insert_subvector undef, (v2f32 FPR64:$src), (Ty 0)),
6698 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
6699 def : Pat<(insert_subvector undef, (v4i16 FPR64:$src), (Ty 0)),
6700 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
6701 def : Pat<(insert_subvector undef, (v4f16 FPR64:$src), (Ty 0)),
6702 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
6703 def : Pat<(insert_subvector undef, (v8i8 FPR64:$src), (Ty 0)),
6704 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
6707 defm : InsertSubvectorUndef<i32>;
6708 defm : InsertSubvectorUndef<i64>;
6710 // Use pair-wise add instructions when summing up the lanes for v2f64, v2i64
6712 def : Pat<(i64 (add (vector_extract (v2i64 FPR128:$Rn), (i64 0)),
6713 (vector_extract (v2i64 FPR128:$Rn), (i64 1)))),
6714 (i64 (ADDPv2i64p (v2i64 FPR128:$Rn)))>;
6715 def : Pat<(f64 (fadd (vector_extract (v2f64 FPR128:$Rn), (i64 0)),
6716 (vector_extract (v2f64 FPR128:$Rn), (i64 1)))),
6717 (f64 (FADDPv2i64p (v2f64 FPR128:$Rn)))>;
6718 // vector_extract on 64-bit vectors gets promoted to a 128 bit vector,
6719 // so we match on v4f32 here, not v2f32. This will also catch adding
6720 // the low two lanes of a true v4f32 vector.
6721 def : Pat<(fadd (vector_extract (v4f32 FPR128:$Rn), (i64 0)),
6722 (vector_extract (v4f32 FPR128:$Rn), (i64 1))),
6723 (f32 (FADDPv2i32p (EXTRACT_SUBREG FPR128:$Rn, dsub)))>;
6725 // Scalar 64-bit shifts in FPR64 registers.
6726 def : Pat<(i64 (int_aarch64_neon_sshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
6727 (SSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
6728 def : Pat<(i64 (int_aarch64_neon_ushl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
6729 (USHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
6730 def : Pat<(i64 (int_aarch64_neon_srshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
6731 (SRSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
6732 def : Pat<(i64 (int_aarch64_neon_urshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
6733 (URSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
6735 // Patterns for nontemporal/no-allocate stores.
6736 // We have to resort to tricks to turn a single-input store into a store pair,
6737 // because there is no single-input nontemporal store, only STNP.
6738 let Predicates = [IsLE] in {
6739 let AddedComplexity = 15 in {
6740 class NTStore128Pat<ValueType VT> :
6741 Pat<(nontemporalstore (VT FPR128:$Rt),
6742 (am_indexed7s64 GPR64sp:$Rn, simm7s8:$offset)),
6743 (STNPDi (EXTRACT_SUBREG FPR128:$Rt, dsub),
6744 (CPYi64 FPR128:$Rt, (i64 1)),
6745 GPR64sp:$Rn, simm7s8:$offset)>;
6747 def : NTStore128Pat<v2i64>;
6748 def : NTStore128Pat<v4i32>;
6749 def : NTStore128Pat<v8i16>;
6750 def : NTStore128Pat<v16i8>;
6752 class NTStore64Pat<ValueType VT> :
6753 Pat<(nontemporalstore (VT FPR64:$Rt),
6754 (am_indexed7s32 GPR64sp:$Rn, simm7s4:$offset)),
6755 (STNPSi (EXTRACT_SUBREG FPR64:$Rt, ssub),
6756 (CPYi32 (SUBREG_TO_REG (i64 0), FPR64:$Rt, dsub), (i64 1)),
6757 GPR64sp:$Rn, simm7s4:$offset)>;
6759 // FIXME: Shouldn't v1f64 loads/stores be promoted to v1i64?
6760 def : NTStore64Pat<v1f64>;
6761 def : NTStore64Pat<v1i64>;
6762 def : NTStore64Pat<v2i32>;
6763 def : NTStore64Pat<v4i16>;
6764 def : NTStore64Pat<v8i8>;
6766 def : Pat<(nontemporalstore GPR64:$Rt,
6767 (am_indexed7s32 GPR64sp:$Rn, simm7s4:$offset)),
6768 (STNPWi (EXTRACT_SUBREG GPR64:$Rt, sub_32),
6769 (EXTRACT_SUBREG (UBFMXri GPR64:$Rt, 32, 63), sub_32),
6770 GPR64sp:$Rn, simm7s4:$offset)>;
6771 } // AddedComplexity=10
6772 } // Predicates = [IsLE]
6774 // Tail call return handling. These are all compiler pseudo-instructions,
6775 // so no encoding information or anything like that.
6776 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
6777 def TCRETURNdi : Pseudo<(outs), (ins i64imm:$dst, i32imm:$FPDiff), []>,
6778 Sched<[WriteBrReg]>;
6779 def TCRETURNri : Pseudo<(outs), (ins tcGPR64:$dst, i32imm:$FPDiff), []>,
6780 Sched<[WriteBrReg]>;
6781 // Indirect tail-call with any register allowed, used by MachineOutliner when
6782 // this is proven safe.
6783 // FIXME: If we have to add any more hacks like this, we should instead relax
6784 // some verifier checks for outlined functions.
6785 def TCRETURNriALL : Pseudo<(outs), (ins GPR64:$dst, i32imm:$FPDiff), []>,
6786 Sched<[WriteBrReg]>;
6787 // Indirect tail-call limited to only use registers (x16 and x17) which are
6788 // allowed to tail-call a "BTI c" instruction.
6789 def TCRETURNriBTI : Pseudo<(outs), (ins rtcGPR64:$dst, i32imm:$FPDiff), []>,
6790 Sched<[WriteBrReg]>;
6793 def : Pat<(AArch64tcret tcGPR64:$dst, (i32 timm:$FPDiff)),
6794 (TCRETURNri tcGPR64:$dst, imm:$FPDiff)>,
6795 Requires<[NotUseBTI]>;
6796 def : Pat<(AArch64tcret rtcGPR64:$dst, (i32 timm:$FPDiff)),
6797 (TCRETURNriBTI rtcGPR64:$dst, imm:$FPDiff)>,
6799 def : Pat<(AArch64tcret tglobaladdr:$dst, (i32 timm:$FPDiff)),
6800 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
6801 def : Pat<(AArch64tcret texternalsym:$dst, (i32 timm:$FPDiff)),
6802 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
6804 include "AArch64InstrAtomics.td"
6805 include "AArch64SVEInstrInfo.td"