1 //===- AArch64InstructionSelector.cpp ----------------------------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file implements the targeting of the InstructionSelector class for
12 /// \todo This should be generated by TableGen.
13 //===----------------------------------------------------------------------===//
15 #include "AArch64InstructionSelector.h"
16 #include "AArch64InstrInfo.h"
17 #include "AArch64RegisterBankInfo.h"
18 #include "AArch64RegisterInfo.h"
19 #include "AArch64Subtarget.h"
20 #include "AArch64TargetMachine.h"
21 #include "MCTargetDesc/AArch64AddressingModes.h"
22 #include "llvm/CodeGen/MachineBasicBlock.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstr.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/IR/Type.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/raw_ostream.h"
31 #define DEBUG_TYPE "aarch64-isel"
35 #ifndef LLVM_BUILD_GLOBAL_ISEL
36 #error "You shouldn't build this"
39 #include "AArch64GenGlobalISel.inc"
41 AArch64InstructionSelector::AArch64InstructionSelector(
42 const AArch64TargetMachine &TM, const AArch64Subtarget &STI,
43 const AArch64RegisterBankInfo &RBI)
44 : InstructionSelector(), TM(TM), STI(STI), TII(*STI.getInstrInfo()),
45 TRI(*STI.getRegisterInfo()), RBI(RBI) {}
47 // FIXME: This should be target-independent, inferred from the types declared
48 // for each class in the bank.
49 static const TargetRegisterClass *
50 getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB,
51 const RegisterBankInfo &RBI) {
52 if (RB.getID() == AArch64::GPRRegBankID) {
53 if (Ty.getSizeInBits() <= 32)
54 return &AArch64::GPR32RegClass;
55 if (Ty.getSizeInBits() == 64)
56 return &AArch64::GPR64RegClass;
60 if (RB.getID() == AArch64::FPRRegBankID) {
61 if (Ty.getSizeInBits() == 32)
62 return &AArch64::FPR32RegClass;
63 if (Ty.getSizeInBits() == 64)
64 return &AArch64::FPR64RegClass;
65 if (Ty.getSizeInBits() == 128)
66 return &AArch64::FPR128RegClass;
73 /// Check whether \p I is a currently unsupported binary operation:
74 /// - it has an unsized type
75 /// - an operand is not a vreg
76 /// - all operands are not in the same bank
77 /// These are checks that should someday live in the verifier, but right now,
78 /// these are mostly limitations of the aarch64 selector.
79 static bool unsupportedBinOp(const MachineInstr &I,
80 const AArch64RegisterBankInfo &RBI,
81 const MachineRegisterInfo &MRI,
82 const AArch64RegisterInfo &TRI) {
83 LLT Ty = MRI.getType(I.getOperand(0).getReg());
85 DEBUG(dbgs() << "Generic binop register should be typed\n");
89 const RegisterBank *PrevOpBank = nullptr;
90 for (auto &MO : I.operands()) {
91 // FIXME: Support non-register operands.
93 DEBUG(dbgs() << "Generic inst non-reg operands are unsupported\n");
97 // FIXME: Can generic operations have physical registers operands? If
98 // so, this will need to be taught about that, and we'll need to get the
99 // bank out of the minimal class for the register.
100 // Either way, this needs to be documented (and possibly verified).
101 if (!TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
102 DEBUG(dbgs() << "Generic inst has physical register operand\n");
106 const RegisterBank *OpBank = RBI.getRegBank(MO.getReg(), MRI, TRI);
108 DEBUG(dbgs() << "Generic register has no bank or class\n");
112 if (PrevOpBank && OpBank != PrevOpBank) {
113 DEBUG(dbgs() << "Generic inst operands have different banks\n");
121 /// Select the AArch64 opcode for the basic binary operation \p GenericOpc
122 /// (such as G_OR or G_ADD), appropriate for the register bank \p RegBankID
123 /// and of size \p OpSize.
124 /// \returns \p GenericOpc if the combination is unsupported.
125 static unsigned selectBinaryOp(unsigned GenericOpc, unsigned RegBankID,
128 case AArch64::GPRRegBankID:
130 assert((OpSize == 32 || (GenericOpc != TargetOpcode::G_SDIV &&
131 GenericOpc != TargetOpcode::G_UDIV &&
132 GenericOpc != TargetOpcode::G_LSHR &&
133 GenericOpc != TargetOpcode::G_ASHR)) &&
134 "operation should have been legalized before now");
136 switch (GenericOpc) {
137 case TargetOpcode::G_OR:
138 return AArch64::ORRWrr;
139 case TargetOpcode::G_XOR:
140 return AArch64::EORWrr;
141 case TargetOpcode::G_AND:
142 return AArch64::ANDWrr;
143 case TargetOpcode::G_ADD:
144 assert(OpSize != 32 && "s32 G_ADD should have been selected");
145 return AArch64::ADDWrr;
146 case TargetOpcode::G_SUB:
147 return AArch64::SUBWrr;
148 case TargetOpcode::G_SHL:
149 return AArch64::LSLVWr;
150 case TargetOpcode::G_LSHR:
151 return AArch64::LSRVWr;
152 case TargetOpcode::G_ASHR:
153 return AArch64::ASRVWr;
154 case TargetOpcode::G_SDIV:
155 return AArch64::SDIVWr;
156 case TargetOpcode::G_UDIV:
157 return AArch64::UDIVWr;
161 } else if (OpSize == 64) {
162 switch (GenericOpc) {
163 case TargetOpcode::G_OR:
164 return AArch64::ORRXrr;
165 case TargetOpcode::G_XOR:
166 return AArch64::EORXrr;
167 case TargetOpcode::G_AND:
168 return AArch64::ANDXrr;
169 case TargetOpcode::G_GEP:
170 return AArch64::ADDXrr;
171 case TargetOpcode::G_SUB:
172 return AArch64::SUBXrr;
173 case TargetOpcode::G_SHL:
174 return AArch64::LSLVXr;
175 case TargetOpcode::G_LSHR:
176 return AArch64::LSRVXr;
177 case TargetOpcode::G_ASHR:
178 return AArch64::ASRVXr;
179 case TargetOpcode::G_SDIV:
180 return AArch64::SDIVXr;
181 case TargetOpcode::G_UDIV:
182 return AArch64::UDIVXr;
187 case AArch64::FPRRegBankID:
190 switch (GenericOpc) {
191 case TargetOpcode::G_FADD:
192 return AArch64::FADDSrr;
193 case TargetOpcode::G_FSUB:
194 return AArch64::FSUBSrr;
195 case TargetOpcode::G_FMUL:
196 return AArch64::FMULSrr;
197 case TargetOpcode::G_FDIV:
198 return AArch64::FDIVSrr;
203 switch (GenericOpc) {
204 case TargetOpcode::G_FADD:
205 return AArch64::FADDDrr;
206 case TargetOpcode::G_FSUB:
207 return AArch64::FSUBDrr;
208 case TargetOpcode::G_FMUL:
209 return AArch64::FMULDrr;
210 case TargetOpcode::G_FDIV:
211 return AArch64::FDIVDrr;
212 case TargetOpcode::G_OR:
213 return AArch64::ORRv8i8;
222 /// Select the AArch64 opcode for the G_LOAD or G_STORE operation \p GenericOpc,
223 /// appropriate for the (value) register bank \p RegBankID and of memory access
224 /// size \p OpSize. This returns the variant with the base+unsigned-immediate
225 /// addressing mode (e.g., LDRXui).
226 /// \returns \p GenericOpc if the combination is unsupported.
227 static unsigned selectLoadStoreUIOp(unsigned GenericOpc, unsigned RegBankID,
229 const bool isStore = GenericOpc == TargetOpcode::G_STORE;
231 case AArch64::GPRRegBankID:
234 return isStore ? AArch64::STRBBui : AArch64::LDRBBui;
236 return isStore ? AArch64::STRHHui : AArch64::LDRHHui;
238 return isStore ? AArch64::STRWui : AArch64::LDRWui;
240 return isStore ? AArch64::STRXui : AArch64::LDRXui;
242 case AArch64::FPRRegBankID:
245 return isStore ? AArch64::STRBui : AArch64::LDRBui;
247 return isStore ? AArch64::STRHui : AArch64::LDRHui;
249 return isStore ? AArch64::STRSui : AArch64::LDRSui;
251 return isStore ? AArch64::STRDui : AArch64::LDRDui;
257 static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
258 MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
259 const RegisterBankInfo &RBI) {
261 unsigned DstReg = I.getOperand(0).getReg();
262 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
263 assert(I.isCopy() && "Generic operators do not allow physical registers");
267 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI);
268 const unsigned DstSize = MRI.getType(DstReg).getSizeInBits();
269 unsigned SrcReg = I.getOperand(1).getReg();
270 const unsigned SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI);
272 assert((!TargetRegisterInfo::isPhysicalRegister(SrcReg) || I.isCopy()) &&
273 "No phys reg on generic operators");
275 (DstSize == SrcSize ||
276 // Copies are a mean to setup initial types, the number of
277 // bits may not exactly match.
278 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
279 DstSize <= RBI.getSizeInBits(SrcReg, MRI, TRI)) ||
280 // Copies are a mean to copy bits around, as long as we are
281 // on the same register class, that's fine. Otherwise, that
282 // means we need some SUBREG_TO_REG or AND & co.
283 (((DstSize + 31) / 32 == (SrcSize + 31) / 32) && DstSize > SrcSize)) &&
284 "Copy with different width?!");
285 assert((DstSize <= 64 || RegBank.getID() == AArch64::FPRRegBankID) &&
286 "GPRs cannot get more than 64-bit width values");
287 const TargetRegisterClass *RC = nullptr;
289 if (RegBank.getID() == AArch64::FPRRegBankID) {
291 RC = &AArch64::FPR32RegClass;
292 else if (DstSize <= 64)
293 RC = &AArch64::FPR64RegClass;
294 else if (DstSize <= 128)
295 RC = &AArch64::FPR128RegClass;
297 DEBUG(dbgs() << "Unexpected bitcast size " << DstSize << '\n');
301 assert(RegBank.getID() == AArch64::GPRRegBankID &&
302 "Bitcast for the flags?");
304 DstSize <= 32 ? &AArch64::GPR32allRegClass : &AArch64::GPR64allRegClass;
307 // No need to constrain SrcReg. It will get constrained when
308 // we hit another of its use or its defs.
309 // Copies do not have constraints.
310 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
311 DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
315 I.setDesc(TII.get(AArch64::COPY));
319 static unsigned selectFPConvOpc(unsigned GenericOpc, LLT DstTy, LLT SrcTy) {
320 if (!DstTy.isScalar() || !SrcTy.isScalar())
323 const unsigned DstSize = DstTy.getSizeInBits();
324 const unsigned SrcSize = SrcTy.getSizeInBits();
330 switch (GenericOpc) {
331 case TargetOpcode::G_SITOFP:
332 return AArch64::SCVTFUWSri;
333 case TargetOpcode::G_UITOFP:
334 return AArch64::UCVTFUWSri;
335 case TargetOpcode::G_FPTOSI:
336 return AArch64::FCVTZSUWSr;
337 case TargetOpcode::G_FPTOUI:
338 return AArch64::FCVTZUUWSr;
343 switch (GenericOpc) {
344 case TargetOpcode::G_SITOFP:
345 return AArch64::SCVTFUXSri;
346 case TargetOpcode::G_UITOFP:
347 return AArch64::UCVTFUXSri;
348 case TargetOpcode::G_FPTOSI:
349 return AArch64::FCVTZSUWDr;
350 case TargetOpcode::G_FPTOUI:
351 return AArch64::FCVTZUUWDr;
361 switch (GenericOpc) {
362 case TargetOpcode::G_SITOFP:
363 return AArch64::SCVTFUWDri;
364 case TargetOpcode::G_UITOFP:
365 return AArch64::UCVTFUWDri;
366 case TargetOpcode::G_FPTOSI:
367 return AArch64::FCVTZSUXSr;
368 case TargetOpcode::G_FPTOUI:
369 return AArch64::FCVTZUUXSr;
374 switch (GenericOpc) {
375 case TargetOpcode::G_SITOFP:
376 return AArch64::SCVTFUXDri;
377 case TargetOpcode::G_UITOFP:
378 return AArch64::UCVTFUXDri;
379 case TargetOpcode::G_FPTOSI:
380 return AArch64::FCVTZSUXDr;
381 case TargetOpcode::G_FPTOUI:
382 return AArch64::FCVTZUUXDr;
395 static AArch64CC::CondCode changeICMPPredToAArch64CC(CmpInst::Predicate P) {
398 llvm_unreachable("Unknown condition code!");
399 case CmpInst::ICMP_NE:
400 return AArch64CC::NE;
401 case CmpInst::ICMP_EQ:
402 return AArch64CC::EQ;
403 case CmpInst::ICMP_SGT:
404 return AArch64CC::GT;
405 case CmpInst::ICMP_SGE:
406 return AArch64CC::GE;
407 case CmpInst::ICMP_SLT:
408 return AArch64CC::LT;
409 case CmpInst::ICMP_SLE:
410 return AArch64CC::LE;
411 case CmpInst::ICMP_UGT:
412 return AArch64CC::HI;
413 case CmpInst::ICMP_UGE:
414 return AArch64CC::HS;
415 case CmpInst::ICMP_ULT:
416 return AArch64CC::LO;
417 case CmpInst::ICMP_ULE:
418 return AArch64CC::LS;
422 static void changeFCMPPredToAArch64CC(CmpInst::Predicate P,
423 AArch64CC::CondCode &CondCode,
424 AArch64CC::CondCode &CondCode2) {
425 CondCode2 = AArch64CC::AL;
428 llvm_unreachable("Unknown FP condition!");
429 case CmpInst::FCMP_OEQ:
430 CondCode = AArch64CC::EQ;
432 case CmpInst::FCMP_OGT:
433 CondCode = AArch64CC::GT;
435 case CmpInst::FCMP_OGE:
436 CondCode = AArch64CC::GE;
438 case CmpInst::FCMP_OLT:
439 CondCode = AArch64CC::MI;
441 case CmpInst::FCMP_OLE:
442 CondCode = AArch64CC::LS;
444 case CmpInst::FCMP_ONE:
445 CondCode = AArch64CC::MI;
446 CondCode2 = AArch64CC::GT;
448 case CmpInst::FCMP_ORD:
449 CondCode = AArch64CC::VC;
451 case CmpInst::FCMP_UNO:
452 CondCode = AArch64CC::VS;
454 case CmpInst::FCMP_UEQ:
455 CondCode = AArch64CC::EQ;
456 CondCode2 = AArch64CC::VS;
458 case CmpInst::FCMP_UGT:
459 CondCode = AArch64CC::HI;
461 case CmpInst::FCMP_UGE:
462 CondCode = AArch64CC::PL;
464 case CmpInst::FCMP_ULT:
465 CondCode = AArch64CC::LT;
467 case CmpInst::FCMP_ULE:
468 CondCode = AArch64CC::LE;
470 case CmpInst::FCMP_UNE:
471 CondCode = AArch64CC::NE;
476 bool AArch64InstructionSelector::select(MachineInstr &I) const {
477 assert(I.getParent() && "Instruction should be in a basic block!");
478 assert(I.getParent()->getParent() && "Instruction should be in a function!");
480 MachineBasicBlock &MBB = *I.getParent();
481 MachineFunction &MF = *MBB.getParent();
482 MachineRegisterInfo &MRI = MF.getRegInfo();
484 unsigned Opcode = I.getOpcode();
485 if (!isPreISelGenericOpcode(I.getOpcode())) {
486 // Certain non-generic instructions also need some special handling.
488 if (Opcode == TargetOpcode::LOAD_STACK_GUARD)
489 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
491 if (Opcode == TargetOpcode::PHI) {
492 const unsigned DefReg = I.getOperand(0).getReg();
493 const LLT DefTy = MRI.getType(DefReg);
495 const TargetRegisterClass *DefRC = nullptr;
496 if (TargetRegisterInfo::isPhysicalRegister(DefReg)) {
497 DefRC = TRI.getRegClass(DefReg);
499 const RegClassOrRegBank &RegClassOrBank =
500 MRI.getRegClassOrRegBank(DefReg);
502 DefRC = RegClassOrBank.dyn_cast<const TargetRegisterClass *>();
504 if (!DefTy.isValid()) {
505 DEBUG(dbgs() << "PHI operand has no type, not a gvreg?\n");
508 const RegisterBank &RB = *RegClassOrBank.get<const RegisterBank *>();
509 DefRC = getRegClassForTypeOnBank(DefTy, RB, RBI);
511 DEBUG(dbgs() << "PHI operand has unexpected size/bank\n");
517 return RBI.constrainGenericRegister(DefReg, *DefRC, MRI);
521 return selectCopy(I, TII, MRI, TRI, RBI);
527 if (I.getNumOperands() != I.getNumExplicitOperands()) {
528 DEBUG(dbgs() << "Generic instruction has unexpected implicit operands\n");
536 I.getOperand(0).isReg() ? MRI.getType(I.getOperand(0).getReg()) : LLT{};
539 case TargetOpcode::G_BRCOND: {
540 if (Ty.getSizeInBits() > 32) {
541 // We shouldn't need this on AArch64, but it would be implemented as an
542 // EXTRACT_SUBREG followed by a TBNZW because TBNZX has no encoding if the
543 // bit being tested is < 32.
544 DEBUG(dbgs() << "G_BRCOND has type: " << Ty
545 << ", expected at most 32-bits");
549 const unsigned CondReg = I.getOperand(0).getReg();
550 MachineBasicBlock *DestMBB = I.getOperand(1).getMBB();
552 auto MIB = BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::TBNZW))
554 .addImm(/*bit offset=*/0)
558 return constrainSelectedInstRegOperands(*MIB.getInstr(), TII, TRI, RBI);
561 case TargetOpcode::G_FCONSTANT:
562 case TargetOpcode::G_CONSTANT: {
563 const bool isFP = Opcode == TargetOpcode::G_FCONSTANT;
565 const LLT s32 = LLT::scalar(32);
566 const LLT s64 = LLT::scalar(64);
567 const LLT p0 = LLT::pointer(0, 64);
569 const unsigned DefReg = I.getOperand(0).getReg();
570 const LLT DefTy = MRI.getType(DefReg);
571 const unsigned DefSize = DefTy.getSizeInBits();
572 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
574 // FIXME: Redundant check, but even less readable when factored out.
576 if (Ty != s32 && Ty != s64) {
577 DEBUG(dbgs() << "Unable to materialize FP " << Ty
578 << " constant, expected: " << s32 << " or " << s64
583 if (RB.getID() != AArch64::FPRRegBankID) {
584 DEBUG(dbgs() << "Unable to materialize FP " << Ty
585 << " constant on bank: " << RB << ", expected: FPR\n");
589 if (Ty != s32 && Ty != s64 && Ty != p0) {
590 DEBUG(dbgs() << "Unable to materialize integer " << Ty
591 << " constant, expected: " << s32 << ", " << s64 << ", or "
596 if (RB.getID() != AArch64::GPRRegBankID) {
597 DEBUG(dbgs() << "Unable to materialize integer " << Ty
598 << " constant on bank: " << RB << ", expected: GPR\n");
603 const unsigned MovOpc =
604 DefSize == 32 ? AArch64::MOVi32imm : AArch64::MOVi64imm;
606 I.setDesc(TII.get(MovOpc));
609 const TargetRegisterClass &GPRRC =
610 DefSize == 32 ? AArch64::GPR32RegClass : AArch64::GPR64RegClass;
611 const TargetRegisterClass &FPRRC =
612 DefSize == 32 ? AArch64::FPR32RegClass : AArch64::FPR64RegClass;
614 const unsigned DefGPRReg = MRI.createVirtualRegister(&GPRRC);
615 MachineOperand &RegOp = I.getOperand(0);
616 RegOp.setReg(DefGPRReg);
618 BuildMI(MBB, std::next(I.getIterator()), I.getDebugLoc(),
619 TII.get(AArch64::COPY))
623 if (!RBI.constrainGenericRegister(DefReg, FPRRC, MRI)) {
624 DEBUG(dbgs() << "Failed to constrain G_FCONSTANT def operand\n");
628 MachineOperand &ImmOp = I.getOperand(1);
629 // FIXME: Is going through int64_t always correct?
630 ImmOp.ChangeToImmediate(
631 ImmOp.getFPImm()->getValueAPF().bitcastToAPInt().getZExtValue());
633 uint64_t Val = I.getOperand(1).getCImm()->getZExtValue();
634 I.getOperand(1).ChangeToImmediate(Val);
637 constrainSelectedInstRegOperands(I, TII, TRI, RBI);
641 case TargetOpcode::G_FRAME_INDEX: {
642 // allocas and G_FRAME_INDEX are only supported in addrspace(0).
643 if (Ty != LLT::pointer(0, 64)) {
644 DEBUG(dbgs() << "G_FRAME_INDEX pointer has type: " << Ty
645 << ", expected: " << LLT::pointer(0, 64) << '\n');
649 I.setDesc(TII.get(AArch64::ADDXri));
651 // MOs for a #0 shifted immediate.
652 I.addOperand(MachineOperand::CreateImm(0));
653 I.addOperand(MachineOperand::CreateImm(0));
655 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
658 case TargetOpcode::G_GLOBAL_VALUE: {
659 auto GV = I.getOperand(1).getGlobal();
660 if (GV->isThreadLocal()) {
661 // FIXME: we don't support TLS yet.
664 unsigned char OpFlags = STI.ClassifyGlobalReference(GV, TM);
665 if (OpFlags & AArch64II::MO_GOT) {
666 I.setDesc(TII.get(AArch64::LOADgot));
667 I.getOperand(1).setTargetFlags(OpFlags);
669 I.setDesc(TII.get(AArch64::MOVaddr));
670 I.getOperand(1).setTargetFlags(OpFlags | AArch64II::MO_PAGE);
671 MachineInstrBuilder MIB(MF, I);
672 MIB.addGlobalAddress(GV, I.getOperand(1).getOffset(),
673 OpFlags | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
675 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
678 case TargetOpcode::G_LOAD:
679 case TargetOpcode::G_STORE: {
681 LLT PtrTy = MRI.getType(I.getOperand(1).getReg());
683 if (PtrTy != LLT::pointer(0, 64)) {
684 DEBUG(dbgs() << "Load/Store pointer has type: " << PtrTy
685 << ", expected: " << LLT::pointer(0, 64) << '\n');
690 // Sanity-check the pointer register.
691 const unsigned PtrReg = I.getOperand(1).getReg();
692 const RegisterBank &PtrRB = *RBI.getRegBank(PtrReg, MRI, TRI);
693 assert(PtrRB.getID() == AArch64::GPRRegBankID &&
694 "Load/Store pointer operand isn't a GPR");
695 assert(MRI.getType(PtrReg).isPointer() &&
696 "Load/Store pointer operand isn't a pointer");
699 const unsigned ValReg = I.getOperand(0).getReg();
700 const RegisterBank &RB = *RBI.getRegBank(ValReg, MRI, TRI);
702 const unsigned NewOpc =
703 selectLoadStoreUIOp(I.getOpcode(), RB.getID(), MemTy.getSizeInBits());
704 if (NewOpc == I.getOpcode())
707 I.setDesc(TII.get(NewOpc));
709 I.addOperand(MachineOperand::CreateImm(0));
710 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
713 case TargetOpcode::G_MUL: {
714 // Reject the various things we don't support yet.
715 if (unsupportedBinOp(I, RBI, MRI, TRI))
718 const unsigned DefReg = I.getOperand(0).getReg();
719 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
721 if (RB.getID() != AArch64::GPRRegBankID) {
722 DEBUG(dbgs() << "G_MUL on bank: " << RB << ", expected: GPR\n");
728 if (Ty.isScalar() && Ty.getSizeInBits() <= 32) {
729 NewOpc = AArch64::MADDWrrr;
730 ZeroReg = AArch64::WZR;
731 } else if (Ty == LLT::scalar(64)) {
732 NewOpc = AArch64::MADDXrrr;
733 ZeroReg = AArch64::XZR;
735 DEBUG(dbgs() << "G_MUL has type: " << Ty << ", expected: "
736 << LLT::scalar(32) << " or " << LLT::scalar(64) << '\n');
740 I.setDesc(TII.get(NewOpc));
742 I.addOperand(MachineOperand::CreateReg(ZeroReg, /*isDef=*/false));
744 // Now that we selected an opcode, we need to constrain the register
745 // operands to use appropriate classes.
746 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
749 case TargetOpcode::G_FADD:
750 case TargetOpcode::G_FSUB:
751 case TargetOpcode::G_FMUL:
752 case TargetOpcode::G_FDIV:
754 case TargetOpcode::G_OR:
755 case TargetOpcode::G_XOR:
756 case TargetOpcode::G_AND:
757 case TargetOpcode::G_SHL:
758 case TargetOpcode::G_LSHR:
759 case TargetOpcode::G_ASHR:
760 case TargetOpcode::G_SDIV:
761 case TargetOpcode::G_UDIV:
762 case TargetOpcode::G_ADD:
763 case TargetOpcode::G_SUB:
764 case TargetOpcode::G_GEP: {
765 // Reject the various things we don't support yet.
766 if (unsupportedBinOp(I, RBI, MRI, TRI))
769 const unsigned OpSize = Ty.getSizeInBits();
771 const unsigned DefReg = I.getOperand(0).getReg();
772 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
774 const unsigned NewOpc = selectBinaryOp(I.getOpcode(), RB.getID(), OpSize);
775 if (NewOpc == I.getOpcode())
778 I.setDesc(TII.get(NewOpc));
779 // FIXME: Should the type be always reset in setDesc?
781 // Now that we selected an opcode, we need to constrain the register
782 // operands to use appropriate classes.
783 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
786 case TargetOpcode::G_PTRTOINT:
787 case TargetOpcode::G_TRUNC: {
788 const LLT DstTy = MRI.getType(I.getOperand(0).getReg());
789 const LLT SrcTy = MRI.getType(I.getOperand(1).getReg());
791 const unsigned DstReg = I.getOperand(0).getReg();
792 const unsigned SrcReg = I.getOperand(1).getReg();
794 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
795 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI);
797 if (DstRB.getID() != SrcRB.getID()) {
798 DEBUG(dbgs() << "G_TRUNC input/output on different banks\n");
802 if (DstRB.getID() == AArch64::GPRRegBankID) {
803 const TargetRegisterClass *DstRC =
804 getRegClassForTypeOnBank(DstTy, DstRB, RBI);
808 const TargetRegisterClass *SrcRC =
809 getRegClassForTypeOnBank(SrcTy, SrcRB, RBI);
813 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
814 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
815 DEBUG(dbgs() << "Failed to constrain G_TRUNC\n");
819 if (DstRC == SrcRC) {
820 // Nothing to be done
821 } else if (DstRC == &AArch64::GPR32RegClass &&
822 SrcRC == &AArch64::GPR64RegClass) {
823 I.getOperand(1).setSubReg(AArch64::sub_32);
828 I.setDesc(TII.get(TargetOpcode::COPY));
830 } else if (DstRB.getID() == AArch64::FPRRegBankID) {
831 if (DstTy == LLT::vector(4, 16) && SrcTy == LLT::vector(4, 32)) {
832 I.setDesc(TII.get(AArch64::XTNv4i16));
833 constrainSelectedInstRegOperands(I, TII, TRI, RBI);
841 case TargetOpcode::G_ANYEXT: {
842 const unsigned DstReg = I.getOperand(0).getReg();
843 const unsigned SrcReg = I.getOperand(1).getReg();
845 const RegisterBank &RBDst = *RBI.getRegBank(DstReg, MRI, TRI);
846 if (RBDst.getID() != AArch64::GPRRegBankID) {
847 DEBUG(dbgs() << "G_ANYEXT on bank: " << RBDst << ", expected: GPR\n");
851 const RegisterBank &RBSrc = *RBI.getRegBank(SrcReg, MRI, TRI);
852 if (RBSrc.getID() != AArch64::GPRRegBankID) {
853 DEBUG(dbgs() << "G_ANYEXT on bank: " << RBSrc << ", expected: GPR\n");
857 const unsigned DstSize = MRI.getType(DstReg).getSizeInBits();
860 DEBUG(dbgs() << "G_ANYEXT operand has no size, not a gvreg?\n");
864 if (DstSize != 64 && DstSize > 32) {
865 DEBUG(dbgs() << "G_ANYEXT to size: " << DstSize
866 << ", expected: 32 or 64\n");
869 // At this point G_ANYEXT is just like a plain COPY, but we need
870 // to explicitly form the 64-bit value if any.
872 unsigned ExtSrc = MRI.createVirtualRegister(&AArch64::GPR64allRegClass);
873 BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::SUBREG_TO_REG))
877 .addImm(AArch64::sub_32);
878 I.getOperand(1).setReg(ExtSrc);
880 return selectCopy(I, TII, MRI, TRI, RBI);
883 case TargetOpcode::G_ZEXT:
884 case TargetOpcode::G_SEXT: {
885 unsigned Opcode = I.getOpcode();
886 const LLT DstTy = MRI.getType(I.getOperand(0).getReg()),
887 SrcTy = MRI.getType(I.getOperand(1).getReg());
888 const bool isSigned = Opcode == TargetOpcode::G_SEXT;
889 const unsigned DefReg = I.getOperand(0).getReg();
890 const unsigned SrcReg = I.getOperand(1).getReg();
891 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
893 if (RB.getID() != AArch64::GPRRegBankID) {
894 DEBUG(dbgs() << TII.getName(I.getOpcode()) << " on bank: " << RB
895 << ", expected: GPR\n");
900 if (DstTy == LLT::scalar(64)) {
901 // FIXME: Can we avoid manually doing this?
902 if (!RBI.constrainGenericRegister(SrcReg, AArch64::GPR32RegClass, MRI)) {
903 DEBUG(dbgs() << "Failed to constrain " << TII.getName(Opcode)
908 const unsigned SrcXReg =
909 MRI.createVirtualRegister(&AArch64::GPR64RegClass);
910 BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::SUBREG_TO_REG))
914 .addImm(AArch64::sub_32);
916 const unsigned NewOpc = isSigned ? AArch64::SBFMXri : AArch64::UBFMXri;
917 ExtI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc))
921 .addImm(SrcTy.getSizeInBits() - 1);
922 } else if (DstTy.isScalar() && DstTy.getSizeInBits() <= 32) {
923 const unsigned NewOpc = isSigned ? AArch64::SBFMWri : AArch64::UBFMWri;
924 ExtI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc))
928 .addImm(SrcTy.getSizeInBits() - 1);
933 constrainSelectedInstRegOperands(*ExtI, TII, TRI, RBI);
939 case TargetOpcode::G_SITOFP:
940 case TargetOpcode::G_UITOFP:
941 case TargetOpcode::G_FPTOSI:
942 case TargetOpcode::G_FPTOUI: {
943 const LLT DstTy = MRI.getType(I.getOperand(0).getReg()),
944 SrcTy = MRI.getType(I.getOperand(1).getReg());
945 const unsigned NewOpc = selectFPConvOpc(Opcode, DstTy, SrcTy);
946 if (NewOpc == Opcode)
949 I.setDesc(TII.get(NewOpc));
950 constrainSelectedInstRegOperands(I, TII, TRI, RBI);
956 case TargetOpcode::G_INTTOPTR:
957 case TargetOpcode::G_BITCAST:
958 return selectCopy(I, TII, MRI, TRI, RBI);
960 case TargetOpcode::G_FPEXT: {
961 if (MRI.getType(I.getOperand(0).getReg()) != LLT::scalar(64)) {
962 DEBUG(dbgs() << "G_FPEXT to type " << Ty
963 << ", expected: " << LLT::scalar(64) << '\n');
967 if (MRI.getType(I.getOperand(1).getReg()) != LLT::scalar(32)) {
968 DEBUG(dbgs() << "G_FPEXT from type " << Ty
969 << ", expected: " << LLT::scalar(32) << '\n');
973 const unsigned DefReg = I.getOperand(0).getReg();
974 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
976 if (RB.getID() != AArch64::FPRRegBankID) {
977 DEBUG(dbgs() << "G_FPEXT on bank: " << RB << ", expected: FPR\n");
981 I.setDesc(TII.get(AArch64::FCVTDSr));
982 constrainSelectedInstRegOperands(I, TII, TRI, RBI);
987 case TargetOpcode::G_FPTRUNC: {
988 if (MRI.getType(I.getOperand(0).getReg()) != LLT::scalar(32)) {
989 DEBUG(dbgs() << "G_FPTRUNC to type " << Ty
990 << ", expected: " << LLT::scalar(32) << '\n');
994 if (MRI.getType(I.getOperand(1).getReg()) != LLT::scalar(64)) {
995 DEBUG(dbgs() << "G_FPTRUNC from type " << Ty
996 << ", expected: " << LLT::scalar(64) << '\n');
1000 const unsigned DefReg = I.getOperand(0).getReg();
1001 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
1003 if (RB.getID() != AArch64::FPRRegBankID) {
1004 DEBUG(dbgs() << "G_FPTRUNC on bank: " << RB << ", expected: FPR\n");
1008 I.setDesc(TII.get(AArch64::FCVTSDr));
1009 constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1014 case TargetOpcode::G_SELECT: {
1015 if (MRI.getType(I.getOperand(1).getReg()) != LLT::scalar(1)) {
1016 DEBUG(dbgs() << "G_SELECT cond has type: " << Ty
1017 << ", expected: " << LLT::scalar(1) << '\n');
1021 const unsigned CondReg = I.getOperand(1).getReg();
1022 const unsigned TReg = I.getOperand(2).getReg();
1023 const unsigned FReg = I.getOperand(3).getReg();
1025 unsigned CSelOpc = 0;
1027 if (Ty == LLT::scalar(32)) {
1028 CSelOpc = AArch64::CSELWr;
1029 } else if (Ty == LLT::scalar(64)) {
1030 CSelOpc = AArch64::CSELXr;
1035 MachineInstr &TstMI =
1036 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::ANDSWri))
1037 .addDef(AArch64::WZR)
1039 .addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
1041 MachineInstr &CSelMI = *BuildMI(MBB, I, I.getDebugLoc(), TII.get(CSelOpc))
1042 .addDef(I.getOperand(0).getReg())
1045 .addImm(AArch64CC::NE);
1047 constrainSelectedInstRegOperands(TstMI, TII, TRI, RBI);
1048 constrainSelectedInstRegOperands(CSelMI, TII, TRI, RBI);
1050 I.eraseFromParent();
1053 case TargetOpcode::G_ICMP: {
1054 if (Ty != LLT::scalar(1)) {
1055 DEBUG(dbgs() << "G_ICMP result has type: " << Ty
1056 << ", expected: " << LLT::scalar(1) << '\n');
1060 unsigned CmpOpc = 0;
1063 LLT CmpTy = MRI.getType(I.getOperand(2).getReg());
1064 if (CmpTy == LLT::scalar(32)) {
1065 CmpOpc = AArch64::SUBSWrr;
1066 ZReg = AArch64::WZR;
1067 } else if (CmpTy == LLT::scalar(64) || CmpTy.isPointer()) {
1068 CmpOpc = AArch64::SUBSXrr;
1069 ZReg = AArch64::XZR;
1074 const AArch64CC::CondCode CC = changeICMPPredToAArch64CC(
1075 (CmpInst::Predicate)I.getOperand(1).getPredicate());
1077 MachineInstr &CmpMI = *BuildMI(MBB, I, I.getDebugLoc(), TII.get(CmpOpc))
1079 .addUse(I.getOperand(2).getReg())
1080 .addUse(I.getOperand(3).getReg());
1082 MachineInstr &CSetMI =
1083 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::CSINCWr))
1084 .addDef(I.getOperand(0).getReg())
1085 .addUse(AArch64::WZR)
1086 .addUse(AArch64::WZR)
1089 constrainSelectedInstRegOperands(CmpMI, TII, TRI, RBI);
1090 constrainSelectedInstRegOperands(CSetMI, TII, TRI, RBI);
1092 I.eraseFromParent();
1096 case TargetOpcode::G_FCMP: {
1097 if (Ty != LLT::scalar(1)) {
1098 DEBUG(dbgs() << "G_FCMP result has type: " << Ty
1099 << ", expected: " << LLT::scalar(1) << '\n');
1103 unsigned CmpOpc = 0;
1104 LLT CmpTy = MRI.getType(I.getOperand(2).getReg());
1105 if (CmpTy == LLT::scalar(32)) {
1106 CmpOpc = AArch64::FCMPSrr;
1107 } else if (CmpTy == LLT::scalar(64)) {
1108 CmpOpc = AArch64::FCMPDrr;
1115 AArch64CC::CondCode CC1, CC2;
1116 changeFCMPPredToAArch64CC(
1117 (CmpInst::Predicate)I.getOperand(1).getPredicate(), CC1, CC2);
1119 MachineInstr &CmpMI = *BuildMI(MBB, I, I.getDebugLoc(), TII.get(CmpOpc))
1120 .addUse(I.getOperand(2).getReg())
1121 .addUse(I.getOperand(3).getReg());
1123 const unsigned DefReg = I.getOperand(0).getReg();
1124 unsigned Def1Reg = DefReg;
1125 if (CC2 != AArch64CC::AL)
1126 Def1Reg = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
1128 MachineInstr &CSetMI =
1129 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::CSINCWr))
1131 .addUse(AArch64::WZR)
1132 .addUse(AArch64::WZR)
1135 if (CC2 != AArch64CC::AL) {
1136 unsigned Def2Reg = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
1137 MachineInstr &CSet2MI =
1138 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::CSINCWr))
1140 .addUse(AArch64::WZR)
1141 .addUse(AArch64::WZR)
1143 MachineInstr &OrMI =
1144 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::ORRWrr))
1148 constrainSelectedInstRegOperands(OrMI, TII, TRI, RBI);
1149 constrainSelectedInstRegOperands(CSet2MI, TII, TRI, RBI);
1152 constrainSelectedInstRegOperands(CmpMI, TII, TRI, RBI);
1153 constrainSelectedInstRegOperands(CSetMI, TII, TRI, RBI);
1155 I.eraseFromParent();