1 //===- AArch64LegalizerInfo.cpp ----------------------------------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file implements the targeting of the Machinelegalizer class for
12 /// \todo This should be generated by TableGen.
13 //===----------------------------------------------------------------------===//
15 #include "AArch64LegalizerInfo.h"
16 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
17 #include "llvm/CodeGen/MachineInstr.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/CodeGen/ValueTypes.h"
20 #include "llvm/IR/DerivedTypes.h"
21 #include "llvm/IR/Type.h"
22 #include "llvm/Target/TargetOpcodes.h"
26 #ifndef LLVM_BUILD_GLOBAL_ISEL
27 #error "You shouldn't build this"
30 AArch64LegalizerInfo::AArch64LegalizerInfo() {
31 using namespace TargetOpcode;
32 const LLT p0 = LLT::pointer(0, 64);
33 const LLT s1 = LLT::scalar(1);
34 const LLT s8 = LLT::scalar(8);
35 const LLT s16 = LLT::scalar(16);
36 const LLT s32 = LLT::scalar(32);
37 const LLT s64 = LLT::scalar(64);
38 const LLT v2s32 = LLT::vector(2, 32);
39 const LLT v4s32 = LLT::vector(4, 32);
40 const LLT v2s64 = LLT::vector(2, 64);
42 for (unsigned BinOp : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR, G_SHL}) {
43 // These operations naturally get the right answer when used on
44 // GPR32, even if the actual type is narrower.
45 for (auto Ty : {s32, s64, v2s32, v4s32, v2s64})
46 setAction({BinOp, Ty}, Legal);
48 for (auto Ty : {s1, s8, s16})
49 setAction({BinOp, Ty}, WidenScalar);
52 setAction({G_GEP, p0}, Legal);
53 setAction({G_GEP, 1, s64}, Legal);
55 for (auto Ty : {s1, s8, s16, s32})
56 setAction({G_GEP, 1, Ty}, WidenScalar);
58 setAction({G_PTR_MASK, p0}, Legal);
60 for (unsigned BinOp : {G_LSHR, G_ASHR, G_SDIV, G_UDIV}) {
61 for (auto Ty : {s32, s64})
62 setAction({BinOp, Ty}, Legal);
64 for (auto Ty : {s1, s8, s16})
65 setAction({BinOp, Ty}, WidenScalar);
68 for (unsigned BinOp : {G_SREM, G_UREM})
69 for (auto Ty : { s1, s8, s16, s32, s64 })
70 setAction({BinOp, Ty}, Lower);
72 for (unsigned Op : {G_SMULO, G_UMULO})
73 setAction({Op, s64}, Lower);
75 for (unsigned Op : {G_UADDE, G_USUBE, G_SADDO, G_SSUBO, G_SMULH, G_UMULH}) {
76 for (auto Ty : { s32, s64 })
77 setAction({Op, Ty}, Legal);
79 setAction({Op, 1, s1}, Legal);
82 for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV})
83 for (auto Ty : {s32, s64})
84 setAction({BinOp, Ty}, Legal);
86 for (unsigned BinOp : {G_FREM, G_FPOW}) {
87 setAction({BinOp, s32}, Libcall);
88 setAction({BinOp, s64}, Libcall);
91 for (auto Ty : {s32, s64, p0}) {
92 setAction({G_INSERT, Ty}, Legal);
93 setAction({G_INSERT, 1, Ty}, Legal);
95 for (auto Ty : {s1, s8, s16}) {
96 setAction({G_INSERT, Ty}, WidenScalar);
97 setAction({G_INSERT, 1, Ty}, Legal);
98 // FIXME: Can't widen the sources because that violates the constraints on
99 // G_INSERT (It seems entirely reasonable that inputs shouldn't overlap).
102 for (unsigned MemOp : {G_LOAD, G_STORE}) {
103 for (auto Ty : {s8, s16, s32, s64, p0, v2s32})
104 setAction({MemOp, Ty}, Legal);
106 setAction({MemOp, s1}, WidenScalar);
108 // And everything's fine in addrspace 0.
109 setAction({MemOp, 1, p0}, Legal);
113 for (auto Ty : {s32, s64}) {
114 setAction({TargetOpcode::G_CONSTANT, Ty}, Legal);
115 setAction({TargetOpcode::G_FCONSTANT, Ty}, Legal);
118 setAction({G_CONSTANT, p0}, Legal);
120 for (auto Ty : {s1, s8, s16})
121 setAction({TargetOpcode::G_CONSTANT, Ty}, WidenScalar);
123 setAction({TargetOpcode::G_FCONSTANT, s16}, WidenScalar);
125 setAction({G_ICMP, s1}, Legal);
126 setAction({G_ICMP, 1, s32}, Legal);
127 setAction({G_ICMP, 1, s64}, Legal);
128 setAction({G_ICMP, 1, p0}, Legal);
130 for (auto Ty : {s1, s8, s16}) {
131 setAction({G_ICMP, 1, Ty}, WidenScalar);
134 setAction({G_FCMP, s1}, Legal);
135 setAction({G_FCMP, 1, s32}, Legal);
136 setAction({G_FCMP, 1, s64}, Legal);
139 for (auto Ty : { s1, s8, s16, s32, s64 }) {
140 setAction({G_ZEXT, Ty}, Legal);
141 setAction({G_SEXT, Ty}, Legal);
142 setAction({G_ANYEXT, Ty}, Legal);
145 for (auto Ty : { s1, s8, s16, s32 }) {
146 setAction({G_ZEXT, 1, Ty}, Legal);
147 setAction({G_SEXT, 1, Ty}, Legal);
148 setAction({G_ANYEXT, 1, Ty}, Legal);
151 setAction({G_FPEXT, s64}, Legal);
152 setAction({G_FPEXT, 1, s32}, Legal);
155 for (auto Ty : { s16, s32 })
156 setAction({G_FPTRUNC, Ty}, Legal);
158 for (auto Ty : { s32, s64 })
159 setAction({G_FPTRUNC, 1, Ty}, Legal);
161 for (auto Ty : { s1, s8, s16, s32 })
162 setAction({G_TRUNC, Ty}, Legal);
164 for (auto Ty : { s8, s16, s32, s64 })
165 setAction({G_TRUNC, 1, Ty}, Legal);
168 for (auto Ty : { s32, s64 }) {
169 setAction({G_FPTOSI, 0, Ty}, Legal);
170 setAction({G_FPTOUI, 0, Ty}, Legal);
171 setAction({G_SITOFP, 1, Ty}, Legal);
172 setAction({G_UITOFP, 1, Ty}, Legal);
174 for (auto Ty : { s1, s8, s16 }) {
175 setAction({G_FPTOSI, 0, Ty}, WidenScalar);
176 setAction({G_FPTOUI, 0, Ty}, WidenScalar);
177 setAction({G_SITOFP, 1, Ty}, WidenScalar);
178 setAction({G_UITOFP, 1, Ty}, WidenScalar);
181 for (auto Ty : { s32, s64 }) {
182 setAction({G_FPTOSI, 1, Ty}, Legal);
183 setAction({G_FPTOUI, 1, Ty}, Legal);
184 setAction({G_SITOFP, 0, Ty}, Legal);
185 setAction({G_UITOFP, 0, Ty}, Legal);
189 for (auto Ty : {s1, s8, s16, s32})
190 setAction({G_BRCOND, Ty}, Legal);
191 setAction({G_BRINDIRECT, p0}, Legal);
194 for (auto Ty : {s1, s8, s16})
195 setAction({G_SELECT, Ty}, WidenScalar);
197 for (auto Ty : {s32, s64, p0})
198 setAction({G_SELECT, Ty}, Legal);
200 setAction({G_SELECT, 1, s1}, Legal);
203 setAction({G_FRAME_INDEX, p0}, Legal);
204 setAction({G_GLOBAL_VALUE, p0}, Legal);
206 for (auto Ty : {s1, s8, s16, s32, s64})
207 setAction({G_PTRTOINT, 0, Ty}, Legal);
209 setAction({G_PTRTOINT, 1, p0}, Legal);
211 setAction({G_INTTOPTR, 0, p0}, Legal);
212 setAction({G_INTTOPTR, 1, s64}, Legal);
214 // Casts for 32 and 64-bit width type are just copies.
215 for (auto Ty : {s1, s8, s16, s32, s64}) {
216 setAction({G_BITCAST, 0, Ty}, Legal);
217 setAction({G_BITCAST, 1, Ty}, Legal);
220 // For the sake of copying bits around, the type does not really
221 // matter as long as it fits a register.
222 for (int EltSize = 8; EltSize <= 64; EltSize *= 2) {
223 setAction({G_BITCAST, 0, LLT::vector(128/EltSize, EltSize)}, Legal);
224 setAction({G_BITCAST, 1, LLT::vector(128/EltSize, EltSize)}, Legal);
228 setAction({G_BITCAST, 0, LLT::vector(64/EltSize, EltSize)}, Legal);
229 setAction({G_BITCAST, 1, LLT::vector(64/EltSize, EltSize)}, Legal);
233 setAction({G_BITCAST, 0, LLT::vector(32/EltSize, EltSize)}, Legal);
234 setAction({G_BITCAST, 1, LLT::vector(32/EltSize, EltSize)}, Legal);
237 setAction({G_VASTART, p0}, Legal);
239 // va_list must be a pointer, but most sized types are pretty easy to handle
240 // as the destination.
241 setAction({G_VAARG, 1, p0}, Legal);
243 for (auto Ty : {s8, s16, s32, s64, p0})
244 setAction({G_VAARG, Ty}, Custom);
249 bool AArch64LegalizerInfo::legalizeCustom(MachineInstr &MI,
250 MachineRegisterInfo &MRI,
251 MachineIRBuilder &MIRBuilder) const {
252 switch (MI.getOpcode()) {
254 // No idea what to do.
256 case TargetOpcode::G_VAARG:
257 return legalizeVaArg(MI, MRI, MIRBuilder);
260 llvm_unreachable("expected switch to return");
263 bool AArch64LegalizerInfo::legalizeVaArg(MachineInstr &MI,
264 MachineRegisterInfo &MRI,
265 MachineIRBuilder &MIRBuilder) const {
266 MIRBuilder.setInstr(MI);
267 MachineFunction &MF = MIRBuilder.getMF();
268 unsigned Align = MI.getOperand(2).getImm();
269 unsigned Dst = MI.getOperand(0).getReg();
270 unsigned ListPtr = MI.getOperand(1).getReg();
272 LLT PtrTy = MRI.getType(ListPtr);
273 LLT IntPtrTy = LLT::scalar(PtrTy.getSizeInBits());
275 const unsigned PtrSize = PtrTy.getSizeInBits() / 8;
276 unsigned List = MRI.createGenericVirtualRegister(PtrTy);
277 MIRBuilder.buildLoad(
279 *MF.getMachineMemOperand(MachinePointerInfo(), MachineMemOperand::MOLoad,
280 PtrSize, /* Align = */ PtrSize));
283 if (Align > PtrSize) {
284 // Realign the list to the actual required alignment.
285 unsigned AlignMinus1 = MRI.createGenericVirtualRegister(IntPtrTy);
286 MIRBuilder.buildConstant(AlignMinus1, Align - 1);
288 unsigned ListTmp = MRI.createGenericVirtualRegister(PtrTy);
289 MIRBuilder.buildGEP(ListTmp, List, AlignMinus1);
291 DstPtr = MRI.createGenericVirtualRegister(PtrTy);
292 MIRBuilder.buildPtrMask(DstPtr, ListTmp, Log2_64(Align));
296 uint64_t ValSize = MRI.getType(Dst).getSizeInBits() / 8;
297 MIRBuilder.buildLoad(
299 *MF.getMachineMemOperand(MachinePointerInfo(), MachineMemOperand::MOLoad,
300 ValSize, std::max(Align, PtrSize)));
302 unsigned SizeReg = MRI.createGenericVirtualRegister(IntPtrTy);
303 MIRBuilder.buildConstant(SizeReg, alignTo(ValSize, PtrSize));
305 unsigned NewList = MRI.createGenericVirtualRegister(PtrTy);
306 MIRBuilder.buildGEP(NewList, DstPtr, SizeReg);
308 MIRBuilder.buildStore(
310 *MF.getMachineMemOperand(MachinePointerInfo(), MachineMemOperand::MOStore,
311 PtrSize, /* Align = */ PtrSize));
313 MI.eraseFromParent();