1 //=- AArch64RedundantCopyElimination.cpp - Remove useless copy for AArch64 -=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 // This pass removes unnecessary zero copies in BBs that are targets of
9 // cbz/cbnz instructions. For instance, the copy instruction in the code below
10 // can be removed because the CBZW jumps to BB#2 when W0 is zero.
15 // This pass should be run after register allocation.
17 // FIXME: This should be extended to handle any constant other than zero. E.g.,
23 // FIXME: This could also be extended to check the whole dominance subtree below
24 // the comparison if the compile time regression is acceptable.
26 //===----------------------------------------------------------------------===//
29 #include "llvm/ADT/SetVector.h"
30 #include "llvm/ADT/Statistic.h"
31 #include "llvm/ADT/iterator_range.h"
32 #include "llvm/CodeGen/MachineFunctionPass.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/Support/Debug.h"
38 #define DEBUG_TYPE "aarch64-copyelim"
40 STATISTIC(NumCopiesRemoved, "Number of copies removed.");
43 void initializeAArch64RedundantCopyEliminationPass(PassRegistry &);
47 class AArch64RedundantCopyElimination : public MachineFunctionPass {
48 const MachineRegisterInfo *MRI;
49 const TargetRegisterInfo *TRI;
53 AArch64RedundantCopyElimination() : MachineFunctionPass(ID) {}
54 bool optimizeCopy(MachineBasicBlock *MBB);
55 bool runOnMachineFunction(MachineFunction &MF) override;
56 MachineFunctionProperties getRequiredProperties() const override {
57 return MachineFunctionProperties().set(
58 MachineFunctionProperties::Property::AllVRegsAllocated);
60 const char *getPassName() const override {
61 return "AArch64 Redundant Copy Elimination";
64 char AArch64RedundantCopyElimination::ID = 0;
67 INITIALIZE_PASS(AArch64RedundantCopyElimination, "aarch64-copyelim",
68 "AArch64 redundant copy elimination pass", false, false)
70 static bool guaranteesZeroRegInBlock(MachineInstr &MI, MachineBasicBlock *MBB) {
71 unsigned Opc = MI.getOpcode();
72 // Check if the current basic block is the target block to which the
73 // CBZ/CBNZ instruction jumps when its Wt/Xt is zero.
74 if ((Opc == AArch64::CBZW || Opc == AArch64::CBZX) &&
75 MBB == MI.getOperand(1).getMBB())
77 else if ((Opc == AArch64::CBNZW || Opc == AArch64::CBNZX) &&
78 MBB != MI.getOperand(1).getMBB())
84 bool AArch64RedundantCopyElimination::optimizeCopy(MachineBasicBlock *MBB) {
85 // Check if the current basic block has a single predecessor.
86 if (MBB->pred_size() != 1)
89 MachineBasicBlock *PredMBB = *MBB->pred_begin();
90 MachineBasicBlock::iterator CompBr = PredMBB->getLastNonDebugInstr();
91 if (CompBr == PredMBB->end() || PredMBB->succ_size() != 2)
97 if (guaranteesZeroRegInBlock(*CompBr, MBB))
99 } while (CompBr != PredMBB->begin() && CompBr->isTerminator());
101 // We've not found a CBZ/CBNZ, time to bail out.
102 if (!guaranteesZeroRegInBlock(*CompBr, MBB))
105 unsigned TargetReg = CompBr->getOperand(0).getReg();
108 assert(TargetRegisterInfo::isPhysicalRegister(TargetReg) &&
109 "Expect physical register");
111 // Remember all registers aliasing with TargetReg.
112 SmallSetVector<unsigned, 8> TargetRegs;
113 for (MCRegAliasIterator AI(TargetReg, TRI, true); AI.isValid(); ++AI)
114 TargetRegs.insert(*AI);
116 bool Changed = false;
117 MachineBasicBlock::iterator LastChange = MBB->begin();
118 unsigned SmallestDef = TargetReg;
119 // Remove redundant Copy instructions unless TargetReg is modified.
120 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;) {
121 MachineInstr *MI = &*I;
123 if (MI->isCopy() && MI->getOperand(0).isReg() &&
124 MI->getOperand(1).isReg()) {
126 unsigned DefReg = MI->getOperand(0).getReg();
127 unsigned SrcReg = MI->getOperand(1).getReg();
129 if ((SrcReg == AArch64::XZR || SrcReg == AArch64::WZR) &&
130 !MRI->isReserved(DefReg) &&
131 (TargetReg == DefReg || TRI->isSuperRegister(DefReg, TargetReg))) {
132 DEBUG(dbgs() << "Remove redundant Copy : ");
133 DEBUG((MI)->print(dbgs()));
135 MI->eraseFromParent();
140 TRI->isSubRegister(SmallestDef, DefReg) ? DefReg : SmallestDef;
145 if (MI->modifiesRegister(TargetReg, TRI))
152 // Otherwise, we have to fixup the use-def chain, starting with the
153 // CBZ/CBNZ. Conservatively mark as much as we can live.
154 CompBr->clearRegisterKills(SmallestDef, TRI);
156 if (std::none_of(TargetRegs.begin(), TargetRegs.end(),
157 [&](unsigned Reg) { return MBB->isLiveIn(Reg); }))
158 MBB->addLiveIn(TargetReg);
160 // Clear any kills of TargetReg between CompBr and the last removed COPY.
161 for (MachineInstr &MMI :
162 make_range(MBB->begin()->getIterator(), LastChange->getIterator()))
163 MMI.clearRegisterKills(SmallestDef, TRI);
168 bool AArch64RedundantCopyElimination::runOnMachineFunction(
169 MachineFunction &MF) {
170 if (skipFunction(*MF.getFunction()))
172 TRI = MF.getSubtarget().getRegisterInfo();
173 MRI = &MF.getRegInfo();
174 bool Changed = false;
175 for (MachineBasicBlock &MBB : MF)
176 Changed |= optimizeCopy(&MBB);
180 FunctionPass *llvm::createAArch64RedundantCopyEliminationPass() {
181 return new AArch64RedundantCopyElimination();