1 //=- AArch64RedundantCopyElimination.cpp - Remove useless copy for AArch64 -=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 // This pass removes unnecessary zero copies in BBs that are targets of
9 // cbz/cbnz instructions. For instance, the copy instruction in the code below
10 // can be removed because the CBZW jumps to BB#2 when W0 is zero.
15 // This pass should be run after register allocation.
17 // FIXME: This should be extended to handle any constant other than zero. E.g.,
23 // FIXME: This could also be extended to check the whole dominance subtree below
24 // the comparison if the compile time regression is acceptable.
26 //===----------------------------------------------------------------------===//
29 #include "llvm/ADT/SetVector.h"
30 #include "llvm/ADT/Statistic.h"
31 #include "llvm/ADT/iterator_range.h"
32 #include "llvm/CodeGen/MachineFunctionPass.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/Support/Debug.h"
38 #define DEBUG_TYPE "aarch64-copyelim"
40 STATISTIC(NumCopiesRemoved, "Number of copies removed.");
43 class AArch64RedundantCopyElimination : public MachineFunctionPass {
44 const MachineRegisterInfo *MRI;
45 const TargetRegisterInfo *TRI;
49 AArch64RedundantCopyElimination() : MachineFunctionPass(ID) {
50 initializeAArch64RedundantCopyEliminationPass(
51 *PassRegistry::getPassRegistry());
53 bool optimizeCopy(MachineBasicBlock *MBB);
54 bool runOnMachineFunction(MachineFunction &MF) override;
55 MachineFunctionProperties getRequiredProperties() const override {
56 return MachineFunctionProperties().set(
57 MachineFunctionProperties::Property::NoVRegs);
59 StringRef getPassName() const override {
60 return "AArch64 Redundant Copy Elimination";
63 char AArch64RedundantCopyElimination::ID = 0;
66 INITIALIZE_PASS(AArch64RedundantCopyElimination, "aarch64-copyelim",
67 "AArch64 redundant copy elimination pass", false, false)
69 static bool guaranteesZeroRegInBlock(MachineInstr &MI, MachineBasicBlock *MBB) {
70 unsigned Opc = MI.getOpcode();
71 // Check if the current basic block is the target block to which the
72 // CBZ/CBNZ instruction jumps when its Wt/Xt is zero.
73 if ((Opc == AArch64::CBZW || Opc == AArch64::CBZX) &&
74 MBB == MI.getOperand(1).getMBB())
76 else if ((Opc == AArch64::CBNZW || Opc == AArch64::CBNZX) &&
77 MBB != MI.getOperand(1).getMBB())
83 bool AArch64RedundantCopyElimination::optimizeCopy(MachineBasicBlock *MBB) {
84 // Check if the current basic block has a single predecessor.
85 if (MBB->pred_size() != 1)
88 MachineBasicBlock *PredMBB = *MBB->pred_begin();
89 MachineBasicBlock::iterator CompBr = PredMBB->getLastNonDebugInstr();
90 if (CompBr == PredMBB->end() || PredMBB->succ_size() != 2)
96 if (guaranteesZeroRegInBlock(*CompBr, MBB))
98 } while (CompBr != PredMBB->begin() && CompBr->isTerminator());
100 // We've not found a CBZ/CBNZ, time to bail out.
101 if (!guaranteesZeroRegInBlock(*CompBr, MBB))
104 unsigned TargetReg = CompBr->getOperand(0).getReg();
107 assert(TargetRegisterInfo::isPhysicalRegister(TargetReg) &&
108 "Expect physical register");
110 // Remember all registers aliasing with TargetReg.
111 SmallSetVector<unsigned, 8> TargetRegs;
112 for (MCRegAliasIterator AI(TargetReg, TRI, true); AI.isValid(); ++AI)
113 TargetRegs.insert(*AI);
115 bool Changed = false;
116 MachineBasicBlock::iterator LastChange = MBB->begin();
117 unsigned SmallestDef = TargetReg;
118 // Remove redundant Copy instructions unless TargetReg is modified.
119 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;) {
120 MachineInstr *MI = &*I;
122 if (MI->isCopy() && MI->getOperand(0).isReg() &&
123 MI->getOperand(1).isReg()) {
125 unsigned DefReg = MI->getOperand(0).getReg();
126 unsigned SrcReg = MI->getOperand(1).getReg();
128 if ((SrcReg == AArch64::XZR || SrcReg == AArch64::WZR) &&
129 !MRI->isReserved(DefReg) &&
130 (TargetReg == DefReg || TRI->isSuperRegister(DefReg, TargetReg))) {
131 DEBUG(dbgs() << "Remove redundant Copy : ");
132 DEBUG((MI)->print(dbgs()));
134 MI->eraseFromParent();
139 TRI->isSubRegister(SmallestDef, DefReg) ? DefReg : SmallestDef;
144 if (MI->modifiesRegister(TargetReg, TRI))
151 // Otherwise, we have to fixup the use-def chain, starting with the
152 // CBZ/CBNZ. Conservatively mark as much as we can live.
153 CompBr->clearRegisterKills(SmallestDef, TRI);
155 if (none_of(TargetRegs, [&](unsigned Reg) { return MBB->isLiveIn(Reg); }))
156 MBB->addLiveIn(TargetReg);
158 // Clear any kills of TargetReg between CompBr and the last removed COPY.
159 for (MachineInstr &MMI : make_range(MBB->begin(), LastChange))
160 MMI.clearRegisterKills(SmallestDef, TRI);
165 bool AArch64RedundantCopyElimination::runOnMachineFunction(
166 MachineFunction &MF) {
167 if (skipFunction(*MF.getFunction()))
169 TRI = MF.getSubtarget().getRegisterInfo();
170 MRI = &MF.getRegInfo();
171 bool Changed = false;
172 for (MachineBasicBlock &MBB : MF)
173 Changed |= optimizeCopy(&MBB);
177 FunctionPass *llvm::createAArch64RedundantCopyEliminationPass() {
178 return new AArch64RedundantCopyElimination();